drivers/gpu/drm/tilcdc/tilcdc_drv.h

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __TILCDC_DRV_H__
  19 #define __TILCDC_DRV_H__
  20
  21 #include <linux/clk.h>
  22 #include <linux/cpufreq.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/slab.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/list.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_gem_cma_helper.h>
  35 #include <drm/drm_fb_cma_helper.h>
  36
  37 /* Defaulting to pixel clock defined on AM335x */
  38 #define TILCDC_DEFAULT_MAX_PIXELCLOCK  126000
  39 /* Defaulting to max width as defined on AM335x */
  40 #define TILCDC_DEFAULT_MAX_WIDTH  2048
  41 /*
  42  * This may need some tweaking, but want to allow at least 1280x1024@60
  43  * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
  44  * be supportable
  45  */
  46 #define TILCDC_DEFAULT_MAX_BANDWIDTH  (1280*1024*60)
  47
  48
  49 struct tilcdc_drm_private {
  50         void __iomem *mmio;
  51
  52         struct clk *clk;         /* functional clock */
  53         int rev;                 /* IP revision */
  54
  55         /* don't attempt resolutions w/ higher W * H * Hz: */
  56         uint32_t max_bandwidth;
  57         /*
  58          * Pixel Clock will be restricted to some value as
  59          * defined in the device datasheet measured in KHz
  60          */
  61         uint32_t max_pixelclock;
  62         /*
  63          * Max allowable width is limited on a per device basis
  64          * measured in pixels
  65          */
  66         uint32_t max_width;
  67
  68         /* register contents saved across suspend/resume: */
  69         u32 *saved_register;
  70         bool ctx_valid;
  71
  72 #ifdef CONFIG_CPU_FREQ
  73         struct notifier_block freq_transition;
  74         unsigned int lcd_fck_rate;
  75 #endif
  76
  77         struct workqueue_struct *wq;
  78
  79         struct drm_fbdev_cma *fbdev;
  80
  81         struct drm_crtc *crtc;
  82
  83         unsigned int num_encoders;
  84         struct drm_encoder *encoders[8];
  85
  86         unsigned int num_connectors;
  87         struct drm_connector *connectors[8];
  88         const struct drm_connector_helper_funcs *connector_funcs[8];
  89
  90         bool is_componentized;
  91 };
  92
  93 /* Sub-module for display.  Since we don't know at compile time what panels
  94  * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
  95  * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
  96  * separate drivers.  If they are probed and found to be present, they
  97  * register themselves with tilcdc_register_module().
  98  */
  99 struct tilcdc_module;
 100
 101 struct tilcdc_module_ops {
 102         /* create appropriate encoders/connectors: */
 103         int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
 104 #ifdef CONFIG_DEBUG_FS
 105         /* create debugfs nodes (can be NULL): */
 106         int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
 107         /* cleanup debugfs nodes (can be NULL): */
 108         void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
 109 #endif
 110 };
 111
 112 struct tilcdc_module {
 113         const char *name;
 114         struct list_head list;
 115         const struct tilcdc_module_ops *funcs;
 116         unsigned int preferred_bpp;
 117 };
 118
 119 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
 120                 const struct tilcdc_module_ops *funcs);
 121 void tilcdc_module_cleanup(struct tilcdc_module *mod);
 122
 123 /* Panel config that needs to be set in the crtc, but is not coming from
 124  * the mode timings.  The display module is expected to call
 125  * tilcdc_crtc_set_panel_info() to set this during modeset.
 126  */
 127 struct tilcdc_panel_info {
 128
 129         /* AC Bias Pin Frequency */
 130         uint32_t ac_bias;
 131
 132         /* AC Bias Pin Transitions per Interrupt */
 133         uint32_t ac_bias_intrpt;
 134
 135         /* DMA burst size */
 136         uint32_t dma_burst_sz;
 137
 138         /* Bits per pixel */
 139         uint32_t bpp;
 140
 141         /* FIFO DMA Request Delay */
 142         uint32_t fdd;
 143
 144         /* TFT Alternative Signal Mapping (Only for active) */
 145         bool tft_alt_mode;
 146
 147         /* Invert pixel clock */
 148         bool invert_pxl_clk;
 149
 150         /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
 151         uint32_t sync_edge;
 152
 153         /* Horizontal and Vertical Sync: Control: 0=ignore */
 154         uint32_t sync_ctrl;
 155
 156         /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
 157         uint32_t raster_order;
 158
 159         /* DMA FIFO threshold */
 160         uint32_t fifo_th;
 161 };
 162
 163 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 164
 165 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev);
 166 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
 167 void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
 168 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 169                 const struct tilcdc_panel_info *info);
 170 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 171                                         bool simulate_vesa_sync);
 172 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
 173 int tilcdc_crtc_max_width(struct drm_crtc *crtc);
 174 void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode);
 175
 176 #endif /* __TILCDC_DRV_H__ */