2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "drm_gem_cma_helper.h"
13 struct drm_device
*dev
;
15 struct vc4_hdmi
*hdmi
;
17 struct vc4_crtc
*crtc
[3];
20 struct drm_fbdev_cma
*fbdev
;
22 struct vc4_hang_state
*hang_state
;
24 /* The kernel-space BO cache. Tracks buffers that have been
25 * unreferenced by all other users (refcounts of 0!) but not
26 * yet freed, so we can do cheap allocations.
29 /* Array of list heads for entries in the BO cache,
30 * based on number of pages, so we can do O(1) lookups
31 * in the cache when allocating.
33 struct list_head
*size_list
;
34 uint32_t size_list_size
;
36 /* List of all BOs in the cache, ordered by age, so we
37 * can do O(1) lookups when trying to free old
40 struct list_head time_list
;
41 struct work_struct time_work
;
42 struct timer_list time_timer
;
52 /* Protects bo_cache and the BO stats. */
55 /* Sequence number for the last job queued in job_list.
56 * Starts at 0 (no jobs emitted).
60 /* Sequence number for the last completed job on the GPU.
61 * Starts at 0 (no jobs completed).
63 uint64_t finished_seqno
;
65 /* List of all struct vc4_exec_info for jobs to be executed.
66 * The first job in the list is the one currently programmed
67 * into ct0ca/ct1ca for execution.
69 struct list_head job_list
;
70 /* List of the finished vc4_exec_infos waiting to be freed by
73 struct list_head job_done_list
;
74 /* Spinlock used to synchronize the job_list and seqno
75 * accesses between the IRQ handler and GEM ioctls.
78 wait_queue_head_t job_wait_queue
;
79 struct work_struct job_done_work
;
81 /* List of struct vc4_seqno_cb for callbacks to be made from a
82 * workqueue when the given seqno is passed.
84 struct list_head seqno_cb_list
;
86 /* The binner overflow memory that's currently set up in
87 * BPOA/BPOS registers. When overflow occurs and a new one is
88 * allocated, the previous one will be moved to
89 * vc4->current_exec's free list.
91 struct vc4_bo
*overflow_mem
;
92 struct work_struct overflow_mem_work
;
96 /* Mutex controlling the power refcount. */
97 struct mutex power_lock
;
100 struct timer_list timer
;
101 struct work_struct reset_work
;
104 struct semaphore async_modeset
;
107 static inline struct vc4_dev
*
108 to_vc4_dev(struct drm_device
*dev
)
110 return (struct vc4_dev
*)dev
->dev_private
;
114 struct drm_gem_cma_object base
;
116 /* seqno of the last job to render to this BO. */
119 /* List entry for the BO's position in either
120 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
122 struct list_head unref_head
;
124 /* Time in jiffies when the BO was put in vc4->bo_cache. */
125 unsigned long free_time
;
127 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
128 struct list_head size_head
;
130 /* Struct for shader validation state, if created by
131 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
133 struct vc4_validated_shader_info
*validated_shader
;
136 static inline struct vc4_bo
*
137 to_vc4_bo(struct drm_gem_object
*bo
)
139 return (struct vc4_bo
*)bo
;
142 struct vc4_seqno_cb
{
143 struct work_struct work
;
145 void (*func
)(struct vc4_seqno_cb
*cb
);
150 struct platform_device
*pdev
;
155 struct platform_device
*pdev
;
159 /* Memory manager for CRTCs to allocate space in the display
160 * list. Units are dwords.
162 struct drm_mm dlist_mm
;
163 /* Memory manager for the LBM memory used by HVS scaling. */
164 struct drm_mm lbm_mm
;
167 struct drm_mm_node mitchell_netravali_filter
;
171 struct drm_plane base
;
174 static inline struct vc4_plane
*
175 to_vc4_plane(struct drm_plane
*plane
)
177 return (struct vc4_plane
*)plane
;
180 enum vc4_encoder_type
{
181 VC4_ENCODER_TYPE_HDMI
,
182 VC4_ENCODER_TYPE_VEC
,
183 VC4_ENCODER_TYPE_DSI0
,
184 VC4_ENCODER_TYPE_DSI1
,
185 VC4_ENCODER_TYPE_SMI
,
186 VC4_ENCODER_TYPE_DPI
,
190 struct drm_encoder base
;
191 enum vc4_encoder_type type
;
195 static inline struct vc4_encoder
*
196 to_vc4_encoder(struct drm_encoder
*encoder
)
198 return container_of(encoder
, struct vc4_encoder
, base
);
201 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
202 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
203 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
204 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
206 struct vc4_exec_info
{
207 /* Sequence number for this bin/render job. */
210 /* Last current addresses the hardware was processing when the
211 * hangcheck timer checked on us.
213 uint32_t last_ct0ca
, last_ct1ca
;
215 /* Kernel-space copy of the ioctl arguments */
216 struct drm_vc4_submit_cl
*args
;
218 /* This is the array of BOs that were looked up at the start of exec.
219 * Command validation will use indices into this array.
221 struct drm_gem_cma_object
**bo
;
224 /* Pointers for our position in vc4->job_list */
225 struct list_head head
;
227 /* List of other BOs used in the job that need to be released
228 * once the job is complete.
230 struct list_head unref_list
;
232 /* Current unvalidated indices into @bo loaded by the non-hardware
233 * VC4_PACKET_GEM_HANDLES.
235 uint32_t bo_index
[2];
237 /* This is the BO where we store the validated command lists, shader
238 * records, and uniforms.
240 struct drm_gem_cma_object
*exec_bo
;
243 * This tracks the per-shader-record state (packet 64) that
244 * determines the length of the shader record and the offset
245 * it's expected to be found at. It gets read in from the
248 struct vc4_shader_state
{
250 /* Maximum vertex index referenced by any primitive using this
256 /** How many shader states the user declared they were using. */
257 uint32_t shader_state_size
;
258 /** How many shader state records the validator has seen. */
259 uint32_t shader_state_count
;
261 bool found_tile_binning_mode_config_packet
;
262 bool found_start_tile_binning_packet
;
263 bool found_increment_semaphore_packet
;
265 uint8_t bin_tiles_x
, bin_tiles_y
;
266 struct drm_gem_cma_object
*tile_bo
;
267 uint32_t tile_alloc_offset
;
270 * Computed addresses pointing into exec_bo where we start the
271 * bin thread (ct0) and render thread (ct1).
273 uint32_t ct0ca
, ct0ea
;
274 uint32_t ct1ca
, ct1ea
;
276 /* Pointer to the unvalidated bin CL (if present). */
279 /* Pointers to the shader recs. These paddr gets incremented as CL
280 * packets are relocated in validate_gl_shader_state, and the vaddrs
281 * (u and v) get incremented and size decremented as the shader recs
282 * themselves are validated.
286 uint32_t shader_rec_p
;
287 uint32_t shader_rec_size
;
289 /* Pointers to the uniform data. These pointers are incremented, and
290 * size decremented, as each batch of uniforms is uploaded.
295 uint32_t uniforms_size
;
298 static inline struct vc4_exec_info
*
299 vc4_first_job(struct vc4_dev
*vc4
)
301 if (list_empty(&vc4
->job_list
))
303 return list_first_entry(&vc4
->job_list
, struct vc4_exec_info
, head
);
307 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
310 * This will be used at draw time to relocate the reference to the texture
311 * contents in p0, and validate that the offset combined with
312 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
313 * Note that the hardware treats unprovided config parameters as 0, so not all
314 * of them need to be set up for every texure sample, and we'll store ~0 as
315 * the offset to mark the unused ones.
317 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
318 * Setup") for definitions of the texture parameters.
320 struct vc4_texture_sample_info
{
322 uint32_t p_offset
[4];
326 * struct vc4_validated_shader_info - information about validated shaders that
327 * needs to be used from command list validation.
329 * For a given shader, each time a shader state record references it, we need
330 * to verify that the shader doesn't read more uniforms than the shader state
331 * record's uniform BO pointer can provide, and we need to apply relocations
332 * and validate the shader state record's uniforms that define the texture
335 struct vc4_validated_shader_info
{
336 uint32_t uniforms_size
;
337 uint32_t uniforms_src_size
;
338 uint32_t num_texture_samples
;
339 struct vc4_texture_sample_info
*texture_samples
;
343 * _wait_for - magic (register) wait macro
345 * Does the right thing for modeset paths when run under kdgb or similar atomic
346 * contexts. Note that it's important that we check the condition again after
347 * having timed out, since the timeout could be due to preemption or similar and
348 * we've never had a chance to check the condition before the timeout.
350 #define _wait_for(COND, MS, W) ({ \
351 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
354 if (time_after(jiffies, timeout__)) { \
356 ret__ = -ETIMEDOUT; \
359 if (W && drm_can_sleep()) { \
368 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
371 struct drm_gem_object
*vc4_create_object(struct drm_device
*dev
, size_t size
);
372 void vc4_free_object(struct drm_gem_object
*gem_obj
);
373 struct vc4_bo
*vc4_bo_create(struct drm_device
*dev
, size_t size
,
375 int vc4_dumb_create(struct drm_file
*file_priv
,
376 struct drm_device
*dev
,
377 struct drm_mode_create_dumb
*args
);
378 struct dma_buf
*vc4_prime_export(struct drm_device
*dev
,
379 struct drm_gem_object
*obj
, int flags
);
380 int vc4_create_bo_ioctl(struct drm_device
*dev
, void *data
,
381 struct drm_file
*file_priv
);
382 int vc4_create_shader_bo_ioctl(struct drm_device
*dev
, void *data
,
383 struct drm_file
*file_priv
);
384 int vc4_mmap_bo_ioctl(struct drm_device
*dev
, void *data
,
385 struct drm_file
*file_priv
);
386 int vc4_get_hang_state_ioctl(struct drm_device
*dev
, void *data
,
387 struct drm_file
*file_priv
);
388 int vc4_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
389 int vc4_prime_mmap(struct drm_gem_object
*obj
, struct vm_area_struct
*vma
);
390 void *vc4_prime_vmap(struct drm_gem_object
*obj
);
391 void vc4_bo_cache_init(struct drm_device
*dev
);
392 void vc4_bo_cache_destroy(struct drm_device
*dev
);
393 int vc4_bo_stats_debugfs(struct seq_file
*m
, void *arg
);
396 extern struct platform_driver vc4_crtc_driver
;
397 int vc4_enable_vblank(struct drm_device
*dev
, unsigned int crtc_id
);
398 void vc4_disable_vblank(struct drm_device
*dev
, unsigned int crtc_id
);
399 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *arg
);
402 int vc4_debugfs_init(struct drm_minor
*minor
);
403 void vc4_debugfs_cleanup(struct drm_minor
*minor
);
406 void __iomem
*vc4_ioremap_regs(struct platform_device
*dev
, int index
);
409 void vc4_gem_init(struct drm_device
*dev
);
410 void vc4_gem_destroy(struct drm_device
*dev
);
411 int vc4_submit_cl_ioctl(struct drm_device
*dev
, void *data
,
412 struct drm_file
*file_priv
);
413 int vc4_wait_seqno_ioctl(struct drm_device
*dev
, void *data
,
414 struct drm_file
*file_priv
);
415 int vc4_wait_bo_ioctl(struct drm_device
*dev
, void *data
,
416 struct drm_file
*file_priv
);
417 void vc4_submit_next_job(struct drm_device
*dev
);
418 int vc4_wait_for_seqno(struct drm_device
*dev
, uint64_t seqno
,
419 uint64_t timeout_ns
, bool interruptible
);
420 void vc4_job_handle_completed(struct vc4_dev
*vc4
);
421 int vc4_queue_seqno_cb(struct drm_device
*dev
,
422 struct vc4_seqno_cb
*cb
, uint64_t seqno
,
423 void (*func
)(struct vc4_seqno_cb
*cb
));
426 extern struct platform_driver vc4_hdmi_driver
;
427 int vc4_hdmi_debugfs_regs(struct seq_file
*m
, void *unused
);
430 irqreturn_t
vc4_irq(int irq
, void *arg
);
431 void vc4_irq_preinstall(struct drm_device
*dev
);
432 int vc4_irq_postinstall(struct drm_device
*dev
);
433 void vc4_irq_uninstall(struct drm_device
*dev
);
434 void vc4_irq_reset(struct drm_device
*dev
);
437 extern struct platform_driver vc4_hvs_driver
;
438 void vc4_hvs_dump_state(struct drm_device
*dev
);
439 int vc4_hvs_debugfs_regs(struct seq_file
*m
, void *unused
);
442 int vc4_kms_load(struct drm_device
*dev
);
445 struct drm_plane
*vc4_plane_init(struct drm_device
*dev
,
446 enum drm_plane_type type
);
447 u32
vc4_plane_write_dlist(struct drm_plane
*plane
, u32 __iomem
*dlist
);
448 u32
vc4_plane_dlist_size(struct drm_plane_state
*state
);
449 void vc4_plane_async_set_fb(struct drm_plane
*plane
,
450 struct drm_framebuffer
*fb
);
453 extern struct platform_driver vc4_v3d_driver
;
454 int vc4_v3d_debugfs_ident(struct seq_file
*m
, void *unused
);
455 int vc4_v3d_debugfs_regs(struct seq_file
*m
, void *unused
);
459 vc4_validate_bin_cl(struct drm_device
*dev
,
462 struct vc4_exec_info
*exec
);
465 vc4_validate_shader_recs(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
467 struct drm_gem_cma_object
*vc4_use_bo(struct vc4_exec_info
*exec
,
470 int vc4_get_rcl(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
472 bool vc4_check_tex_size(struct vc4_exec_info
*exec
,
473 struct drm_gem_cma_object
*fbo
,
474 uint32_t offset
, uint8_t tiling_format
,
475 uint32_t width
, uint32_t height
, uint8_t cpp
);
477 /* vc4_validate_shader.c */
478 struct vc4_validated_shader_info
*
479 vc4_validate_shader(struct drm_gem_cma_object
*shader_obj
);