drivers/gpu/ipu-v3/ipu-csi.c

   1 /*
   2  * Copyright (C) 2012-2014 Mentor Graphics Inc.
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/export.h>
  16 #include <linux/module.h>
  17 #include <linux/types.h>
  18 #include <linux/errno.h>
  19 #include <linux/delay.h>
  20 #include <linux/io.h>
  21 #include <linux/err.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/videodev2.h>
  24 #include <uapi/linux/v4l2-mediabus.h>
  25 #include <linux/clk.h>
  26 #include <linux/clk-provider.h>
  27 #include <linux/clkdev.h>
  28
  29 #include "ipu-prv.h"
  30
  31 struct ipu_csi {
  32         void __iomem *base;
  33         int id;
  34         u32 module;
  35         struct clk *clk_ipu;    /* IPU bus clock */
  36         spinlock_t lock;
  37         bool inuse;
  38         struct ipu_soc *ipu;
  39 };
  40
  41 /* CSI Register Offsets */
  42 #define CSI_SENS_CONF           0x0000
  43 #define CSI_SENS_FRM_SIZE       0x0004
  44 #define CSI_ACT_FRM_SIZE        0x0008
  45 #define CSI_OUT_FRM_CTRL        0x000c
  46 #define CSI_TST_CTRL            0x0010
  47 #define CSI_CCIR_CODE_1         0x0014
  48 #define CSI_CCIR_CODE_2         0x0018
  49 #define CSI_CCIR_CODE_3         0x001c
  50 #define CSI_MIPI_DI             0x0020
  51 #define CSI_SKIP                0x0024
  52 #define CSI_CPD_CTRL            0x0028
  53 #define CSI_CPD_RC(n)           (0x002c + ((n)*4))
  54 #define CSI_CPD_RS(n)           (0x004c + ((n)*4))
  55 #define CSI_CPD_GRC(n)          (0x005c + ((n)*4))
  56 #define CSI_CPD_GRS(n)          (0x007c + ((n)*4))
  57 #define CSI_CPD_GBC(n)          (0x008c + ((n)*4))
  58 #define CSI_CPD_GBS(n)          (0x00Ac + ((n)*4))
  59 #define CSI_CPD_BC(n)           (0x00Bc + ((n)*4))
  60 #define CSI_CPD_BS(n)           (0x00Dc + ((n)*4))
  61 #define CSI_CPD_OFFSET1         0x00ec
  62 #define CSI_CPD_OFFSET2         0x00f0
  63
  64 /* CSI Register Fields */
  65 #define CSI_SENS_CONF_DATA_FMT_SHIFT            8
  66 #define CSI_SENS_CONF_DATA_FMT_MASK             0x00000700
  67 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444       0L
  68 #define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV      1L
  69 #define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY      2L
  70 #define CSI_SENS_CONF_DATA_FMT_BAYER            3L
  71 #define CSI_SENS_CONF_DATA_FMT_RGB565           4L
  72 #define CSI_SENS_CONF_DATA_FMT_RGB555           5L
  73 #define CSI_SENS_CONF_DATA_FMT_RGB444           6L
  74 #define CSI_SENS_CONF_DATA_FMT_JPEG             7L
  75
  76 #define CSI_SENS_CONF_VSYNC_POL_SHIFT           0
  77 #define CSI_SENS_CONF_HSYNC_POL_SHIFT           1
  78 #define CSI_SENS_CONF_DATA_POL_SHIFT            2
  79 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT         3
  80 #define CSI_SENS_CONF_SENS_PRTCL_MASK           0x00000070
  81 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT          4
  82 #define CSI_SENS_CONF_PACK_TIGHT_SHIFT          7
  83 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT          11
  84 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT           15
  85 #define CSI_SENS_CONF_DIVRATIO_SHIFT            16
  86
  87 #define CSI_SENS_CONF_DIVRATIO_MASK             0x00ff0000
  88 #define CSI_SENS_CONF_DATA_DEST_SHIFT           24
  89 #define CSI_SENS_CONF_DATA_DEST_MASK            0x07000000
  90 #define CSI_SENS_CONF_JPEG8_EN_SHIFT            27
  91 #define CSI_SENS_CONF_JPEG_EN_SHIFT             28
  92 #define CSI_SENS_CONF_FORCE_EOF_SHIFT           29
  93 #define CSI_SENS_CONF_DATA_EN_POL_SHIFT         31
  94
  95 #define CSI_DATA_DEST_IC                        2
  96 #define CSI_DATA_DEST_IDMAC                     4
  97
  98 #define CSI_CCIR_ERR_DET_EN                     0x01000000
  99 #define CSI_HORI_DOWNSIZE_EN                    0x80000000
 100 #define CSI_VERT_DOWNSIZE_EN                    0x40000000
 101 #define CSI_TEST_GEN_MODE_EN                    0x01000000
 102
 103 #define CSI_HSC_MASK                            0x1fff0000
 104 #define CSI_HSC_SHIFT                           16
 105 #define CSI_VSC_MASK                            0x00000fff
 106 #define CSI_VSC_SHIFT                           0
 107
 108 #define CSI_TEST_GEN_R_MASK                     0x000000ff
 109 #define CSI_TEST_GEN_R_SHIFT                    0
 110 #define CSI_TEST_GEN_G_MASK                     0x0000ff00
 111 #define CSI_TEST_GEN_G_SHIFT                    8
 112 #define CSI_TEST_GEN_B_MASK                     0x00ff0000
 113 #define CSI_TEST_GEN_B_SHIFT                    16
 114
 115 #define CSI_MAX_RATIO_SKIP_SMFC_MASK            0x00000007
 116 #define CSI_MAX_RATIO_SKIP_SMFC_SHIFT           0
 117 #define CSI_SKIP_SMFC_MASK                      0x000000f8
 118 #define CSI_SKIP_SMFC_SHIFT                     3
 119 #define CSI_ID_2_SKIP_MASK                      0x00000300
 120 #define CSI_ID_2_SKIP_SHIFT                     8
 121
 122 #define CSI_COLOR_FIRST_ROW_MASK                0x00000002
 123 #define CSI_COLOR_FIRST_COMP_MASK               0x00000001
 124
 125 /* MIPI CSI-2 data types */
 126 #define MIPI_DT_YUV420          0x18 /* YYY.../UYVY.... */
 127 #define MIPI_DT_YUV420_LEGACY   0x1a /* UYY.../VYY...   */
 128 #define MIPI_DT_YUV422          0x1e /* UYVY...         */
 129 #define MIPI_DT_RGB444          0x20
 130 #define MIPI_DT_RGB555          0x21
 131 #define MIPI_DT_RGB565          0x22
 132 #define MIPI_DT_RGB666          0x23
 133 #define MIPI_DT_RGB888          0x24
 134 #define MIPI_DT_RAW6            0x28
 135 #define MIPI_DT_RAW7            0x29
 136 #define MIPI_DT_RAW8            0x2a
 137 #define MIPI_DT_RAW10           0x2b
 138 #define MIPI_DT_RAW12           0x2c
 139 #define MIPI_DT_RAW14           0x2d
 140
 141 /*
 142  * Bitfield of CSI bus signal polarities and modes.
 143  */
 144 struct ipu_csi_bus_config {
 145         unsigned data_width:4;
 146         unsigned clk_mode:3;
 147         unsigned ext_vsync:1;
 148         unsigned vsync_pol:1;
 149         unsigned hsync_pol:1;
 150         unsigned pixclk_pol:1;
 151         unsigned data_pol:1;
 152         unsigned sens_clksrc:1;
 153         unsigned pack_tight:1;
 154         unsigned force_eof:1;
 155         unsigned data_en_pol:1;
 156
 157         unsigned data_fmt;
 158         unsigned mipi_dt;
 159 };
 160
 161 /*
 162  * Enumeration of CSI data bus widths.
 163  */
 164 enum ipu_csi_data_width {
 165         IPU_CSI_DATA_WIDTH_4   = 0,
 166         IPU_CSI_DATA_WIDTH_8   = 1,
 167         IPU_CSI_DATA_WIDTH_10  = 3,
 168         IPU_CSI_DATA_WIDTH_12  = 5,
 169         IPU_CSI_DATA_WIDTH_16  = 9,
 170 };
 171
 172 /*
 173  * Enumeration of CSI clock modes.
 174  */
 175 enum ipu_csi_clk_mode {
 176         IPU_CSI_CLK_MODE_GATED_CLK,
 177         IPU_CSI_CLK_MODE_NONGATED_CLK,
 178         IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
 179         IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
 180         IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
 181         IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
 182         IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
 183         IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
 184 };
 185
 186 static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
 187 {
 188         return readl(csi->base + offset);
 189 }
 190
 191 static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
 192                                  unsigned offset)
 193 {
 194         writel(value, csi->base + offset);
 195 }
 196
 197 /*
 198  * Set mclk division ratio for generating test mode mclk. Only used
 199  * for test generator.
 200  */
 201 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
 202                                         u32 ipu_clk)
 203 {
 204         u32 temp;
 205         int div_ratio;
 206
 207         div_ratio = (ipu_clk / pixel_clk) - 1;
 208
 209         if (div_ratio > 0xFF || div_ratio < 0) {
 210                 dev_err(csi->ipu->dev,
 211                         "value of pixel_clk extends normal range\n");
 212                 return -EINVAL;
 213         }
 214
 215         temp = ipu_csi_read(csi, CSI_SENS_CONF);
 216         temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
 217         ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
 218                           CSI_SENS_CONF);
 219
 220         return 0;
 221 }
 222
 223 /*
 224  * Find the CSI data format and data width for the given V4L2 media
 225  * bus pixel format code.
 226  */
 227 static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
 228 {
 229         switch (mbus_code) {
 230         case MEDIA_BUS_FMT_BGR565_2X8_BE:
 231         case MEDIA_BUS_FMT_BGR565_2X8_LE:
 232         case MEDIA_BUS_FMT_RGB565_2X8_BE:
 233         case MEDIA_BUS_FMT_RGB565_2X8_LE:
 234                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
 235                 cfg->mipi_dt = MIPI_DT_RGB565;
 236                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 237                 break;
 238         case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
 239         case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
 240                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
 241                 cfg->mipi_dt = MIPI_DT_RGB444;
 242                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 243                 break;
 244         case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
 245         case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
 246                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
 247                 cfg->mipi_dt = MIPI_DT_RGB555;
 248                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 249                 break;
 250         case MEDIA_BUS_FMT_UYVY8_2X8:
 251                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
 252                 cfg->mipi_dt = MIPI_DT_YUV422;
 253                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 254                 break;
 255         case MEDIA_BUS_FMT_YUYV8_2X8:
 256                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
 257                 cfg->mipi_dt = MIPI_DT_YUV422;
 258                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 259                 break;
 260         case MEDIA_BUS_FMT_UYVY8_1X16:
 261         case MEDIA_BUS_FMT_YUYV8_1X16:
 262                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
 263                 cfg->mipi_dt = MIPI_DT_YUV422;
 264                 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
 265                 break;
 266         case MEDIA_BUS_FMT_SBGGR8_1X8:
 267         case MEDIA_BUS_FMT_SGBRG8_1X8:
 268         case MEDIA_BUS_FMT_SGRBG8_1X8:
 269         case MEDIA_BUS_FMT_SRGGB8_1X8:
 270         case MEDIA_BUS_FMT_Y8_1X8:
 271                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
 272                 cfg->mipi_dt = MIPI_DT_RAW8;
 273                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 274                 break;
 275         case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
 276         case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
 277         case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
 278         case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
 279         case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
 280         case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
 281         case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
 282         case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
 283                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
 284                 cfg->mipi_dt = MIPI_DT_RAW10;
 285                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 286                 break;
 287         case MEDIA_BUS_FMT_SBGGR10_1X10:
 288         case MEDIA_BUS_FMT_SGBRG10_1X10:
 289         case MEDIA_BUS_FMT_SGRBG10_1X10:
 290         case MEDIA_BUS_FMT_SRGGB10_1X10:
 291                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
 292                 cfg->mipi_dt = MIPI_DT_RAW10;
 293                 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
 294                 break;
 295         case MEDIA_BUS_FMT_SBGGR12_1X12:
 296         case MEDIA_BUS_FMT_SGBRG12_1X12:
 297         case MEDIA_BUS_FMT_SGRBG12_1X12:
 298         case MEDIA_BUS_FMT_SRGGB12_1X12:
 299                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
 300                 cfg->mipi_dt = MIPI_DT_RAW12;
 301                 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
 302                 break;
 303         case MEDIA_BUS_FMT_JPEG_1X8:
 304                 /* TODO */
 305                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
 306                 cfg->mipi_dt = MIPI_DT_RAW8;
 307                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
 308                 break;
 309         default:
 310                 return -EINVAL;
 311         }
 312
 313         return 0;
 314 }
 315
 316 /*
 317  * Fill a CSI bus config struct from mbus_config and mbus_framefmt.
 318  */
 319 static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
 320                                  struct v4l2_mbus_config *mbus_cfg,
 321                                  struct v4l2_mbus_framefmt *mbus_fmt)
 322 {
 323         memset(csicfg, 0, sizeof(*csicfg));
 324
 325         mbus_code_to_bus_cfg(csicfg, mbus_fmt->code);
 326
 327         switch (mbus_cfg->type) {
 328         case V4L2_MBUS_PARALLEL:
 329                 csicfg->ext_vsync = 1;
 330                 csicfg->vsync_pol = (mbus_cfg->flags &
 331                                      V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
 332                 csicfg->hsync_pol = (mbus_cfg->flags &
 333                                      V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
 334                 csicfg->pixclk_pol = (mbus_cfg->flags &
 335                                       V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
 336                 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
 337                 break;
 338         case V4L2_MBUS_BT656:
 339                 csicfg->ext_vsync = 0;
 340                 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field))
 341                         csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
 342                 else
 343                         csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
 344                 break;
 345         case V4L2_MBUS_CSI2:
 346                 /*
 347                  * MIPI CSI-2 requires non gated clock mode, all other
 348                  * parameters are not applicable for MIPI CSI-2 bus.
 349                  */
 350                 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
 351                 break;
 352         default:
 353                 /* will never get here, keep compiler quiet */
 354                 break;
 355         }
 356 }
 357
 358 int ipu_csi_init_interface(struct ipu_csi *csi,
 359                            struct v4l2_mbus_config *mbus_cfg,
 360                            struct v4l2_mbus_framefmt *mbus_fmt)
 361 {
 362         struct ipu_csi_bus_config cfg;
 363         unsigned long flags;
 364         u32 width, height, data = 0;
 365
 366         fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt);
 367
 368         /* set default sensor frame width and height */
 369         width = mbus_fmt->width;
 370         height = mbus_fmt->height;
 371
 372         /* Set the CSI_SENS_CONF register remaining fields */
 373         data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
 374                 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
 375                 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
 376                 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
 377                 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
 378                 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
 379                 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
 380                 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
 381                 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
 382                 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
 383                 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
 384
 385         spin_lock_irqsave(&csi->lock, flags);
 386
 387         ipu_csi_write(csi, data, CSI_SENS_CONF);
 388
 389         /* Set CCIR registers */
 390
 391         switch (cfg.clk_mode) {
 392         case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
 393                 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
 394                 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
 395                 break;
 396         case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
 397                 if (mbus_fmt->width == 720 && mbus_fmt->height == 576) {
 398                         /*
 399                          * PAL case
 400                          *
 401                          * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
 402                          * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
 403                          * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
 404                          * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
 405                          */
 406                         height = 625; /* framelines for PAL */
 407
 408                         ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
 409                                           CSI_CCIR_CODE_1);
 410                         ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
 411                         ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
 412                 } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) {
 413                         /*
 414                          * NTSC case
 415                          *
 416                          * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
 417                          * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
 418                          * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
 419                          * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
 420                          */
 421                         height = 525; /* framelines for NTSC */
 422
 423                         ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
 424                                           CSI_CCIR_CODE_1);
 425                         ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
 426                         ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
 427                 } else {
 428                         dev_err(csi->ipu->dev,
 429                                 "Unsupported CCIR656 interlaced video mode\n");
 430                         spin_unlock_irqrestore(&csi->lock, flags);
 431                         return -EINVAL;
 432                 }
 433                 break;
 434         case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
 435         case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
 436         case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
 437         case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
 438                 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
 439                                    CSI_CCIR_CODE_1);
 440                 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
 441                 break;
 442         case IPU_CSI_CLK_MODE_GATED_CLK:
 443         case IPU_CSI_CLK_MODE_NONGATED_CLK:
 444                 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
 445                 break;
 446         }
 447
 448         /* Setup sensor frame size */
 449         ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
 450                       CSI_SENS_FRM_SIZE);
 451
 452         dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
 453                 ipu_csi_read(csi, CSI_SENS_CONF));
 454         dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
 455                 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
 456
 457         spin_unlock_irqrestore(&csi->lock, flags);
 458
 459         return 0;
 460 }
 461 EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
 462
 463 bool ipu_csi_is_interlaced(struct ipu_csi *csi)
 464 {
 465         unsigned long flags;
 466         u32 sensor_protocol;
 467
 468         spin_lock_irqsave(&csi->lock, flags);
 469         sensor_protocol =
 470                 (ipu_csi_read(csi, CSI_SENS_CONF) &
 471                  CSI_SENS_CONF_SENS_PRTCL_MASK) >>
 472                 CSI_SENS_CONF_SENS_PRTCL_SHIFT;
 473         spin_unlock_irqrestore(&csi->lock, flags);
 474
 475         switch (sensor_protocol) {
 476         case IPU_CSI_CLK_MODE_GATED_CLK:
 477         case IPU_CSI_CLK_MODE_NONGATED_CLK:
 478         case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
 479         case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
 480         case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
 481                 return false;
 482         case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
 483         case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
 484         case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
 485                 return true;
 486         default:
 487                 dev_err(csi->ipu->dev,
 488                         "CSI %d sensor protocol unsupported\n", csi->id);
 489                 return false;
 490         }
 491 }
 492 EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
 493
 494 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
 495 {
 496         unsigned long flags;
 497         u32 reg;
 498
 499         spin_lock_irqsave(&csi->lock, flags);
 500
 501         reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
 502         w->width = (reg & 0xFFFF) + 1;
 503         w->height = (reg >> 16 & 0xFFFF) + 1;
 504
 505         reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
 506         w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
 507         w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
 508
 509         spin_unlock_irqrestore(&csi->lock, flags);
 510 }
 511 EXPORT_SYMBOL_GPL(ipu_csi_get_window);
 512
 513 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
 514 {
 515         unsigned long flags;
 516         u32 reg;
 517
 518         spin_lock_irqsave(&csi->lock, flags);
 519
 520         ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
 521                           CSI_ACT_FRM_SIZE);
 522
 523         reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
 524         reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
 525         reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
 526         ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
 527
 528         spin_unlock_irqrestore(&csi->lock, flags);
 529 }
 530 EXPORT_SYMBOL_GPL(ipu_csi_set_window);
 531
 532 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
 533                                 u32 r_value, u32 g_value, u32 b_value,
 534                                 u32 pix_clk)
 535 {
 536         unsigned long flags;
 537         u32 ipu_clk = clk_get_rate(csi->clk_ipu);
 538         u32 temp;
 539
 540         spin_lock_irqsave(&csi->lock, flags);
 541
 542         temp = ipu_csi_read(csi, CSI_TST_CTRL);
 543
 544         if (!active) {
 545                 temp &= ~CSI_TEST_GEN_MODE_EN;
 546                 ipu_csi_write(csi, temp, CSI_TST_CTRL);
 547         } else {
 548                 /* Set sensb_mclk div_ratio */
 549                 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
 550
 551                 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
 552                           CSI_TEST_GEN_B_MASK);
 553                 temp |= CSI_TEST_GEN_MODE_EN;
 554                 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
 555                         (g_value << CSI_TEST_GEN_G_SHIFT) |
 556                         (b_value << CSI_TEST_GEN_B_SHIFT);
 557                 ipu_csi_write(csi, temp, CSI_TST_CTRL);
 558         }
 559
 560         spin_unlock_irqrestore(&csi->lock, flags);
 561 }
 562 EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
 563
 564 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
 565                               struct v4l2_mbus_framefmt *mbus_fmt)
 566 {
 567         struct ipu_csi_bus_config cfg;
 568         unsigned long flags;
 569         u32 temp;
 570
 571         if (vc > 3)
 572                 return -EINVAL;
 573
 574         mbus_code_to_bus_cfg(&cfg, mbus_fmt->code);
 575
 576         spin_lock_irqsave(&csi->lock, flags);
 577
 578         temp = ipu_csi_read(csi, CSI_MIPI_DI);
 579         temp &= ~(0xff << (vc * 8));
 580         temp |= (cfg.mipi_dt << (vc * 8));
 581         ipu_csi_write(csi, temp, CSI_MIPI_DI);
 582
 583         spin_unlock_irqrestore(&csi->lock, flags);
 584
 585         return 0;
 586 }
 587 EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
 588
 589 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
 590                           u32 max_ratio, u32 id)
 591 {
 592         unsigned long flags;
 593         u32 temp;
 594
 595         if (max_ratio > 5 || id > 3)
 596                 return -EINVAL;
 597
 598         spin_lock_irqsave(&csi->lock, flags);
 599
 600         temp = ipu_csi_read(csi, CSI_SKIP);
 601         temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
 602                   CSI_SKIP_SMFC_MASK);
 603         temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
 604                 (id << CSI_ID_2_SKIP_SHIFT) |
 605                 (skip << CSI_SKIP_SMFC_SHIFT);
 606         ipu_csi_write(csi, temp, CSI_SKIP);
 607
 608         spin_unlock_irqrestore(&csi->lock, flags);
 609
 610         return 0;
 611 }
 612 EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
 613
 614 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
 615 {
 616         unsigned long flags;
 617         u32 csi_sens_conf, dest;
 618
 619         if (csi_dest == IPU_CSI_DEST_IDMAC)
 620                 dest = CSI_DATA_DEST_IDMAC;
 621         else
 622                 dest = CSI_DATA_DEST_IC; /* IC or VDIC */
 623
 624         spin_lock_irqsave(&csi->lock, flags);
 625
 626         csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
 627         csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
 628         csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
 629         ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
 630
 631         spin_unlock_irqrestore(&csi->lock, flags);
 632
 633         return 0;
 634 }
 635 EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
 636
 637 int ipu_csi_enable(struct ipu_csi *csi)
 638 {
 639         ipu_module_enable(csi->ipu, csi->module);
 640
 641         return 0;
 642 }
 643 EXPORT_SYMBOL_GPL(ipu_csi_enable);
 644
 645 int ipu_csi_disable(struct ipu_csi *csi)
 646 {
 647         ipu_module_disable(csi->ipu, csi->module);
 648
 649         return 0;
 650 }
 651 EXPORT_SYMBOL_GPL(ipu_csi_disable);
 652
 653 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
 654 {
 655         unsigned long flags;
 656         struct ipu_csi *csi, *ret;
 657
 658         if (id > 1)
 659                 return ERR_PTR(-EINVAL);
 660
 661         csi = ipu->csi_priv[id];
 662         ret = csi;
 663
 664         spin_lock_irqsave(&csi->lock, flags);
 665
 666         if (csi->inuse) {
 667                 ret = ERR_PTR(-EBUSY);
 668                 goto unlock;
 669         }
 670
 671         csi->inuse = true;
 672 unlock:
 673         spin_unlock_irqrestore(&csi->lock, flags);
 674         return ret;
 675 }
 676 EXPORT_SYMBOL_GPL(ipu_csi_get);
 677
 678 void ipu_csi_put(struct ipu_csi *csi)
 679 {
 680         unsigned long flags;
 681
 682         spin_lock_irqsave(&csi->lock, flags);
 683         csi->inuse = false;
 684         spin_unlock_irqrestore(&csi->lock, flags);
 685 }
 686 EXPORT_SYMBOL_GPL(ipu_csi_put);
 687
 688 int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
 689                  unsigned long base, u32 module, struct clk *clk_ipu)
 690 {
 691         struct ipu_csi *csi;
 692
 693         if (id > 1)
 694                 return -ENODEV;
 695
 696         csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
 697         if (!csi)
 698                 return -ENOMEM;
 699
 700         ipu->csi_priv[id] = csi;
 701
 702         spin_lock_init(&csi->lock);
 703         csi->module = module;
 704         csi->id = id;
 705         csi->clk_ipu = clk_ipu;
 706         csi->base = devm_ioremap(dev, base, PAGE_SIZE);
 707         if (!csi->base)
 708                 return -ENOMEM;
 709
 710         dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
 711                 id, base, csi->base);
 712         csi->ipu = ipu;
 713
 714         return 0;
 715 }
 716
 717 void ipu_csi_exit(struct ipu_soc *ipu, int id)
 718 {
 719 }
 720
 721 void ipu_csi_dump(struct ipu_csi *csi)
 722 {
 723         dev_dbg(csi->ipu->dev, "CSI_SENS_CONF:     %08x\n",
 724                 ipu_csi_read(csi, CSI_SENS_CONF));
 725         dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
 726                 ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
 727         dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE:  %08x\n",
 728                 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
 729         dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL:  %08x\n",
 730                 ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
 731         dev_dbg(csi->ipu->dev, "CSI_TST_CTRL:      %08x\n",
 732                 ipu_csi_read(csi, CSI_TST_CTRL));
 733         dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1:   %08x\n",
 734                 ipu_csi_read(csi, CSI_CCIR_CODE_1));
 735         dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2:   %08x\n",
 736                 ipu_csi_read(csi, CSI_CCIR_CODE_2));
 737         dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3:   %08x\n",
 738                 ipu_csi_read(csi, CSI_CCIR_CODE_3));
 739         dev_dbg(csi->ipu->dev, "CSI_MIPI_DI:       %08x\n",
 740                 ipu_csi_read(csi, CSI_MIPI_DI));
 741         dev_dbg(csi->ipu->dev, "CSI_SKIP:          %08x\n",
 742                 ipu_csi_read(csi, CSI_SKIP));
 743 }
 744 EXPORT_SYMBOL_GPL(ipu_csi_dump);