Merge remote-tracking branch 'battery/for-next'
[deliverable/linux.git] / drivers / i2c / busses / i2c-designware-core.h
1 /*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
22 *
23 */
24
25
26 #define DW_IC_CON_MASTER 0x1
27 #define DW_IC_CON_SPEED_STD 0x2
28 #define DW_IC_CON_SPEED_FAST 0x4
29 #define DW_IC_CON_SPEED_HIGH 0x6
30 #define DW_IC_CON_SPEED_MASK 0x6
31 #define DW_IC_CON_10BITADDR_MASTER 0x10
32 #define DW_IC_CON_RESTART_EN 0x20
33 #define DW_IC_CON_SLAVE_DISABLE 0x40
34
35
36 /**
37 * struct dw_i2c_dev - private i2c-designware data
38 * @dev: driver model device node
39 * @base: IO registers pointer
40 * @cmd_complete: tx completion indicator
41 * @clk: input reference clock
42 * @cmd_err: run time hadware error code
43 * @msgs: points to an array of messages currently being transfered
44 * @msgs_num: the number of elements in msgs
45 * @msg_write_idx: the element index of the current tx message in the msgs
46 * array
47 * @tx_buf_len: the length of the current tx buffer
48 * @tx_buf: the current tx buffer
49 * @msg_read_idx: the element index of the current rx message in the msgs
50 * array
51 * @rx_buf_len: the length of the current rx buffer
52 * @rx_buf: the current rx buffer
53 * @msg_err: error status of the current transfer
54 * @status: i2c master status, one of STATUS_*
55 * @abort_source: copy of the TX_ABRT_SOURCE register
56 * @irq: interrupt number for the i2c master
57 * @adapter: i2c subsystem adapter node
58 * @tx_fifo_depth: depth of the hardware tx fifo
59 * @rx_fifo_depth: depth of the hardware rx fifo
60 * @rx_outstanding: current master-rx elements in tx fifo
61 * @clk_freq: bus clock frequency
62 * @ss_hcnt: standard speed HCNT value
63 * @ss_lcnt: standard speed LCNT value
64 * @fs_hcnt: fast speed HCNT value
65 * @fs_lcnt: fast speed LCNT value
66 * @fp_hcnt: fast plus HCNT value
67 * @fp_lcnt: fast plus LCNT value
68 * @hs_hcnt: high speed HCNT value
69 * @hs_lcnt: high speed LCNT value
70 * @acquire_lock: function to acquire a hardware lock on the bus
71 * @release_lock: function to release a hardware lock on the bus
72 * @pm_runtime_disabled: true if pm runtime is disabled
73 *
74 * HCNT and LCNT parameters can be used if the platform knows more accurate
75 * values than the one computed based only on the input clock frequency.
76 * Leave them to be %0 if not used.
77 */
78 struct dw_i2c_dev {
79 struct device *dev;
80 void __iomem *base;
81 struct completion cmd_complete;
82 struct clk *clk;
83 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
84 struct dw_pci_controller *controller;
85 int cmd_err;
86 struct i2c_msg *msgs;
87 int msgs_num;
88 int msg_write_idx;
89 u32 tx_buf_len;
90 u8 *tx_buf;
91 int msg_read_idx;
92 u32 rx_buf_len;
93 u8 *rx_buf;
94 int msg_err;
95 unsigned int status;
96 u32 abort_source;
97 int irq;
98 u32 accessor_flags;
99 struct i2c_adapter adapter;
100 u32 functionality;
101 u32 master_cfg;
102 unsigned int tx_fifo_depth;
103 unsigned int rx_fifo_depth;
104 int rx_outstanding;
105 u32 clk_freq;
106 u32 sda_hold_time;
107 u32 sda_falling_time;
108 u32 scl_falling_time;
109 u16 ss_hcnt;
110 u16 ss_lcnt;
111 u16 fs_hcnt;
112 u16 fs_lcnt;
113 u16 fp_hcnt;
114 u16 fp_lcnt;
115 u16 hs_hcnt;
116 u16 hs_lcnt;
117 int (*acquire_lock)(struct dw_i2c_dev *dev);
118 void (*release_lock)(struct dw_i2c_dev *dev);
119 bool pm_runtime_disabled;
120 bool dynamic_tar_update_enabled;
121 };
122
123 #define ACCESS_SWAP 0x00000001
124 #define ACCESS_16BIT 0x00000002
125 #define ACCESS_INTR_MASK 0x00000004
126
127 extern int i2c_dw_init(struct dw_i2c_dev *dev);
128 extern void i2c_dw_disable(struct dw_i2c_dev *dev);
129 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
130 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
131 extern int i2c_dw_probe(struct dw_i2c_dev *dev);
132
133 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
134 extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
135 #else
136 static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }
137 #endif
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