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RDMA/nes: don't leak skb if carrier down
[deliverable/linux.git] / drivers / i2c / busses / i2c-exynos5.c
1 /**
2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13
14 #include <linux/i2c.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/io.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/spinlock.h>
27
28 /*
29 * HSI2C controller from Samsung supports 2 modes of operation
30 * 1. Auto mode: Where in master automatically controls the whole transaction
31 * 2. Manual mode: Software controls the transaction by issuing commands
32 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
33 *
34 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
35 *
36 * Special bits are available for both modes of operation to set commands
37 * and for checking transfer status
38 */
39
40 /* Register Map */
41 #define HSI2C_CTL 0x00
42 #define HSI2C_FIFO_CTL 0x04
43 #define HSI2C_TRAILIG_CTL 0x08
44 #define HSI2C_CLK_CTL 0x0C
45 #define HSI2C_CLK_SLOT 0x10
46 #define HSI2C_INT_ENABLE 0x20
47 #define HSI2C_INT_STATUS 0x24
48 #define HSI2C_ERR_STATUS 0x2C
49 #define HSI2C_FIFO_STATUS 0x30
50 #define HSI2C_TX_DATA 0x34
51 #define HSI2C_RX_DATA 0x38
52 #define HSI2C_CONF 0x40
53 #define HSI2C_AUTO_CONF 0x44
54 #define HSI2C_TIMEOUT 0x48
55 #define HSI2C_MANUAL_CMD 0x4C
56 #define HSI2C_TRANS_STATUS 0x50
57 #define HSI2C_TIMING_HS1 0x54
58 #define HSI2C_TIMING_HS2 0x58
59 #define HSI2C_TIMING_HS3 0x5C
60 #define HSI2C_TIMING_FS1 0x60
61 #define HSI2C_TIMING_FS2 0x64
62 #define HSI2C_TIMING_FS3 0x68
63 #define HSI2C_TIMING_SLA 0x6C
64 #define HSI2C_ADDR 0x70
65
66 /* I2C_CTL Register bits */
67 #define HSI2C_FUNC_MODE_I2C (1u << 0)
68 #define HSI2C_MASTER (1u << 3)
69 #define HSI2C_RXCHON (1u << 6)
70 #define HSI2C_TXCHON (1u << 7)
71 #define HSI2C_SW_RST (1u << 31)
72
73 /* I2C_FIFO_CTL Register bits */
74 #define HSI2C_RXFIFO_EN (1u << 0)
75 #define HSI2C_TXFIFO_EN (1u << 1)
76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
78
79 /* I2C_TRAILING_CTL Register bits */
80 #define HSI2C_TRAILING_COUNT (0xf)
81
82 /* I2C_INT_EN Register bits */
83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
84 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
85 #define HSI2C_INT_TRAILING_EN (1u << 6)
86
87 /* I2C_INT_STAT Register bits */
88 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
89 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
90 #define HSI2C_INT_TX_UNDERRUN (1u << 2)
91 #define HSI2C_INT_TX_OVERRUN (1u << 3)
92 #define HSI2C_INT_RX_UNDERRUN (1u << 4)
93 #define HSI2C_INT_RX_OVERRUN (1u << 5)
94 #define HSI2C_INT_TRAILING (1u << 6)
95 #define HSI2C_INT_I2C (1u << 9)
96
97 #define HSI2C_INT_TRANS_DONE (1u << 7)
98 #define HSI2C_INT_TRANS_ABORT (1u << 8)
99 #define HSI2C_INT_NO_DEV_ACK (1u << 9)
100 #define HSI2C_INT_NO_DEV (1u << 10)
101 #define HSI2C_INT_TIMEOUT (1u << 11)
102 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
103 HSI2C_INT_TRANS_ABORT | \
104 HSI2C_INT_NO_DEV_ACK | \
105 HSI2C_INT_NO_DEV | \
106 HSI2C_INT_TIMEOUT)
107
108 /* I2C_FIFO_STAT Register bits */
109 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
110 #define HSI2C_RX_FIFO_FULL (1u << 23)
111 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
112 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
113 #define HSI2C_TX_FIFO_FULL (1u << 7)
114 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
115
116 /* I2C_CONF Register bits */
117 #define HSI2C_AUTO_MODE (1u << 31)
118 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
119 #define HSI2C_HS_MODE (1u << 29)
120
121 /* I2C_AUTO_CONF Register bits */
122 #define HSI2C_READ_WRITE (1u << 16)
123 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
124 #define HSI2C_MASTER_RUN (1u << 31)
125
126 /* I2C_TIMEOUT Register bits */
127 #define HSI2C_TIMEOUT_EN (1u << 31)
128 #define HSI2C_TIMEOUT_MASK 0xff
129
130 /* I2C_TRANS_STATUS register bits */
131 #define HSI2C_MASTER_BUSY (1u << 17)
132 #define HSI2C_SLAVE_BUSY (1u << 16)
133 #define HSI2C_TIMEOUT_AUTO (1u << 4)
134 #define HSI2C_NO_DEV (1u << 3)
135 #define HSI2C_NO_DEV_ACK (1u << 2)
136 #define HSI2C_TRANS_ABORT (1u << 1)
137 #define HSI2C_TRANS_DONE (1u << 0)
138
139 /* I2C_ADDR register bits */
140 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
141 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
142 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
143 #define MASTER_ID(x) ((x & 0x7) + 0x08)
144
145 /*
146 * Controller operating frequency, timing values for operation
147 * are calculated against this frequency
148 */
149 #define HSI2C_HS_TX_CLOCK 1000000
150 #define HSI2C_FS_TX_CLOCK 100000
151 #define HSI2C_HIGH_SPD 1
152 #define HSI2C_FAST_SPD 0
153
154 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
155
156 #define HSI2C_EXYNOS7 BIT(0)
157
158 struct exynos5_i2c {
159 struct i2c_adapter adap;
160 unsigned int suspended:1;
161
162 struct i2c_msg *msg;
163 struct completion msg_complete;
164 unsigned int msg_ptr;
165
166 unsigned int irq;
167
168 void __iomem *regs;
169 struct clk *clk;
170 struct device *dev;
171 int state;
172
173 spinlock_t lock; /* IRQ synchronization */
174
175 /*
176 * Since the TRANS_DONE bit is cleared on read, and we may read it
177 * either during an IRQ or after a transaction, keep track of its
178 * state here.
179 */
180 int trans_done;
181
182 /* Controller operating frequency */
183 unsigned int fs_clock;
184 unsigned int hs_clock;
185
186 /*
187 * HSI2C Controller can operate in
188 * 1. High speed upto 3.4Mbps
189 * 2. Fast speed upto 1Mbps
190 */
191 int speed_mode;
192
193 /* Version of HS-I2C Hardware */
194 struct exynos_hsi2c_variant *variant;
195 };
196
197 /**
198 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
199 * @fifo_depth: the fifo depth supported by the HSI2C module
200 *
201 * Specifies platform specific configuration of HSI2C module.
202 * Note: A structure for driver specific platform data is used for future
203 * expansion of its usage.
204 */
205 struct exynos_hsi2c_variant {
206 unsigned int fifo_depth;
207 unsigned int hw;
208 };
209
210 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
211 .fifo_depth = 64,
212 };
213
214 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
215 .fifo_depth = 16,
216 };
217
218 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
219 .fifo_depth = 16,
220 .hw = HSI2C_EXYNOS7,
221 };
222
223 static const struct of_device_id exynos5_i2c_match[] = {
224 {
225 .compatible = "samsung,exynos5-hsi2c",
226 .data = &exynos5250_hsi2c_data
227 }, {
228 .compatible = "samsung,exynos5250-hsi2c",
229 .data = &exynos5250_hsi2c_data
230 }, {
231 .compatible = "samsung,exynos5260-hsi2c",
232 .data = &exynos5260_hsi2c_data
233 }, {
234 .compatible = "samsung,exynos7-hsi2c",
235 .data = &exynos7_hsi2c_data
236 }, {},
237 };
238 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
239
240 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
241 (struct platform_device *pdev)
242 {
243 const struct of_device_id *match;
244
245 match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
246 return (struct exynos_hsi2c_variant *)match->data;
247 }
248
249 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
250 {
251 writel(readl(i2c->regs + HSI2C_INT_STATUS),
252 i2c->regs + HSI2C_INT_STATUS);
253 }
254
255 /*
256 * exynos5_i2c_set_timing: updates the registers with appropriate
257 * timing values calculated
258 *
259 * Returns 0 on success, -EINVAL if the cycle length cannot
260 * be calculated.
261 */
262 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
263 {
264 u32 i2c_timing_s1;
265 u32 i2c_timing_s2;
266 u32 i2c_timing_s3;
267 u32 i2c_timing_sla;
268 unsigned int t_start_su, t_start_hd;
269 unsigned int t_stop_su;
270 unsigned int t_data_su, t_data_hd;
271 unsigned int t_scl_l, t_scl_h;
272 unsigned int t_sr_release;
273 unsigned int t_ftl_cycle;
274 unsigned int clkin = clk_get_rate(i2c->clk);
275 unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;
276 unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
277 i2c->hs_clock : i2c->fs_clock;
278
279 /*
280 * In case of HSI2C controller in Exynos5 series
281 * FPCLK / FI2C =
282 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
283 *
284 * In case of HSI2C controllers in Exynos7 series
285 * FPCLK / FI2C =
286 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
287 *
288 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
289 * utemp1 = (TSCLK_L + TSCLK_H + 2)
290 */
291 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
292 utemp0 = (clkin / op_clk) - 8;
293
294 if (i2c->variant->hw == HSI2C_EXYNOS7)
295 utemp0 -= t_ftl_cycle;
296 else
297 utemp0 -= 2 * t_ftl_cycle;
298
299 /* CLK_DIV max is 256 */
300 for (div = 0; div < 256; div++) {
301 utemp1 = utemp0 / (div + 1);
302
303 /*
304 * SCL_L and SCL_H each has max value of 255
305 * Hence, For the clk_cycle to the have right value
306 * utemp1 has to be less then 512 and more than 4.
307 */
308 if ((utemp1 < 512) && (utemp1 > 4)) {
309 clk_cycle = utemp1 - 2;
310 break;
311 } else if (div == 255) {
312 dev_warn(i2c->dev, "Failed to calculate divisor");
313 return -EINVAL;
314 }
315 }
316
317 t_scl_l = clk_cycle / 2;
318 t_scl_h = clk_cycle / 2;
319 t_start_su = t_scl_l;
320 t_start_hd = t_scl_l;
321 t_stop_su = t_scl_l;
322 t_data_su = t_scl_l / 2;
323 t_data_hd = t_scl_l / 2;
324 t_sr_release = clk_cycle;
325
326 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
327 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
328 i2c_timing_s3 = div << 16 | t_sr_release << 0;
329 i2c_timing_sla = t_data_hd << 0;
330
331 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
332 t_start_su, t_start_hd, t_stop_su);
333 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
334 t_data_su, t_scl_l, t_scl_h);
335 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
336 div, t_sr_release);
337 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
338
339 if (mode == HSI2C_HIGH_SPD) {
340 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
341 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
342 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
343 } else {
344 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
345 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
346 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
347 }
348 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
349
350 return 0;
351 }
352
353 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
354 {
355 /*
356 * Configure the Fast speed timing values
357 * Even the High Speed mode initially starts with Fast mode
358 */
359 if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
360 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
361 return -EINVAL;
362 }
363
364 /* configure the High speed timing values */
365 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
366 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
367 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
368 return -EINVAL;
369 }
370 }
371
372 return 0;
373 }
374
375 /*
376 * exynos5_i2c_init: configures the controller for I2C functionality
377 * Programs I2C controller for Master mode operation
378 */
379 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
380 {
381 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
382 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
383
384 /* Clear to disable Timeout */
385 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
386 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
387
388 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
389 i2c->regs + HSI2C_CTL);
390 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
391
392 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
393 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
394 i2c->regs + HSI2C_ADDR);
395 i2c_conf |= HSI2C_HS_MODE;
396 }
397
398 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
399 }
400
401 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
402 {
403 u32 i2c_ctl;
404
405 /* Set and clear the bit for reset */
406 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
407 i2c_ctl |= HSI2C_SW_RST;
408 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
409
410 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
411 i2c_ctl &= ~HSI2C_SW_RST;
412 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
413
414 /* We don't expect calculations to fail during the run */
415 exynos5_hsi2c_clock_setup(i2c);
416 /* Initialize the configure registers */
417 exynos5_i2c_init(i2c);
418 }
419
420 /*
421 * exynos5_i2c_irq: top level IRQ servicing routine
422 *
423 * INT_STATUS registers gives the interrupt details. Further,
424 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
425 * state of the bus.
426 */
427 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
428 {
429 struct exynos5_i2c *i2c = dev_id;
430 u32 fifo_level, int_status, fifo_status, trans_status;
431 unsigned char byte;
432 int len = 0;
433
434 i2c->state = -EINVAL;
435
436 spin_lock(&i2c->lock);
437
438 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
439 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
440
441 /* handle interrupt related to the transfer status */
442 if (i2c->variant->hw == HSI2C_EXYNOS7) {
443 if (int_status & HSI2C_INT_TRANS_DONE) {
444 i2c->trans_done = 1;
445 i2c->state = 0;
446 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
447 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
448 i2c->state = -EAGAIN;
449 goto stop;
450 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
451 dev_dbg(i2c->dev, "No ACK from device\n");
452 i2c->state = -ENXIO;
453 goto stop;
454 } else if (int_status & HSI2C_INT_NO_DEV) {
455 dev_dbg(i2c->dev, "No device\n");
456 i2c->state = -ENXIO;
457 goto stop;
458 } else if (int_status & HSI2C_INT_TIMEOUT) {
459 dev_dbg(i2c->dev, "Accessing device timed out\n");
460 i2c->state = -ETIMEDOUT;
461 goto stop;
462 }
463 } else if (int_status & HSI2C_INT_I2C) {
464 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
465 if (trans_status & HSI2C_NO_DEV_ACK) {
466 dev_dbg(i2c->dev, "No ACK from device\n");
467 i2c->state = -ENXIO;
468 goto stop;
469 } else if (trans_status & HSI2C_NO_DEV) {
470 dev_dbg(i2c->dev, "No device\n");
471 i2c->state = -ENXIO;
472 goto stop;
473 } else if (trans_status & HSI2C_TRANS_ABORT) {
474 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
475 i2c->state = -EAGAIN;
476 goto stop;
477 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
478 dev_dbg(i2c->dev, "Accessing device timed out\n");
479 i2c->state = -ETIMEDOUT;
480 goto stop;
481 } else if (trans_status & HSI2C_TRANS_DONE) {
482 i2c->trans_done = 1;
483 i2c->state = 0;
484 }
485 }
486
487 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
488 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
489 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
490 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
491 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
492
493 while (len > 0) {
494 byte = (unsigned char)
495 readl(i2c->regs + HSI2C_RX_DATA);
496 i2c->msg->buf[i2c->msg_ptr++] = byte;
497 len--;
498 }
499 i2c->state = 0;
500 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
501 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
502 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
503
504 len = i2c->variant->fifo_depth - fifo_level;
505 if (len > (i2c->msg->len - i2c->msg_ptr))
506 len = i2c->msg->len - i2c->msg_ptr;
507
508 while (len > 0) {
509 byte = i2c->msg->buf[i2c->msg_ptr++];
510 writel(byte, i2c->regs + HSI2C_TX_DATA);
511 len--;
512 }
513 i2c->state = 0;
514 }
515
516 stop:
517 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
518 (i2c->state < 0)) {
519 writel(0, i2c->regs + HSI2C_INT_ENABLE);
520 exynos5_i2c_clr_pend_irq(i2c);
521 complete(&i2c->msg_complete);
522 }
523
524 spin_unlock(&i2c->lock);
525
526 return IRQ_HANDLED;
527 }
528
529 /*
530 * exynos5_i2c_wait_bus_idle
531 *
532 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
533 * cleared.
534 *
535 * Returns -EBUSY if the bus cannot be bought to idle
536 */
537 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
538 {
539 unsigned long stop_time;
540 u32 trans_status;
541
542 /* wait for 100 milli seconds for the bus to be idle */
543 stop_time = jiffies + msecs_to_jiffies(100) + 1;
544 do {
545 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
546 if (!(trans_status & HSI2C_MASTER_BUSY))
547 return 0;
548
549 usleep_range(50, 200);
550 } while (time_before(jiffies, stop_time));
551
552 return -EBUSY;
553 }
554
555 /*
556 * exynos5_i2c_message_start: Configures the bus and starts the xfer
557 * i2c: struct exynos5_i2c pointer for the current bus
558 * stop: Enables stop after transfer if set. Set for last transfer of
559 * in the list of messages.
560 *
561 * Configures the bus for read/write function
562 * Sets chip address to talk to, message length to be sent.
563 * Enables appropriate interrupts and sends start xfer command.
564 */
565 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
566 {
567 u32 i2c_ctl;
568 u32 int_en = 0;
569 u32 i2c_auto_conf = 0;
570 u32 fifo_ctl;
571 unsigned long flags;
572 unsigned short trig_lvl;
573
574 if (i2c->variant->hw == HSI2C_EXYNOS7)
575 int_en |= HSI2C_INT_I2C_TRANS;
576 else
577 int_en |= HSI2C_INT_I2C;
578
579 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
580 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
581 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
582
583 if (i2c->msg->flags & I2C_M_RD) {
584 i2c_ctl |= HSI2C_RXCHON;
585
586 i2c_auto_conf |= HSI2C_READ_WRITE;
587
588 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
589 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
590 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
591
592 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
593 HSI2C_INT_TRAILING_EN);
594 } else {
595 i2c_ctl |= HSI2C_TXCHON;
596
597 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
598 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
599 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
600
601 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
602 }
603
604 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
605
606 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
607 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
608
609 /*
610 * Enable interrupts before starting the transfer so that we don't
611 * miss any INT_I2C interrupts.
612 */
613 spin_lock_irqsave(&i2c->lock, flags);
614 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
615
616 if (stop == 1)
617 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
618 i2c_auto_conf |= i2c->msg->len;
619 i2c_auto_conf |= HSI2C_MASTER_RUN;
620 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
621 spin_unlock_irqrestore(&i2c->lock, flags);
622 }
623
624 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
625 struct i2c_msg *msgs, int stop)
626 {
627 unsigned long timeout;
628 int ret;
629
630 i2c->msg = msgs;
631 i2c->msg_ptr = 0;
632 i2c->trans_done = 0;
633
634 reinit_completion(&i2c->msg_complete);
635
636 exynos5_i2c_message_start(i2c, stop);
637
638 timeout = wait_for_completion_timeout(&i2c->msg_complete,
639 EXYNOS5_I2C_TIMEOUT);
640 if (timeout == 0)
641 ret = -ETIMEDOUT;
642 else
643 ret = i2c->state;
644
645 /*
646 * If this is the last message to be transfered (stop == 1)
647 * Then check if the bus can be brought back to idle.
648 */
649 if (ret == 0 && stop)
650 ret = exynos5_i2c_wait_bus_idle(i2c);
651
652 if (ret < 0) {
653 exynos5_i2c_reset(i2c);
654 if (ret == -ETIMEDOUT)
655 dev_warn(i2c->dev, "%s timeout\n",
656 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
657 }
658
659 /* Return the state as in interrupt routine */
660 return ret;
661 }
662
663 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
664 struct i2c_msg *msgs, int num)
665 {
666 struct exynos5_i2c *i2c = adap->algo_data;
667 int i = 0, ret = 0, stop = 0;
668
669 if (i2c->suspended) {
670 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
671 return -EIO;
672 }
673
674 clk_prepare_enable(i2c->clk);
675
676 for (i = 0; i < num; i++, msgs++) {
677 stop = (i == num - 1);
678
679 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
680
681 if (ret < 0)
682 goto out;
683 }
684
685 if (i == num) {
686 ret = num;
687 } else {
688 /* Only one message, cannot access the device */
689 if (i == 1)
690 ret = -EREMOTEIO;
691 else
692 ret = i;
693
694 dev_warn(i2c->dev, "xfer message failed\n");
695 }
696
697 out:
698 clk_disable_unprepare(i2c->clk);
699 return ret;
700 }
701
702 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
703 {
704 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
705 }
706
707 static const struct i2c_algorithm exynos5_i2c_algorithm = {
708 .master_xfer = exynos5_i2c_xfer,
709 .functionality = exynos5_i2c_func,
710 };
711
712 static int exynos5_i2c_probe(struct platform_device *pdev)
713 {
714 struct device_node *np = pdev->dev.of_node;
715 struct exynos5_i2c *i2c;
716 struct resource *mem;
717 unsigned int op_clock;
718 int ret;
719
720 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
721 if (!i2c)
722 return -ENOMEM;
723
724 if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
725 i2c->speed_mode = HSI2C_FAST_SPD;
726 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
727 } else {
728 if (op_clock >= HSI2C_HS_TX_CLOCK) {
729 i2c->speed_mode = HSI2C_HIGH_SPD;
730 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
731 i2c->hs_clock = op_clock;
732 } else {
733 i2c->speed_mode = HSI2C_FAST_SPD;
734 i2c->fs_clock = op_clock;
735 }
736 }
737
738 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
739 i2c->adap.owner = THIS_MODULE;
740 i2c->adap.algo = &exynos5_i2c_algorithm;
741 i2c->adap.retries = 3;
742
743 i2c->dev = &pdev->dev;
744 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
745 if (IS_ERR(i2c->clk)) {
746 dev_err(&pdev->dev, "cannot get clock\n");
747 return -ENOENT;
748 }
749
750 clk_prepare_enable(i2c->clk);
751
752 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
754 if (IS_ERR(i2c->regs)) {
755 ret = PTR_ERR(i2c->regs);
756 goto err_clk;
757 }
758
759 i2c->adap.dev.of_node = np;
760 i2c->adap.algo_data = i2c;
761 i2c->adap.dev.parent = &pdev->dev;
762
763 /* Clear pending interrupts from u-boot or misc causes */
764 exynos5_i2c_clr_pend_irq(i2c);
765
766 spin_lock_init(&i2c->lock);
767 init_completion(&i2c->msg_complete);
768
769 i2c->irq = ret = platform_get_irq(pdev, 0);
770 if (ret <= 0) {
771 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
772 ret = -EINVAL;
773 goto err_clk;
774 }
775
776 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
777 IRQF_NO_SUSPEND | IRQF_ONESHOT,
778 dev_name(&pdev->dev), i2c);
779
780 if (ret != 0) {
781 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
782 goto err_clk;
783 }
784
785 /* Need to check the variant before setting up. */
786 i2c->variant = exynos5_i2c_get_variant(pdev);
787
788 ret = exynos5_hsi2c_clock_setup(i2c);
789 if (ret)
790 goto err_clk;
791
792 exynos5_i2c_reset(i2c);
793
794 ret = i2c_add_adapter(&i2c->adap);
795 if (ret < 0) {
796 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
797 goto err_clk;
798 }
799
800 platform_set_drvdata(pdev, i2c);
801
802 err_clk:
803 clk_disable_unprepare(i2c->clk);
804 return ret;
805 }
806
807 static int exynos5_i2c_remove(struct platform_device *pdev)
808 {
809 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
810
811 i2c_del_adapter(&i2c->adap);
812
813 return 0;
814 }
815
816 #ifdef CONFIG_PM_SLEEP
817 static int exynos5_i2c_suspend_noirq(struct device *dev)
818 {
819 struct platform_device *pdev = to_platform_device(dev);
820 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
821
822 i2c->suspended = 1;
823
824 return 0;
825 }
826
827 static int exynos5_i2c_resume_noirq(struct device *dev)
828 {
829 struct platform_device *pdev = to_platform_device(dev);
830 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
831 int ret = 0;
832
833 clk_prepare_enable(i2c->clk);
834
835 ret = exynos5_hsi2c_clock_setup(i2c);
836 if (ret) {
837 clk_disable_unprepare(i2c->clk);
838 return ret;
839 }
840
841 exynos5_i2c_init(i2c);
842 clk_disable_unprepare(i2c->clk);
843 i2c->suspended = 0;
844
845 return 0;
846 }
847 #endif
848
849 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
850 #ifdef CONFIG_PM_SLEEP
851 .suspend_noirq = exynos5_i2c_suspend_noirq,
852 .resume_noirq = exynos5_i2c_resume_noirq,
853 .freeze_noirq = exynos5_i2c_suspend_noirq,
854 .thaw_noirq = exynos5_i2c_resume_noirq,
855 .poweroff_noirq = exynos5_i2c_suspend_noirq,
856 .restore_noirq = exynos5_i2c_resume_noirq,
857 #endif
858 };
859
860 static struct platform_driver exynos5_i2c_driver = {
861 .probe = exynos5_i2c_probe,
862 .remove = exynos5_i2c_remove,
863 .driver = {
864 .name = "exynos5-hsi2c",
865 .pm = &exynos5_i2c_dev_pm_ops,
866 .of_match_table = exynos5_i2c_match,
867 },
868 };
869
870 module_platform_driver(exynos5_i2c_driver);
871
872 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
873 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
874 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
875 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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