drivers/i2c/busses/i2c-octeon-core.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
   6  *
   7  * This file contains the shared part of the driver for the i2c adapter in
   8  * Cavium Networks' OCTEON processors and ThunderX SOCs.
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2. This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20
  21 #include "i2c-octeon-core.h"
  22
  23 /* interrupt service routine */
  24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
  25 {
  26         struct octeon_i2c *i2c = dev_id;
  27
  28         i2c->int_disable(i2c);
  29         wake_up(&i2c->queue);
  30
  31         return IRQ_HANDLED;
  32 }
  33
  34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
  35 {
  36         return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
  37 }
  38
  39 static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
  40 {
  41         if (octeon_i2c_test_iflg(i2c))
  42                 return true;
  43
  44         if (*first) {
  45                 *first = false;
  46                 return false;
  47         }
  48
  49         /*
  50          * IRQ has signaled an event but IFLG hasn't changed.
  51          * Sleep and retry once.
  52          */
  53         usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
  54         return octeon_i2c_test_iflg(i2c);
  55 }
  56
  57 /**
  58  * octeon_i2c_wait - wait for the IFLG to be set
  59  * @i2c: The struct octeon_i2c
  60  *
  61  * Returns 0 on success, otherwise a negative errno.
  62  */
  63 static int octeon_i2c_wait(struct octeon_i2c *i2c)
  64 {
  65         long time_left;
  66         bool first = true;
  67
  68         /*
  69          * Some chip revisions don't assert the irq in the interrupt
  70          * controller. So we must poll for the IFLG change.
  71          */
  72         if (i2c->broken_irq_mode) {
  73                 u64 end = get_jiffies_64() + i2c->adap.timeout;
  74
  75                 while (!octeon_i2c_test_iflg(i2c) &&
  76                        time_before64(get_jiffies_64(), end))
  77                         usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
  78
  79                 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
  80         }
  81
  82         i2c->int_enable(i2c);
  83         time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_ready(i2c, &first),
  84                                        i2c->adap.timeout);
  85         i2c->int_disable(i2c);
  86
  87         if (i2c->broken_irq_check && !time_left &&
  88             octeon_i2c_test_iflg(i2c)) {
  89                 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
  90                 i2c->broken_irq_mode = true;
  91                 return 0;
  92         }
  93
  94         if (!time_left)
  95                 return -ETIMEDOUT;
  96
  97         return 0;
  98 }
  99
 100 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
 101 {
 102         return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
 103 }
 104
 105 static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c, bool *first)
 106 {
 107         /* check if valid bit is cleared */
 108         if (octeon_i2c_hlc_test_valid(i2c))
 109                 return true;
 110
 111         if (*first) {
 112                 *first = false;
 113                 return false;
 114         }
 115
 116         /*
 117          * IRQ has signaled an event but valid bit isn't cleared.
 118          * Sleep and retry once.
 119          */
 120         usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
 121         return octeon_i2c_hlc_test_valid(i2c);
 122 }
 123
 124 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
 125 {
 126         /* clear ST/TS events, listen for neither */
 127         octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
 128 }
 129
 130 /*
 131  * Cleanup low-level state & enable high-level controller.
 132  */
 133 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
 134 {
 135         int try = 0;
 136         u64 val;
 137
 138         if (i2c->hlc_enabled)
 139                 return;
 140         i2c->hlc_enabled = true;
 141
 142         while (1) {
 143                 val = octeon_i2c_ctl_read(i2c);
 144                 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
 145                         break;
 146
 147                 /* clear IFLG event */
 148                 if (val & TWSI_CTL_IFLG)
 149                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 150
 151                 if (try++ > 100) {
 152                         pr_err("%s: giving up\n", __func__);
 153                         break;
 154                 }
 155
 156                 /* spin until any start/stop has finished */
 157                 udelay(10);
 158         }
 159         octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
 160 }
 161
 162 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
 163 {
 164         if (!i2c->hlc_enabled)
 165                 return;
 166
 167         i2c->hlc_enabled = false;
 168         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 169 }
 170
 171 /**
 172  * octeon_i2c_hlc_wait - wait for an HLC operation to complete
 173  * @i2c: The struct octeon_i2c
 174  *
 175  * Returns 0 on success, otherwise -ETIMEDOUT.
 176  */
 177 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
 178 {
 179         bool first = true;
 180         int time_left;
 181
 182         /*
 183          * Some cn38xx boards don't assert the irq in the interrupt
 184          * controller. So we must poll for the valid bit change.
 185          */
 186         if (i2c->broken_irq_mode) {
 187                 u64 end = get_jiffies_64() + i2c->adap.timeout;
 188
 189                 while (!octeon_i2c_hlc_test_valid(i2c) &&
 190                        time_before64(get_jiffies_64(), end))
 191                         usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
 192
 193                 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
 194         }
 195
 196         i2c->hlc_int_enable(i2c);
 197         time_left = wait_event_timeout(i2c->queue,
 198                                        octeon_i2c_hlc_test_ready(i2c, &first),
 199                                        i2c->adap.timeout);
 200         i2c->hlc_int_disable(i2c);
 201         if (!time_left)
 202                 octeon_i2c_hlc_int_clear(i2c);
 203
 204         if (i2c->broken_irq_check && !time_left &&
 205             octeon_i2c_hlc_test_valid(i2c)) {
 206                 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
 207                 i2c->broken_irq_mode = true;
 208                 return 0;
 209         }
 210
 211         if (!time_left)
 212                 return -ETIMEDOUT;
 213         return 0;
 214 }
 215
 216 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
 217 {
 218         u8 stat = octeon_i2c_stat_read(i2c);
 219
 220         switch (stat) {
 221         /* Everything is fine */
 222         case STAT_IDLE:
 223         case STAT_AD2W_ACK:
 224         case STAT_RXADDR_ACK:
 225         case STAT_TXADDR_ACK:
 226         case STAT_TXDATA_ACK:
 227                 return 0;
 228
 229         /* ACK allowed on pre-terminal bytes only */
 230         case STAT_RXDATA_ACK:
 231                 if (!final_read)
 232                         return 0;
 233                 return -EIO;
 234
 235         /* NAK allowed on terminal byte only */
 236         case STAT_RXDATA_NAK:
 237                 if (final_read)
 238                         return 0;
 239                 return -EIO;
 240
 241         /* Arbitration lost */
 242         case STAT_LOST_ARB_38:
 243         case STAT_LOST_ARB_68:
 244         case STAT_LOST_ARB_78:
 245         case STAT_LOST_ARB_B0:
 246                 return -EAGAIN;
 247
 248         /* Being addressed as slave, should back off & listen */
 249         case STAT_SLAVE_60:
 250         case STAT_SLAVE_70:
 251         case STAT_GENDATA_ACK:
 252         case STAT_GENDATA_NAK:
 253                 return -EOPNOTSUPP;
 254
 255         /* Core busy as slave */
 256         case STAT_SLAVE_80:
 257         case STAT_SLAVE_88:
 258         case STAT_SLAVE_A0:
 259         case STAT_SLAVE_A8:
 260         case STAT_SLAVE_LOST:
 261         case STAT_SLAVE_NAK:
 262         case STAT_SLAVE_ACK:
 263                 return -EOPNOTSUPP;
 264
 265         case STAT_TXDATA_NAK:
 266                 return -EIO;
 267         case STAT_TXADDR_NAK:
 268         case STAT_RXADDR_NAK:
 269         case STAT_AD2W_NAK:
 270                 return -ENXIO;
 271         default:
 272                 dev_err(i2c->dev, "unhandled state: %d\n", stat);
 273                 return -EIO;
 274         }
 275 }
 276
 277 static int octeon_i2c_recovery(struct octeon_i2c *i2c)
 278 {
 279         int ret;
 280
 281         ret = i2c_recover_bus(&i2c->adap);
 282         if (ret)
 283                 /* recover failed, try hardware re-init */
 284                 ret = octeon_i2c_init_lowlevel(i2c);
 285         return ret;
 286 }
 287
 288 /**
 289  * octeon_i2c_start - send START to the bus
 290  * @i2c: The struct octeon_i2c
 291  *
 292  * Returns 0 on success, otherwise a negative errno.
 293  */
 294 static int octeon_i2c_start(struct octeon_i2c *i2c)
 295 {
 296         int ret;
 297         u8 stat;
 298
 299         octeon_i2c_hlc_disable(i2c);
 300
 301         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
 302         ret = octeon_i2c_wait(i2c);
 303         if (ret)
 304                 goto error;
 305
 306         stat = octeon_i2c_stat_read(i2c);
 307         if (stat == STAT_START || stat == STAT_REP_START)
 308                 /* START successful, bail out */
 309                 return 0;
 310
 311 error:
 312         /* START failed, try to recover */
 313         ret = octeon_i2c_recovery(i2c);
 314         return (ret) ? ret : -EAGAIN;
 315 }
 316
 317 /* send STOP to the bus */
 318 static void octeon_i2c_stop(struct octeon_i2c *i2c)
 319 {
 320         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
 321 }
 322
 323 /**
 324  * octeon_i2c_read - receive data from the bus via low-level controller
 325  * @i2c: The struct octeon_i2c
 326  * @target: Target address
 327  * @data: Pointer to the location to store the data
 328  * @rlength: Length of the data
 329  * @recv_len: flag for length byte
 330  *
 331  * The address is sent over the bus, then the data is read.
 332  *
 333  * Returns 0 on success, otherwise a negative errno.
 334  */
 335 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 336                            u8 *data, u16 *rlength, bool recv_len)
 337 {
 338         int i, result, length = *rlength;
 339         bool final_read = false;
 340
 341         octeon_i2c_data_write(i2c, (target << 1) | 1);
 342         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 343
 344         result = octeon_i2c_wait(i2c);
 345         if (result)
 346                 return result;
 347
 348         /* address OK ? */
 349         result = octeon_i2c_check_status(i2c, false);
 350         if (result)
 351                 return result;
 352
 353         for (i = 0; i < length; i++) {
 354                 /*
 355                  * For the last byte to receive TWSI_CTL_AAK must not be set.
 356                  *
 357                  * A special case is I2C_M_RECV_LEN where we don't know the
 358                  * additional length yet. If recv_len is set we assume we're
 359                  * not reading the final byte and therefore need to set
 360                  * TWSI_CTL_AAK.
 361                  */
 362                 if ((i + 1 == length) && !(recv_len && i == 0))
 363                         final_read = true;
 364
 365                 /* clear iflg to allow next event */
 366                 if (final_read)
 367                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 368                 else
 369                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
 370
 371                 result = octeon_i2c_wait(i2c);
 372                 if (result)
 373                         return result;
 374
 375                 data[i] = octeon_i2c_data_read(i2c);
 376                 if (recv_len && i == 0) {
 377                         if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
 378                                 return -EPROTO;
 379                         length += data[i];
 380                 }
 381
 382                 result = octeon_i2c_check_status(i2c, final_read);
 383                 if (result)
 384                         return result;
 385         }
 386         *rlength = length;
 387         return 0;
 388 }
 389
 390 /**
 391  * octeon_i2c_write - send data to the bus via low-level controller
 392  * @i2c: The struct octeon_i2c
 393  * @target: Target address
 394  * @data: Pointer to the data to be sent
 395  * @length: Length of the data
 396  *
 397  * The address is sent over the bus, then the data.
 398  *
 399  * Returns 0 on success, otherwise a negative errno.
 400  */
 401 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 402                             const u8 *data, int length)
 403 {
 404         int i, result;
 405
 406         octeon_i2c_data_write(i2c, target << 1);
 407         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 408
 409         result = octeon_i2c_wait(i2c);
 410         if (result)
 411                 return result;
 412
 413         for (i = 0; i < length; i++) {
 414                 result = octeon_i2c_check_status(i2c, false);
 415                 if (result)
 416                         return result;
 417
 418                 octeon_i2c_data_write(i2c, data[i]);
 419                 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 420
 421                 result = octeon_i2c_wait(i2c);
 422                 if (result)
 423                         return result;
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* high-level-controller pure read of up to 8 bytes */
 430 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 431 {
 432         int i, j, ret = 0;
 433         u64 cmd;
 434
 435         octeon_i2c_hlc_enable(i2c);
 436         octeon_i2c_hlc_int_clear(i2c);
 437
 438         cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
 439         /* SIZE */
 440         cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
 441         /* A */
 442         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 443
 444         if (msgs[0].flags & I2C_M_TEN)
 445                 cmd |= SW_TWSI_OP_10;
 446         else
 447                 cmd |= SW_TWSI_OP_7;
 448
 449         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 450         ret = octeon_i2c_hlc_wait(i2c);
 451         if (ret)
 452                 goto err;
 453
 454         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 455         if ((cmd & SW_TWSI_R) == 0)
 456                 return -EAGAIN;
 457
 458         for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)
 459                 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
 460
 461         if (msgs[0].len > 4) {
 462                 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
 463                 for (i = 0; i  < msgs[0].len - 4 && i < 4; i++, j--)
 464                         msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
 465         }
 466
 467 err:
 468         return ret;
 469 }
 470
 471 /* high-level-controller pure write of up to 8 bytes */
 472 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 473 {
 474         int i, j, ret = 0;
 475         u64 cmd;
 476
 477         octeon_i2c_hlc_enable(i2c);
 478         octeon_i2c_hlc_int_clear(i2c);
 479
 480         cmd = SW_TWSI_V | SW_TWSI_SOVR;
 481         /* SIZE */
 482         cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
 483         /* A */
 484         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 485
 486         if (msgs[0].flags & I2C_M_TEN)
 487                 cmd |= SW_TWSI_OP_10;
 488         else
 489                 cmd |= SW_TWSI_OP_7;
 490
 491         for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)
 492                 cmd |= (u64)msgs[0].buf[j] << (8 * i);
 493
 494         if (msgs[0].len > 4) {
 495                 u64 ext = 0;
 496
 497                 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
 498                         ext |= (u64)msgs[0].buf[j] << (8 * i);
 499                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
 500         }
 501
 502         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 503         ret = octeon_i2c_hlc_wait(i2c);
 504         if (ret)
 505                 goto err;
 506
 507         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 508         if ((cmd & SW_TWSI_R) == 0)
 509                 return -EAGAIN;
 510
 511         ret = octeon_i2c_check_status(i2c, false);
 512
 513 err:
 514         return ret;
 515 }
 516
 517 /* high-level-controller composite write+read, msg0=addr, msg1=data */
 518 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 519 {
 520         int i, j, ret = 0;
 521         u64 cmd;
 522
 523         octeon_i2c_hlc_enable(i2c);
 524
 525         cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
 526         /* SIZE */
 527         cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
 528         /* A */
 529         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 530
 531         if (msgs[0].flags & I2C_M_TEN)
 532                 cmd |= SW_TWSI_OP_10_IA;
 533         else
 534                 cmd |= SW_TWSI_OP_7_IA;
 535
 536         if (msgs[0].len == 2) {
 537                 u64 ext = 0;
 538
 539                 cmd |= SW_TWSI_EIA;
 540                 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 541                 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
 542                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
 543         } else {
 544                 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 545         }
 546
 547         octeon_i2c_hlc_int_clear(i2c);
 548         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 549
 550         ret = octeon_i2c_hlc_wait(i2c);
 551         if (ret)
 552                 goto err;
 553
 554         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 555         if ((cmd & SW_TWSI_R) == 0)
 556                 return -EAGAIN;
 557
 558         for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)
 559                 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
 560
 561         if (msgs[1].len > 4) {
 562                 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
 563                 for (i = 0; i  < msgs[1].len - 4 && i < 4; i++, j--)
 564                         msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
 565         }
 566
 567 err:
 568         return ret;
 569 }
 570
 571 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
 572 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 573 {
 574         bool set_ext = false;
 575         int i, j, ret = 0;
 576         u64 cmd, ext = 0;
 577
 578         octeon_i2c_hlc_enable(i2c);
 579
 580         cmd = SW_TWSI_V | SW_TWSI_SOVR;
 581         /* SIZE */
 582         cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
 583         /* A */
 584         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 585
 586         if (msgs[0].flags & I2C_M_TEN)
 587                 cmd |= SW_TWSI_OP_10_IA;
 588         else
 589                 cmd |= SW_TWSI_OP_7_IA;
 590
 591         if (msgs[0].len == 2) {
 592                 cmd |= SW_TWSI_EIA;
 593                 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 594                 set_ext = true;
 595                 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
 596         } else {
 597                 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 598         }
 599
 600         for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)
 601                 cmd |= (u64)msgs[1].buf[j] << (8 * i);
 602
 603         if (msgs[1].len > 4) {
 604                 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
 605                         ext |= (u64)msgs[1].buf[j] << (8 * i);
 606                 set_ext = true;
 607         }
 608         if (set_ext)
 609                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
 610
 611         octeon_i2c_hlc_int_clear(i2c);
 612         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 613
 614         ret = octeon_i2c_hlc_wait(i2c);
 615         if (ret)
 616                 goto err;
 617
 618         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 619         if ((cmd & SW_TWSI_R) == 0)
 620                 return -EAGAIN;
 621
 622         ret = octeon_i2c_check_status(i2c, false);
 623
 624 err:
 625         return ret;
 626 }
 627
 628 /**
 629  * octeon_i2c_xfer - The driver's master_xfer function
 630  * @adap: Pointer to the i2c_adapter structure
 631  * @msgs: Pointer to the messages to be processed
 632  * @num: Length of the MSGS array
 633  *
 634  * Returns the number of messages processed, or a negative errno on failure.
 635  */
 636 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 637 {
 638         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 639         int i, ret = 0;
 640
 641         if (num == 1) {
 642                 if (msgs[0].len > 0 && msgs[0].len <= 8) {
 643                         if (msgs[0].flags & I2C_M_RD)
 644                                 ret = octeon_i2c_hlc_read(i2c, msgs);
 645                         else
 646                                 ret = octeon_i2c_hlc_write(i2c, msgs);
 647                         goto out;
 648                 }
 649         } else if (num == 2) {
 650                 if ((msgs[0].flags & I2C_M_RD) == 0 &&
 651                     (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
 652                     msgs[0].len > 0 && msgs[0].len <= 2 &&
 653                     msgs[1].len > 0 && msgs[1].len <= 8 &&
 654                     msgs[0].addr == msgs[1].addr) {
 655                         if (msgs[1].flags & I2C_M_RD)
 656                                 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
 657                         else
 658                                 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
 659                         goto out;
 660                 }
 661         }
 662
 663         for (i = 0; ret == 0 && i < num; i++) {
 664                 struct i2c_msg *pmsg = &msgs[i];
 665
 666                 /* zero-length messages are not supported */
 667                 if (!pmsg->len) {
 668                         ret = -EOPNOTSUPP;
 669                         break;
 670                 }
 671
 672                 ret = octeon_i2c_start(i2c);
 673                 if (ret)
 674                         return ret;
 675
 676                 if (pmsg->flags & I2C_M_RD)
 677                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 678                                               &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
 679                 else
 680                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 681                                                pmsg->len);
 682         }
 683         octeon_i2c_stop(i2c);
 684 out:
 685         return (ret != 0) ? ret : num;
 686 }
 687
 688 /* calculate and set clock divisors */
 689 void octeon_i2c_set_clock(struct octeon_i2c *i2c)
 690 {
 691         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 692         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 693
 694         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 695                 /*
 696                  * An mdiv value of less than 2 seems to not work well
 697                  * with ds1337 RTCs, so we constrain it to larger values.
 698                  */
 699                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 700                         /*
 701                          * For given ndiv and mdiv values check the
 702                          * two closest thp values.
 703                          */
 704                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 705                         tclk *= (1 << ndiv_idx);
 706                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 707
 708                         for (inc = 0; inc <= 1; inc++) {
 709                                 thp_idx = thp_base + inc;
 710                                 if (thp_idx < 5 || thp_idx > 0xff)
 711                                         continue;
 712
 713                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 714                                 foscl = foscl / (1 << ndiv_idx);
 715                                 foscl = foscl / (mdiv_idx + 1) / 10;
 716                                 diff = abs(foscl - i2c->twsi_freq);
 717                                 if (diff < delta_hz) {
 718                                         delta_hz = diff;
 719                                         thp = thp_idx;
 720                                         mdiv = mdiv_idx;
 721                                         ndiv = ndiv_idx;
 722                                 }
 723                         }
 724                 }
 725         }
 726         octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 727         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 728 }
 729
 730 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
 731 {
 732         u8 status = 0;
 733         int tries;
 734
 735         /* reset controller */
 736         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 737
 738         for (tries = 10; tries && status != STAT_IDLE; tries--) {
 739                 udelay(1);
 740                 status = octeon_i2c_stat_read(i2c);
 741                 if (status == STAT_IDLE)
 742                         break;
 743         }
 744
 745         if (status != STAT_IDLE) {
 746                 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
 747                         __func__, status);
 748                 return -EIO;
 749         }
 750
 751         /* toggle twice to force both teardowns */
 752         octeon_i2c_hlc_enable(i2c);
 753         octeon_i2c_hlc_disable(i2c);
 754         return 0;
 755 }
 756
 757 static int octeon_i2c_get_scl(struct i2c_adapter *adap)
 758 {
 759         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 760         u64 state;
 761
 762         state = octeon_i2c_read_int(i2c);
 763         return state & TWSI_INT_SCL;
 764 }
 765
 766 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
 767 {
 768         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 769
 770         octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
 771 }
 772
 773 static int octeon_i2c_get_sda(struct i2c_adapter *adap)
 774 {
 775         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 776         u64 state;
 777
 778         state = octeon_i2c_read_int(i2c);
 779         return state & TWSI_INT_SDA;
 780 }
 781
 782 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
 783 {
 784         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 785
 786         /*
 787          * The stop resets the state machine, does not _transmit_ STOP unless
 788          * engine was active.
 789          */
 790         octeon_i2c_stop(i2c);
 791
 792         octeon_i2c_hlc_disable(i2c);
 793         octeon_i2c_write_int(i2c, 0);
 794 }
 795
 796 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
 797 {
 798         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 799
 800         octeon_i2c_write_int(i2c, 0);
 801 }
 802
 803 struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
 804         .recover_bus = i2c_generic_scl_recovery,
 805         .get_scl = octeon_i2c_get_scl,
 806         .set_scl = octeon_i2c_set_scl,
 807         .get_sda = octeon_i2c_get_sda,
 808         .prepare_recovery = octeon_i2c_prepare_recovery,
 809         .unprepare_recovery = octeon_i2c_unprepare_recovery,
 810 };