drivers/i2c/busses/i2c-uniphier-f.c

   1 /*
   2  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21
  22 #define UNIPHIER_FI2C_CR        0x00    /* control register */
  23 #define     UNIPHIER_FI2C_CR_MST        BIT(3)  /* master mode */
  24 #define     UNIPHIER_FI2C_CR_STA        BIT(2)  /* start condition */
  25 #define     UNIPHIER_FI2C_CR_STO        BIT(1)  /* stop condition */
  26 #define     UNIPHIER_FI2C_CR_NACK       BIT(0)  /* do not return ACK */
  27 #define UNIPHIER_FI2C_DTTX      0x04    /* TX FIFO */
  28 #define     UNIPHIER_FI2C_DTTX_CMD      BIT(8)  /* send command (slave addr) */
  29 #define     UNIPHIER_FI2C_DTTX_RD       BIT(0)  /* read transaction */
  30 #define UNIPHIER_FI2C_DTRX      0x04    /* RX FIFO */
  31 #define UNIPHIER_FI2C_SLAD      0x0c    /* slave address */
  32 #define UNIPHIER_FI2C_CYC       0x10    /* clock cycle control */
  33 #define UNIPHIER_FI2C_LCTL      0x14    /* clock low period control */
  34 #define UNIPHIER_FI2C_SSUT      0x18    /* restart/stop setup time control */
  35 #define UNIPHIER_FI2C_DSUT      0x1c    /* data setup time control */
  36 #define UNIPHIER_FI2C_INT       0x20    /* interrupt status */
  37 #define UNIPHIER_FI2C_IE        0x24    /* interrupt enable */
  38 #define UNIPHIER_FI2C_IC        0x28    /* interrupt clear */
  39 #define     UNIPHIER_FI2C_INT_TE        BIT(9)  /* TX FIFO empty */
  40 #define     UNIPHIER_FI2C_INT_RF        BIT(8)  /* RX FIFO full */
  41 #define     UNIPHIER_FI2C_INT_TC        BIT(7)  /* send complete (STOP) */
  42 #define     UNIPHIER_FI2C_INT_RC        BIT(6)  /* receive complete (STOP) */
  43 #define     UNIPHIER_FI2C_INT_TB        BIT(5)  /* sent specified bytes */
  44 #define     UNIPHIER_FI2C_INT_RB        BIT(4)  /* received specified bytes */
  45 #define     UNIPHIER_FI2C_INT_NA        BIT(2)  /* no ACK */
  46 #define     UNIPHIER_FI2C_INT_AL        BIT(1)  /* arbitration lost */
  47 #define UNIPHIER_FI2C_SR        0x2c    /* status register */
  48 #define     UNIPHIER_FI2C_SR_DB         BIT(12) /* device busy */
  49 #define     UNIPHIER_FI2C_SR_STS        BIT(11) /* stop condition detected */
  50 #define     UNIPHIER_FI2C_SR_BB         BIT(8)  /* bus busy */
  51 #define     UNIPHIER_FI2C_SR_RFF        BIT(3)  /* RX FIFO full */
  52 #define     UNIPHIER_FI2C_SR_RNE        BIT(2)  /* RX FIFO not empty */
  53 #define     UNIPHIER_FI2C_SR_TNF        BIT(1)  /* TX FIFO not full */
  54 #define     UNIPHIER_FI2C_SR_TFE        BIT(0)  /* TX FIFO empty */
  55 #define UNIPHIER_FI2C_RST       0x34    /* reset control */
  56 #define     UNIPHIER_FI2C_RST_TBRST     BIT(2)  /* clear TX FIFO */
  57 #define     UNIPHIER_FI2C_RST_RBRST     BIT(1)  /* clear RX FIFO */
  58 #define     UNIPHIER_FI2C_RST_RST       BIT(0)  /* forcible bus reset */
  59 #define UNIPHIER_FI2C_BM        0x38    /* bus monitor */
  60 #define     UNIPHIER_FI2C_BM_SDAO       BIT(3)  /* output for SDA line */
  61 #define     UNIPHIER_FI2C_BM_SDAS       BIT(2)  /* readback of SDA line */
  62 #define     UNIPHIER_FI2C_BM_SCLO       BIT(1)  /* output for SCL line */
  63 #define     UNIPHIER_FI2C_BM_SCLS       BIT(0)  /* readback of SCL line */
  64 #define UNIPHIER_FI2C_NOISE     0x3c    /* noise filter control */
  65 #define UNIPHIER_FI2C_TBC       0x40    /* TX byte count setting */
  66 #define UNIPHIER_FI2C_RBC       0x44    /* RX byte count setting */
  67 #define UNIPHIER_FI2C_TBCM      0x48    /* TX byte count monitor */
  68 #define UNIPHIER_FI2C_RBCM      0x4c    /* RX byte count monitor */
  69 #define UNIPHIER_FI2C_BRST      0x50    /* bus reset */
  70 #define     UNIPHIER_FI2C_BRST_FOEN     BIT(1)  /* normal operation */
  71 #define     UNIPHIER_FI2C_BRST_RSCL     BIT(0)  /* release SCL */
  72
  73 #define UNIPHIER_FI2C_INT_FAULTS        \
  74                                 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
  75 #define UNIPHIER_FI2C_INT_STOP          \
  76                                 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
  77
  78 #define UNIPHIER_FI2C_RD                BIT(0)
  79 #define UNIPHIER_FI2C_STOP              BIT(1)
  80 #define UNIPHIER_FI2C_MANUAL_NACK       BIT(2)
  81 #define UNIPHIER_FI2C_BYTE_WISE         BIT(3)
  82 #define UNIPHIER_FI2C_DEFER_STOP_COMP   BIT(4)
  83
  84 #define UNIPHIER_FI2C_DEFAULT_SPEED     100000
  85 #define UNIPHIER_FI2C_MAX_SPEED         400000
  86 #define UNIPHIER_FI2C_FIFO_SIZE         8
  87
  88 struct uniphier_fi2c_priv {
  89         struct completion comp;
  90         struct i2c_adapter adap;
  91         void __iomem *membase;
  92         struct clk *clk;
  93         unsigned int len;
  94         u8 *buf;
  95         u32 enabled_irqs;
  96         int error;
  97         unsigned int flags;
  98         unsigned int busy_cnt;
  99 };
 100
 101 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
 102                                       bool first)
 103 {
 104         int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
 105
 106         /*
 107          * TX-FIFO stores slave address in it for the first access.
 108          * Decrement the counter.
 109          */
 110         if (first)
 111                 fifo_space--;
 112
 113         while (priv->len) {
 114                 if (fifo_space-- <= 0)
 115                         break;
 116
 117                 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf);
 118                 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
 119                 priv->len--;
 120         }
 121 }
 122
 123 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
 124 {
 125         int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
 126                                                 1 : UNIPHIER_FI2C_FIFO_SIZE;
 127
 128         while (priv->len) {
 129                 if (fifo_left-- <= 0)
 130                         break;
 131
 132                 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
 133                 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]);
 134                 priv->len--;
 135         }
 136 }
 137
 138 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
 139 {
 140         writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
 141 }
 142
 143 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv)
 144 {
 145         writel(-1, priv->membase + UNIPHIER_FI2C_IC);
 146 }
 147
 148 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
 149 {
 150         dev_dbg(&priv->adap.dev, "stop condition\n");
 151
 152         priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
 153         uniphier_fi2c_set_irqs(priv);
 154         writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
 155                priv->membase + UNIPHIER_FI2C_CR);
 156 }
 157
 158 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
 159 {
 160         struct uniphier_fi2c_priv *priv = dev_id;
 161         u32 irq_status;
 162
 163         irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
 164
 165         dev_dbg(&priv->adap.dev,
 166                 "interrupt: enabled_irqs=%04x, irq_status=%04x\n",
 167                 priv->enabled_irqs, irq_status);
 168
 169         if (irq_status & UNIPHIER_FI2C_INT_STOP)
 170                 goto complete;
 171
 172         if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
 173                 dev_dbg(&priv->adap.dev, "arbitration lost\n");
 174                 priv->error = -EAGAIN;
 175                 goto complete;
 176         }
 177
 178         if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
 179                 dev_dbg(&priv->adap.dev, "could not get ACK\n");
 180                 priv->error = -ENXIO;
 181                 if (priv->flags & UNIPHIER_FI2C_RD) {
 182                         /*
 183                          * work around a hardware bug:
 184                          * The receive-completed interrupt is never set even if
 185                          * STOP condition is detected after the address phase
 186                          * of read transaction fails to get ACK.
 187                          * To avoid time-out error, we issue STOP here,
 188                          * but do not wait for its completion.
 189                          * It should be checked after exiting this handler.
 190                          */
 191                         uniphier_fi2c_stop(priv);
 192                         priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
 193                         goto complete;
 194                 }
 195                 goto stop;
 196         }
 197
 198         if (irq_status & UNIPHIER_FI2C_INT_TE) {
 199                 if (!priv->len)
 200                         goto data_done;
 201
 202                 uniphier_fi2c_fill_txfifo(priv, false);
 203                 goto handled;
 204         }
 205
 206         if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
 207                 uniphier_fi2c_drain_rxfifo(priv);
 208                 if (!priv->len)
 209                         goto data_done;
 210
 211                 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
 212                         if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
 213                             !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
 214                                 dev_dbg(&priv->adap.dev,
 215                                         "enable read byte count IRQ\n");
 216                                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
 217                                 uniphier_fi2c_set_irqs(priv);
 218                                 priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
 219                         }
 220                         if (priv->len <= 1) {
 221                                 dev_dbg(&priv->adap.dev, "set NACK\n");
 222                                 writel(UNIPHIER_FI2C_CR_MST |
 223                                        UNIPHIER_FI2C_CR_NACK,
 224                                        priv->membase + UNIPHIER_FI2C_CR);
 225                         }
 226                 }
 227
 228                 goto handled;
 229         }
 230
 231         return IRQ_NONE;
 232
 233 data_done:
 234         if (priv->flags & UNIPHIER_FI2C_STOP) {
 235 stop:
 236                 uniphier_fi2c_stop(priv);
 237         } else {
 238 complete:
 239                 priv->enabled_irqs = 0;
 240                 uniphier_fi2c_set_irqs(priv);
 241                 complete(&priv->comp);
 242         }
 243
 244 handled:
 245         uniphier_fi2c_clear_irqs(priv);
 246
 247         return IRQ_HANDLED;
 248 }
 249
 250 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr)
 251 {
 252         priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
 253         /* do not use TX byte counter */
 254         writel(0, priv->membase + UNIPHIER_FI2C_TBC);
 255         /* set slave address */
 256         writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
 257                priv->membase + UNIPHIER_FI2C_DTTX);
 258         /* first chunk of data */
 259         uniphier_fi2c_fill_txfifo(priv, true);
 260 }
 261
 262 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
 263 {
 264         priv->flags |= UNIPHIER_FI2C_RD;
 265
 266         if (likely(priv->len < 256)) {
 267                 /*
 268                  * If possible, use RX byte counter.
 269                  * It can automatically handle NACK for the last byte.
 270                  */
 271                 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
 272                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
 273                                       UNIPHIER_FI2C_INT_RB;
 274         } else {
 275                 /*
 276                  * The byte counter can not count over 256.  In this case,
 277                  * do not use it at all.  Drain data when FIFO gets full,
 278                  * but treat the last portion as a special case.
 279                  */
 280                 writel(0, priv->membase + UNIPHIER_FI2C_RBC);
 281                 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
 282                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
 283         }
 284
 285         /* set slave address with RD bit */
 286         writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
 287                priv->membase + UNIPHIER_FI2C_DTTX);
 288 }
 289
 290 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
 291 {
 292         writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
 293 }
 294
 295 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
 296 {
 297         writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
 298                priv->membase + UNIPHIER_FI2C_BRST);
 299 }
 300
 301 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
 302 {
 303         uniphier_fi2c_reset(priv);
 304         i2c_recover_bus(&priv->adap);
 305 }
 306
 307 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
 308                                          struct i2c_msg *msg, bool stop)
 309 {
 310         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 311         bool is_read = msg->flags & I2C_M_RD;
 312         unsigned long time_left;
 313
 314         dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
 315                 is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
 316
 317         priv->len = msg->len;
 318         priv->buf = msg->buf;
 319         priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
 320         priv->error = 0;
 321         priv->flags = 0;
 322
 323         if (stop)
 324                 priv->flags |= UNIPHIER_FI2C_STOP;
 325
 326         reinit_completion(&priv->comp);
 327         uniphier_fi2c_clear_irqs(priv);
 328         writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
 329                priv->membase + UNIPHIER_FI2C_RST);      /* reset TX/RX FIFO */
 330
 331         if (is_read)
 332                 uniphier_fi2c_rx_init(priv, msg->addr);
 333         else
 334                 uniphier_fi2c_tx_init(priv, msg->addr);
 335
 336         uniphier_fi2c_set_irqs(priv);
 337
 338         dev_dbg(&adap->dev, "start condition\n");
 339         writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
 340                priv->membase + UNIPHIER_FI2C_CR);
 341
 342         time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
 343         if (!time_left) {
 344                 dev_err(&adap->dev, "transaction timeout.\n");
 345                 uniphier_fi2c_recover(priv);
 346                 return -ETIMEDOUT;
 347         }
 348         dev_dbg(&adap->dev, "complete\n");
 349
 350         if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
 351                 u32 status = readl(priv->membase + UNIPHIER_FI2C_SR);
 352
 353                 if (!(status & UNIPHIER_FI2C_SR_STS) ||
 354                     status & UNIPHIER_FI2C_SR_BB) {
 355                         dev_err(&adap->dev,
 356                                 "stop condition was not completed.\n");
 357                         uniphier_fi2c_recover(priv);
 358                         return -EBUSY;
 359                 }
 360         }
 361
 362         return priv->error;
 363 }
 364
 365 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
 366 {
 367         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 368
 369         if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
 370                 if (priv->busy_cnt++ > 3) {
 371                         /*
 372                          * If bus busy continues too long, it is probably
 373                          * in a wrong state.  Try bus recovery.
 374                          */
 375                         uniphier_fi2c_recover(priv);
 376                         priv->busy_cnt = 0;
 377                 }
 378
 379                 return -EAGAIN;
 380         }
 381
 382         priv->busy_cnt = 0;
 383         return 0;
 384 }
 385
 386 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
 387                                      struct i2c_msg *msgs, int num)
 388 {
 389         struct i2c_msg *msg, *emsg = msgs + num;
 390         int ret;
 391
 392         ret = uniphier_fi2c_check_bus_busy(adap);
 393         if (ret)
 394                 return ret;
 395
 396         for (msg = msgs; msg < emsg; msg++) {
 397                 /* If next message is read, skip the stop condition */
 398                 bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
 399                 /* but, force it if I2C_M_STOP is set */
 400                 if (msg->flags & I2C_M_STOP)
 401                         stop = true;
 402
 403                 ret = uniphier_fi2c_master_xfer_one(adap, msg, stop);
 404                 if (ret)
 405                         return ret;
 406         }
 407
 408         return num;
 409 }
 410
 411 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
 412 {
 413         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 414 }
 415
 416 static const struct i2c_algorithm uniphier_fi2c_algo = {
 417         .master_xfer = uniphier_fi2c_master_xfer,
 418         .functionality = uniphier_fi2c_functionality,
 419 };
 420
 421 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
 422 {
 423         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 424
 425         return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
 426                                                         UNIPHIER_FI2C_BM_SCLS);
 427 }
 428
 429 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
 430 {
 431         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 432
 433         writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
 434                priv->membase + UNIPHIER_FI2C_BRST);
 435 }
 436
 437 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
 438 {
 439         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 440
 441         return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
 442                                                         UNIPHIER_FI2C_BM_SDAS);
 443 }
 444
 445 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
 446 {
 447         uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
 448 }
 449
 450 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
 451         .recover_bus = i2c_generic_scl_recovery,
 452         .get_scl = uniphier_fi2c_get_scl,
 453         .set_scl = uniphier_fi2c_set_scl,
 454         .get_sda = uniphier_fi2c_get_sda,
 455         .unprepare_recovery = uniphier_fi2c_unprepare_recovery,
 456 };
 457
 458 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv,
 459                                   u32 bus_speed, unsigned long clk_rate)
 460 {
 461         u32 tmp;
 462
 463         tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
 464         tmp |= UNIPHIER_FI2C_CR_MST;
 465         writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
 466
 467         uniphier_fi2c_reset(priv);
 468
 469         tmp = clk_rate / bus_speed;
 470
 471         writel(tmp, priv->membase + UNIPHIER_FI2C_CYC);
 472         writel(tmp / 2, priv->membase + UNIPHIER_FI2C_LCTL);
 473         writel(tmp / 2, priv->membase + UNIPHIER_FI2C_SSUT);
 474         writel(tmp / 16, priv->membase + UNIPHIER_FI2C_DSUT);
 475
 476         uniphier_fi2c_prepare_operation(priv);
 477 }
 478
 479 static int uniphier_fi2c_probe(struct platform_device *pdev)
 480 {
 481         struct device *dev = &pdev->dev;
 482         struct uniphier_fi2c_priv *priv;
 483         struct resource *regs;
 484         u32 bus_speed;
 485         unsigned long clk_rate;
 486         int irq, ret;
 487
 488         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 489         if (!priv)
 490                 return -ENOMEM;
 491
 492         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 493         priv->membase = devm_ioremap_resource(dev, regs);
 494         if (IS_ERR(priv->membase))
 495                 return PTR_ERR(priv->membase);
 496
 497         irq = platform_get_irq(pdev, 0);
 498         if (irq < 0) {
 499                 dev_err(dev, "failed to get IRQ number\n");
 500                 return irq;
 501         }
 502
 503         if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
 504                 bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED;
 505
 506         if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) {
 507                 dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
 508                 return -EINVAL;
 509         }
 510
 511         priv->clk = devm_clk_get(dev, NULL);
 512         if (IS_ERR(priv->clk)) {
 513                 dev_err(dev, "failed to get clock\n");
 514                 return PTR_ERR(priv->clk);
 515         }
 516
 517         ret = clk_prepare_enable(priv->clk);
 518         if (ret)
 519                 return ret;
 520
 521         clk_rate = clk_get_rate(priv->clk);
 522         if (!clk_rate) {
 523                 dev_err(dev, "input clock rate should not be zero\n");
 524                 ret = -EINVAL;
 525                 goto err;
 526         }
 527
 528         init_completion(&priv->comp);
 529         priv->adap.owner = THIS_MODULE;
 530         priv->adap.algo = &uniphier_fi2c_algo;
 531         priv->adap.dev.parent = dev;
 532         priv->adap.dev.of_node = dev->of_node;
 533         strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
 534         priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
 535         i2c_set_adapdata(&priv->adap, priv);
 536         platform_set_drvdata(pdev, priv);
 537
 538         uniphier_fi2c_hw_init(priv, bus_speed, clk_rate);
 539
 540         ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
 541                                pdev->name, priv);
 542         if (ret) {
 543                 dev_err(dev, "failed to request irq %d\n", irq);
 544                 goto err;
 545         }
 546
 547         ret = i2c_add_adapter(&priv->adap);
 548 err:
 549         if (ret)
 550                 clk_disable_unprepare(priv->clk);
 551
 552         return ret;
 553 }
 554
 555 static int uniphier_fi2c_remove(struct platform_device *pdev)
 556 {
 557         struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
 558
 559         i2c_del_adapter(&priv->adap);
 560         clk_disable_unprepare(priv->clk);
 561
 562         return 0;
 563 }
 564
 565 static const struct of_device_id uniphier_fi2c_match[] = {
 566         { .compatible = "socionext,uniphier-fi2c" },
 567         { /* sentinel */ }
 568 };
 569 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
 570
 571 static struct platform_driver uniphier_fi2c_drv = {
 572         .probe  = uniphier_fi2c_probe,
 573         .remove = uniphier_fi2c_remove,
 574         .driver = {
 575                 .name  = "uniphier-fi2c",
 576                 .of_match_table = uniphier_fi2c_match,
 577         },
 578 };
 579 module_platform_driver(uniphier_fi2c_drv);
 580
 581 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 582 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
 583 MODULE_LICENSE("GPL");