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[deliverable/linux.git] / drivers / iio / adc / mxs-lradc.c
1 /*
2 * Freescale MXS LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/device.h>
22 #include <linux/err.h>
23 #include <linux/input.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/stmp_device.h>
34 #include <linux/sysfs.h>
35
36 #include <linux/iio/buffer.h>
37 #include <linux/iio/iio.h>
38 #include <linux/iio/trigger.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41 #include <linux/iio/sysfs.h>
42
43 #define DRIVER_NAME "mxs-lradc"
44
45 #define LRADC_MAX_DELAY_CHANS 4
46 #define LRADC_MAX_MAPPED_CHANS 8
47 #define LRADC_MAX_TOTAL_CHANS 16
48
49 #define LRADC_DELAY_TIMER_HZ 2000
50
51 /*
52 * Make this runtime configurable if necessary. Currently, if the buffered mode
53 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
54 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
55 * seconds. The result is that the samples arrive every 500mS.
56 */
57 #define LRADC_DELAY_TIMER_PER 200
58 #define LRADC_DELAY_TIMER_LOOP 5
59
60 /*
61 * Once the pen touches the touchscreen, the touchscreen switches from
62 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
63 * is realized by worker thread, which is called every 20 or so milliseconds.
64 * This gives the touchscreen enough fluency and does not strain the system
65 * too much.
66 */
67 #define LRADC_TS_SAMPLE_DELAY_MS 5
68
69 /*
70 * The LRADC reads the following amount of samples from each touchscreen
71 * channel and the driver then computes average of these.
72 */
73 #define LRADC_TS_SAMPLE_AMOUNT 4
74
75 enum mxs_lradc_id {
76 IMX23_LRADC,
77 IMX28_LRADC,
78 };
79
80 static const char * const mx23_lradc_irq_names[] = {
81 "mxs-lradc-touchscreen",
82 "mxs-lradc-channel0",
83 "mxs-lradc-channel1",
84 "mxs-lradc-channel2",
85 "mxs-lradc-channel3",
86 "mxs-lradc-channel4",
87 "mxs-lradc-channel5",
88 "mxs-lradc-channel6",
89 "mxs-lradc-channel7",
90 };
91
92 static const char * const mx28_lradc_irq_names[] = {
93 "mxs-lradc-touchscreen",
94 "mxs-lradc-thresh0",
95 "mxs-lradc-thresh1",
96 "mxs-lradc-channel0",
97 "mxs-lradc-channel1",
98 "mxs-lradc-channel2",
99 "mxs-lradc-channel3",
100 "mxs-lradc-channel4",
101 "mxs-lradc-channel5",
102 "mxs-lradc-channel6",
103 "mxs-lradc-channel7",
104 "mxs-lradc-button0",
105 "mxs-lradc-button1",
106 };
107
108 struct mxs_lradc_of_config {
109 const int irq_count;
110 const char * const *irq_name;
111 const u32 *vref_mv;
112 };
113
114 #define VREF_MV_BASE 1850
115
116 static const u32 mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
117 VREF_MV_BASE, /* CH0 */
118 VREF_MV_BASE, /* CH1 */
119 VREF_MV_BASE, /* CH2 */
120 VREF_MV_BASE, /* CH3 */
121 VREF_MV_BASE, /* CH4 */
122 VREF_MV_BASE, /* CH5 */
123 VREF_MV_BASE * 2, /* CH6 VDDIO */
124 VREF_MV_BASE * 4, /* CH7 VBATT */
125 VREF_MV_BASE, /* CH8 Temp sense 0 */
126 VREF_MV_BASE, /* CH9 Temp sense 1 */
127 VREF_MV_BASE, /* CH10 */
128 VREF_MV_BASE, /* CH11 */
129 VREF_MV_BASE, /* CH12 USB_DP */
130 VREF_MV_BASE, /* CH13 USB_DN */
131 VREF_MV_BASE, /* CH14 VBG */
132 VREF_MV_BASE * 4, /* CH15 VDD5V */
133 };
134
135 static const u32 mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
136 VREF_MV_BASE, /* CH0 */
137 VREF_MV_BASE, /* CH1 */
138 VREF_MV_BASE, /* CH2 */
139 VREF_MV_BASE, /* CH3 */
140 VREF_MV_BASE, /* CH4 */
141 VREF_MV_BASE, /* CH5 */
142 VREF_MV_BASE, /* CH6 */
143 VREF_MV_BASE * 4, /* CH7 VBATT */
144 VREF_MV_BASE, /* CH8 Temp sense 0 */
145 VREF_MV_BASE, /* CH9 Temp sense 1 */
146 VREF_MV_BASE * 2, /* CH10 VDDIO */
147 VREF_MV_BASE, /* CH11 VTH */
148 VREF_MV_BASE * 2, /* CH12 VDDA */
149 VREF_MV_BASE, /* CH13 VDDD */
150 VREF_MV_BASE, /* CH14 VBG */
151 VREF_MV_BASE * 4, /* CH15 VDD5V */
152 };
153
154 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
155 [IMX23_LRADC] = {
156 .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
157 .irq_name = mx23_lradc_irq_names,
158 .vref_mv = mx23_vref_mv,
159 },
160 [IMX28_LRADC] = {
161 .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
162 .irq_name = mx28_lradc_irq_names,
163 .vref_mv = mx28_vref_mv,
164 },
165 };
166
167 enum mxs_lradc_ts {
168 MXS_LRADC_TOUCHSCREEN_NONE = 0,
169 MXS_LRADC_TOUCHSCREEN_4WIRE,
170 MXS_LRADC_TOUCHSCREEN_5WIRE,
171 };
172
173 /*
174 * Touchscreen handling
175 */
176 enum lradc_ts_plate {
177 LRADC_TOUCH = 0,
178 LRADC_SAMPLE_X,
179 LRADC_SAMPLE_Y,
180 LRADC_SAMPLE_PRESSURE,
181 LRADC_SAMPLE_VALID,
182 };
183
184 enum mxs_lradc_divbytwo {
185 MXS_LRADC_DIV_DISABLED = 0,
186 MXS_LRADC_DIV_ENABLED,
187 };
188
189 struct mxs_lradc_scale {
190 unsigned int integer;
191 unsigned int nano;
192 };
193
194 struct mxs_lradc {
195 struct device *dev;
196 void __iomem *base;
197 int irq[13];
198
199 struct clk *clk;
200
201 u32 *buffer;
202 struct iio_trigger *trig;
203
204 struct mutex lock;
205
206 struct completion completion;
207
208 const u32 *vref_mv;
209 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
210 unsigned long is_divided;
211
212 /*
213 * When the touchscreen is enabled, we give it two private virtual
214 * channels: #6 and #7. This means that only 6 virtual channels (instead
215 * of 8) will be available for buffered capture.
216 */
217 #define TOUCHSCREEN_VCHANNEL1 7
218 #define TOUCHSCREEN_VCHANNEL2 6
219 #define BUFFER_VCHANS_LIMITED 0x3f
220 #define BUFFER_VCHANS_ALL 0xff
221 u8 buffer_vchans;
222
223 /*
224 * Furthermore, certain LRADC channels are shared between touchscreen
225 * and/or touch-buttons and generic LRADC block. Therefore when using
226 * either of these, these channels are not available for the regular
227 * sampling. The shared channels are as follows:
228 *
229 * CH0 -- Touch button #0
230 * CH1 -- Touch button #1
231 * CH2 -- Touch screen XPUL
232 * CH3 -- Touch screen YPLL
233 * CH4 -- Touch screen XNUL
234 * CH5 -- Touch screen YNLR
235 * CH6 -- Touch screen WIPER (5-wire only)
236 *
237 * The bit fields below represents which parts of the LRADC block are
238 * switched into special mode of operation. These channels can not
239 * be sampled as regular LRADC channels. The driver will refuse any
240 * attempt to sample these channels.
241 */
242 #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0))
243 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
244 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
245 enum mxs_lradc_ts use_touchscreen;
246 bool use_touchbutton;
247
248 struct input_dev *ts_input;
249
250 enum mxs_lradc_id soc;
251 enum lradc_ts_plate cur_plate; /* state machine */
252 bool ts_valid;
253 unsigned ts_x_pos;
254 unsigned ts_y_pos;
255 unsigned ts_pressure;
256
257 /* handle touchscreen's physical behaviour */
258 /* samples per coordinate */
259 unsigned over_sample_cnt;
260 /* time clocks between samples */
261 unsigned over_sample_delay;
262 /* time in clocks to wait after the plates where switched */
263 unsigned settling_delay;
264 };
265
266 #define LRADC_CTRL0 0x00
267 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23)
268 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22)
269 # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21)
270 # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20)
271 # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19)
272 # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18)
273 # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17)
274 # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16)
275
276 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20)
277 # define LRADC_CTRL0_MX23_YM BIT(19)
278 # define LRADC_CTRL0_MX23_XM BIT(18)
279 # define LRADC_CTRL0_MX23_YP BIT(17)
280 # define LRADC_CTRL0_MX23_XP BIT(16)
281
282 # define LRADC_CTRL0_MX28_PLATE_MASK \
283 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
284 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
285 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
286 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
287
288 # define LRADC_CTRL0_MX23_PLATE_MASK \
289 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
290 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
291 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
292
293 #define LRADC_CTRL1 0x10
294 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24)
295 #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
296 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
297 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
298 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
299 #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8)
300 #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
301 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
302 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
303 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
304
305 #define LRADC_CTRL2 0x20
306 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
307 #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15)
308
309 #define LRADC_STATUS 0x40
310 #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
311
312 #define LRADC_CH(n) (0x50 + (0x10 * (n)))
313 #define LRADC_CH_ACCUMULATE BIT(29)
314 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
315 #define LRADC_CH_NUM_SAMPLES_OFFSET 24
316 #define LRADC_CH_NUM_SAMPLES(x) \
317 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
318 #define LRADC_CH_VALUE_MASK 0x3ffff
319 #define LRADC_CH_VALUE_OFFSET 0
320
321 #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
322 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24)
323 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
324 #define LRADC_DELAY_TRIGGER(x) \
325 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
326 LRADC_DELAY_TRIGGER_LRADCS_MASK)
327 #define LRADC_DELAY_KICK BIT(20)
328 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
329 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
330 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
331 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
332 LRADC_DELAY_TRIGGER_DELAYS_MASK)
333 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
334 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
335 #define LRADC_DELAY_LOOP(x) \
336 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
337 LRADC_DELAY_LOOP_COUNT_MASK)
338 #define LRADC_DELAY_DELAY_MASK 0x7ff
339 #define LRADC_DELAY_DELAY_OFFSET 0
340 #define LRADC_DELAY_DELAY(x) \
341 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
342 LRADC_DELAY_DELAY_MASK)
343
344 #define LRADC_CTRL4 0x140
345 #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
346 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
347 #define LRADC_CTRL4_LRADCSELECT(n, x) \
348 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
349 LRADC_CTRL4_LRADCSELECT_MASK(n))
350
351 #define LRADC_RESOLUTION 12
352 #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
353
354 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356 writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
357 }
358
359 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361 writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
362 }
363
364 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
365 {
366 writel(val, lradc->base + reg);
367 }
368
369 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
370 {
371 if (lradc->soc == IMX23_LRADC)
372 return LRADC_CTRL0_MX23_PLATE_MASK;
373 return LRADC_CTRL0_MX28_PLATE_MASK;
374 }
375
376 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
377 {
378 if (lradc->soc == IMX23_LRADC)
379 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
380 return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
381 }
382
383 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
384 {
385 if (lradc->soc == IMX23_LRADC)
386 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
387 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
388 }
389
390 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
391 {
392 if (lradc->soc == IMX23_LRADC)
393 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
394 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
395 }
396
397 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
398 {
399 if (lradc->soc == IMX23_LRADC)
400 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
401 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
402 }
403
404 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
405 {
406 if (lradc->soc == IMX23_LRADC)
407 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
408 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
409 }
410
411 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
412 {
413 if (lradc->soc == IMX23_LRADC)
414 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
415 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
416 }
417
418 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
419 {
420 return !!(readl(lradc->base + LRADC_STATUS) &
421 LRADC_STATUS_TOUCH_DETECT_RAW);
422 }
423
424 static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch,
425 unsigned ch)
426 {
427 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch),
428 LRADC_CTRL4);
429 mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4);
430 }
431
432 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
433 {
434 /*
435 * prepare for oversampling conversion
436 *
437 * from the datasheet:
438 * "The ACCUMULATE bit in the appropriate channel register
439 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
440 * otherwise, the IRQs will not fire."
441 */
442 mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
443 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
444 LRADC_CH(ch));
445
446 /*
447 * from the datasheet:
448 * "Software must clear this register in preparation for a
449 * multi-cycle accumulation.
450 */
451 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
452
453 /*
454 * prepare the delay/loop unit according to the oversampling count
455 *
456 * from the datasheet:
457 * "The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1,
458 * HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise,
459 * the LRADC will not trigger the delay group."
460 */
461 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
462 LRADC_DELAY_TRIGGER_DELAYS(0) |
463 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
464 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
465 LRADC_DELAY(3));
466
467 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1);
468
469 /*
470 * after changing the touchscreen plates setting
471 * the signals need some initial time to settle. Start the
472 * SoC's delay unit and start the conversion later
473 * and automatically.
474 */
475 mxs_lradc_reg_wrt(
476 lradc,
477 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
478 LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
479 LRADC_DELAY_KICK |
480 LRADC_DELAY_DELAY(lradc->settling_delay),
481 LRADC_DELAY(2));
482 }
483
484 /*
485 * Pressure detection is special:
486 * We want to do both required measurements for the pressure detection in
487 * one turn. Use the hardware features to chain both conversions and let the
488 * hardware report one interrupt if both conversions are done
489 */
490 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
491 unsigned ch2)
492 {
493 u32 reg;
494
495 /*
496 * prepare for oversampling conversion
497 *
498 * from the datasheet:
499 * "The ACCUMULATE bit in the appropriate channel register
500 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
501 * otherwise, the IRQs will not fire."
502 */
503 reg = LRADC_CH_ACCUMULATE |
504 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
505 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
506 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
507
508 /*
509 * from the datasheet:
510 * "Software must clear this register in preparation for a
511 * multi-cycle accumulation.
512 */
513 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
514 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
515
516 /* prepare the delay/loop unit according to the oversampling count */
517 mxs_lradc_reg_wrt(
518 lradc,
519 LRADC_DELAY_TRIGGER(1 << ch1) |
520 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
521 LRADC_DELAY_TRIGGER_DELAYS(0) |
522 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
523 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
524 LRADC_DELAY(3));
525
526 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1);
527
528 /*
529 * after changing the touchscreen plates setting
530 * the signals need some initial time to settle. Start the
531 * SoC's delay unit and start the conversion later
532 * and automatically.
533 */
534 mxs_lradc_reg_wrt(
535 lradc,
536 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
537 LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
538 LRADC_DELAY_KICK |
539 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
540 }
541
542 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
543 unsigned channel)
544 {
545 u32 reg;
546 unsigned num_samples, val;
547
548 reg = readl(lradc->base + LRADC_CH(channel));
549 if (reg & LRADC_CH_ACCUMULATE)
550 num_samples = lradc->over_sample_cnt;
551 else
552 num_samples = 1;
553
554 val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
555 return val / num_samples;
556 }
557
558 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
559 unsigned ch1, unsigned ch2)
560 {
561 u32 reg, mask;
562 unsigned pressure, m1, m2;
563
564 mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
565 reg = readl(lradc->base + LRADC_CTRL1) & mask;
566
567 while (reg != mask) {
568 reg = readl(lradc->base + LRADC_CTRL1) & mask;
569 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
570 }
571
572 m1 = mxs_lradc_read_raw_channel(lradc, ch1);
573 m2 = mxs_lradc_read_raw_channel(lradc, ch2);
574
575 if (m2 == 0) {
576 dev_warn(lradc->dev, "Cannot calculate pressure\n");
577 return 1 << (LRADC_RESOLUTION - 1);
578 }
579
580 /* simply scale the value from 0 ... max ADC resolution */
581 pressure = m1;
582 pressure *= (1 << LRADC_RESOLUTION);
583 pressure /= m2;
584
585 dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
586 return pressure;
587 }
588
589 #define TS_CH_XP 2
590 #define TS_CH_YP 3
591 #define TS_CH_XM 4
592 #define TS_CH_YM 5
593
594 /*
595 * YP(open)--+-------------+
596 * | |--+
597 * | | |
598 * YM(-)--+-------------+ |
599 * +--------------+
600 * | |
601 * XP(weak+) XM(open)
602 *
603 * "weak+" means 200k Ohm VDDIO
604 * (-) means GND
605 */
606 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
607 {
608 /*
609 * In order to detect a touch event the 'touch detect enable' bit
610 * enables:
611 * - a weak pullup to the X+ connector
612 * - a strong ground at the Y- connector
613 */
614 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
615 mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
616 LRADC_CTRL0);
617 }
618
619 /*
620 * YP(meas)--+-------------+
621 * | |--+
622 * | | |
623 * YM(open)--+-------------+ |
624 * +--------------+
625 * | |
626 * XP(+) XM(-)
627 *
628 * (+) means here 1.85 V
629 * (-) means here GND
630 */
631 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
632 {
633 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
634 mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
635
636 lradc->cur_plate = LRADC_SAMPLE_X;
637 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP);
638 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
639 }
640
641 /*
642 * YP(+)--+-------------+
643 * | |--+
644 * | | |
645 * YM(-)--+-------------+ |
646 * +--------------+
647 * | |
648 * XP(open) XM(meas)
649 *
650 * (+) means here 1.85 V
651 * (-) means here GND
652 */
653 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
654 {
655 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
656 mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
657
658 lradc->cur_plate = LRADC_SAMPLE_Y;
659 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM);
660 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
661 }
662
663 /*
664 * YP(+)--+-------------+
665 * | |--+
666 * | | |
667 * YM(meas)--+-------------+ |
668 * +--------------+
669 * | |
670 * XP(meas) XM(-)
671 *
672 * (+) means here 1.85 V
673 * (-) means here GND
674 */
675 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
676 {
677 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
678 mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
679
680 lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
681 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM);
682 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP);
683 mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2,
684 TOUCHSCREEN_VCHANNEL1);
685 }
686
687 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
688 {
689 mxs_lradc_setup_touch_detection(lradc);
690
691 lradc->cur_plate = LRADC_TOUCH;
692 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
693 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
694 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
695 }
696
697 static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc)
698 {
699 mxs_lradc_reg_clear(lradc,
700 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
701 LRADC_CTRL1);
702 mxs_lradc_reg_set(lradc,
703 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1),
704 LRADC_CTRL1);
705 /*
706 * start with the Y-pos, because it uses nearly the same plate
707 * settings like the touch detection
708 */
709 mxs_lradc_prepare_y_pos(lradc);
710 }
711
712 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
713 {
714 input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
715 input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
716 input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
717 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
718 input_sync(lradc->ts_input);
719 }
720
721 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
722 {
723 mxs_lradc_setup_touch_detection(lradc);
724 lradc->cur_plate = LRADC_SAMPLE_VALID;
725 /*
726 * start a dummy conversion to burn time to settle the signals
727 * note: we are not interested in the conversion's value
728 */
729 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1));
730 mxs_lradc_reg_clear(lradc,
731 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
732 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2),
733 LRADC_CTRL1);
734 mxs_lradc_reg_wrt(
735 lradc,
736 LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
737 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
738 LRADC_DELAY(2));
739 }
740
741 /*
742 * in order to avoid false measurements, report only samples where
743 * the surface is still touched after the position measurement
744 */
745 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
746 {
747 /* if it is still touched, report the sample */
748 if (valid && mxs_lradc_check_touch_event(lradc)) {
749 lradc->ts_valid = true;
750 mxs_lradc_report_ts_event(lradc);
751 }
752
753 /* if it is even still touched, continue with the next measurement */
754 if (mxs_lradc_check_touch_event(lradc)) {
755 mxs_lradc_prepare_y_pos(lradc);
756 return;
757 }
758
759 if (lradc->ts_valid) {
760 /* signal the release */
761 lradc->ts_valid = false;
762 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
763 input_sync(lradc->ts_input);
764 }
765
766 /* if it is released, wait for the next touch via IRQ */
767 lradc->cur_plate = LRADC_TOUCH;
768 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
769 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
770 mxs_lradc_reg_clear(lradc,
771 LRADC_CTRL1_TOUCH_DETECT_IRQ |
772 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
773 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1),
774 LRADC_CTRL1);
775 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
776 }
777
778 /* touchscreen's state machine */
779 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
780 {
781 switch (lradc->cur_plate) {
782 case LRADC_TOUCH:
783 if (mxs_lradc_check_touch_event(lradc))
784 mxs_lradc_start_touch_event(lradc);
785 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
786 LRADC_CTRL1);
787 return;
788
789 case LRADC_SAMPLE_Y:
790 lradc->ts_y_pos =
791 mxs_lradc_read_raw_channel(lradc,
792 TOUCHSCREEN_VCHANNEL1);
793 mxs_lradc_prepare_x_pos(lradc);
794 return;
795
796 case LRADC_SAMPLE_X:
797 lradc->ts_x_pos =
798 mxs_lradc_read_raw_channel(lradc,
799 TOUCHSCREEN_VCHANNEL1);
800 mxs_lradc_prepare_pressure(lradc);
801 return;
802
803 case LRADC_SAMPLE_PRESSURE:
804 lradc->ts_pressure =
805 mxs_lradc_read_ts_pressure(lradc,
806 TOUCHSCREEN_VCHANNEL2,
807 TOUCHSCREEN_VCHANNEL1);
808 mxs_lradc_complete_touch_event(lradc);
809 return;
810
811 case LRADC_SAMPLE_VALID:
812 mxs_lradc_finish_touch_event(lradc, 1);
813 break;
814 }
815 }
816
817 /*
818 * Raw I/O operations
819 */
820 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
821 {
822 struct mxs_lradc *lradc = iio_priv(iio_dev);
823 int ret;
824
825 /*
826 * See if there is no buffered operation in progress. If there is, simply
827 * bail out. This can be improved to support both buffered and raw IO at
828 * the same time, yet the code becomes horribly complicated. Therefore I
829 * applied KISS principle here.
830 */
831 ret = mutex_trylock(&lradc->lock);
832 if (!ret)
833 return -EBUSY;
834
835 reinit_completion(&lradc->completion);
836
837 /*
838 * No buffered operation in progress, map the channel and trigger it.
839 * Virtual channel 0 is always used here as the others are always not
840 * used if doing raw sampling.
841 */
842 if (lradc->soc == IMX28_LRADC)
843 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0),
844 LRADC_CTRL1);
845 mxs_lradc_reg_clear(lradc, 0x1, LRADC_CTRL0);
846
847 /* Enable / disable the divider per requirement */
848 if (test_bit(chan, &lradc->is_divided))
849 mxs_lradc_reg_set(lradc,
850 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
851 LRADC_CTRL2);
852 else
853 mxs_lradc_reg_clear(lradc,
854 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
855 LRADC_CTRL2);
856
857 /* Clean the slot's previous content, then set new one. */
858 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
859 LRADC_CTRL4);
860 mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
861
862 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
863
864 /* Enable the IRQ and start sampling the channel. */
865 mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
866 mxs_lradc_reg_set(lradc, BIT(0), LRADC_CTRL0);
867
868 /* Wait for completion on the channel, 1 second max. */
869 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
870 if (!ret)
871 ret = -ETIMEDOUT;
872 if (ret < 0)
873 goto err;
874
875 /* Read the data. */
876 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
877 ret = IIO_VAL_INT;
878
879 err:
880 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
881
882 mutex_unlock(&lradc->lock);
883
884 return ret;
885 }
886
887 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
888 {
889 int ret, min, max;
890
891 ret = mxs_lradc_read_single(iio_dev, 8, &min);
892 if (ret != IIO_VAL_INT)
893 return ret;
894
895 ret = mxs_lradc_read_single(iio_dev, 9, &max);
896 if (ret != IIO_VAL_INT)
897 return ret;
898
899 *val = max - min;
900
901 return IIO_VAL_INT;
902 }
903
904 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
905 const struct iio_chan_spec *chan,
906 int *val, int *val2, long m)
907 {
908 struct mxs_lradc *lradc = iio_priv(iio_dev);
909
910 switch (m) {
911 case IIO_CHAN_INFO_RAW:
912 if (chan->type == IIO_TEMP)
913 return mxs_lradc_read_temp(iio_dev, val);
914
915 return mxs_lradc_read_single(iio_dev, chan->channel, val);
916
917 case IIO_CHAN_INFO_SCALE:
918 if (chan->type == IIO_TEMP) {
919 /*
920 * From the datasheet, we have to multiply by 1.012 and
921 * divide by 4
922 */
923 *val = 0;
924 *val2 = 253000;
925 return IIO_VAL_INT_PLUS_MICRO;
926 }
927
928 *val = lradc->vref_mv[chan->channel];
929 *val2 = chan->scan_type.realbits -
930 test_bit(chan->channel, &lradc->is_divided);
931 return IIO_VAL_FRACTIONAL_LOG2;
932
933 case IIO_CHAN_INFO_OFFSET:
934 if (chan->type == IIO_TEMP) {
935 /*
936 * The calculated value from the ADC is in Kelvin, we
937 * want Celsius for hwmon so the offset is -273.15
938 * The offset is applied before scaling so it is
939 * actually -213.15 * 4 / 1.012 = -1079.644268
940 */
941 *val = -1079;
942 *val2 = 644268;
943
944 return IIO_VAL_INT_PLUS_MICRO;
945 }
946
947 return -EINVAL;
948
949 default:
950 break;
951 }
952
953 return -EINVAL;
954 }
955
956 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
957 const struct iio_chan_spec *chan,
958 int val, int val2, long m)
959 {
960 struct mxs_lradc *lradc = iio_priv(iio_dev);
961 struct mxs_lradc_scale *scale_avail =
962 lradc->scale_avail[chan->channel];
963 int ret;
964
965 ret = mutex_trylock(&lradc->lock);
966 if (!ret)
967 return -EBUSY;
968
969 switch (m) {
970 case IIO_CHAN_INFO_SCALE:
971 ret = -EINVAL;
972 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
973 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
974 /* divider by two disabled */
975 clear_bit(chan->channel, &lradc->is_divided);
976 ret = 0;
977 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
978 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
979 /* divider by two enabled */
980 set_bit(chan->channel, &lradc->is_divided);
981 ret = 0;
982 }
983
984 break;
985 default:
986 ret = -EINVAL;
987 break;
988 }
989
990 mutex_unlock(&lradc->lock);
991
992 return ret;
993 }
994
995 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
996 const struct iio_chan_spec *chan,
997 long m)
998 {
999 return IIO_VAL_INT_PLUS_NANO;
1000 }
1001
1002 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
1003 struct device_attribute *attr,
1004 char *buf,
1005 int ch)
1006 {
1007 struct iio_dev *iio = dev_to_iio_dev(dev);
1008 struct mxs_lradc *lradc = iio_priv(iio);
1009 int i, len = 0;
1010
1011 for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
1012 len += sprintf(buf + len, "%u.%09u ",
1013 lradc->scale_avail[ch][i].integer,
1014 lradc->scale_avail[ch][i].nano);
1015
1016 len += sprintf(buf + len, "\n");
1017
1018 return len;
1019 }
1020
1021 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1022 struct device_attribute *attr,
1023 char *buf)
1024 {
1025 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1026
1027 return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1028 iio_attr->address);
1029 }
1030
1031 #define SHOW_SCALE_AVAILABLE_ATTR(ch) \
1032 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \
1033 mxs_lradc_show_scale_available, NULL, ch)
1034
1035 SHOW_SCALE_AVAILABLE_ATTR(0);
1036 SHOW_SCALE_AVAILABLE_ATTR(1);
1037 SHOW_SCALE_AVAILABLE_ATTR(2);
1038 SHOW_SCALE_AVAILABLE_ATTR(3);
1039 SHOW_SCALE_AVAILABLE_ATTR(4);
1040 SHOW_SCALE_AVAILABLE_ATTR(5);
1041 SHOW_SCALE_AVAILABLE_ATTR(6);
1042 SHOW_SCALE_AVAILABLE_ATTR(7);
1043 SHOW_SCALE_AVAILABLE_ATTR(10);
1044 SHOW_SCALE_AVAILABLE_ATTR(11);
1045 SHOW_SCALE_AVAILABLE_ATTR(12);
1046 SHOW_SCALE_AVAILABLE_ATTR(13);
1047 SHOW_SCALE_AVAILABLE_ATTR(14);
1048 SHOW_SCALE_AVAILABLE_ATTR(15);
1049
1050 static struct attribute *mxs_lradc_attributes[] = {
1051 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1052 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1053 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1054 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1055 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1056 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1057 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1058 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1059 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1060 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1061 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1062 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1063 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1064 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1065 NULL
1066 };
1067
1068 static const struct attribute_group mxs_lradc_attribute_group = {
1069 .attrs = mxs_lradc_attributes,
1070 };
1071
1072 static const struct iio_info mxs_lradc_iio_info = {
1073 .driver_module = THIS_MODULE,
1074 .read_raw = mxs_lradc_read_raw,
1075 .write_raw = mxs_lradc_write_raw,
1076 .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt,
1077 .attrs = &mxs_lradc_attribute_group,
1078 };
1079
1080 static int mxs_lradc_ts_open(struct input_dev *dev)
1081 {
1082 struct mxs_lradc *lradc = input_get_drvdata(dev);
1083
1084 /* Enable the touch-detect circuitry. */
1085 mxs_lradc_enable_touch_detection(lradc);
1086
1087 return 0;
1088 }
1089
1090 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1091 {
1092 /* stop all interrupts from firing */
1093 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1094 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
1095 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
1096
1097 /* Power-down touchscreen touch-detect circuitry. */
1098 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1099 }
1100
1101 static void mxs_lradc_ts_close(struct input_dev *dev)
1102 {
1103 struct mxs_lradc *lradc = input_get_drvdata(dev);
1104
1105 mxs_lradc_disable_ts(lradc);
1106 }
1107
1108 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1109 {
1110 struct input_dev *input;
1111 struct device *dev = lradc->dev;
1112 int ret;
1113
1114 if (!lradc->use_touchscreen)
1115 return 0;
1116
1117 input = input_allocate_device();
1118 if (!input)
1119 return -ENOMEM;
1120
1121 input->name = DRIVER_NAME;
1122 input->id.bustype = BUS_HOST;
1123 input->dev.parent = dev;
1124 input->open = mxs_lradc_ts_open;
1125 input->close = mxs_lradc_ts_close;
1126
1127 __set_bit(EV_ABS, input->evbit);
1128 __set_bit(EV_KEY, input->evbit);
1129 __set_bit(BTN_TOUCH, input->keybit);
1130 input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1131 input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1132 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1133 0, 0);
1134
1135 lradc->ts_input = input;
1136 input_set_drvdata(input, lradc);
1137 ret = input_register_device(input);
1138 if (ret)
1139 input_free_device(lradc->ts_input);
1140
1141 return ret;
1142 }
1143
1144 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1145 {
1146 if (!lradc->use_touchscreen)
1147 return;
1148
1149 mxs_lradc_disable_ts(lradc);
1150 input_unregister_device(lradc->ts_input);
1151 }
1152
1153 /*
1154 * IRQ Handling
1155 */
1156 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1157 {
1158 struct iio_dev *iio = data;
1159 struct mxs_lradc *lradc = iio_priv(iio);
1160 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1161 u32 clr_irq = mxs_lradc_irq_mask(lradc);
1162 const u32 ts_irq_mask =
1163 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1164 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1165 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2);
1166
1167 if (!(reg & mxs_lradc_irq_mask(lradc)))
1168 return IRQ_NONE;
1169
1170 if (lradc->use_touchscreen && (reg & ts_irq_mask)) {
1171 mxs_lradc_handle_touch(lradc);
1172
1173 /* Make sure we don't clear the next conversion's interrupt. */
1174 clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1175 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2));
1176 }
1177
1178 if (iio_buffer_enabled(iio)) {
1179 if (reg & lradc->buffer_vchans)
1180 iio_trigger_poll(iio->trig);
1181 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
1182 complete(&lradc->completion);
1183 }
1184
1185 mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1);
1186
1187 return IRQ_HANDLED;
1188 }
1189
1190 /*
1191 * Trigger handling
1192 */
1193 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1194 {
1195 struct iio_poll_func *pf = p;
1196 struct iio_dev *iio = pf->indio_dev;
1197 struct mxs_lradc *lradc = iio_priv(iio);
1198 const u32 chan_value = LRADC_CH_ACCUMULATE |
1199 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1200 unsigned int i, j = 0;
1201
1202 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1203 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1204 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1205 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1206 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1207 j++;
1208 }
1209
1210 iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1211
1212 iio_trigger_notify_done(iio->trig);
1213
1214 return IRQ_HANDLED;
1215 }
1216
1217 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1218 {
1219 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1220 struct mxs_lradc *lradc = iio_priv(iio);
1221 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1222
1223 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1224
1225 return 0;
1226 }
1227
1228 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1229 .owner = THIS_MODULE,
1230 .set_trigger_state = &mxs_lradc_configure_trigger,
1231 };
1232
1233 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1234 {
1235 int ret;
1236 struct iio_trigger *trig;
1237 struct mxs_lradc *lradc = iio_priv(iio);
1238
1239 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1240 if (!trig)
1241 return -ENOMEM;
1242
1243 trig->dev.parent = lradc->dev;
1244 iio_trigger_set_drvdata(trig, iio);
1245 trig->ops = &mxs_lradc_trigger_ops;
1246
1247 ret = iio_trigger_register(trig);
1248 if (ret) {
1249 iio_trigger_free(trig);
1250 return ret;
1251 }
1252
1253 lradc->trig = trig;
1254
1255 return 0;
1256 }
1257
1258 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1259 {
1260 struct mxs_lradc *lradc = iio_priv(iio);
1261
1262 iio_trigger_unregister(lradc->trig);
1263 iio_trigger_free(lradc->trig);
1264 }
1265
1266 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1267 {
1268 struct mxs_lradc *lradc = iio_priv(iio);
1269 int ret = 0, chan, ofs = 0;
1270 unsigned long enable = 0;
1271 u32 ctrl4_set = 0;
1272 u32 ctrl4_clr = 0;
1273 u32 ctrl1_irq = 0;
1274 const u32 chan_value = LRADC_CH_ACCUMULATE |
1275 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1276 const int len = bitmap_weight(iio->active_scan_mask,
1277 LRADC_MAX_TOTAL_CHANS);
1278
1279 if (!len)
1280 return -EINVAL;
1281
1282 /*
1283 * Lock the driver so raw access can not be done during buffered
1284 * operation. This simplifies the code a lot.
1285 */
1286 ret = mutex_trylock(&lradc->lock);
1287 if (!ret)
1288 return -EBUSY;
1289
1290 lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1291 if (!lradc->buffer) {
1292 ret = -ENOMEM;
1293 goto err_mem;
1294 }
1295
1296 if (lradc->soc == IMX28_LRADC)
1297 mxs_lradc_reg_clear(
1298 lradc,
1299 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1300 LRADC_CTRL1);
1301 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1302
1303 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1304 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1305 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1306 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1307 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1308 bitmap_set(&enable, ofs, 1);
1309 ofs++;
1310 }
1311
1312 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1313 LRADC_DELAY_KICK, LRADC_DELAY(0));
1314 mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1315 mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1316 mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1317 mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1318 LRADC_DELAY(0));
1319
1320 return 0;
1321
1322 err_mem:
1323 mutex_unlock(&lradc->lock);
1324 return ret;
1325 }
1326
1327 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1328 {
1329 struct mxs_lradc *lradc = iio_priv(iio);
1330
1331 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1332 LRADC_DELAY_KICK, LRADC_DELAY(0));
1333
1334 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1335 if (lradc->soc == IMX28_LRADC)
1336 mxs_lradc_reg_clear(
1337 lradc,
1338 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1339 LRADC_CTRL1);
1340
1341 kfree(lradc->buffer);
1342 mutex_unlock(&lradc->lock);
1343
1344 return 0;
1345 }
1346
1347 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1348 const unsigned long *mask)
1349 {
1350 struct mxs_lradc *lradc = iio_priv(iio);
1351 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1352 int rsvd_chans = 0;
1353 unsigned long rsvd_mask = 0;
1354
1355 if (lradc->use_touchbutton)
1356 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1357 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1358 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1359 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1360 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1361
1362 if (lradc->use_touchbutton)
1363 rsvd_chans++;
1364 if (lradc->use_touchscreen)
1365 rsvd_chans += 2;
1366
1367 /* Test for attempts to map channels with special mode of operation. */
1368 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1369 return false;
1370
1371 /* Test for attempts to map more channels then available slots. */
1372 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1373 return false;
1374
1375 return true;
1376 }
1377
1378 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1379 .preenable = &mxs_lradc_buffer_preenable,
1380 .postenable = &iio_triggered_buffer_postenable,
1381 .predisable = &iio_triggered_buffer_predisable,
1382 .postdisable = &mxs_lradc_buffer_postdisable,
1383 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1384 };
1385
1386 /*
1387 * Driver initialization
1388 */
1389
1390 #define MXS_ADC_CHAN(idx, chan_type, name) { \
1391 .type = (chan_type), \
1392 .indexed = 1, \
1393 .scan_index = (idx), \
1394 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1395 BIT(IIO_CHAN_INFO_SCALE), \
1396 .channel = (idx), \
1397 .address = (idx), \
1398 .scan_type = { \
1399 .sign = 'u', \
1400 .realbits = LRADC_RESOLUTION, \
1401 .storagebits = 32, \
1402 }, \
1403 .datasheet_name = (name), \
1404 }
1405
1406 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
1407 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
1408 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
1409 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
1410 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
1411 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
1412 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
1413 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
1414 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
1415 /* Combined Temperature sensors */
1416 {
1417 .type = IIO_TEMP,
1418 .indexed = 1,
1419 .scan_index = 8,
1420 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1421 BIT(IIO_CHAN_INFO_OFFSET) |
1422 BIT(IIO_CHAN_INFO_SCALE),
1423 .channel = 8,
1424 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1425 .datasheet_name = "TEMP_DIE",
1426 },
1427 /* Hidden channel to keep indexes */
1428 {
1429 .type = IIO_TEMP,
1430 .indexed = 1,
1431 .scan_index = -1,
1432 .channel = 9,
1433 },
1434 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
1435 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
1436 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
1437 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
1438 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
1439 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
1440 };
1441
1442 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
1443 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
1444 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
1445 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
1446 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
1447 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
1448 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
1449 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
1450 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
1451 /* Combined Temperature sensors */
1452 {
1453 .type = IIO_TEMP,
1454 .indexed = 1,
1455 .scan_index = 8,
1456 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1457 BIT(IIO_CHAN_INFO_OFFSET) |
1458 BIT(IIO_CHAN_INFO_SCALE),
1459 .channel = 8,
1460 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1461 .datasheet_name = "TEMP_DIE",
1462 },
1463 /* Hidden channel to keep indexes */
1464 {
1465 .type = IIO_TEMP,
1466 .indexed = 1,
1467 .scan_index = -1,
1468 .channel = 9,
1469 },
1470 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
1471 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
1472 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
1473 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
1474 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
1475 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
1476 };
1477
1478 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1479 {
1480 /* The ADC always uses DELAY CHANNEL 0. */
1481 const u32 adc_cfg =
1482 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1483 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1484
1485 int ret = stmp_reset_block(lradc->base);
1486
1487 if (ret)
1488 return ret;
1489
1490 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1491 mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1492
1493 /* Disable remaining DELAY CHANNELs */
1494 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1495 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1496 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1497
1498 /* Configure the touchscreen type */
1499 if (lradc->soc == IMX28_LRADC) {
1500 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1501 LRADC_CTRL0);
1502
1503 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1504 mxs_lradc_reg_set(lradc,
1505 LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1506 LRADC_CTRL0);
1507 }
1508
1509 /* Start internal temperature sensing. */
1510 mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1511
1512 return 0;
1513 }
1514
1515 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1516 {
1517 int i;
1518
1519 mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1520
1521 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1522 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1523 }
1524
1525 static const struct of_device_id mxs_lradc_dt_ids[] = {
1526 { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1527 { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1528 { /* sentinel */ }
1529 };
1530 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1531
1532 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1533 struct device_node *lradc_node)
1534 {
1535 int ret;
1536 u32 ts_wires = 0, adapt;
1537
1538 ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1539 &ts_wires);
1540 if (ret)
1541 return -ENODEV; /* touchscreen feature disabled */
1542
1543 switch (ts_wires) {
1544 case 4:
1545 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1546 break;
1547 case 5:
1548 if (lradc->soc == IMX28_LRADC) {
1549 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1550 break;
1551 }
1552 /* fall through an error message for i.MX23 */
1553 default:
1554 dev_err(lradc->dev,
1555 "Unsupported number of touchscreen wires (%d)\n",
1556 ts_wires);
1557 return -EINVAL;
1558 }
1559
1560 if (of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt)) {
1561 lradc->over_sample_cnt = 4;
1562 } else {
1563 if (adapt < 1 || adapt > 32) {
1564 dev_err(lradc->dev, "Invalid sample count (%u)\n",
1565 adapt);
1566 return -EINVAL;
1567 }
1568 lradc->over_sample_cnt = adapt;
1569 }
1570
1571 if (of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt)) {
1572 lradc->over_sample_delay = 2;
1573 } else {
1574 if (adapt < 2 || adapt > LRADC_DELAY_DELAY_MASK + 1) {
1575 dev_err(lradc->dev, "Invalid sample delay (%u)\n",
1576 adapt);
1577 return -EINVAL;
1578 }
1579 lradc->over_sample_delay = adapt;
1580 }
1581
1582 if (of_property_read_u32(lradc_node, "fsl,settling", &adapt)) {
1583 lradc->settling_delay = 10;
1584 } else {
1585 if (adapt < 1 || adapt > LRADC_DELAY_DELAY_MASK) {
1586 dev_err(lradc->dev, "Invalid settling delay (%u)\n",
1587 adapt);
1588 return -EINVAL;
1589 }
1590 lradc->settling_delay = adapt;
1591 }
1592
1593 return 0;
1594 }
1595
1596 static int mxs_lradc_probe(struct platform_device *pdev)
1597 {
1598 const struct of_device_id *of_id =
1599 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1600 const struct mxs_lradc_of_config *of_cfg =
1601 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1602 struct device *dev = &pdev->dev;
1603 struct device_node *node = dev->of_node;
1604 struct mxs_lradc *lradc;
1605 struct iio_dev *iio;
1606 struct resource *iores;
1607 int ret = 0, touch_ret;
1608 int i, s;
1609 u64 scale_uv;
1610
1611 /* Allocate the IIO device. */
1612 iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1613 if (!iio) {
1614 dev_err(dev, "Failed to allocate IIO device\n");
1615 return -ENOMEM;
1616 }
1617
1618 lradc = iio_priv(iio);
1619 lradc->soc = (enum mxs_lradc_id)of_id->data;
1620
1621 /* Grab the memory area */
1622 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623 lradc->dev = &pdev->dev;
1624 lradc->base = devm_ioremap_resource(dev, iores);
1625 if (IS_ERR(lradc->base))
1626 return PTR_ERR(lradc->base);
1627
1628 lradc->clk = devm_clk_get(&pdev->dev, NULL);
1629 if (IS_ERR(lradc->clk)) {
1630 dev_err(dev, "Failed to get the delay unit clock\n");
1631 return PTR_ERR(lradc->clk);
1632 }
1633 ret = clk_prepare_enable(lradc->clk);
1634 if (ret != 0) {
1635 dev_err(dev, "Failed to enable the delay unit clock\n");
1636 return ret;
1637 }
1638
1639 touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1640
1641 if (touch_ret == 0)
1642 lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
1643 else
1644 lradc->buffer_vchans = BUFFER_VCHANS_ALL;
1645
1646 /* Grab all IRQ sources */
1647 for (i = 0; i < of_cfg->irq_count; i++) {
1648 lradc->irq[i] = platform_get_irq(pdev, i);
1649 if (lradc->irq[i] < 0) {
1650 ret = lradc->irq[i];
1651 goto err_clk;
1652 }
1653
1654 ret = devm_request_irq(dev, lradc->irq[i],
1655 mxs_lradc_handle_irq, 0,
1656 of_cfg->irq_name[i], iio);
1657 if (ret)
1658 goto err_clk;
1659 }
1660
1661 lradc->vref_mv = of_cfg->vref_mv;
1662
1663 platform_set_drvdata(pdev, iio);
1664
1665 init_completion(&lradc->completion);
1666 mutex_init(&lradc->lock);
1667
1668 iio->name = pdev->name;
1669 iio->dev.parent = &pdev->dev;
1670 iio->info = &mxs_lradc_iio_info;
1671 iio->modes = INDIO_DIRECT_MODE;
1672 iio->masklength = LRADC_MAX_TOTAL_CHANS;
1673
1674 if (lradc->soc == IMX23_LRADC) {
1675 iio->channels = mx23_lradc_chan_spec;
1676 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
1677 } else {
1678 iio->channels = mx28_lradc_chan_spec;
1679 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
1680 }
1681
1682 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1683 &mxs_lradc_trigger_handler,
1684 &mxs_lradc_buffer_ops);
1685 if (ret)
1686 goto err_clk;
1687
1688 ret = mxs_lradc_trigger_init(iio);
1689 if (ret)
1690 goto err_trig;
1691
1692 /* Populate available ADC input ranges */
1693 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1694 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1695 /*
1696 * [s=0] = optional divider by two disabled (default)
1697 * [s=1] = optional divider by two enabled
1698 *
1699 * The scale is calculated by doing:
1700 * Vref >> (realbits - s)
1701 * which multiplies by two on the second component
1702 * of the array.
1703 */
1704 scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1705 (LRADC_RESOLUTION - s);
1706 lradc->scale_avail[i][s].nano =
1707 do_div(scale_uv, 100000000) * 10;
1708 lradc->scale_avail[i][s].integer = scale_uv;
1709 }
1710 }
1711
1712 /* Configure the hardware. */
1713 ret = mxs_lradc_hw_init(lradc);
1714 if (ret)
1715 goto err_dev;
1716
1717 /* Register the touchscreen input device. */
1718 if (touch_ret == 0) {
1719 ret = mxs_lradc_ts_register(lradc);
1720 if (ret)
1721 goto err_ts_register;
1722 }
1723
1724 /* Register IIO device. */
1725 ret = iio_device_register(iio);
1726 if (ret) {
1727 dev_err(dev, "Failed to register IIO device\n");
1728 goto err_ts;
1729 }
1730
1731 return 0;
1732
1733 err_ts:
1734 mxs_lradc_ts_unregister(lradc);
1735 err_ts_register:
1736 mxs_lradc_hw_stop(lradc);
1737 err_dev:
1738 mxs_lradc_trigger_remove(iio);
1739 err_trig:
1740 iio_triggered_buffer_cleanup(iio);
1741 err_clk:
1742 clk_disable_unprepare(lradc->clk);
1743 return ret;
1744 }
1745
1746 static int mxs_lradc_remove(struct platform_device *pdev)
1747 {
1748 struct iio_dev *iio = platform_get_drvdata(pdev);
1749 struct mxs_lradc *lradc = iio_priv(iio);
1750
1751 iio_device_unregister(iio);
1752 mxs_lradc_ts_unregister(lradc);
1753 mxs_lradc_hw_stop(lradc);
1754 mxs_lradc_trigger_remove(iio);
1755 iio_triggered_buffer_cleanup(iio);
1756
1757 clk_disable_unprepare(lradc->clk);
1758
1759 return 0;
1760 }
1761
1762 static struct platform_driver mxs_lradc_driver = {
1763 .driver = {
1764 .name = DRIVER_NAME,
1765 .of_match_table = mxs_lradc_dt_ids,
1766 },
1767 .probe = mxs_lradc_probe,
1768 .remove = mxs_lradc_remove,
1769 };
1770
1771 module_platform_driver(mxs_lradc_driver);
1772
1773 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1774 MODULE_DESCRIPTION("Freescale MXS LRADC driver");
1775 MODULE_LICENSE("GPL v2");
1776 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
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