drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /*
   2 * Copyright (C) 2012 Invensense, Inc.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 #include <linux/i2c.h>
  14 #include <linux/kfifo.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/iio/iio.h>
  17 #include <linux/iio/buffer.h>
  18 #include <linux/regmap.h>
  19 #include <linux/iio/sysfs.h>
  20 #include <linux/iio/kfifo_buf.h>
  21 #include <linux/iio/trigger.h>
  22 #include <linux/iio/triggered_buffer.h>
  23 #include <linux/iio/trigger_consumer.h>
  24 #include <linux/platform_data/invensense_mpu6050.h>
  25
  26 /**
  27  *  struct inv_mpu6050_reg_map - Notable registers.
  28  *  @sample_rate_div:   Divider applied to gyro output rate.
  29  *  @lpf:               Configures internal low pass filter.
  30  *  @user_ctrl:         Enables/resets the FIFO.
  31  *  @fifo_en:           Determines which data will appear in FIFO.
  32  *  @gyro_config:       gyro config register.
  33  *  @accl_config:       accel config register
  34  *  @fifo_count_h:      Upper byte of FIFO count.
  35  *  @fifo_r_w:          FIFO register.
  36  *  @raw_gyro:          Address of first gyro register.
  37  *  @raw_accl:          Address of first accel register.
  38  *  @temperature:       temperature register
  39  *  @int_enable:        Interrupt enable register.
  40  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  41  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  42  */
  43 struct inv_mpu6050_reg_map {
  44         u8 sample_rate_div;
  45         u8 lpf;
  46         u8 user_ctrl;
  47         u8 fifo_en;
  48         u8 gyro_config;
  49         u8 accl_config;
  50         u8 fifo_count_h;
  51         u8 fifo_r_w;
  52         u8 raw_gyro;
  53         u8 raw_accl;
  54         u8 temperature;
  55         u8 int_enable;
  56         u8 pwr_mgmt_1;
  57         u8 pwr_mgmt_2;
  58         u8 int_pin_cfg;
  59 };
  60
  61 /*device enum */
  62 enum inv_devices {
  63         INV_MPU6050,
  64         INV_MPU6500,
  65         INV_NUM_PARTS
  66 };
  67
  68 /**
  69  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  70  *  @fsr:               Full scale range.
  71  *  @lpf:               Digital low pass filter frequency.
  72  *  @accl_fs:           accel full scale range.
  73  *  @enable:            master enable state.
  74  *  @accl_fifo_enable:  enable accel data output
  75  *  @gyro_fifo_enable:  enable gyro data output
  76  *  @fifo_rate:         FIFO update rate.
  77  */
  78 struct inv_mpu6050_chip_config {
  79         unsigned int fsr:2;
  80         unsigned int lpf:3;
  81         unsigned int accl_fs:2;
  82         unsigned int enable:1;
  83         unsigned int accl_fifo_enable:1;
  84         unsigned int gyro_fifo_enable:1;
  85         u16 fifo_rate;
  86 };
  87
  88 /**
  89  *  struct inv_mpu6050_hw - Other important hardware information.
  90  *  @num_reg:   Number of registers on device.
  91  *  @name:      name of the chip.
  92  *  @reg:   register map of the chip.
  93  *  @config:    configuration of the chip.
  94  */
  95 struct inv_mpu6050_hw {
  96         u8 num_reg;
  97         u8 *name;
  98         const struct inv_mpu6050_reg_map *reg;
  99         const struct inv_mpu6050_chip_config *config;
 100 };
 101
 102 /*
 103  *  struct inv_mpu6050_state - Driver state variables.
 104  *  @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
 105  *  @trig:              IIO trigger.
 106  *  @chip_config:       Cached attribute information.
 107  *  @reg:               Map of important registers.
 108  *  @hw:                Other hardware-specific information.
 109  *  @chip_type:         chip type.
 110  *  @time_stamp_lock:   spin lock to time stamp.
 111  *  @plat_data:         platform data.
 112  *  @timestamps:        kfifo queue to store time stamp.
 113  *  @map                regmap pointer.
 114  *  @irq                interrupt number.
 115  */
 116 struct inv_mpu6050_state {
 117 #define TIMESTAMP_FIFO_SIZE 16
 118         struct iio_trigger  *trig;
 119         struct inv_mpu6050_chip_config chip_config;
 120         const struct inv_mpu6050_reg_map *reg;
 121         const struct inv_mpu6050_hw *hw;
 122         enum   inv_devices chip_type;
 123         spinlock_t time_stamp_lock;
 124         struct i2c_adapter *mux_adapter;
 125         struct i2c_client *mux_client;
 126         unsigned int powerup_count;
 127         struct inv_mpu6050_platform_data plat_data;
 128         DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
 129         struct regmap *map;
 130         int irq;
 131 };
 132
 133 /*register and associated bit definition*/
 134 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 135 #define INV_MPU6050_REG_CONFIG              0x1A
 136 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 137 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 138
 139 #define INV_MPU6050_REG_FIFO_EN             0x23
 140 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 141 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 142
 143 #define INV_MPU6050_REG_INT_ENABLE          0x38
 144 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 145 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 146
 147 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 148 #define INV_MPU6050_REG_TEMPERATURE         0x41
 149 #define INV_MPU6050_REG_RAW_GYRO            0x43
 150
 151 #define INV_MPU6050_REG_USER_CTRL           0x6A
 152 #define INV_MPU6050_BIT_FIFO_RST            0x04
 153 #define INV_MPU6050_BIT_DMP_RST             0x08
 154 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 155 #define INV_MPU6050_BIT_FIFO_EN             0x40
 156 #define INV_MPU6050_BIT_DMP_EN              0x80
 157
 158 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 159 #define INV_MPU6050_BIT_H_RESET             0x80
 160 #define INV_MPU6050_BIT_SLEEP               0x40
 161 #define INV_MPU6050_BIT_CLK_MASK            0x7
 162
 163 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 164 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 165 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 166
 167 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 168 #define INV_MPU6050_REG_FIFO_R_W            0x74
 169
 170 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 171 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 172 #define INV_MPU6050_FIFO_THRESHOLD           500
 173 #define INV_MPU6050_POWER_UP_TIME            100
 174 #define INV_MPU6050_TEMP_UP_TIME             100
 175 #define INV_MPU6050_SENSOR_UP_TIME           30
 176 #define INV_MPU6050_REG_UP_TIME              5
 177
 178 #define INV_MPU6050_TEMP_OFFSET              12421
 179 #define INV_MPU6050_TEMP_SCALE               2941
 180 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 181 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 182 #define INV_MPU6050_THREE_AXIS               3
 183 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 184 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 185
 186 /* 6 + 6 round up and plus 8 */
 187 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 188
 189 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 190 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 191 #define INV_MPU6050_INT_PIN_CFG         0
 192
 193 /* init parameters */
 194 #define INV_MPU6050_INIT_FIFO_RATE           50
 195 #define INV_MPU6050_TIME_STAMP_TOR           5
 196 #define INV_MPU6050_MAX_FIFO_RATE            1000
 197 #define INV_MPU6050_MIN_FIFO_RATE            4
 198 #define INV_MPU6050_ONE_K_HZ                 1000
 199
 200 /* scan element definition */
 201 enum inv_mpu6050_scan {
 202         INV_MPU6050_SCAN_ACCL_X,
 203         INV_MPU6050_SCAN_ACCL_Y,
 204         INV_MPU6050_SCAN_ACCL_Z,
 205         INV_MPU6050_SCAN_GYRO_X,
 206         INV_MPU6050_SCAN_GYRO_Y,
 207         INV_MPU6050_SCAN_GYRO_Z,
 208         INV_MPU6050_SCAN_TIMESTAMP,
 209 };
 210
 211 enum inv_mpu6050_filter_e {
 212         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 213         INV_MPU6050_FILTER_188HZ,
 214         INV_MPU6050_FILTER_98HZ,
 215         INV_MPU6050_FILTER_42HZ,
 216         INV_MPU6050_FILTER_20HZ,
 217         INV_MPU6050_FILTER_10HZ,
 218         INV_MPU6050_FILTER_5HZ,
 219         INV_MPU6050_FILTER_2100HZ_NOLPF,
 220         NUM_MPU6050_FILTER
 221 };
 222
 223 /* IIO attribute address */
 224 enum INV_MPU6050_IIO_ATTR_ADDR {
 225         ATTR_GYRO_MATRIX,
 226         ATTR_ACCL_MATRIX,
 227 };
 228
 229 enum inv_mpu6050_accl_fs_e {
 230         INV_MPU6050_FS_02G = 0,
 231         INV_MPU6050_FS_04G,
 232         INV_MPU6050_FS_08G,
 233         INV_MPU6050_FS_16G,
 234         NUM_ACCL_FSR
 235 };
 236
 237 enum inv_mpu6050_fsr_e {
 238         INV_MPU6050_FSR_250DPS = 0,
 239         INV_MPU6050_FSR_500DPS,
 240         INV_MPU6050_FSR_1000DPS,
 241         INV_MPU6050_FSR_2000DPS,
 242         NUM_MPU6050_FSR
 243 };
 244
 245 enum inv_mpu6050_clock_sel_e {
 246         INV_CLK_INTERNAL = 0,
 247         INV_CLK_PLL,
 248         NUM_CLK
 249 };
 250
 251 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
 252 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 253 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
 254 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
 255 int inv_reset_fifo(struct iio_dev *indio_dev);
 256 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 257 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 258 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 259 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 260 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 261 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name);
 262 int inv_mpu_core_remove(struct device *dev);
 263 extern const struct dev_pm_ops inv_mpu_pmops;