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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / drivers / infiniband / hw / cxgb4 / qp.c
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
44
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
56
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
62 {
63 int ret = 0;
64
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
68 else
69 ret = -ENOMEM;
70 spin_unlock_irq(&dev->lock);
71
72 if (ret)
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
75
76 return ret;
77 }
78
79 static void free_ird(struct c4iw_dev *dev, int ird)
80 {
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
84 }
85
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
87 {
88 unsigned long flag;
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
92 }
93
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
95 {
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
97 }
98
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100 {
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
103 }
104
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
106 {
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
109 else
110 dealloc_host_sq(rdev, sq);
111 }
112
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
114 {
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
116 return -ENOSYS;
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
118 if (!sq->dma_addr)
119 return -ENOMEM;
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
125 return 0;
126 }
127
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
129 {
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
132 if (!sq->queue)
133 return -ENOMEM;
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
136 return 0;
137 }
138
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
140 {
141 int ret = -ENOSYS;
142 if (user)
143 ret = alloc_oc_sq(rdev, sq);
144 if (ret)
145 ret = alloc_host_sq(rdev, sq);
146 return ret;
147 }
148
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
151 {
152 /*
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
155 */
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
161 kfree(wq->rq.sw_rq);
162 kfree(wq->sq.sw_sq);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
165 return 0;
166 }
167
168 /*
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
171 * for mapping.
172 */
173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
176 {
177 u64 bar2_qoffset;
178 int ret;
179
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
181 pbar2_pa ? 1 : 0,
182 &bar2_qoffset, pbar2_qid);
183 if (ret)
184 return NULL;
185
186 if (pbar2_pa)
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
188
189 if (is_t4(rdev->lldi.adapter_type))
190 return NULL;
191
192 return rdev->bar2_kva + bar2_qoffset;
193 }
194
195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx)
198 {
199 int user = (uctx != &rdev->uctx);
200 struct fw_ri_res_wr *res_wr;
201 struct fw_ri_res *res;
202 int wr_len;
203 struct c4iw_wr_wait wr_wait;
204 struct sk_buff *skb;
205 int ret = 0;
206 int eqsize;
207
208 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
209 if (!wq->sq.qid)
210 return -ENOMEM;
211
212 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
213 if (!wq->rq.qid) {
214 ret = -ENOMEM;
215 goto free_sq_qid;
216 }
217
218 if (!user) {
219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
220 GFP_KERNEL);
221 if (!wq->sq.sw_sq) {
222 ret = -ENOMEM;
223 goto free_rq_qid;
224 }
225
226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
227 GFP_KERNEL);
228 if (!wq->rq.sw_rq) {
229 ret = -ENOMEM;
230 goto free_sw_sq;
231 }
232 }
233
234 /*
235 * RQT must be a power of 2 and at least 16 deep.
236 */
237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
239 if (!wq->rq.rqt_hwaddr) {
240 ret = -ENOMEM;
241 goto free_sw_rq;
242 }
243
244 ret = alloc_sq(rdev, &wq->sq, user);
245 if (ret)
246 goto free_hwaddr;
247 memset(wq->sq.queue, 0, wq->sq.memsize);
248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
249
250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
251 wq->rq.memsize, &(wq->rq.dma_addr),
252 GFP_KERNEL);
253 if (!wq->rq.queue) {
254 ret = -ENOMEM;
255 goto free_sq;
256 }
257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__, wq->sq.queue,
259 (unsigned long long)virt_to_phys(wq->sq.queue),
260 wq->rq.queue,
261 (unsigned long long)virt_to_phys(wq->rq.queue));
262 memset(wq->rq.queue, 0, wq->rq.memsize);
263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
264
265 wq->db = rdev->lldi.db_reg;
266
267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
268 &wq->sq.bar2_qid,
269 user ? &wq->sq.bar2_pa : NULL);
270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
271 &wq->rq.bar2_qid,
272 user ? &wq->rq.bar2_pa : NULL);
273
274 /*
275 * User mode must have bar2 access.
276 */
277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
278 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n",
279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
280 goto free_dma;
281 }
282
283 wq->rdev = rdev;
284 wq->rq.msn = 1;
285
286 /* build fw_ri_res_wr */
287 wr_len = sizeof *res_wr + 2 * sizeof *res;
288
289 skb = alloc_skb(wr_len, GFP_KERNEL);
290 if (!skb) {
291 ret = -ENOMEM;
292 goto free_dma;
293 }
294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
295
296 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
297 memset(res_wr, 0, wr_len);
298 res_wr->op_nres = cpu_to_be32(
299 FW_WR_OP_V(FW_RI_RES_WR) |
300 FW_RI_RES_WR_NRES_V(2) |
301 FW_WR_COMPL_F);
302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
303 res_wr->cookie = (uintptr_t)&wr_wait;
304 res = res_wr->res;
305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
306 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
307
308 /*
309 * eqsize is the number of 64B entries plus the status page size.
310 */
311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
312 rdev->hw_queue.t4_eq_status_entries;
313
314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
319 FW_RI_RES_WR_IQID_V(scq->cqid));
320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
321 FW_RI_RES_WR_DCAEN_V(0) |
322 FW_RI_RES_WR_DCACPU_V(0) |
323 FW_RI_RES_WR_FBMIN_V(2) |
324 FW_RI_RES_WR_FBMAX_V(2) |
325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
326 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
327 FW_RI_RES_WR_EQSIZE_V(eqsize));
328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
330 res++;
331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
332 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
333
334 /*
335 * eqsize is the number of 64B entries plus the status page size.
336 */
337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
338 rdev->hw_queue.t4_eq_status_entries;
339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
343 FW_RI_RES_WR_IQID_V(rcq->cqid));
344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
345 FW_RI_RES_WR_DCAEN_V(0) |
346 FW_RI_RES_WR_DCACPU_V(0) |
347 FW_RI_RES_WR_FBMIN_V(2) |
348 FW_RI_RES_WR_FBMAX_V(2) |
349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
350 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
351 FW_RI_RES_WR_EQSIZE_V(eqsize));
352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
354
355 c4iw_init_wr_wait(&wr_wait);
356
357 ret = c4iw_ofld_send(rdev, skb);
358 if (ret)
359 goto free_dma;
360 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
361 if (ret)
362 goto free_dma;
363
364 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
365 __func__, wq->sq.qid, wq->rq.qid, wq->db,
366 wq->sq.bar2_va, wq->rq.bar2_va);
367
368 return 0;
369 free_dma:
370 dma_free_coherent(&(rdev->lldi.pdev->dev),
371 wq->rq.memsize, wq->rq.queue,
372 dma_unmap_addr(&wq->rq, mapping));
373 free_sq:
374 dealloc_sq(rdev, &wq->sq);
375 free_hwaddr:
376 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
377 free_sw_rq:
378 kfree(wq->rq.sw_rq);
379 free_sw_sq:
380 kfree(wq->sq.sw_sq);
381 free_rq_qid:
382 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
383 free_sq_qid:
384 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
385 return ret;
386 }
387
388 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
389 struct ib_send_wr *wr, int max, u32 *plenp)
390 {
391 u8 *dstp, *srcp;
392 u32 plen = 0;
393 int i;
394 int rem, len;
395
396 dstp = (u8 *)immdp->data;
397 for (i = 0; i < wr->num_sge; i++) {
398 if ((plen + wr->sg_list[i].length) > max)
399 return -EMSGSIZE;
400 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
401 plen += wr->sg_list[i].length;
402 rem = wr->sg_list[i].length;
403 while (rem) {
404 if (dstp == (u8 *)&sq->queue[sq->size])
405 dstp = (u8 *)sq->queue;
406 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
407 len = rem;
408 else
409 len = (u8 *)&sq->queue[sq->size] - dstp;
410 memcpy(dstp, srcp, len);
411 dstp += len;
412 srcp += len;
413 rem -= len;
414 }
415 }
416 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
417 if (len)
418 memset(dstp, 0, len);
419 immdp->op = FW_RI_DATA_IMMD;
420 immdp->r1 = 0;
421 immdp->r2 = 0;
422 immdp->immdlen = cpu_to_be32(plen);
423 *plenp = plen;
424 return 0;
425 }
426
427 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
428 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
429 int num_sge, u32 *plenp)
430
431 {
432 int i;
433 u32 plen = 0;
434 __be64 *flitp = (__be64 *)isglp->sge;
435
436 for (i = 0; i < num_sge; i++) {
437 if ((plen + sg_list[i].length) < plen)
438 return -EMSGSIZE;
439 plen += sg_list[i].length;
440 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
441 sg_list[i].length);
442 if (++flitp == queue_end)
443 flitp = queue_start;
444 *flitp = cpu_to_be64(sg_list[i].addr);
445 if (++flitp == queue_end)
446 flitp = queue_start;
447 }
448 *flitp = (__force __be64)0;
449 isglp->op = FW_RI_DATA_ISGL;
450 isglp->r1 = 0;
451 isglp->nsge = cpu_to_be16(num_sge);
452 isglp->r2 = 0;
453 if (plenp)
454 *plenp = plen;
455 return 0;
456 }
457
458 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
459 struct ib_send_wr *wr, u8 *len16)
460 {
461 u32 plen;
462 int size;
463 int ret;
464
465 if (wr->num_sge > T4_MAX_SEND_SGE)
466 return -EINVAL;
467 switch (wr->opcode) {
468 case IB_WR_SEND:
469 if (wr->send_flags & IB_SEND_SOLICITED)
470 wqe->send.sendop_pkd = cpu_to_be32(
471 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
472 else
473 wqe->send.sendop_pkd = cpu_to_be32(
474 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
475 wqe->send.stag_inv = 0;
476 break;
477 case IB_WR_SEND_WITH_INV:
478 if (wr->send_flags & IB_SEND_SOLICITED)
479 wqe->send.sendop_pkd = cpu_to_be32(
480 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
481 else
482 wqe->send.sendop_pkd = cpu_to_be32(
483 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
484 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
485 break;
486
487 default:
488 return -EINVAL;
489 }
490 wqe->send.r3 = 0;
491 wqe->send.r4 = 0;
492
493 plen = 0;
494 if (wr->num_sge) {
495 if (wr->send_flags & IB_SEND_INLINE) {
496 ret = build_immd(sq, wqe->send.u.immd_src, wr,
497 T4_MAX_SEND_INLINE, &plen);
498 if (ret)
499 return ret;
500 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
501 plen;
502 } else {
503 ret = build_isgl((__be64 *)sq->queue,
504 (__be64 *)&sq->queue[sq->size],
505 wqe->send.u.isgl_src,
506 wr->sg_list, wr->num_sge, &plen);
507 if (ret)
508 return ret;
509 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
510 wr->num_sge * sizeof(struct fw_ri_sge);
511 }
512 } else {
513 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
514 wqe->send.u.immd_src[0].r1 = 0;
515 wqe->send.u.immd_src[0].r2 = 0;
516 wqe->send.u.immd_src[0].immdlen = 0;
517 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
518 plen = 0;
519 }
520 *len16 = DIV_ROUND_UP(size, 16);
521 wqe->send.plen = cpu_to_be32(plen);
522 return 0;
523 }
524
525 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
526 struct ib_send_wr *wr, u8 *len16)
527 {
528 u32 plen;
529 int size;
530 int ret;
531
532 if (wr->num_sge > T4_MAX_SEND_SGE)
533 return -EINVAL;
534 wqe->write.r2 = 0;
535 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
536 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
537 if (wr->num_sge) {
538 if (wr->send_flags & IB_SEND_INLINE) {
539 ret = build_immd(sq, wqe->write.u.immd_src, wr,
540 T4_MAX_WRITE_INLINE, &plen);
541 if (ret)
542 return ret;
543 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
544 plen;
545 } else {
546 ret = build_isgl((__be64 *)sq->queue,
547 (__be64 *)&sq->queue[sq->size],
548 wqe->write.u.isgl_src,
549 wr->sg_list, wr->num_sge, &plen);
550 if (ret)
551 return ret;
552 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
553 wr->num_sge * sizeof(struct fw_ri_sge);
554 }
555 } else {
556 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
557 wqe->write.u.immd_src[0].r1 = 0;
558 wqe->write.u.immd_src[0].r2 = 0;
559 wqe->write.u.immd_src[0].immdlen = 0;
560 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
561 plen = 0;
562 }
563 *len16 = DIV_ROUND_UP(size, 16);
564 wqe->write.plen = cpu_to_be32(plen);
565 return 0;
566 }
567
568 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
569 {
570 if (wr->num_sge > 1)
571 return -EINVAL;
572 if (wr->num_sge) {
573 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
574 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
575 >> 32));
576 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
577 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
578 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
579 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
580 >> 32));
581 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
582 } else {
583 wqe->read.stag_src = cpu_to_be32(2);
584 wqe->read.to_src_hi = 0;
585 wqe->read.to_src_lo = 0;
586 wqe->read.stag_sink = cpu_to_be32(2);
587 wqe->read.plen = 0;
588 wqe->read.to_sink_hi = 0;
589 wqe->read.to_sink_lo = 0;
590 }
591 wqe->read.r2 = 0;
592 wqe->read.r5 = 0;
593 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
594 return 0;
595 }
596
597 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
598 struct ib_recv_wr *wr, u8 *len16)
599 {
600 int ret;
601
602 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
603 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
604 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
605 if (ret)
606 return ret;
607 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
608 wr->num_sge * sizeof(struct fw_ri_sge), 16);
609 return 0;
610 }
611
612 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
613 struct ib_reg_wr *wr, u8 *len16, bool dsgl_supported)
614 {
615 struct c4iw_mr *mhp = to_c4iw_mr(wr->mr);
616 struct fw_ri_immd *imdp;
617 __be64 *p;
618 int i;
619 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
620 int rem;
621
622 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
623 return -EINVAL;
624
625 wqe->fr.qpbinde_to_dcacpu = 0;
626 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
627 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
628 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
629 wqe->fr.len_hi = 0;
630 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
631 wqe->fr.stag = cpu_to_be32(wr->key);
632 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
633 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
634 0xffffffff);
635
636 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
637 struct fw_ri_dsgl *sglp;
638
639 for (i = 0; i < mhp->mpl_len; i++)
640 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
641
642 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
643 sglp->op = FW_RI_DATA_DSGL;
644 sglp->r1 = 0;
645 sglp->nsge = cpu_to_be16(1);
646 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
647 sglp->len0 = cpu_to_be32(pbllen);
648
649 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
650 } else {
651 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
652 imdp->op = FW_RI_DATA_IMMD;
653 imdp->r1 = 0;
654 imdp->r2 = 0;
655 imdp->immdlen = cpu_to_be32(pbllen);
656 p = (__be64 *)(imdp + 1);
657 rem = pbllen;
658 for (i = 0; i < mhp->mpl_len; i++) {
659 *p = cpu_to_be64((u64)mhp->mpl[i]);
660 rem -= sizeof(*p);
661 if (++p == (__be64 *)&sq->queue[sq->size])
662 p = (__be64 *)sq->queue;
663 }
664 BUG_ON(rem < 0);
665 while (rem) {
666 *p = 0;
667 rem -= sizeof(*p);
668 if (++p == (__be64 *)&sq->queue[sq->size])
669 p = (__be64 *)sq->queue;
670 }
671 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
672 + pbllen, 16);
673 }
674 return 0;
675 }
676
677 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
678 u8 *len16)
679 {
680 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
681 wqe->inv.r2 = 0;
682 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
683 return 0;
684 }
685
686 static void _free_qp(struct kref *kref)
687 {
688 struct c4iw_qp *qhp;
689
690 qhp = container_of(kref, struct c4iw_qp, kref);
691 PDBG("%s qhp %p\n", __func__, qhp);
692 kfree(qhp);
693 }
694
695 void c4iw_qp_add_ref(struct ib_qp *qp)
696 {
697 PDBG("%s ib_qp %p\n", __func__, qp);
698 kref_get(&to_c4iw_qp(qp)->kref);
699 }
700
701 void c4iw_qp_rem_ref(struct ib_qp *qp)
702 {
703 PDBG("%s ib_qp %p\n", __func__, qp);
704 kref_put(&to_c4iw_qp(qp)->kref, _free_qp);
705 }
706
707 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
708 {
709 if (list_empty(entry))
710 list_add_tail(entry, head);
711 }
712
713 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
714 {
715 unsigned long flags;
716
717 spin_lock_irqsave(&qhp->rhp->lock, flags);
718 spin_lock(&qhp->lock);
719 if (qhp->rhp->db_state == NORMAL)
720 t4_ring_sq_db(&qhp->wq, inc, NULL);
721 else {
722 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
723 qhp->wq.sq.wq_pidx_inc += inc;
724 }
725 spin_unlock(&qhp->lock);
726 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
727 return 0;
728 }
729
730 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
731 {
732 unsigned long flags;
733
734 spin_lock_irqsave(&qhp->rhp->lock, flags);
735 spin_lock(&qhp->lock);
736 if (qhp->rhp->db_state == NORMAL)
737 t4_ring_rq_db(&qhp->wq, inc, NULL);
738 else {
739 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
740 qhp->wq.rq.wq_pidx_inc += inc;
741 }
742 spin_unlock(&qhp->lock);
743 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
744 return 0;
745 }
746
747 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
748 struct ib_send_wr **bad_wr)
749 {
750 int err = 0;
751 u8 len16 = 0;
752 enum fw_wr_opcodes fw_opcode = 0;
753 enum fw_ri_wr_flags fw_flags;
754 struct c4iw_qp *qhp;
755 union t4_wr *wqe = NULL;
756 u32 num_wrs;
757 struct t4_swsqe *swsqe;
758 unsigned long flag;
759 u16 idx = 0;
760
761 qhp = to_c4iw_qp(ibqp);
762 spin_lock_irqsave(&qhp->lock, flag);
763 if (t4_wq_in_error(&qhp->wq)) {
764 spin_unlock_irqrestore(&qhp->lock, flag);
765 return -EINVAL;
766 }
767 num_wrs = t4_sq_avail(&qhp->wq);
768 if (num_wrs == 0) {
769 spin_unlock_irqrestore(&qhp->lock, flag);
770 return -ENOMEM;
771 }
772 while (wr) {
773 if (num_wrs == 0) {
774 err = -ENOMEM;
775 *bad_wr = wr;
776 break;
777 }
778 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
779 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
780
781 fw_flags = 0;
782 if (wr->send_flags & IB_SEND_SOLICITED)
783 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
784 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
785 fw_flags |= FW_RI_COMPLETION_FLAG;
786 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
787 switch (wr->opcode) {
788 case IB_WR_SEND_WITH_INV:
789 case IB_WR_SEND:
790 if (wr->send_flags & IB_SEND_FENCE)
791 fw_flags |= FW_RI_READ_FENCE_FLAG;
792 fw_opcode = FW_RI_SEND_WR;
793 if (wr->opcode == IB_WR_SEND)
794 swsqe->opcode = FW_RI_SEND;
795 else
796 swsqe->opcode = FW_RI_SEND_WITH_INV;
797 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
798 break;
799 case IB_WR_RDMA_WRITE:
800 fw_opcode = FW_RI_RDMA_WRITE_WR;
801 swsqe->opcode = FW_RI_RDMA_WRITE;
802 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
803 break;
804 case IB_WR_RDMA_READ:
805 case IB_WR_RDMA_READ_WITH_INV:
806 fw_opcode = FW_RI_RDMA_READ_WR;
807 swsqe->opcode = FW_RI_READ_REQ;
808 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
809 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
810 else
811 fw_flags = 0;
812 err = build_rdma_read(wqe, wr, &len16);
813 if (err)
814 break;
815 swsqe->read_len = wr->sg_list[0].length;
816 if (!qhp->wq.sq.oldest_read)
817 qhp->wq.sq.oldest_read = swsqe;
818 break;
819 case IB_WR_REG_MR:
820 fw_opcode = FW_RI_FR_NSMR_WR;
821 swsqe->opcode = FW_RI_FAST_REGISTER;
822 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), &len16,
823 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
824 break;
825 case IB_WR_LOCAL_INV:
826 if (wr->send_flags & IB_SEND_FENCE)
827 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
828 fw_opcode = FW_RI_INV_LSTAG_WR;
829 swsqe->opcode = FW_RI_LOCAL_INV;
830 err = build_inv_stag(wqe, wr, &len16);
831 break;
832 default:
833 PDBG("%s post of type=%d TBD!\n", __func__,
834 wr->opcode);
835 err = -EINVAL;
836 }
837 if (err) {
838 *bad_wr = wr;
839 break;
840 }
841 swsqe->idx = qhp->wq.sq.pidx;
842 swsqe->complete = 0;
843 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
844 qhp->sq_sig_all;
845 swsqe->flushed = 0;
846 swsqe->wr_id = wr->wr_id;
847 if (c4iw_wr_log) {
848 swsqe->sge_ts = cxgb4_read_sge_timestamp(
849 qhp->rhp->rdev.lldi.ports[0]);
850 getnstimeofday(&swsqe->host_ts);
851 }
852
853 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
854
855 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
856 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
857 swsqe->opcode, swsqe->read_len);
858 wr = wr->next;
859 num_wrs--;
860 t4_sq_produce(&qhp->wq, len16);
861 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
862 }
863 if (!qhp->rhp->rdev.status_page->db_off) {
864 t4_ring_sq_db(&qhp->wq, idx, wqe);
865 spin_unlock_irqrestore(&qhp->lock, flag);
866 } else {
867 spin_unlock_irqrestore(&qhp->lock, flag);
868 ring_kernel_sq_db(qhp, idx);
869 }
870 return err;
871 }
872
873 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
874 struct ib_recv_wr **bad_wr)
875 {
876 int err = 0;
877 struct c4iw_qp *qhp;
878 union t4_recv_wr *wqe = NULL;
879 u32 num_wrs;
880 u8 len16 = 0;
881 unsigned long flag;
882 u16 idx = 0;
883
884 qhp = to_c4iw_qp(ibqp);
885 spin_lock_irqsave(&qhp->lock, flag);
886 if (t4_wq_in_error(&qhp->wq)) {
887 spin_unlock_irqrestore(&qhp->lock, flag);
888 return -EINVAL;
889 }
890 num_wrs = t4_rq_avail(&qhp->wq);
891 if (num_wrs == 0) {
892 spin_unlock_irqrestore(&qhp->lock, flag);
893 return -ENOMEM;
894 }
895 while (wr) {
896 if (wr->num_sge > T4_MAX_RECV_SGE) {
897 err = -EINVAL;
898 *bad_wr = wr;
899 break;
900 }
901 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
902 qhp->wq.rq.wq_pidx *
903 T4_EQ_ENTRY_SIZE);
904 if (num_wrs)
905 err = build_rdma_recv(qhp, wqe, wr, &len16);
906 else
907 err = -ENOMEM;
908 if (err) {
909 *bad_wr = wr;
910 break;
911 }
912
913 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
914 if (c4iw_wr_log) {
915 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
916 cxgb4_read_sge_timestamp(
917 qhp->rhp->rdev.lldi.ports[0]);
918 getnstimeofday(
919 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
920 }
921
922 wqe->recv.opcode = FW_RI_RECV_WR;
923 wqe->recv.r1 = 0;
924 wqe->recv.wrid = qhp->wq.rq.pidx;
925 wqe->recv.r2[0] = 0;
926 wqe->recv.r2[1] = 0;
927 wqe->recv.r2[2] = 0;
928 wqe->recv.len16 = len16;
929 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
930 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
931 t4_rq_produce(&qhp->wq, len16);
932 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
933 wr = wr->next;
934 num_wrs--;
935 }
936 if (!qhp->rhp->rdev.status_page->db_off) {
937 t4_ring_rq_db(&qhp->wq, idx, wqe);
938 spin_unlock_irqrestore(&qhp->lock, flag);
939 } else {
940 spin_unlock_irqrestore(&qhp->lock, flag);
941 ring_kernel_rq_db(qhp, idx);
942 }
943 return err;
944 }
945
946 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
947 u8 *ecode)
948 {
949 int status;
950 int tagged;
951 int opcode;
952 int rqtype;
953 int send_inv;
954
955 if (!err_cqe) {
956 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
957 *ecode = 0;
958 return;
959 }
960
961 status = CQE_STATUS(err_cqe);
962 opcode = CQE_OPCODE(err_cqe);
963 rqtype = RQ_TYPE(err_cqe);
964 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
965 (opcode == FW_RI_SEND_WITH_SE_INV);
966 tagged = (opcode == FW_RI_RDMA_WRITE) ||
967 (rqtype && (opcode == FW_RI_READ_RESP));
968
969 switch (status) {
970 case T4_ERR_STAG:
971 if (send_inv) {
972 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
973 *ecode = RDMAP_CANT_INV_STAG;
974 } else {
975 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
976 *ecode = RDMAP_INV_STAG;
977 }
978 break;
979 case T4_ERR_PDID:
980 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
981 if ((opcode == FW_RI_SEND_WITH_INV) ||
982 (opcode == FW_RI_SEND_WITH_SE_INV))
983 *ecode = RDMAP_CANT_INV_STAG;
984 else
985 *ecode = RDMAP_STAG_NOT_ASSOC;
986 break;
987 case T4_ERR_QPID:
988 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
989 *ecode = RDMAP_STAG_NOT_ASSOC;
990 break;
991 case T4_ERR_ACCESS:
992 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
993 *ecode = RDMAP_ACC_VIOL;
994 break;
995 case T4_ERR_WRAP:
996 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
997 *ecode = RDMAP_TO_WRAP;
998 break;
999 case T4_ERR_BOUND:
1000 if (tagged) {
1001 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1002 *ecode = DDPT_BASE_BOUNDS;
1003 } else {
1004 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1005 *ecode = RDMAP_BASE_BOUNDS;
1006 }
1007 break;
1008 case T4_ERR_INVALIDATE_SHARED_MR:
1009 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1010 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1011 *ecode = RDMAP_CANT_INV_STAG;
1012 break;
1013 case T4_ERR_ECC:
1014 case T4_ERR_ECC_PSTAG:
1015 case T4_ERR_INTERNAL_ERR:
1016 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1017 *ecode = 0;
1018 break;
1019 case T4_ERR_OUT_OF_RQE:
1020 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1021 *ecode = DDPU_INV_MSN_NOBUF;
1022 break;
1023 case T4_ERR_PBL_ADDR_BOUND:
1024 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1025 *ecode = DDPT_BASE_BOUNDS;
1026 break;
1027 case T4_ERR_CRC:
1028 *layer_type = LAYER_MPA|DDP_LLP;
1029 *ecode = MPA_CRC_ERR;
1030 break;
1031 case T4_ERR_MARKER:
1032 *layer_type = LAYER_MPA|DDP_LLP;
1033 *ecode = MPA_MARKER_ERR;
1034 break;
1035 case T4_ERR_PDU_LEN_ERR:
1036 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1037 *ecode = DDPU_MSG_TOOBIG;
1038 break;
1039 case T4_ERR_DDP_VERSION:
1040 if (tagged) {
1041 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1042 *ecode = DDPT_INV_VERS;
1043 } else {
1044 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1045 *ecode = DDPU_INV_VERS;
1046 }
1047 break;
1048 case T4_ERR_RDMA_VERSION:
1049 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1050 *ecode = RDMAP_INV_VERS;
1051 break;
1052 case T4_ERR_OPCODE:
1053 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1054 *ecode = RDMAP_INV_OPCODE;
1055 break;
1056 case T4_ERR_DDP_QUEUE_NUM:
1057 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1058 *ecode = DDPU_INV_QN;
1059 break;
1060 case T4_ERR_MSN:
1061 case T4_ERR_MSN_GAP:
1062 case T4_ERR_MSN_RANGE:
1063 case T4_ERR_IRD_OVERFLOW:
1064 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1065 *ecode = DDPU_INV_MSN_RANGE;
1066 break;
1067 case T4_ERR_TBIT:
1068 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1069 *ecode = 0;
1070 break;
1071 case T4_ERR_MO:
1072 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1073 *ecode = DDPU_INV_MO;
1074 break;
1075 default:
1076 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1077 *ecode = 0;
1078 break;
1079 }
1080 }
1081
1082 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1083 gfp_t gfp)
1084 {
1085 struct fw_ri_wr *wqe;
1086 struct sk_buff *skb;
1087 struct terminate_message *term;
1088
1089 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1090 qhp->ep->hwtid);
1091
1092 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1093 if (WARN_ON(!skb))
1094 return;
1095
1096 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1097
1098 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1099 memset(wqe, 0, sizeof *wqe);
1100 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1101 wqe->flowid_len16 = cpu_to_be32(
1102 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1103 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1104
1105 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1106 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1107 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1108 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1109 term->layer_etype = qhp->attr.layer_etype;
1110 term->ecode = qhp->attr.ecode;
1111 } else
1112 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1113 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1114 }
1115
1116 /*
1117 * Assumes qhp lock is held.
1118 */
1119 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1120 struct c4iw_cq *schp)
1121 {
1122 int count;
1123 int rq_flushed, sq_flushed;
1124 unsigned long flag;
1125
1126 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1127
1128 /* locking hierarchy: cq lock first, then qp lock. */
1129 spin_lock_irqsave(&rchp->lock, flag);
1130 spin_lock(&qhp->lock);
1131
1132 if (qhp->wq.flushed) {
1133 spin_unlock(&qhp->lock);
1134 spin_unlock_irqrestore(&rchp->lock, flag);
1135 return;
1136 }
1137 qhp->wq.flushed = 1;
1138
1139 c4iw_flush_hw_cq(rchp);
1140 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1141 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1142 spin_unlock(&qhp->lock);
1143 spin_unlock_irqrestore(&rchp->lock, flag);
1144
1145 /* locking hierarchy: cq lock first, then qp lock. */
1146 spin_lock_irqsave(&schp->lock, flag);
1147 spin_lock(&qhp->lock);
1148 if (schp != rchp)
1149 c4iw_flush_hw_cq(schp);
1150 sq_flushed = c4iw_flush_sq(qhp);
1151 spin_unlock(&qhp->lock);
1152 spin_unlock_irqrestore(&schp->lock, flag);
1153
1154 if (schp == rchp) {
1155 if (t4_clear_cq_armed(&rchp->cq) &&
1156 (rq_flushed || sq_flushed)) {
1157 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1158 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1159 rchp->ibcq.cq_context);
1160 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1161 }
1162 } else {
1163 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1164 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1165 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1166 rchp->ibcq.cq_context);
1167 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1168 }
1169 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1170 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1171 (*schp->ibcq.comp_handler)(&schp->ibcq,
1172 schp->ibcq.cq_context);
1173 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1174 }
1175 }
1176 }
1177
1178 static void flush_qp(struct c4iw_qp *qhp)
1179 {
1180 struct c4iw_cq *rchp, *schp;
1181 unsigned long flag;
1182
1183 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1184 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1185
1186 t4_set_wq_in_error(&qhp->wq);
1187 if (qhp->ibqp.uobject) {
1188 t4_set_cq_in_error(&rchp->cq);
1189 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1190 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1191 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1192 if (schp != rchp) {
1193 t4_set_cq_in_error(&schp->cq);
1194 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1195 (*schp->ibcq.comp_handler)(&schp->ibcq,
1196 schp->ibcq.cq_context);
1197 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1198 }
1199 return;
1200 }
1201 __flush_qp(qhp, rchp, schp);
1202 }
1203
1204 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1205 struct c4iw_ep *ep)
1206 {
1207 struct fw_ri_wr *wqe;
1208 int ret;
1209 struct sk_buff *skb;
1210
1211 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1212 ep->hwtid);
1213
1214 skb = skb_dequeue(&ep->com.ep_skb_list);
1215 if (WARN_ON(!skb))
1216 return -ENOMEM;
1217
1218 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1219
1220 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1221 memset(wqe, 0, sizeof *wqe);
1222 wqe->op_compl = cpu_to_be32(
1223 FW_WR_OP_V(FW_RI_INIT_WR) |
1224 FW_WR_COMPL_F);
1225 wqe->flowid_len16 = cpu_to_be32(
1226 FW_WR_FLOWID_V(ep->hwtid) |
1227 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1228 wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1229
1230 wqe->u.fini.type = FW_RI_TYPE_FINI;
1231 ret = c4iw_ofld_send(&rhp->rdev, skb);
1232 if (ret)
1233 goto out;
1234
1235 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1236 qhp->wq.sq.qid, __func__);
1237 out:
1238 PDBG("%s ret %d\n", __func__, ret);
1239 return ret;
1240 }
1241
1242 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1243 {
1244 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1245 memset(&init->u, 0, sizeof init->u);
1246 switch (p2p_type) {
1247 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1248 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1249 init->u.write.stag_sink = cpu_to_be32(1);
1250 init->u.write.to_sink = cpu_to_be64(1);
1251 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1252 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1253 sizeof(struct fw_ri_immd),
1254 16);
1255 break;
1256 case FW_RI_INIT_P2PTYPE_READ_REQ:
1257 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1258 init->u.read.stag_src = cpu_to_be32(1);
1259 init->u.read.to_src_lo = cpu_to_be32(1);
1260 init->u.read.stag_sink = cpu_to_be32(1);
1261 init->u.read.to_sink_lo = cpu_to_be32(1);
1262 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1263 break;
1264 }
1265 }
1266
1267 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1268 {
1269 struct fw_ri_wr *wqe;
1270 int ret;
1271 struct sk_buff *skb;
1272
1273 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1274 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1275
1276 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1277 if (!skb) {
1278 ret = -ENOMEM;
1279 goto out;
1280 }
1281 ret = alloc_ird(rhp, qhp->attr.max_ird);
1282 if (ret) {
1283 qhp->attr.max_ird = 0;
1284 kfree_skb(skb);
1285 goto out;
1286 }
1287 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1288
1289 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1290 memset(wqe, 0, sizeof *wqe);
1291 wqe->op_compl = cpu_to_be32(
1292 FW_WR_OP_V(FW_RI_INIT_WR) |
1293 FW_WR_COMPL_F);
1294 wqe->flowid_len16 = cpu_to_be32(
1295 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1296 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1297
1298 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1299
1300 wqe->u.init.type = FW_RI_TYPE_INIT;
1301 wqe->u.init.mpareqbit_p2ptype =
1302 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1303 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1304 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1305 if (qhp->attr.mpa_attr.recv_marker_enabled)
1306 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1307 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1308 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1309 if (qhp->attr.mpa_attr.crc_enabled)
1310 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1311
1312 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1313 FW_RI_QP_RDMA_WRITE_ENABLE |
1314 FW_RI_QP_BIND_ENABLE;
1315 if (!qhp->ibqp.uobject)
1316 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1317 FW_RI_QP_STAG0_ENABLE;
1318 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1319 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1320 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1321 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1322 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1323 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1324 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1325 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1326 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1327 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1328 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1329 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1330 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1331 rhp->rdev.lldi.vr->rq.start);
1332 if (qhp->attr.mpa_attr.initiator)
1333 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1334
1335 ret = c4iw_ofld_send(&rhp->rdev, skb);
1336 if (ret)
1337 goto err1;
1338
1339 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1340 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1341 if (!ret)
1342 goto out;
1343 err1:
1344 free_ird(rhp, qhp->attr.max_ird);
1345 out:
1346 PDBG("%s ret %d\n", __func__, ret);
1347 return ret;
1348 }
1349
1350 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1351 enum c4iw_qp_attr_mask mask,
1352 struct c4iw_qp_attributes *attrs,
1353 int internal)
1354 {
1355 int ret = 0;
1356 struct c4iw_qp_attributes newattr = qhp->attr;
1357 int disconnect = 0;
1358 int terminate = 0;
1359 int abort = 0;
1360 int free = 0;
1361 struct c4iw_ep *ep = NULL;
1362
1363 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1364 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1365 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1366
1367 mutex_lock(&qhp->mutex);
1368
1369 /* Process attr changes if in IDLE */
1370 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1371 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1372 ret = -EIO;
1373 goto out;
1374 }
1375 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1376 newattr.enable_rdma_read = attrs->enable_rdma_read;
1377 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1378 newattr.enable_rdma_write = attrs->enable_rdma_write;
1379 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1380 newattr.enable_bind = attrs->enable_bind;
1381 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1382 if (attrs->max_ord > c4iw_max_read_depth) {
1383 ret = -EINVAL;
1384 goto out;
1385 }
1386 newattr.max_ord = attrs->max_ord;
1387 }
1388 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1389 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1390 ret = -EINVAL;
1391 goto out;
1392 }
1393 newattr.max_ird = attrs->max_ird;
1394 }
1395 qhp->attr = newattr;
1396 }
1397
1398 if (mask & C4IW_QP_ATTR_SQ_DB) {
1399 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1400 goto out;
1401 }
1402 if (mask & C4IW_QP_ATTR_RQ_DB) {
1403 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1404 goto out;
1405 }
1406
1407 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1408 goto out;
1409 if (qhp->attr.state == attrs->next_state)
1410 goto out;
1411
1412 switch (qhp->attr.state) {
1413 case C4IW_QP_STATE_IDLE:
1414 switch (attrs->next_state) {
1415 case C4IW_QP_STATE_RTS:
1416 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1417 ret = -EINVAL;
1418 goto out;
1419 }
1420 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1421 ret = -EINVAL;
1422 goto out;
1423 }
1424 qhp->attr.mpa_attr = attrs->mpa_attr;
1425 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1426 qhp->ep = qhp->attr.llp_stream_handle;
1427 set_state(qhp, C4IW_QP_STATE_RTS);
1428
1429 /*
1430 * Ref the endpoint here and deref when we
1431 * disassociate the endpoint from the QP. This
1432 * happens in CLOSING->IDLE transition or *->ERROR
1433 * transition.
1434 */
1435 c4iw_get_ep(&qhp->ep->com);
1436 ret = rdma_init(rhp, qhp);
1437 if (ret)
1438 goto err;
1439 break;
1440 case C4IW_QP_STATE_ERROR:
1441 set_state(qhp, C4IW_QP_STATE_ERROR);
1442 flush_qp(qhp);
1443 break;
1444 default:
1445 ret = -EINVAL;
1446 goto out;
1447 }
1448 break;
1449 case C4IW_QP_STATE_RTS:
1450 switch (attrs->next_state) {
1451 case C4IW_QP_STATE_CLOSING:
1452 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1453 t4_set_wq_in_error(&qhp->wq);
1454 set_state(qhp, C4IW_QP_STATE_CLOSING);
1455 ep = qhp->ep;
1456 if (!internal) {
1457 abort = 0;
1458 disconnect = 1;
1459 c4iw_get_ep(&qhp->ep->com);
1460 }
1461 ret = rdma_fini(rhp, qhp, ep);
1462 if (ret)
1463 goto err;
1464 break;
1465 case C4IW_QP_STATE_TERMINATE:
1466 t4_set_wq_in_error(&qhp->wq);
1467 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1468 qhp->attr.layer_etype = attrs->layer_etype;
1469 qhp->attr.ecode = attrs->ecode;
1470 ep = qhp->ep;
1471 if (!internal) {
1472 c4iw_get_ep(&qhp->ep->com);
1473 terminate = 1;
1474 disconnect = 1;
1475 } else {
1476 terminate = qhp->attr.send_term;
1477 ret = rdma_fini(rhp, qhp, ep);
1478 if (ret)
1479 goto err;
1480 }
1481 break;
1482 case C4IW_QP_STATE_ERROR:
1483 t4_set_wq_in_error(&qhp->wq);
1484 set_state(qhp, C4IW_QP_STATE_ERROR);
1485 if (!internal) {
1486 abort = 1;
1487 disconnect = 1;
1488 ep = qhp->ep;
1489 c4iw_get_ep(&qhp->ep->com);
1490 }
1491 goto err;
1492 break;
1493 default:
1494 ret = -EINVAL;
1495 goto out;
1496 }
1497 break;
1498 case C4IW_QP_STATE_CLOSING:
1499 if (!internal) {
1500 ret = -EINVAL;
1501 goto out;
1502 }
1503 switch (attrs->next_state) {
1504 case C4IW_QP_STATE_IDLE:
1505 flush_qp(qhp);
1506 set_state(qhp, C4IW_QP_STATE_IDLE);
1507 qhp->attr.llp_stream_handle = NULL;
1508 c4iw_put_ep(&qhp->ep->com);
1509 qhp->ep = NULL;
1510 wake_up(&qhp->wait);
1511 break;
1512 case C4IW_QP_STATE_ERROR:
1513 goto err;
1514 default:
1515 ret = -EINVAL;
1516 goto err;
1517 }
1518 break;
1519 case C4IW_QP_STATE_ERROR:
1520 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1521 ret = -EINVAL;
1522 goto out;
1523 }
1524 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1525 ret = -EINVAL;
1526 goto out;
1527 }
1528 set_state(qhp, C4IW_QP_STATE_IDLE);
1529 break;
1530 case C4IW_QP_STATE_TERMINATE:
1531 if (!internal) {
1532 ret = -EINVAL;
1533 goto out;
1534 }
1535 goto err;
1536 break;
1537 default:
1538 printk(KERN_ERR "%s in a bad state %d\n",
1539 __func__, qhp->attr.state);
1540 ret = -EINVAL;
1541 goto err;
1542 break;
1543 }
1544 goto out;
1545 err:
1546 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1547 qhp->wq.sq.qid);
1548
1549 /* disassociate the LLP connection */
1550 qhp->attr.llp_stream_handle = NULL;
1551 if (!ep)
1552 ep = qhp->ep;
1553 qhp->ep = NULL;
1554 set_state(qhp, C4IW_QP_STATE_ERROR);
1555 free = 1;
1556 abort = 1;
1557 BUG_ON(!ep);
1558 flush_qp(qhp);
1559 wake_up(&qhp->wait);
1560 out:
1561 mutex_unlock(&qhp->mutex);
1562
1563 if (terminate)
1564 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1565
1566 /*
1567 * If disconnect is 1, then we need to initiate a disconnect
1568 * on the EP. This can be a normal close (RTS->CLOSING) or
1569 * an abnormal close (RTS/CLOSING->ERROR).
1570 */
1571 if (disconnect) {
1572 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1573 GFP_KERNEL);
1574 c4iw_put_ep(&ep->com);
1575 }
1576
1577 /*
1578 * If free is 1, then we've disassociated the EP from the QP
1579 * and we need to dereference the EP.
1580 */
1581 if (free)
1582 c4iw_put_ep(&ep->com);
1583 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1584 return ret;
1585 }
1586
1587 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1588 {
1589 struct c4iw_dev *rhp;
1590 struct c4iw_qp *qhp;
1591 struct c4iw_qp_attributes attrs;
1592 struct c4iw_ucontext *ucontext;
1593
1594 qhp = to_c4iw_qp(ib_qp);
1595 rhp = qhp->rhp;
1596
1597 attrs.next_state = C4IW_QP_STATE_ERROR;
1598 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1599 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1600 else
1601 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1602 wait_event(qhp->wait, !qhp->ep);
1603
1604 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1605
1606 spin_lock_irq(&rhp->lock);
1607 if (!list_empty(&qhp->db_fc_entry))
1608 list_del_init(&qhp->db_fc_entry);
1609 spin_unlock_irq(&rhp->lock);
1610 free_ird(rhp, qhp->attr.max_ird);
1611
1612 ucontext = ib_qp->uobject ?
1613 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1614 destroy_qp(&rhp->rdev, &qhp->wq,
1615 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1616
1617 c4iw_qp_rem_ref(ib_qp);
1618
1619 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1620 return 0;
1621 }
1622
1623 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1624 struct ib_udata *udata)
1625 {
1626 struct c4iw_dev *rhp;
1627 struct c4iw_qp *qhp;
1628 struct c4iw_pd *php;
1629 struct c4iw_cq *schp;
1630 struct c4iw_cq *rchp;
1631 struct c4iw_create_qp_resp uresp;
1632 unsigned int sqsize, rqsize;
1633 struct c4iw_ucontext *ucontext;
1634 int ret;
1635 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1636 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1637
1638 PDBG("%s ib_pd %p\n", __func__, pd);
1639
1640 if (attrs->qp_type != IB_QPT_RC)
1641 return ERR_PTR(-EINVAL);
1642
1643 php = to_c4iw_pd(pd);
1644 rhp = php->rhp;
1645 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1646 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1647 if (!schp || !rchp)
1648 return ERR_PTR(-EINVAL);
1649
1650 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1651 return ERR_PTR(-EINVAL);
1652
1653 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1654 return ERR_PTR(-E2BIG);
1655 rqsize = attrs->cap.max_recv_wr + 1;
1656 if (rqsize < 8)
1657 rqsize = 8;
1658
1659 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1660 return ERR_PTR(-E2BIG);
1661 sqsize = attrs->cap.max_send_wr + 1;
1662 if (sqsize < 8)
1663 sqsize = 8;
1664
1665 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1666
1667 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1668 if (!qhp)
1669 return ERR_PTR(-ENOMEM);
1670 qhp->wq.sq.size = sqsize;
1671 qhp->wq.sq.memsize =
1672 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1673 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1674 qhp->wq.sq.flush_cidx = -1;
1675 qhp->wq.rq.size = rqsize;
1676 qhp->wq.rq.memsize =
1677 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1678 sizeof(*qhp->wq.rq.queue);
1679
1680 if (ucontext) {
1681 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1682 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1683 }
1684
1685 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1686 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1687 if (ret)
1688 goto err1;
1689
1690 attrs->cap.max_recv_wr = rqsize - 1;
1691 attrs->cap.max_send_wr = sqsize - 1;
1692 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1693
1694 qhp->rhp = rhp;
1695 qhp->attr.pd = php->pdid;
1696 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1697 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1698 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1699 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1700 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1701 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1702 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1703 qhp->attr.state = C4IW_QP_STATE_IDLE;
1704 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1705 qhp->attr.enable_rdma_read = 1;
1706 qhp->attr.enable_rdma_write = 1;
1707 qhp->attr.enable_bind = 1;
1708 qhp->attr.max_ord = 0;
1709 qhp->attr.max_ird = 0;
1710 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1711 spin_lock_init(&qhp->lock);
1712 init_completion(&qhp->sq_drained);
1713 init_completion(&qhp->rq_drained);
1714 mutex_init(&qhp->mutex);
1715 init_waitqueue_head(&qhp->wait);
1716 kref_init(&qhp->kref);
1717
1718 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1719 if (ret)
1720 goto err2;
1721
1722 if (udata) {
1723 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1724 if (!sq_key_mm) {
1725 ret = -ENOMEM;
1726 goto err3;
1727 }
1728 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1729 if (!rq_key_mm) {
1730 ret = -ENOMEM;
1731 goto err4;
1732 }
1733 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1734 if (!sq_db_key_mm) {
1735 ret = -ENOMEM;
1736 goto err5;
1737 }
1738 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1739 if (!rq_db_key_mm) {
1740 ret = -ENOMEM;
1741 goto err6;
1742 }
1743 if (t4_sq_onchip(&qhp->wq.sq)) {
1744 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1745 GFP_KERNEL);
1746 if (!ma_sync_key_mm) {
1747 ret = -ENOMEM;
1748 goto err7;
1749 }
1750 uresp.flags = C4IW_QPF_ONCHIP;
1751 } else
1752 uresp.flags = 0;
1753 uresp.qid_mask = rhp->rdev.qpmask;
1754 uresp.sqid = qhp->wq.sq.qid;
1755 uresp.sq_size = qhp->wq.sq.size;
1756 uresp.sq_memsize = qhp->wq.sq.memsize;
1757 uresp.rqid = qhp->wq.rq.qid;
1758 uresp.rq_size = qhp->wq.rq.size;
1759 uresp.rq_memsize = qhp->wq.rq.memsize;
1760 spin_lock(&ucontext->mmap_lock);
1761 if (ma_sync_key_mm) {
1762 uresp.ma_sync_key = ucontext->key;
1763 ucontext->key += PAGE_SIZE;
1764 } else {
1765 uresp.ma_sync_key = 0;
1766 }
1767 uresp.sq_key = ucontext->key;
1768 ucontext->key += PAGE_SIZE;
1769 uresp.rq_key = ucontext->key;
1770 ucontext->key += PAGE_SIZE;
1771 uresp.sq_db_gts_key = ucontext->key;
1772 ucontext->key += PAGE_SIZE;
1773 uresp.rq_db_gts_key = ucontext->key;
1774 ucontext->key += PAGE_SIZE;
1775 spin_unlock(&ucontext->mmap_lock);
1776 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1777 if (ret)
1778 goto err8;
1779 sq_key_mm->key = uresp.sq_key;
1780 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1781 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1782 insert_mmap(ucontext, sq_key_mm);
1783 rq_key_mm->key = uresp.rq_key;
1784 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
1785 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1786 insert_mmap(ucontext, rq_key_mm);
1787 sq_db_key_mm->key = uresp.sq_db_gts_key;
1788 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
1789 sq_db_key_mm->len = PAGE_SIZE;
1790 insert_mmap(ucontext, sq_db_key_mm);
1791 rq_db_key_mm->key = uresp.rq_db_gts_key;
1792 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
1793 rq_db_key_mm->len = PAGE_SIZE;
1794 insert_mmap(ucontext, rq_db_key_mm);
1795 if (ma_sync_key_mm) {
1796 ma_sync_key_mm->key = uresp.ma_sync_key;
1797 ma_sync_key_mm->addr =
1798 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
1799 PCIE_MA_SYNC_A) & PAGE_MASK;
1800 ma_sync_key_mm->len = PAGE_SIZE;
1801 insert_mmap(ucontext, ma_sync_key_mm);
1802 }
1803 }
1804 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1805 init_timer(&(qhp->timer));
1806 INIT_LIST_HEAD(&qhp->db_fc_entry);
1807 PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1808 "rq id %u size %u memsize %zu num_entries %u\n", __func__,
1809 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1810 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1811 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1812 return &qhp->ibqp;
1813 err8:
1814 kfree(ma_sync_key_mm);
1815 err7:
1816 kfree(rq_db_key_mm);
1817 err6:
1818 kfree(sq_db_key_mm);
1819 err5:
1820 kfree(rq_key_mm);
1821 err4:
1822 kfree(sq_key_mm);
1823 err3:
1824 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1825 err2:
1826 destroy_qp(&rhp->rdev, &qhp->wq,
1827 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1828 err1:
1829 kfree(qhp);
1830 return ERR_PTR(ret);
1831 }
1832
1833 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1834 int attr_mask, struct ib_udata *udata)
1835 {
1836 struct c4iw_dev *rhp;
1837 struct c4iw_qp *qhp;
1838 enum c4iw_qp_attr_mask mask = 0;
1839 struct c4iw_qp_attributes attrs;
1840
1841 PDBG("%s ib_qp %p\n", __func__, ibqp);
1842
1843 /* iwarp does not support the RTR state */
1844 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1845 attr_mask &= ~IB_QP_STATE;
1846
1847 /* Make sure we still have something left to do */
1848 if (!attr_mask)
1849 return 0;
1850
1851 memset(&attrs, 0, sizeof attrs);
1852 qhp = to_c4iw_qp(ibqp);
1853 rhp = qhp->rhp;
1854
1855 attrs.next_state = c4iw_convert_state(attr->qp_state);
1856 attrs.enable_rdma_read = (attr->qp_access_flags &
1857 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1858 attrs.enable_rdma_write = (attr->qp_access_flags &
1859 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1860 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1861
1862
1863 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1864 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1865 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1866 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1867 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1868
1869 /*
1870 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1871 * ringing the queue db when we're in DB_FULL mode.
1872 * Only allow this on T4 devices.
1873 */
1874 attrs.sq_db_inc = attr->sq_psn;
1875 attrs.rq_db_inc = attr->rq_psn;
1876 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1877 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1878 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1879 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1880 return -EINVAL;
1881
1882 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1883 }
1884
1885 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1886 {
1887 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1888 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1889 }
1890
1891 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1892 int attr_mask, struct ib_qp_init_attr *init_attr)
1893 {
1894 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1895
1896 memset(attr, 0, sizeof *attr);
1897 memset(init_attr, 0, sizeof *init_attr);
1898 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1899 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
1900 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
1901 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
1902 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
1903 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
1904 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
1905 return 0;
1906 }
1907
1908 static void move_qp_to_err(struct c4iw_qp *qp)
1909 {
1910 struct c4iw_qp_attributes attrs = { .next_state = C4IW_QP_STATE_ERROR };
1911
1912 (void)c4iw_modify_qp(qp->rhp, qp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1913 }
1914
1915 void c4iw_drain_sq(struct ib_qp *ibqp)
1916 {
1917 struct c4iw_qp *qp = to_c4iw_qp(ibqp);
1918 unsigned long flag;
1919 bool need_to_wait;
1920
1921 move_qp_to_err(qp);
1922 spin_lock_irqsave(&qp->lock, flag);
1923 need_to_wait = !t4_sq_empty(&qp->wq);
1924 spin_unlock_irqrestore(&qp->lock, flag);
1925
1926 if (need_to_wait)
1927 wait_for_completion(&qp->sq_drained);
1928 }
1929
1930 void c4iw_drain_rq(struct ib_qp *ibqp)
1931 {
1932 struct c4iw_qp *qp = to_c4iw_qp(ibqp);
1933 unsigned long flag;
1934 bool need_to_wait;
1935
1936 move_qp_to_err(qp);
1937 spin_lock_irqsave(&qp->lock, flag);
1938 need_to_wait = !t4_rq_empty(&qp->wq);
1939 spin_unlock_irqrestore(&qp->lock, flag);
1940
1941 if (need_to_wait)
1942 wait_for_completion(&qp->rq_drained);
1943 }
Linux kernel - Deliverables
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