2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V1_H
34 #define _HNS_ROCE_HW_V1_H
36 #define CQ_STATE_VALID 2
38 #define HNS_ROCE_V1_MAX_PD_NUM 0x8000
39 #define HNS_ROCE_V1_MAX_CQ_NUM 0x10000
40 #define HNS_ROCE_V1_MAX_CQE_NUM 0x8000
42 #define HNS_ROCE_V1_MAX_QP_NUM 0x40000
43 #define HNS_ROCE_V1_MAX_WQE_NUM 0x4000
45 #define HNS_ROCE_V1_MAX_MTPT_NUM 0x80000
47 #define HNS_ROCE_V1_MAX_MTT_SEGS 0x100000
49 #define HNS_ROCE_V1_MAX_QP_INIT_RDMA 128
50 #define HNS_ROCE_V1_MAX_QP_DEST_RDMA 128
52 #define HNS_ROCE_V1_MAX_SQ_DESC_SZ 64
53 #define HNS_ROCE_V1_MAX_RQ_DESC_SZ 64
54 #define HNS_ROCE_V1_SG_NUM 2
55 #define HNS_ROCE_V1_INLINE_SIZE 32
57 #define HNS_ROCE_V1_UAR_NUM 256
58 #define HNS_ROCE_V1_PHY_UAR_NUM 8
60 #define HNS_ROCE_V1_GID_NUM 16
62 #define HNS_ROCE_V1_NUM_COMP_EQE 0x8000
63 #define HNS_ROCE_V1_NUM_ASYNC_EQE 0x400
65 #define HNS_ROCE_V1_QPC_ENTRY_SIZE 256
66 #define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
67 #define HNS_ROCE_V1_CQC_ENTRY_SIZE 64
68 #define HNS_ROCE_V1_MTPT_ENTRY_SIZE 64
69 #define HNS_ROCE_V1_MTT_ENTRY_SIZE 64
71 #define HNS_ROCE_V1_CQE_ENTRY_SIZE 32
72 #define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000
74 #define HNS_ROCE_V1_EXT_RAQ_WF 8
75 #define HNS_ROCE_V1_RAQ_ENTRY 64
76 #define HNS_ROCE_V1_RAQ_DEPTH 32768
77 #define HNS_ROCE_V1_RAQ_SIZE (HNS_ROCE_V1_RAQ_ENTRY * HNS_ROCE_V1_RAQ_DEPTH)
79 #define HNS_ROCE_V1_SDB_DEPTH 0x400
80 #define HNS_ROCE_V1_ODB_DEPTH 0x400
82 #define HNS_ROCE_V1_DB_RSVD 0x80
84 #define HNS_ROCE_V1_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
85 #define HNS_ROCE_V1_SDB_ALFUL (HNS_ROCE_V1_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
86 #define HNS_ROCE_V1_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
87 #define HNS_ROCE_V1_ODB_ALFUL (HNS_ROCE_V1_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
89 #define HNS_ROCE_V1_EXT_SDB_DEPTH 0x4000
90 #define HNS_ROCE_V1_EXT_ODB_DEPTH 0x4000
91 #define HNS_ROCE_V1_EXT_SDB_ENTRY 16
92 #define HNS_ROCE_V1_EXT_ODB_ENTRY 16
93 #define HNS_ROCE_V1_EXT_SDB_SIZE \
94 (HNS_ROCE_V1_EXT_SDB_DEPTH * HNS_ROCE_V1_EXT_SDB_ENTRY)
95 #define HNS_ROCE_V1_EXT_ODB_SIZE \
96 (HNS_ROCE_V1_EXT_ODB_DEPTH * HNS_ROCE_V1_EXT_ODB_ENTRY)
98 #define HNS_ROCE_V1_EXT_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
99 #define HNS_ROCE_V1_EXT_SDB_ALFUL \
100 (HNS_ROCE_V1_EXT_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
101 #define HNS_ROCE_V1_EXT_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
102 #define HNS_ROCE_V1_EXT_ODB_ALFUL \
103 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
105 #define HNS_ROCE_ODB_POLL_MODE 0
107 #define HNS_ROCE_SDB_NORMAL_MODE 0
108 #define HNS_ROCE_SDB_EXTEND_MODE 1
110 #define HNS_ROCE_ODB_EXTEND_MODE 1
112 #define KEY_VALID 0x02
114 #define HNS_ROCE_CQE_QPN_MASK 0x3ffff
115 #define HNS_ROCE_CQE_STATUS_MASK 0x1f
116 #define HNS_ROCE_CQE_OPCODE_MASK 0xf
118 #define HNS_ROCE_CQE_SUCCESS 0x00
119 #define HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR 0x01
120 #define HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR 0x02
121 #define HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR 0x03
122 #define HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR 0x04
123 #define HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR 0x05
124 #define HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR 0x06
125 #define HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR 0x07
126 #define HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR 0x08
127 #define HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR 0x09
128 #define HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR 0x0a
129 #define HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR 0x0b
130 #define HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR 0x0c
132 #define QP1C_CFGN_OFFSET 0x28
133 #define PHY_PORT_OFFSET 0x8
134 #define MTPT_IDX_SHIFT 16
135 #define ALL_PORT_VAL_OPEN 0x3f
136 #define POL_TIME_INTERVAL_VAL 0x80
137 #define SLEEP_TIME_INTERVAL 20
138 #define SQ_PSN_SHIFT 8
139 #define QKEY_VAL 0x80010000
140 #define SDB_INV_CNT_OFFSET 8
142 struct hns_roce_cq_context
{
153 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S 0
154 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M \
155 (((1UL << 2) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S)
157 #define CQ_CONTEXT_CQC_BYTE_4_CQN_S 16
158 #define CQ_CONTEXT_CQC_BYTE_4_CQN_M \
159 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQN_S)
161 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S 0
162 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M \
163 (((1UL << 17) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S)
165 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S 20
166 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M \
167 (((1UL << 4) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S)
169 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_S 24
170 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_M \
171 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_12_CEQN_S)
173 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S 0
174 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M \
175 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S)
177 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S 16
178 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M \
179 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S)
181 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S 8
182 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M \
183 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S)
185 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S 0
186 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M \
187 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S)
189 #define CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S 9
191 #define CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S 8
192 #define CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S 14
193 #define CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S 15
195 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S 16
196 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M \
197 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S)
199 struct hns_roce_cqe
{
213 #define CQE_BYTE_4_OWNER_S 7
214 #define CQE_BYTE_4_SQ_RQ_FLAG_S 14
216 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_S 8
217 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_M \
218 (((1UL << 5) - 1) << CQE_BYTE_4_STATUS_OF_THE_OPERATION_S)
220 #define CQE_BYTE_4_WQE_INDEX_S 16
221 #define CQE_BYTE_4_WQE_INDEX_M (((1UL << 14) - 1) << CQE_BYTE_4_WQE_INDEX_S)
223 #define CQE_BYTE_4_OPERATION_TYPE_S 0
224 #define CQE_BYTE_4_OPERATION_TYPE_M \
225 (((1UL << 4) - 1) << CQE_BYTE_4_OPERATION_TYPE_S)
227 #define CQE_BYTE_4_IMM_INDICATOR_S 15
229 #define CQE_BYTE_16_LOCAL_QPN_S 0
230 #define CQE_BYTE_16_LOCAL_QPN_M (((1UL << 24) - 1) << CQE_BYTE_16_LOCAL_QPN_S)
232 #define CQE_BYTE_20_PORT_NUM_S 26
233 #define CQE_BYTE_20_PORT_NUM_M (((1UL << 3) - 1) << CQE_BYTE_20_PORT_NUM_S)
235 #define CQE_BYTE_20_SL_S 24
236 #define CQE_BYTE_20_SL_M (((1UL << 2) - 1) << CQE_BYTE_20_SL_S)
238 #define CQE_BYTE_20_REMOTE_QPN_S 0
239 #define CQE_BYTE_20_REMOTE_QPN_M \
240 (((1UL << 24) - 1) << CQE_BYTE_20_REMOTE_QPN_S)
242 #define CQE_BYTE_20_GRH_PRESENT_S 29
244 #define CQE_BYTE_28_P_KEY_IDX_S 16
245 #define CQE_BYTE_28_P_KEY_IDX_M (((1UL << 16) - 1) << CQE_BYTE_28_P_KEY_IDX_S)
247 #define CQ_DB_REQ_NOT_SOL 0
248 #define CQ_DB_REQ_NOT (1 << 16)
250 struct hns_roce_v1_mpt_entry
{
269 #define MPT_BYTE_4_KEY_STATE_S 0
270 #define MPT_BYTE_4_KEY_STATE_M (((1UL << 2) - 1) << MPT_BYTE_4_KEY_STATE_S)
272 #define MPT_BYTE_4_KEY_S 8
273 #define MPT_BYTE_4_KEY_M (((1UL << 8) - 1) << MPT_BYTE_4_KEY_S)
275 #define MPT_BYTE_4_PAGE_SIZE_S 16
276 #define MPT_BYTE_4_PAGE_SIZE_M (((1UL << 2) - 1) << MPT_BYTE_4_PAGE_SIZE_S)
278 #define MPT_BYTE_4_MW_TYPE_S 20
280 #define MPT_BYTE_4_MW_BIND_ENABLE_S 21
282 #define MPT_BYTE_4_OWN_S 22
284 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_S 24
285 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_M \
286 (((1UL << 2) - 1) << MPT_BYTE_4_MEMORY_LOCATION_TYPE_S)
288 #define MPT_BYTE_4_REMOTE_ATOMIC_S 26
289 #define MPT_BYTE_4_LOCAL_WRITE_S 27
290 #define MPT_BYTE_4_REMOTE_WRITE_S 28
291 #define MPT_BYTE_4_REMOTE_READ_S 29
292 #define MPT_BYTE_4_REMOTE_INVAL_ENABLE_S 30
293 #define MPT_BYTE_4_ADDRESS_TYPE_S 31
295 #define MPT_BYTE_12_PBL_ADDR_H_S 0
296 #define MPT_BYTE_12_PBL_ADDR_H_M \
297 (((1UL << 17) - 1) << MPT_BYTE_12_PBL_ADDR_H_S)
299 #define MPT_BYTE_12_MW_BIND_COUNTER_S 17
300 #define MPT_BYTE_12_MW_BIND_COUNTER_M \
301 (((1UL << 15) - 1) << MPT_BYTE_12_MW_BIND_COUNTER_S)
303 #define MPT_BYTE_28_PD_S 0
304 #define MPT_BYTE_28_PD_M (((1UL << 16) - 1) << MPT_BYTE_28_PD_S)
306 #define MPT_BYTE_28_L_KEY_IDX_L_S 16
307 #define MPT_BYTE_28_L_KEY_IDX_L_M \
308 (((1UL << 16) - 1) << MPT_BYTE_28_L_KEY_IDX_L_S)
310 #define MPT_BYTE_36_PA0_H_S 0
311 #define MPT_BYTE_36_PA0_H_M (((1UL << 5) - 1) << MPT_BYTE_36_PA0_H_S)
313 #define MPT_BYTE_36_PA1_L_S 8
314 #define MPT_BYTE_36_PA1_L_M (((1UL << 24) - 1) << MPT_BYTE_36_PA1_L_S)
316 #define MPT_BYTE_40_PA1_H_S 0
317 #define MPT_BYTE_40_PA1_H_M (((1UL << 13) - 1) << MPT_BYTE_40_PA1_H_S)
319 #define MPT_BYTE_40_PA2_L_S 16
320 #define MPT_BYTE_40_PA2_L_M (((1UL << 16) - 1) << MPT_BYTE_40_PA2_L_S)
322 #define MPT_BYTE_44_PA2_H_S 0
323 #define MPT_BYTE_44_PA2_H_M (((1UL << 21) - 1) << MPT_BYTE_44_PA2_H_S)
325 #define MPT_BYTE_44_PA3_L_S 24
326 #define MPT_BYTE_44_PA3_L_M (((1UL << 8) - 1) << MPT_BYTE_44_PA3_L_S)
328 #define MPT_BYTE_48_PA3_H_S 0
329 #define MPT_BYTE_48_PA3_H_M (((1UL << 29) - 1) << MPT_BYTE_48_PA3_H_S)
331 #define MPT_BYTE_56_PA4_H_S 0
332 #define MPT_BYTE_56_PA4_H_M (((1UL << 5) - 1) << MPT_BYTE_56_PA4_H_S)
334 #define MPT_BYTE_56_PA5_L_S 8
335 #define MPT_BYTE_56_PA5_L_M (((1UL << 24) - 1) << MPT_BYTE_56_PA5_L_S)
337 #define MPT_BYTE_60_PA5_H_S 0
338 #define MPT_BYTE_60_PA5_H_M (((1UL << 13) - 1) << MPT_BYTE_60_PA5_H_S)
340 #define MPT_BYTE_60_PA6_L_S 16
341 #define MPT_BYTE_60_PA6_L_M (((1UL << 16) - 1) << MPT_BYTE_60_PA6_L_S)
343 #define MPT_BYTE_64_PA6_H_S 0
344 #define MPT_BYTE_64_PA6_H_M (((1UL << 21) - 1) << MPT_BYTE_64_PA6_H_S)
346 #define MPT_BYTE_64_L_KEY_IDX_H_S 24
347 #define MPT_BYTE_64_L_KEY_IDX_H_M \
348 (((1UL << 8) - 1) << MPT_BYTE_64_L_KEY_IDX_H_S)
350 struct hns_roce_wqe_ctrl_seg
{
357 struct hns_roce_wqe_data_seg
{
363 struct hns_roce_wqe_raddr_seg
{
365 __be32 len
;/* reserved */
369 struct hns_roce_rq_wqe_ctrl
{
377 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S 16
378 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M \
379 (((1UL << 6) - 1) << RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S)
381 #define HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS 10000
385 struct hns_roce_ud_send_wqe
{
392 unsigned char dgid
[GID_LEN
];
413 #define UD_SEND_WQE_U32_4_DMAC_0_S 0
414 #define UD_SEND_WQE_U32_4_DMAC_0_M \
415 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_0_S)
417 #define UD_SEND_WQE_U32_4_DMAC_1_S 8
418 #define UD_SEND_WQE_U32_4_DMAC_1_M \
419 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_1_S)
421 #define UD_SEND_WQE_U32_4_DMAC_2_S 16
422 #define UD_SEND_WQE_U32_4_DMAC_2_M \
423 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_2_S)
425 #define UD_SEND_WQE_U32_4_DMAC_3_S 24
426 #define UD_SEND_WQE_U32_4_DMAC_3_M \
427 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_3_S)
429 #define UD_SEND_WQE_U32_8_DMAC_4_S 0
430 #define UD_SEND_WQE_U32_8_DMAC_4_M \
431 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_4_S)
433 #define UD_SEND_WQE_U32_8_DMAC_5_S 8
434 #define UD_SEND_WQE_U32_8_DMAC_5_M \
435 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S)
437 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16
438 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \
439 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S)
441 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S 24
442 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M \
443 (((1UL << 6) - 1) << UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S)
445 #define UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S 31
447 #define UD_SEND_WQE_U32_16_DEST_QP_S 0
448 #define UD_SEND_WQE_U32_16_DEST_QP_M \
449 (((1UL << 24) - 1) << UD_SEND_WQE_U32_16_DEST_QP_S)
451 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S 24
452 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M \
453 (((1UL << 8) - 1) << UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S)
455 #define UD_SEND_WQE_U32_36_FLOW_LABEL_S 0
456 #define UD_SEND_WQE_U32_36_FLOW_LABEL_M \
457 (((1UL << 20) - 1) << UD_SEND_WQE_U32_36_FLOW_LABEL_S)
459 #define UD_SEND_WQE_U32_36_PRIORITY_S 20
460 #define UD_SEND_WQE_U32_36_PRIORITY_M \
461 (((1UL << 4) - 1) << UD_SEND_WQE_U32_36_PRIORITY_S)
463 #define UD_SEND_WQE_U32_36_SGID_INDEX_S 24
464 #define UD_SEND_WQE_U32_36_SGID_INDEX_M \
465 (((1UL << 8) - 1) << UD_SEND_WQE_U32_36_SGID_INDEX_S)
467 #define UD_SEND_WQE_U32_40_HOP_LIMIT_S 0
468 #define UD_SEND_WQE_U32_40_HOP_LIMIT_M \
469 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_HOP_LIMIT_S)
471 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S 8
472 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M \
473 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S)
475 struct hns_roce_sqp_context
{
488 #define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8
489 #define QP1C_BYTES_4_SQ_WQE_SHIFT_M \
490 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S)
492 #define QP1C_BYTES_4_RQ_WQE_SHIFT_S 12
493 #define QP1C_BYTES_4_RQ_WQE_SHIFT_M \
494 (((1UL << 4) - 1) << QP1C_BYTES_4_RQ_WQE_SHIFT_S)
496 #define QP1C_BYTES_4_PD_S 16
497 #define QP1C_BYTES_4_PD_M (((1UL << 16) - 1) << QP1C_BYTES_4_PD_S)
499 #define QP1C_BYTES_12_SQ_RQ_BT_H_S 0
500 #define QP1C_BYTES_12_SQ_RQ_BT_H_M \
501 (((1UL << 17) - 1) << QP1C_BYTES_12_SQ_RQ_BT_H_S)
503 #define QP1C_BYTES_16_RQ_HEAD_S 0
504 #define QP1C_BYTES_16_RQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_16_RQ_HEAD_S)
506 #define QP1C_BYTES_16_PORT_NUM_S 16
507 #define QP1C_BYTES_16_PORT_NUM_M \
508 (((1UL << 3) - 1) << QP1C_BYTES_16_PORT_NUM_S)
510 #define QP1C_BYTES_16_SIGNALING_TYPE_S 27
511 #define QP1C_BYTES_16_LOCAL_ENABLE_E2E_CREDIT_S 28
512 #define QP1C_BYTES_16_RQ_BA_FLG_S 29
513 #define QP1C_BYTES_16_SQ_BA_FLG_S 30
514 #define QP1C_BYTES_16_QP1_ERR_S 31
516 #define QP1C_BYTES_20_SQ_HEAD_S 0
517 #define QP1C_BYTES_20_SQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_20_SQ_HEAD_S)
519 #define QP1C_BYTES_20_PKEY_IDX_S 16
520 #define QP1C_BYTES_20_PKEY_IDX_M \
521 (((1UL << 16) - 1) << QP1C_BYTES_20_PKEY_IDX_S)
523 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S 0
524 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M \
525 (((1UL << 5) - 1) << QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S)
527 #define QP1C_BYTES_28_RQ_CUR_IDX_S 16
528 #define QP1C_BYTES_28_RQ_CUR_IDX_M \
529 (((1UL << 15) - 1) << QP1C_BYTES_28_RQ_CUR_IDX_S)
531 #define QP1C_BYTES_32_TX_CQ_NUM_S 0
532 #define QP1C_BYTES_32_TX_CQ_NUM_M \
533 (((1UL << 16) - 1) << QP1C_BYTES_32_TX_CQ_NUM_S)
535 #define QP1C_BYTES_32_RX_CQ_NUM_S 16
536 #define QP1C_BYTES_32_RX_CQ_NUM_M \
537 (((1UL << 16) - 1) << QP1C_BYTES_32_RX_CQ_NUM_S)
539 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S 0
540 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M \
541 (((1UL << 5) - 1) << QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S)
543 #define QP1C_BYTES_40_SQ_CUR_IDX_S 16
544 #define QP1C_BYTES_40_SQ_CUR_IDX_M \
545 (((1UL << 15) - 1) << QP1C_BYTES_40_SQ_CUR_IDX_S)
547 #define HNS_ROCE_WQE_INLINE (1UL<<31)
548 #define HNS_ROCE_WQE_SE (1UL<<30)
550 #define HNS_ROCE_WQE_SGE_NUM_BIT 24
551 #define HNS_ROCE_WQE_IMM (1UL<<23)
552 #define HNS_ROCE_WQE_FENCE (1UL<<21)
553 #define HNS_ROCE_WQE_CQ_NOTIFY (1UL<<20)
555 #define HNS_ROCE_WQE_OPCODE_SEND (0<<16)
556 #define HNS_ROCE_WQE_OPCODE_RDMA_READ (1<<16)
557 #define HNS_ROCE_WQE_OPCODE_RDMA_WRITE (2<<16)
558 #define HNS_ROCE_WQE_OPCODE_LOCAL_INV (4<<16)
559 #define HNS_ROCE_WQE_OPCODE_UD_SEND (7<<16)
560 #define HNS_ROCE_WQE_OPCODE_MASK (15<<16)
562 struct hns_roce_qp_context
{
595 u32 rx_cur_sq_wqe_ba_l
;
618 u32 tx_cur_sq_wqe_ba_l
;
623 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S 0
624 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M \
625 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S)
627 #define QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S 3
628 #define QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S 4
629 #define QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S 5
630 #define QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S 6
631 #define QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S 7
633 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S 8
634 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M \
635 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S)
637 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S 12
638 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M \
639 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S)
641 #define QP_CONTEXT_QPC_BYTES_4_PD_S 16
642 #define QP_CONTEXT_QPC_BYTES_4_PD_M \
643 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_4_PD_S)
645 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S 0
646 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M \
647 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S)
649 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S 16
650 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M \
651 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S)
653 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S 0
654 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M \
655 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S)
657 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S 16
658 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M \
659 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S)
661 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_S 0
662 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_M \
663 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_16_QP_NUM_S)
665 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S 0
666 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M \
667 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S)
669 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S 18
670 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M \
671 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S)
673 #define QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S 23
675 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S 0
676 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M \
677 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S)
679 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S 18
680 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M \
681 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S)
683 #define QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S 20
684 #define QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S 21
685 #define QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S 22
686 #define QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S 23
688 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S 24
689 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M \
690 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S)
692 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_S 0
693 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_M \
694 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_36_DEST_QP_S)
696 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S 24
697 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M \
698 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S)
700 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_S 0
701 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_M \
702 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_44_DMAC_H_S)
704 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S 16
705 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M \
706 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S)
708 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_S 24
709 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_M \
710 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_HOPLMT_S)
712 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S 0
713 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M \
714 (((1UL << 20) - 1) << QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S)
716 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_S 20
717 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_M \
718 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_48_TCLASS_S)
720 #define QP_CONTEXT_QPC_BYTES_48_MTU_S 28
721 #define QP_CONTEXT_QPC_BYTES_48_MTU_M \
722 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_48_MTU_S)
724 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S 0
725 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M \
726 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S)
728 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S 16
729 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M \
730 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S)
732 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S 0
733 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M \
734 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S)
736 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S 8
737 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M \
738 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S)
740 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S 0
741 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M \
742 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S)
744 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S 24
745 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M \
746 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S)
748 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S 0
749 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M \
750 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S)
752 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S 24
753 #define QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S 25
755 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S 26
756 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M \
757 (((1UL << 2) - 1) << \
758 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S)
760 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S 29
761 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M \
762 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S)
764 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S 0
765 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M \
766 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S)
768 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S 24
769 #define QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S 25
771 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S 0
772 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M \
773 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S)
775 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S 24
776 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M \
777 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S)
779 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S 0
780 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M \
781 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S)
783 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S 0
784 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M \
785 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S)
787 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S 16
788 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M \
789 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S)
791 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S 0
792 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M \
793 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S)
795 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S 24
797 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S 25
798 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M \
799 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S)
801 #define QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S 27
803 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S 0
804 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M \
805 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S)
807 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S 24
808 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M \
809 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S)
811 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S 0
812 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M \
813 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S)
815 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S 24
816 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M \
817 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S)
819 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S 0
820 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M \
821 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S)
823 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S 16
824 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M \
825 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S)
827 #define QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S 31
829 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_S 0
830 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_M \
831 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_144_QP_STATE_S)
833 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S 0
834 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M \
835 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S)
837 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S 2
838 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M \
839 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S)
841 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S 5
842 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M \
843 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S)
845 #define QP_CONTEXT_QPC_BYTES_148_LSN_S 8
846 #define QP_CONTEXT_QPC_BYTES_148_LSN_M \
847 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_148_LSN_S)
849 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S 0
850 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M \
851 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S)
853 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S 3
854 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M \
855 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S)
857 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S 8
858 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M \
859 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S)
861 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S 11
862 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M \
863 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S)
865 #define QP_CONTEXT_QPC_BYTES_156_SL_S 14
866 #define QP_CONTEXT_QPC_BYTES_156_SL_M \
867 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_SL_S)
869 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S 16
870 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M \
871 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S)
873 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S 24
874 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M \
875 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S)
877 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S 0
878 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M \
879 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S)
881 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S 24
882 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M \
883 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S)
885 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S 0
886 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M \
887 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S)
889 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S 24
890 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M \
891 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S)
893 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S 26
894 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M \
895 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S)
897 #define QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S 28
898 #define QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S 29
899 #define QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S 30
901 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S 0
902 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M \
903 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S)
905 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S 16
906 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M \
907 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S)
909 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S 0
910 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M \
911 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S)
913 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S 16
914 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M \
915 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S)
917 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S 0
918 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M \
919 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S)
921 #define QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S 8
923 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S 16
924 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \
925 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S)
927 struct hns_roce_rq_db
{
932 #define RQ_DOORBELL_U32_4_RQ_HEAD_S 0
933 #define RQ_DOORBELL_U32_4_RQ_HEAD_M \
934 (((1UL << 15) - 1) << RQ_DOORBELL_U32_4_RQ_HEAD_S)
936 #define RQ_DOORBELL_U32_8_QPN_S 0
937 #define RQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << RQ_DOORBELL_U32_8_QPN_S)
939 #define RQ_DOORBELL_U32_8_CMD_S 28
940 #define RQ_DOORBELL_U32_8_CMD_M (((1UL << 3) - 1) << RQ_DOORBELL_U32_8_CMD_S)
942 #define RQ_DOORBELL_U32_8_HW_SYNC_S 31
944 struct hns_roce_sq_db
{
949 #define SQ_DOORBELL_U32_4_SQ_HEAD_S 0
950 #define SQ_DOORBELL_U32_4_SQ_HEAD_M \
951 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S)
953 #define SQ_DOORBELL_U32_4_PORT_S 18
954 #define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S)
956 #define SQ_DOORBELL_U32_8_QPN_S 0
957 #define SQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << SQ_DOORBELL_U32_8_QPN_S)
959 #define SQ_DOORBELL_HW_SYNC_S 31
961 struct hns_roce_ext_db
{
964 struct hns_roce_buf_list
*sdb_buf_list
;
965 struct hns_roce_buf_list
*odb_buf_list
;
968 struct hns_roce_db_table
{
971 struct hns_roce_ext_db
*ext_db
;
974 struct hns_roce_v1_priv
{
975 struct hns_roce_db_table db_table
;
976 struct hns_roce_raq_table raq_table
;
979 int hns_dsaf_roce_reset(struct fwnode_handle
*dsaf_fwnode
, bool dereset
);