2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #if defined(CONFIG_X86)
44 #include <linux/sched.h>
45 #include <linux/delay.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_addr.h>
48 #include <rdma/ib_cache.h>
49 #include <linux/mlx5/port.h>
50 #include <linux/mlx5/vport.h>
51 #include <linux/list.h>
52 #include <rdma/ib_smi.h>
53 #include <rdma/ib_umem.h>
55 #include <linux/etherdevice.h>
56 #include <linux/mlx5/fs.h>
60 #define DRIVER_NAME "mlx5_ib"
61 #define DRIVER_VERSION "2.2-1"
62 #define DRIVER_RELDATE "Feb 2014"
64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66 MODULE_LICENSE("Dual BSD/GPL");
67 MODULE_VERSION(DRIVER_VERSION
);
69 static int deprecated_prof_sel
= 2;
70 module_param_named(prof_sel
, deprecated_prof_sel
, int, 0444);
71 MODULE_PARM_DESC(prof_sel
, "profile selector. Deprecated here. Moved to module mlx5_core");
73 static char mlx5_version
[] =
74 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION
" (" DRIVER_RELDATE
")\n";
78 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
81 static enum rdma_link_layer
82 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
84 switch (port_type_cap
) {
85 case MLX5_CAP_PORT_TYPE_IB
:
86 return IB_LINK_LAYER_INFINIBAND
;
87 case MLX5_CAP_PORT_TYPE_ETH
:
88 return IB_LINK_LAYER_ETHERNET
;
90 return IB_LINK_LAYER_UNSPECIFIED
;
94 static enum rdma_link_layer
95 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
97 struct mlx5_ib_dev
*dev
= to_mdev(device
);
98 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
103 static int mlx5_netdev_event(struct notifier_block
*this,
104 unsigned long event
, void *ptr
)
106 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
107 struct mlx5_ib_dev
*ibdev
= container_of(this, struct mlx5_ib_dev
,
110 if ((event
!= NETDEV_UNREGISTER
) && (event
!= NETDEV_REGISTER
))
113 write_lock(&ibdev
->roce
.netdev_lock
);
114 if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
)
115 ibdev
->roce
.netdev
= (event
== NETDEV_UNREGISTER
) ? NULL
: ndev
;
116 write_unlock(&ibdev
->roce
.netdev_lock
);
121 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
124 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
125 struct net_device
*ndev
;
127 /* Ensure ndev does not disappear before we invoke dev_hold()
129 read_lock(&ibdev
->roce
.netdev_lock
);
130 ndev
= ibdev
->roce
.netdev
;
133 read_unlock(&ibdev
->roce
.netdev_lock
);
138 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
139 struct ib_port_attr
*props
)
141 struct mlx5_ib_dev
*dev
= to_mdev(device
);
142 struct net_device
*ndev
;
143 enum ib_mtu ndev_ib_mtu
;
146 memset(props
, 0, sizeof(*props
));
148 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
149 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
151 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
152 roce_address_table_size
);
153 props
->max_mtu
= IB_MTU_4096
;
154 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
155 props
->pkey_tbl_len
= 1;
156 props
->state
= IB_PORT_DOWN
;
157 props
->phys_state
= 3;
159 mlx5_query_nic_vport_qkey_viol_cntr(dev
->mdev
, &qkey_viol_cntr
);
160 props
->qkey_viol_cntr
= qkey_viol_cntr
;
162 ndev
= mlx5_ib_get_netdev(device
, port_num
);
166 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
167 props
->state
= IB_PORT_ACTIVE
;
168 props
->phys_state
= 5;
171 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
175 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
177 props
->active_width
= IB_WIDTH_4X
; /* TODO */
178 props
->active_speed
= IB_SPEED_QDR
; /* TODO */
183 static void ib_gid_to_mlx5_roce_addr(const union ib_gid
*gid
,
184 const struct ib_gid_attr
*attr
,
187 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
190 void *mlx5_addr_mac
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
196 ether_addr_copy(mlx5_addr_mac
, attr
->ndev
->dev_addr
);
198 if (is_vlan_dev(attr
->ndev
)) {
199 MLX5_SET_RA(mlx5_addr
, vlan_valid
, 1);
200 MLX5_SET_RA(mlx5_addr
, vlan_id
, vlan_dev_vlan_id(attr
->ndev
));
203 switch (attr
->gid_type
) {
205 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_1
);
207 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
208 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_2
);
215 if (attr
->gid_type
!= IB_GID_TYPE_IB
) {
216 if (ipv6_addr_v4mapped((void *)gid
))
217 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
218 MLX5_ROCE_L3_TYPE_IPV4
);
220 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
221 MLX5_ROCE_L3_TYPE_IPV6
);
224 if ((attr
->gid_type
== IB_GID_TYPE_IB
) ||
225 !ipv6_addr_v4mapped((void *)gid
))
226 memcpy(mlx5_addr_l3_addr
, gid
, sizeof(*gid
));
228 memcpy(&mlx5_addr_l3_addr
[12], &gid
->raw
[12], 4);
231 static int set_roce_addr(struct ib_device
*device
, u8 port_num
,
233 const union ib_gid
*gid
,
234 const struct ib_gid_attr
*attr
)
236 struct mlx5_ib_dev
*dev
= to_mdev(device
);
237 u32 in
[MLX5_ST_SZ_DW(set_roce_address_in
)];
238 u32 out
[MLX5_ST_SZ_DW(set_roce_address_out
)];
239 void *in_addr
= MLX5_ADDR_OF(set_roce_address_in
, in
, roce_address
);
240 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(device
, port_num
);
242 if (ll
!= IB_LINK_LAYER_ETHERNET
)
245 memset(in
, 0, sizeof(in
));
247 ib_gid_to_mlx5_roce_addr(gid
, attr
, in_addr
);
249 MLX5_SET(set_roce_address_in
, in
, roce_address_index
, index
);
250 MLX5_SET(set_roce_address_in
, in
, opcode
, MLX5_CMD_OP_SET_ROCE_ADDRESS
);
252 memset(out
, 0, sizeof(out
));
253 return mlx5_cmd_exec(dev
->mdev
, in
, sizeof(in
), out
, sizeof(out
));
256 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
257 unsigned int index
, const union ib_gid
*gid
,
258 const struct ib_gid_attr
*attr
,
259 __always_unused
void **context
)
261 return set_roce_addr(device
, port_num
, index
, gid
, attr
);
264 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
265 unsigned int index
, __always_unused
void **context
)
267 return set_roce_addr(device
, port_num
, index
, NULL
, NULL
);
270 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
273 struct ib_gid_attr attr
;
276 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
284 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
287 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
290 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
292 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
296 MLX5_VPORT_ACCESS_METHOD_MAD
,
297 MLX5_VPORT_ACCESS_METHOD_HCA
,
298 MLX5_VPORT_ACCESS_METHOD_NIC
,
301 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
303 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
304 return MLX5_VPORT_ACCESS_METHOD_MAD
;
306 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
307 IB_LINK_LAYER_ETHERNET
)
308 return MLX5_VPORT_ACCESS_METHOD_NIC
;
310 return MLX5_VPORT_ACCESS_METHOD_HCA
;
313 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
314 struct ib_device_attr
*props
)
317 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
318 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
319 u8 atomic_req_8B_endianness_mode
=
320 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianess_mode
);
322 /* Check if HW supports 8 bytes standard atomic operations and capable
323 * of host endianness respond
325 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
326 if (((atomic_operations
& tmp
) == tmp
) &&
327 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
328 (atomic_req_8B_endianness_mode
)) {
329 props
->atomic_cap
= IB_ATOMIC_HCA
;
331 props
->atomic_cap
= IB_ATOMIC_NONE
;
335 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
336 __be64
*sys_image_guid
)
338 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
339 struct mlx5_core_dev
*mdev
= dev
->mdev
;
343 switch (mlx5_get_vport_access_method(ibdev
)) {
344 case MLX5_VPORT_ACCESS_METHOD_MAD
:
345 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
348 case MLX5_VPORT_ACCESS_METHOD_HCA
:
349 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
352 case MLX5_VPORT_ACCESS_METHOD_NIC
:
353 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
361 *sys_image_guid
= cpu_to_be64(tmp
);
367 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
370 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
371 struct mlx5_core_dev
*mdev
= dev
->mdev
;
373 switch (mlx5_get_vport_access_method(ibdev
)) {
374 case MLX5_VPORT_ACCESS_METHOD_MAD
:
375 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
377 case MLX5_VPORT_ACCESS_METHOD_HCA
:
378 case MLX5_VPORT_ACCESS_METHOD_NIC
:
379 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
388 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
391 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
393 switch (mlx5_get_vport_access_method(ibdev
)) {
394 case MLX5_VPORT_ACCESS_METHOD_MAD
:
395 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
397 case MLX5_VPORT_ACCESS_METHOD_HCA
:
398 case MLX5_VPORT_ACCESS_METHOD_NIC
:
399 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
406 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
412 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
413 case MLX5_VPORT_ACCESS_METHOD_MAD
:
414 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
416 case MLX5_VPORT_ACCESS_METHOD_HCA
:
417 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
420 case MLX5_VPORT_ACCESS_METHOD_NIC
:
421 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
429 *node_guid
= cpu_to_be64(tmp
);
434 struct mlx5_reg_node_desc
{
438 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
440 struct mlx5_reg_node_desc in
;
442 if (mlx5_use_mad_ifc(dev
))
443 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
445 memset(&in
, 0, sizeof(in
));
447 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
448 sizeof(struct mlx5_reg_node_desc
),
449 MLX5_REG_NODE_DESC
, 0, 0);
452 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
453 struct ib_device_attr
*props
,
454 struct ib_udata
*uhw
)
456 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
457 struct mlx5_core_dev
*mdev
= dev
->mdev
;
461 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
462 struct mlx5_ib_query_device_resp resp
= {};
466 resp_len
= sizeof(resp
.comp_mask
) + sizeof(resp
.response_length
);
467 if (uhw
->outlen
&& uhw
->outlen
< resp_len
)
470 resp
.response_length
= resp_len
;
472 if (uhw
->inlen
&& !ib_is_udata_cleared(uhw
, 0, uhw
->inlen
))
475 memset(props
, 0, sizeof(*props
));
476 err
= mlx5_query_system_image_guid(ibdev
,
477 &props
->sys_image_guid
);
481 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
485 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
489 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
490 (fw_rev_min(dev
->mdev
) << 16) |
491 fw_rev_sub(dev
->mdev
);
492 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
493 IB_DEVICE_PORT_ACTIVE_EVENT
|
494 IB_DEVICE_SYS_IMAGE_GUID
|
495 IB_DEVICE_RC_RNR_NAK_GEN
;
497 if (MLX5_CAP_GEN(mdev
, pkv
))
498 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
499 if (MLX5_CAP_GEN(mdev
, qkv
))
500 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
501 if (MLX5_CAP_GEN(mdev
, apm
))
502 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
503 if (MLX5_CAP_GEN(mdev
, xrc
))
504 props
->device_cap_flags
|= IB_DEVICE_XRC
;
505 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
506 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
507 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
508 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
509 /* We support 'Gappy' memory registration too */
510 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
512 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
513 if (MLX5_CAP_GEN(mdev
, sho
)) {
514 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
515 /* At this stage no support for signature handover */
516 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
517 IB_PROT_T10DIF_TYPE_2
|
518 IB_PROT_T10DIF_TYPE_3
;
519 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
520 IB_GUARD_T10DIF_CSUM
;
522 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
523 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
525 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
)) {
526 if (MLX5_CAP_ETH(mdev
, csum_cap
))
527 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
529 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
)) {
530 max_tso
= MLX5_CAP_ETH(mdev
, max_lso_cap
);
532 resp
.tso_caps
.max_tso
= 1 << max_tso
;
533 resp
.tso_caps
.supported_qpts
|=
534 1 << IB_QPT_RAW_PACKET
;
535 resp
.response_length
+= sizeof(resp
.tso_caps
);
540 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
541 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
542 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
545 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
546 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
))
547 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
549 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
550 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
552 props
->vendor_part_id
= mdev
->pdev
->device
;
553 props
->hw_ver
= mdev
->pdev
->revision
;
555 props
->max_mr_size
= ~0ull;
556 props
->page_size_cap
= ~(min_page_size
- 1);
557 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
558 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
559 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
560 sizeof(struct mlx5_wqe_data_seg
);
561 max_sq_sg
= (MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
) -
562 sizeof(struct mlx5_wqe_ctrl_seg
)) /
563 sizeof(struct mlx5_wqe_data_seg
);
564 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
565 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
566 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
567 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
568 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
569 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
570 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
571 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
572 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
573 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
574 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
575 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
576 props
->max_srq_sge
= max_rq_sg
- 1;
577 props
->max_fast_reg_page_list_len
=
578 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
579 get_atomic_caps(dev
, props
);
580 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
581 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
582 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
583 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
584 props
->max_mcast_grp
;
585 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
586 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
587 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
589 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
590 if (MLX5_CAP_GEN(mdev
, pg
))
591 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
592 props
->odp_caps
= dev
->odp_caps
;
595 if (MLX5_CAP_GEN(mdev
, cd
))
596 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
598 if (!mlx5_core_is_pf(mdev
))
599 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
602 err
= ib_copy_to_udata(uhw
, &resp
, resp
.response_length
);
612 MLX5_IB_WIDTH_1X
= 1 << 0,
613 MLX5_IB_WIDTH_2X
= 1 << 1,
614 MLX5_IB_WIDTH_4X
= 1 << 2,
615 MLX5_IB_WIDTH_8X
= 1 << 3,
616 MLX5_IB_WIDTH_12X
= 1 << 4
619 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
622 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
625 if (active_width
& MLX5_IB_WIDTH_1X
) {
626 *ib_width
= IB_WIDTH_1X
;
627 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
628 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
631 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
632 *ib_width
= IB_WIDTH_4X
;
633 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
634 *ib_width
= IB_WIDTH_8X
;
635 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
636 *ib_width
= IB_WIDTH_12X
;
638 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
646 static int mlx5_mtu_to_ib_mtu(int mtu
)
655 pr_warn("invalid mtu\n");
665 __IB_MAX_VL_0_14
= 5,
668 enum mlx5_vl_hw_cap
{
680 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
685 *max_vl_num
= __IB_MAX_VL_0
;
688 *max_vl_num
= __IB_MAX_VL_0_1
;
691 *max_vl_num
= __IB_MAX_VL_0_3
;
694 *max_vl_num
= __IB_MAX_VL_0_7
;
696 case MLX5_VL_HW_0_14
:
697 *max_vl_num
= __IB_MAX_VL_0_14
;
707 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
708 struct ib_port_attr
*props
)
710 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
711 struct mlx5_core_dev
*mdev
= dev
->mdev
;
712 struct mlx5_hca_vport_context
*rep
;
716 u8 ib_link_width_oper
;
719 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
725 memset(props
, 0, sizeof(*props
));
727 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
731 props
->lid
= rep
->lid
;
732 props
->lmc
= rep
->lmc
;
733 props
->sm_lid
= rep
->sm_lid
;
734 props
->sm_sl
= rep
->sm_sl
;
735 props
->state
= rep
->vport_state
;
736 props
->phys_state
= rep
->port_physical_state
;
737 props
->port_cap_flags
= rep
->cap_mask1
;
738 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
739 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
740 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
741 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
742 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
743 props
->subnet_timeout
= rep
->subnet_timeout
;
744 props
->init_type_reply
= rep
->init_type_reply
;
745 props
->grh_required
= rep
->grh_required
;
747 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
751 err
= translate_active_width(ibdev
, ib_link_width_oper
,
752 &props
->active_width
);
755 err
= mlx5_query_port_proto_oper(mdev
, &props
->active_speed
, MLX5_PTYS_IB
,
760 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
762 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
764 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
766 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
768 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
772 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
779 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
780 struct ib_port_attr
*props
)
782 switch (mlx5_get_vport_access_method(ibdev
)) {
783 case MLX5_VPORT_ACCESS_METHOD_MAD
:
784 return mlx5_query_mad_ifc_port(ibdev
, port
, props
);
786 case MLX5_VPORT_ACCESS_METHOD_HCA
:
787 return mlx5_query_hca_port(ibdev
, port
, props
);
789 case MLX5_VPORT_ACCESS_METHOD_NIC
:
790 return mlx5_query_port_roce(ibdev
, port
, props
);
797 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
800 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
801 struct mlx5_core_dev
*mdev
= dev
->mdev
;
803 switch (mlx5_get_vport_access_method(ibdev
)) {
804 case MLX5_VPORT_ACCESS_METHOD_MAD
:
805 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
807 case MLX5_VPORT_ACCESS_METHOD_HCA
:
808 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
816 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
819 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
820 struct mlx5_core_dev
*mdev
= dev
->mdev
;
822 switch (mlx5_get_vport_access_method(ibdev
)) {
823 case MLX5_VPORT_ACCESS_METHOD_MAD
:
824 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
826 case MLX5_VPORT_ACCESS_METHOD_HCA
:
827 case MLX5_VPORT_ACCESS_METHOD_NIC
:
828 return mlx5_query_hca_vport_pkey(mdev
, 0, port
, 0, index
,
835 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
836 struct ib_device_modify
*props
)
838 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
839 struct mlx5_reg_node_desc in
;
840 struct mlx5_reg_node_desc out
;
843 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
846 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
850 * If possible, pass node desc to FW, so it can generate
851 * a 144 trap. If cmd fails, just ignore.
853 memcpy(&in
, props
->node_desc
, 64);
854 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
855 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
859 memcpy(ibdev
->node_desc
, props
->node_desc
, 64);
864 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
865 struct ib_port_modify
*props
)
867 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
868 struct ib_port_attr attr
;
872 mutex_lock(&dev
->cap_mask_mutex
);
874 err
= mlx5_ib_query_port(ibdev
, port
, &attr
);
878 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
879 ~props
->clr_port_cap_mask
;
881 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
884 mutex_unlock(&dev
->cap_mask_mutex
);
888 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
889 struct ib_udata
*udata
)
891 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
892 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
893 struct mlx5_ib_alloc_ucontext_resp resp
= {};
894 struct mlx5_ib_ucontext
*context
;
895 struct mlx5_uuar_info
*uuari
;
896 struct mlx5_uar
*uars
;
904 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
908 return ERR_PTR(-EAGAIN
);
910 if (udata
->inlen
< sizeof(struct ib_uverbs_cmd_hdr
))
911 return ERR_PTR(-EINVAL
);
913 reqlen
= udata
->inlen
- sizeof(struct ib_uverbs_cmd_hdr
);
914 if (reqlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
916 else if (reqlen
>= min_req_v2
)
919 return ERR_PTR(-EINVAL
);
921 err
= ib_copy_from_udata(&req
, udata
, min(reqlen
, sizeof(req
)));
926 return ERR_PTR(-EINVAL
);
928 if (req
.total_num_uuars
> MLX5_MAX_UUARS
)
929 return ERR_PTR(-ENOMEM
);
931 if (req
.total_num_uuars
== 0)
932 return ERR_PTR(-EINVAL
);
934 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
935 return ERR_PTR(-EOPNOTSUPP
);
937 if (reqlen
> sizeof(req
) &&
938 !ib_is_udata_cleared(udata
, sizeof(req
),
939 reqlen
- sizeof(req
)))
940 return ERR_PTR(-EOPNOTSUPP
);
942 req
.total_num_uuars
= ALIGN(req
.total_num_uuars
,
943 MLX5_NON_FP_BF_REGS_PER_PAGE
);
944 if (req
.num_low_latency_uuars
> req
.total_num_uuars
- 1)
945 return ERR_PTR(-EINVAL
);
947 num_uars
= req
.total_num_uuars
/ MLX5_NON_FP_BF_REGS_PER_PAGE
;
948 gross_uuars
= num_uars
* MLX5_BF_REGS_PER_PAGE
;
949 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
950 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
951 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
952 resp
.cache_line_size
= L1_CACHE_BYTES
;
953 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
954 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
955 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
956 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
957 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
958 resp
.cqe_version
= min_t(__u8
,
959 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
960 req
.max_cqe_version
);
961 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
962 sizeof(resp
.response_length
), udata
->outlen
);
964 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
966 return ERR_PTR(-ENOMEM
);
968 uuari
= &context
->uuari
;
969 mutex_init(&uuari
->lock
);
970 uars
= kcalloc(num_uars
, sizeof(*uars
), GFP_KERNEL
);
976 uuari
->bitmap
= kcalloc(BITS_TO_LONGS(gross_uuars
),
977 sizeof(*uuari
->bitmap
),
979 if (!uuari
->bitmap
) {
984 * clear all fast path uuars
986 for (i
= 0; i
< gross_uuars
; i
++) {
988 if (uuarn
== 2 || uuarn
== 3)
989 set_bit(i
, uuari
->bitmap
);
992 uuari
->count
= kcalloc(gross_uuars
, sizeof(*uuari
->count
), GFP_KERNEL
);
998 for (i
= 0; i
< num_uars
; i
++) {
999 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &uars
[i
].index
);
1004 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1005 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
1008 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
)) {
1009 err
= mlx5_core_alloc_transport_domain(dev
->mdev
,
1015 INIT_LIST_HEAD(&context
->vma_private_list
);
1016 INIT_LIST_HEAD(&context
->db_page_list
);
1017 mutex_init(&context
->db_page_mutex
);
1019 resp
.tot_uuars
= req
.total_num_uuars
;
1020 resp
.num_ports
= MLX5_CAP_GEN(dev
->mdev
, num_ports
);
1022 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
1023 resp
.response_length
+= sizeof(resp
.cqe_version
);
1025 if (field_avail(typeof(resp
), cmds_supp_uhw
, udata
->outlen
)) {
1026 resp
.cmds_supp_uhw
|= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE
;
1027 resp
.response_length
+= sizeof(resp
.cmds_supp_uhw
);
1031 * We don't want to expose information from the PCI bar that is located
1032 * after 4096 bytes, so if the arch only supports larger pages, let's
1033 * pretend we don't support reading the HCA's core clock. This is also
1034 * forced by mmap function.
1036 if (PAGE_SIZE
<= 4096 &&
1037 field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1039 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1040 resp
.hca_core_clock_offset
=
1041 offsetof(struct mlx5_init_seg
, internal_timer_h
) %
1043 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
) +
1044 sizeof(resp
.reserved2
);
1047 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1052 uuari
->num_low_latency_uuars
= req
.num_low_latency_uuars
;
1054 uuari
->num_uars
= num_uars
;
1055 context
->cqe_version
= resp
.cqe_version
;
1057 return &context
->ibucontext
;
1060 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1061 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1064 for (i
--; i
>= 0; i
--)
1065 mlx5_cmd_free_uar(dev
->mdev
, uars
[i
].index
);
1067 kfree(uuari
->count
);
1070 kfree(uuari
->bitmap
);
1077 return ERR_PTR(err
);
1080 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1082 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1083 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1084 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1087 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1088 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1090 for (i
= 0; i
< uuari
->num_uars
; i
++) {
1091 if (mlx5_cmd_free_uar(dev
->mdev
, uuari
->uars
[i
].index
))
1092 mlx5_ib_warn(dev
, "failed to free UAR 0x%x\n", uuari
->uars
[i
].index
);
1095 kfree(uuari
->count
);
1096 kfree(uuari
->bitmap
);
1103 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
, int index
)
1105 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) + index
;
1108 static int get_command(unsigned long offset
)
1110 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1113 static int get_arg(unsigned long offset
)
1115 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1118 static int get_index(unsigned long offset
)
1120 return get_arg(offset
);
1123 static void mlx5_ib_vma_open(struct vm_area_struct
*area
)
1125 /* vma_open is called when a new VMA is created on top of our VMA. This
1126 * is done through either mremap flow or split_vma (usually due to
1127 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1128 * as this VMA is strongly hardware related. Therefore we set the
1129 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1130 * calling us again and trying to do incorrect actions. We assume that
1131 * the original VMA size is exactly a single page, and therefore all
1132 * "splitting" operation will not happen to it.
1134 area
->vm_ops
= NULL
;
1137 static void mlx5_ib_vma_close(struct vm_area_struct
*area
)
1139 struct mlx5_ib_vma_private_data
*mlx5_ib_vma_priv_data
;
1141 /* It's guaranteed that all VMAs opened on a FD are closed before the
1142 * file itself is closed, therefore no sync is needed with the regular
1143 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1144 * However need a sync with accessing the vma as part of
1145 * mlx5_ib_disassociate_ucontext.
1146 * The close operation is usually called under mm->mmap_sem except when
1147 * process is exiting.
1148 * The exiting case is handled explicitly as part of
1149 * mlx5_ib_disassociate_ucontext.
1151 mlx5_ib_vma_priv_data
= (struct mlx5_ib_vma_private_data
*)area
->vm_private_data
;
1153 /* setting the vma context pointer to null in the mlx5_ib driver's
1154 * private data, to protect a race condition in
1155 * mlx5_ib_disassociate_ucontext().
1157 mlx5_ib_vma_priv_data
->vma
= NULL
;
1158 list_del(&mlx5_ib_vma_priv_data
->list
);
1159 kfree(mlx5_ib_vma_priv_data
);
1162 static const struct vm_operations_struct mlx5_ib_vm_ops
= {
1163 .open
= mlx5_ib_vma_open
,
1164 .close
= mlx5_ib_vma_close
1167 static int mlx5_ib_set_vma_data(struct vm_area_struct
*vma
,
1168 struct mlx5_ib_ucontext
*ctx
)
1170 struct mlx5_ib_vma_private_data
*vma_prv
;
1171 struct list_head
*vma_head
= &ctx
->vma_private_list
;
1173 vma_prv
= kzalloc(sizeof(*vma_prv
), GFP_KERNEL
);
1178 vma
->vm_private_data
= vma_prv
;
1179 vma
->vm_ops
= &mlx5_ib_vm_ops
;
1181 list_add(&vma_prv
->list
, vma_head
);
1186 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext
*ibcontext
)
1189 struct vm_area_struct
*vma
;
1190 struct mlx5_ib_vma_private_data
*vma_private
, *n
;
1191 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1192 struct task_struct
*owning_process
= NULL
;
1193 struct mm_struct
*owning_mm
= NULL
;
1195 owning_process
= get_pid_task(ibcontext
->tgid
, PIDTYPE_PID
);
1196 if (!owning_process
)
1199 owning_mm
= get_task_mm(owning_process
);
1201 pr_info("no mm, disassociate ucontext is pending task termination\n");
1203 put_task_struct(owning_process
);
1204 usleep_range(1000, 2000);
1205 owning_process
= get_pid_task(ibcontext
->tgid
,
1207 if (!owning_process
||
1208 owning_process
->state
== TASK_DEAD
) {
1209 pr_info("disassociate ucontext done, task was terminated\n");
1210 /* in case task was dead need to release the
1214 put_task_struct(owning_process
);
1220 /* need to protect from a race on closing the vma as part of
1221 * mlx5_ib_vma_close.
1223 down_read(&owning_mm
->mmap_sem
);
1224 list_for_each_entry_safe(vma_private
, n
, &context
->vma_private_list
,
1226 vma
= vma_private
->vma
;
1227 ret
= zap_vma_ptes(vma
, vma
->vm_start
,
1229 WARN_ONCE(ret
, "%s: zap_vma_ptes failed", __func__
);
1230 /* context going to be destroyed, should
1231 * not access ops any more.
1234 list_del(&vma_private
->list
);
1237 up_read(&owning_mm
->mmap_sem
);
1239 put_task_struct(owning_process
);
1242 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
1245 case MLX5_IB_MMAP_WC_PAGE
:
1247 case MLX5_IB_MMAP_REGULAR_PAGE
:
1248 return "best effort WC";
1249 case MLX5_IB_MMAP_NC_PAGE
:
1256 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
1257 struct vm_area_struct
*vma
,
1258 struct mlx5_ib_ucontext
*context
)
1260 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1263 phys_addr_t pfn
, pa
;
1267 case MLX5_IB_MMAP_WC_PAGE
:
1268 /* Some architectures don't support WC memory */
1269 #if defined(CONFIG_X86)
1272 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1276 case MLX5_IB_MMAP_REGULAR_PAGE
:
1277 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1278 prot
= pgprot_writecombine(vma
->vm_page_prot
);
1280 case MLX5_IB_MMAP_NC_PAGE
:
1281 prot
= pgprot_noncached(vma
->vm_page_prot
);
1287 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1290 idx
= get_index(vma
->vm_pgoff
);
1291 if (idx
>= uuari
->num_uars
)
1294 pfn
= uar_index2pfn(dev
, uuari
->uars
[idx
].index
);
1295 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
1297 vma
->vm_page_prot
= prot
;
1298 err
= io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1299 PAGE_SIZE
, vma
->vm_page_prot
);
1301 mlx5_ib_err(dev
, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1302 err
, vma
->vm_start
, &pfn
, mmap_cmd2str(cmd
));
1306 pa
= pfn
<< PAGE_SHIFT
;
1307 mlx5_ib_dbg(dev
, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd
),
1308 vma
->vm_start
, &pa
);
1310 return mlx5_ib_set_vma_data(vma
, context
);
1313 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
1315 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1316 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1317 unsigned long command
;
1320 command
= get_command(vma
->vm_pgoff
);
1322 case MLX5_IB_MMAP_WC_PAGE
:
1323 case MLX5_IB_MMAP_NC_PAGE
:
1324 case MLX5_IB_MMAP_REGULAR_PAGE
:
1325 return uar_mmap(dev
, command
, vma
, context
);
1327 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
1330 case MLX5_IB_MMAP_CORE_CLOCK
:
1331 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1334 if (vma
->vm_flags
& VM_WRITE
)
1337 /* Don't expose to user-space information it shouldn't have */
1338 if (PAGE_SIZE
> 4096)
1341 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1342 pfn
= (dev
->mdev
->iseg_base
+
1343 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
1345 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1346 PAGE_SIZE
, vma
->vm_page_prot
))
1349 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1351 (unsigned long long)pfn
<< PAGE_SHIFT
);
1361 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
1362 struct ib_ucontext
*context
,
1363 struct ib_udata
*udata
)
1365 struct mlx5_ib_alloc_pd_resp resp
;
1366 struct mlx5_ib_pd
*pd
;
1369 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
1371 return ERR_PTR(-ENOMEM
);
1373 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
1376 return ERR_PTR(err
);
1381 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
1382 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
1384 return ERR_PTR(-EFAULT
);
1391 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
1393 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
1394 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
1396 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
1402 static bool outer_header_zero(u32
*match_criteria
)
1404 int size
= MLX5_ST_SZ_BYTES(fte_match_param
);
1405 char *outer_headers_c
= MLX5_ADDR_OF(fte_match_param
, match_criteria
,
1408 return outer_headers_c
[0] == 0 && !memcmp(outer_headers_c
,
1409 outer_headers_c
+ 1,
1413 static int parse_flow_attr(u32
*match_c
, u32
*match_v
,
1414 union ib_flow_spec
*ib_spec
)
1416 void *outer_headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1418 void *outer_headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1420 switch (ib_spec
->type
) {
1421 case IB_FLOW_SPEC_ETH
:
1422 if (ib_spec
->size
!= sizeof(ib_spec
->eth
))
1425 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1427 ib_spec
->eth
.mask
.dst_mac
);
1428 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1430 ib_spec
->eth
.val
.dst_mac
);
1432 if (ib_spec
->eth
.mask
.vlan_tag
) {
1433 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1435 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1438 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1439 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
1440 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1441 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
1443 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1445 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
1446 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1448 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
1450 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1452 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
1453 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1455 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
1457 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1458 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
1459 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1460 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
1462 case IB_FLOW_SPEC_IPV4
:
1463 if (ib_spec
->size
!= sizeof(ib_spec
->ipv4
))
1466 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1468 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1469 ethertype
, ETH_P_IP
);
1471 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1472 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1473 &ib_spec
->ipv4
.mask
.src_ip
,
1474 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
1475 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1476 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1477 &ib_spec
->ipv4
.val
.src_ip
,
1478 sizeof(ib_spec
->ipv4
.val
.src_ip
));
1479 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1480 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1481 &ib_spec
->ipv4
.mask
.dst_ip
,
1482 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
1483 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1484 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1485 &ib_spec
->ipv4
.val
.dst_ip
,
1486 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
1488 case IB_FLOW_SPEC_IPV6
:
1489 if (ib_spec
->size
!= sizeof(ib_spec
->ipv6
))
1492 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1494 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1495 ethertype
, ETH_P_IPV6
);
1497 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1498 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1499 &ib_spec
->ipv6
.mask
.src_ip
,
1500 sizeof(ib_spec
->ipv6
.mask
.src_ip
));
1501 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1502 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1503 &ib_spec
->ipv6
.val
.src_ip
,
1504 sizeof(ib_spec
->ipv6
.val
.src_ip
));
1505 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1506 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1507 &ib_spec
->ipv6
.mask
.dst_ip
,
1508 sizeof(ib_spec
->ipv6
.mask
.dst_ip
));
1509 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1510 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1511 &ib_spec
->ipv6
.val
.dst_ip
,
1512 sizeof(ib_spec
->ipv6
.val
.dst_ip
));
1514 case IB_FLOW_SPEC_TCP
:
1515 if (ib_spec
->size
!= sizeof(ib_spec
->tcp_udp
))
1518 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, ip_protocol
,
1520 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, ip_protocol
,
1523 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, tcp_sport
,
1524 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1525 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, tcp_sport
,
1526 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1528 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, tcp_dport
,
1529 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1530 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, tcp_dport
,
1531 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1533 case IB_FLOW_SPEC_UDP
:
1534 if (ib_spec
->size
!= sizeof(ib_spec
->tcp_udp
))
1537 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, ip_protocol
,
1539 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, ip_protocol
,
1542 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, udp_sport
,
1543 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1544 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, udp_sport
,
1545 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1547 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, udp_dport
,
1548 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1549 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, udp_dport
,
1550 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1559 /* If a flow could catch both multicast and unicast packets,
1560 * it won't fall into the multicast flow steering table and this rule
1561 * could steal other multicast packets.
1563 static bool flow_is_multicast_only(struct ib_flow_attr
*ib_attr
)
1565 struct ib_flow_spec_eth
*eth_spec
;
1567 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
1568 ib_attr
->size
< sizeof(struct ib_flow_attr
) +
1569 sizeof(struct ib_flow_spec_eth
) ||
1570 ib_attr
->num_of_specs
< 1)
1573 eth_spec
= (struct ib_flow_spec_eth
*)(ib_attr
+ 1);
1574 if (eth_spec
->type
!= IB_FLOW_SPEC_ETH
||
1575 eth_spec
->size
!= sizeof(*eth_spec
))
1578 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
1579 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
1582 static bool is_valid_attr(struct ib_flow_attr
*flow_attr
)
1584 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
1585 bool has_ipv4_spec
= false;
1586 bool eth_type_ipv4
= true;
1587 unsigned int spec_index
;
1589 /* Validate that ethertype is correct */
1590 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1591 if (ib_spec
->type
== IB_FLOW_SPEC_ETH
&&
1592 ib_spec
->eth
.mask
.ether_type
) {
1593 if (!((ib_spec
->eth
.mask
.ether_type
== htons(0xffff)) &&
1594 ib_spec
->eth
.val
.ether_type
== htons(ETH_P_IP
)))
1595 eth_type_ipv4
= false;
1596 } else if (ib_spec
->type
== IB_FLOW_SPEC_IPV4
) {
1597 has_ipv4_spec
= true;
1599 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
1601 return !has_ipv4_spec
|| eth_type_ipv4
;
1604 static void put_flow_table(struct mlx5_ib_dev
*dev
,
1605 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
1607 prio
->refcount
-= !!ft_added
;
1608 if (!prio
->refcount
) {
1609 mlx5_destroy_flow_table(prio
->flow_table
);
1610 prio
->flow_table
= NULL
;
1614 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
1616 struct mlx5_ib_dev
*dev
= to_mdev(flow_id
->qp
->device
);
1617 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
1618 struct mlx5_ib_flow_handler
,
1620 struct mlx5_ib_flow_handler
*iter
, *tmp
;
1622 mutex_lock(&dev
->flow_db
.lock
);
1624 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
1625 mlx5_del_flow_rule(iter
->rule
);
1626 list_del(&iter
->list
);
1630 mlx5_del_flow_rule(handler
->rule
);
1631 put_flow_table(dev
, &dev
->flow_db
.prios
[handler
->prio
], true);
1632 mutex_unlock(&dev
->flow_db
.lock
);
1639 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
1647 #define MLX5_FS_MAX_TYPES 10
1648 #define MLX5_FS_MAX_ENTRIES 32000UL
1649 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
1650 struct ib_flow_attr
*flow_attr
)
1652 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
1653 struct mlx5_flow_namespace
*ns
= NULL
;
1654 struct mlx5_ib_flow_prio
*prio
;
1655 struct mlx5_flow_table
*ft
;
1661 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1662 if (flow_is_multicast_only(flow_attr
) &&
1664 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
1666 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
1668 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1669 MLX5_FLOW_NAMESPACE_BYPASS
);
1670 num_entries
= MLX5_FS_MAX_ENTRIES
;
1671 num_groups
= MLX5_FS_MAX_TYPES
;
1672 prio
= &dev
->flow_db
.prios
[priority
];
1673 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1674 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1675 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1676 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
1677 build_leftovers_ft_param(&priority
,
1680 prio
= &dev
->flow_db
.prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
1684 return ERR_PTR(-ENOTSUPP
);
1686 ft
= prio
->flow_table
;
1688 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
1695 prio
->flow_table
= ft
;
1701 return err
? ERR_PTR(err
) : prio
;
1704 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
1705 struct mlx5_ib_flow_prio
*ft_prio
,
1706 struct ib_flow_attr
*flow_attr
,
1707 struct mlx5_flow_destination
*dst
)
1709 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
1710 struct mlx5_ib_flow_handler
*handler
;
1711 struct mlx5_flow_spec
*spec
;
1712 void *ib_flow
= flow_attr
+ 1;
1713 unsigned int spec_index
;
1717 if (!is_valid_attr(flow_attr
))
1718 return ERR_PTR(-EINVAL
);
1720 spec
= mlx5_vzalloc(sizeof(*spec
));
1721 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
1722 if (!handler
|| !spec
) {
1727 INIT_LIST_HEAD(&handler
->list
);
1729 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1730 err
= parse_flow_attr(spec
->match_criteria
,
1731 spec
->match_value
, ib_flow
);
1735 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
1738 /* Outer header support only */
1739 spec
->match_criteria_enable
= (!outer_header_zero(spec
->match_criteria
))
1741 action
= dst
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
1742 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
1743 handler
->rule
= mlx5_add_flow_rule(ft
, spec
,
1745 MLX5_FS_DEFAULT_FLOW_TAG
,
1748 if (IS_ERR(handler
->rule
)) {
1749 err
= PTR_ERR(handler
->rule
);
1753 handler
->prio
= ft_prio
- dev
->flow_db
.prios
;
1755 ft_prio
->flow_table
= ft
;
1760 return err
? ERR_PTR(err
) : handler
;
1763 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
1764 struct mlx5_ib_flow_prio
*ft_prio
,
1765 struct ib_flow_attr
*flow_attr
,
1766 struct mlx5_flow_destination
*dst
)
1768 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
1769 struct mlx5_ib_flow_handler
*handler
= NULL
;
1771 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
1772 if (!IS_ERR(handler
)) {
1773 handler_dst
= create_flow_rule(dev
, ft_prio
,
1775 if (IS_ERR(handler_dst
)) {
1776 mlx5_del_flow_rule(handler
->rule
);
1778 handler
= handler_dst
;
1780 list_add(&handler_dst
->list
, &handler
->list
);
1791 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
1792 struct mlx5_ib_flow_prio
*ft_prio
,
1793 struct ib_flow_attr
*flow_attr
,
1794 struct mlx5_flow_destination
*dst
)
1796 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
1797 struct mlx5_ib_flow_handler
*handler
= NULL
;
1800 struct ib_flow_attr flow_attr
;
1801 struct ib_flow_spec_eth eth_flow
;
1802 } leftovers_specs
[] = {
1806 .size
= sizeof(leftovers_specs
[0])
1809 .type
= IB_FLOW_SPEC_ETH
,
1810 .size
= sizeof(struct ib_flow_spec_eth
),
1811 .mask
= {.dst_mac
= {0x1} },
1812 .val
= {.dst_mac
= {0x1} }
1818 .size
= sizeof(leftovers_specs
[0])
1821 .type
= IB_FLOW_SPEC_ETH
,
1822 .size
= sizeof(struct ib_flow_spec_eth
),
1823 .mask
= {.dst_mac
= {0x1} },
1824 .val
= {.dst_mac
= {} }
1829 handler
= create_flow_rule(dev
, ft_prio
,
1830 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
1832 if (!IS_ERR(handler
) &&
1833 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
1834 handler_ucast
= create_flow_rule(dev
, ft_prio
,
1835 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
1837 if (IS_ERR(handler_ucast
)) {
1839 handler
= handler_ucast
;
1841 list_add(&handler_ucast
->list
, &handler
->list
);
1848 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
1849 struct ib_flow_attr
*flow_attr
,
1852 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
1853 struct mlx5_ib_flow_handler
*handler
= NULL
;
1854 struct mlx5_flow_destination
*dst
= NULL
;
1855 struct mlx5_ib_flow_prio
*ft_prio
;
1858 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
1859 return ERR_PTR(-ENOSPC
);
1861 if (domain
!= IB_FLOW_DOMAIN_USER
||
1862 flow_attr
->port
> MLX5_CAP_GEN(dev
->mdev
, num_ports
) ||
1863 (flow_attr
->flags
& ~IB_FLOW_ATTR_FLAGS_DONT_TRAP
))
1864 return ERR_PTR(-EINVAL
);
1866 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
1868 return ERR_PTR(-ENOMEM
);
1870 mutex_lock(&dev
->flow_db
.lock
);
1872 ft_prio
= get_flow_table(dev
, flow_attr
);
1873 if (IS_ERR(ft_prio
)) {
1874 err
= PTR_ERR(ft_prio
);
1878 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
1879 dst
->tir_num
= to_mqp(qp
)->raw_packet_qp
.rq
.tirn
;
1881 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1882 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
1883 handler
= create_dont_trap_rule(dev
, ft_prio
,
1886 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
,
1889 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1890 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1891 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
1898 if (IS_ERR(handler
)) {
1899 err
= PTR_ERR(handler
);
1904 ft_prio
->refcount
++;
1905 mutex_unlock(&dev
->flow_db
.lock
);
1908 return &handler
->ibflow
;
1911 put_flow_table(dev
, ft_prio
, false);
1913 mutex_unlock(&dev
->flow_db
.lock
);
1916 return ERR_PTR(err
);
1919 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1921 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1924 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1926 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
1927 ibqp
->qp_num
, gid
->raw
);
1932 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1934 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1937 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1939 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
1940 ibqp
->qp_num
, gid
->raw
);
1945 static int init_node_data(struct mlx5_ib_dev
*dev
)
1949 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
1953 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
1955 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
1958 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
1961 struct mlx5_ib_dev
*dev
=
1962 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1964 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
1967 static ssize_t
show_reg_pages(struct device
*device
,
1968 struct device_attribute
*attr
, char *buf
)
1970 struct mlx5_ib_dev
*dev
=
1971 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1973 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
1976 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
1979 struct mlx5_ib_dev
*dev
=
1980 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1981 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
1984 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
1987 struct mlx5_ib_dev
*dev
=
1988 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1989 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
1992 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
1995 struct mlx5_ib_dev
*dev
=
1996 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1997 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
1998 dev
->mdev
->board_id
);
2001 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
2002 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
2003 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
2004 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
2005 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
2007 static struct device_attribute
*mlx5_class_attributes
[] = {
2012 &dev_attr_reg_pages
,
2015 static void pkey_change_handler(struct work_struct
*work
)
2017 struct mlx5_ib_port_resources
*ports
=
2018 container_of(work
, struct mlx5_ib_port_resources
,
2021 mutex_lock(&ports
->devr
->mutex
);
2022 mlx5_ib_gsi_pkey_change(ports
->gsi
);
2023 mutex_unlock(&ports
->devr
->mutex
);
2026 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev
*ibdev
)
2028 struct mlx5_ib_qp
*mqp
;
2029 struct mlx5_ib_cq
*send_mcq
, *recv_mcq
;
2030 struct mlx5_core_cq
*mcq
;
2031 struct list_head cq_armed_list
;
2032 unsigned long flags_qp
;
2033 unsigned long flags_cq
;
2034 unsigned long flags
;
2036 INIT_LIST_HEAD(&cq_armed_list
);
2038 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2039 spin_lock_irqsave(&ibdev
->reset_flow_resource_lock
, flags
);
2040 list_for_each_entry(mqp
, &ibdev
->qp_list
, qps_list
) {
2041 spin_lock_irqsave(&mqp
->sq
.lock
, flags_qp
);
2042 if (mqp
->sq
.tail
!= mqp
->sq
.head
) {
2043 send_mcq
= to_mcq(mqp
->ibqp
.send_cq
);
2044 spin_lock_irqsave(&send_mcq
->lock
, flags_cq
);
2045 if (send_mcq
->mcq
.comp
&&
2046 mqp
->ibqp
.send_cq
->comp_handler
) {
2047 if (!send_mcq
->mcq
.reset_notify_added
) {
2048 send_mcq
->mcq
.reset_notify_added
= 1;
2049 list_add_tail(&send_mcq
->mcq
.reset_notify
,
2053 spin_unlock_irqrestore(&send_mcq
->lock
, flags_cq
);
2055 spin_unlock_irqrestore(&mqp
->sq
.lock
, flags_qp
);
2056 spin_lock_irqsave(&mqp
->rq
.lock
, flags_qp
);
2057 /* no handling is needed for SRQ */
2058 if (!mqp
->ibqp
.srq
) {
2059 if (mqp
->rq
.tail
!= mqp
->rq
.head
) {
2060 recv_mcq
= to_mcq(mqp
->ibqp
.recv_cq
);
2061 spin_lock_irqsave(&recv_mcq
->lock
, flags_cq
);
2062 if (recv_mcq
->mcq
.comp
&&
2063 mqp
->ibqp
.recv_cq
->comp_handler
) {
2064 if (!recv_mcq
->mcq
.reset_notify_added
) {
2065 recv_mcq
->mcq
.reset_notify_added
= 1;
2066 list_add_tail(&recv_mcq
->mcq
.reset_notify
,
2070 spin_unlock_irqrestore(&recv_mcq
->lock
,
2074 spin_unlock_irqrestore(&mqp
->rq
.lock
, flags_qp
);
2076 /*At that point all inflight post send were put to be executed as of we
2077 * lock/unlock above locks Now need to arm all involved CQs.
2079 list_for_each_entry(mcq
, &cq_armed_list
, reset_notify
) {
2082 spin_unlock_irqrestore(&ibdev
->reset_flow_resource_lock
, flags
);
2085 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
2086 enum mlx5_dev_event event
, unsigned long param
)
2088 struct mlx5_ib_dev
*ibdev
= (struct mlx5_ib_dev
*)context
;
2089 struct ib_event ibev
;
2094 case MLX5_DEV_EVENT_SYS_ERROR
:
2095 ibdev
->ib_active
= false;
2096 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
2097 mlx5_ib_handle_internal_error(ibdev
);
2100 case MLX5_DEV_EVENT_PORT_UP
:
2101 ibev
.event
= IB_EVENT_PORT_ACTIVE
;
2105 case MLX5_DEV_EVENT_PORT_DOWN
:
2106 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
2107 ibev
.event
= IB_EVENT_PORT_ERR
;
2111 case MLX5_DEV_EVENT_LID_CHANGE
:
2112 ibev
.event
= IB_EVENT_LID_CHANGE
;
2116 case MLX5_DEV_EVENT_PKEY_CHANGE
:
2117 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
2120 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
2123 case MLX5_DEV_EVENT_GUID_CHANGE
:
2124 ibev
.event
= IB_EVENT_GID_CHANGE
;
2128 case MLX5_DEV_EVENT_CLIENT_REREG
:
2129 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
2134 ibev
.device
= &ibdev
->ib_dev
;
2135 ibev
.element
.port_num
= port
;
2137 if (port
< 1 || port
> ibdev
->num_ports
) {
2138 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
2142 if (ibdev
->ib_active
)
2143 ib_dispatch_event(&ibev
);
2146 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
2150 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++)
2151 mlx5_query_ext_port_caps(dev
, port
);
2154 static int get_port_caps(struct mlx5_ib_dev
*dev
)
2156 struct ib_device_attr
*dprops
= NULL
;
2157 struct ib_port_attr
*pprops
= NULL
;
2160 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
2162 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
2166 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
2170 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
2172 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
2176 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
2177 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
2179 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
2183 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
2185 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
2186 pprops
->gid_tbl_len
;
2187 mlx5_ib_dbg(dev
, "pkey_table_len %d, gid_table_len %d\n",
2188 dprops
->max_pkeys
, pprops
->gid_tbl_len
);
2198 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
2202 err
= mlx5_mr_cache_cleanup(dev
);
2204 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
2206 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
2207 ib_free_cq(dev
->umrc
.cq
);
2208 ib_dealloc_pd(dev
->umrc
.pd
);
2215 static int create_umr_res(struct mlx5_ib_dev
*dev
)
2217 struct ib_qp_init_attr
*init_attr
= NULL
;
2218 struct ib_qp_attr
*attr
= NULL
;
2224 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
2225 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
2226 if (!attr
|| !init_attr
) {
2231 pd
= ib_alloc_pd(&dev
->ib_dev
);
2233 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
2238 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
2240 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
2245 init_attr
->send_cq
= cq
;
2246 init_attr
->recv_cq
= cq
;
2247 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
2248 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
2249 init_attr
->cap
.max_send_sge
= 1;
2250 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2251 init_attr
->port_num
= 1;
2252 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
2254 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
2258 qp
->device
= &dev
->ib_dev
;
2261 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2263 attr
->qp_state
= IB_QPS_INIT
;
2265 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
2268 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
2272 memset(attr
, 0, sizeof(*attr
));
2273 attr
->qp_state
= IB_QPS_RTR
;
2274 attr
->path_mtu
= IB_MTU_256
;
2276 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2278 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
2282 memset(attr
, 0, sizeof(*attr
));
2283 attr
->qp_state
= IB_QPS_RTS
;
2284 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2286 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
2294 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
2295 ret
= mlx5_mr_cache_init(dev
);
2297 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
2307 mlx5_ib_destroy_qp(qp
);
2321 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
2323 struct ib_srq_init_attr attr
;
2324 struct mlx5_ib_dev
*dev
;
2325 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
2329 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
2331 mutex_init(&devr
->mutex
);
2333 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
2334 if (IS_ERR(devr
->p0
)) {
2335 ret
= PTR_ERR(devr
->p0
);
2338 devr
->p0
->device
= &dev
->ib_dev
;
2339 devr
->p0
->uobject
= NULL
;
2340 atomic_set(&devr
->p0
->usecnt
, 0);
2342 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
2343 if (IS_ERR(devr
->c0
)) {
2344 ret
= PTR_ERR(devr
->c0
);
2347 devr
->c0
->device
= &dev
->ib_dev
;
2348 devr
->c0
->uobject
= NULL
;
2349 devr
->c0
->comp_handler
= NULL
;
2350 devr
->c0
->event_handler
= NULL
;
2351 devr
->c0
->cq_context
= NULL
;
2352 atomic_set(&devr
->c0
->usecnt
, 0);
2354 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2355 if (IS_ERR(devr
->x0
)) {
2356 ret
= PTR_ERR(devr
->x0
);
2359 devr
->x0
->device
= &dev
->ib_dev
;
2360 devr
->x0
->inode
= NULL
;
2361 atomic_set(&devr
->x0
->usecnt
, 0);
2362 mutex_init(&devr
->x0
->tgt_qp_mutex
);
2363 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
2365 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2366 if (IS_ERR(devr
->x1
)) {
2367 ret
= PTR_ERR(devr
->x1
);
2370 devr
->x1
->device
= &dev
->ib_dev
;
2371 devr
->x1
->inode
= NULL
;
2372 atomic_set(&devr
->x1
->usecnt
, 0);
2373 mutex_init(&devr
->x1
->tgt_qp_mutex
);
2374 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
2376 memset(&attr
, 0, sizeof(attr
));
2377 attr
.attr
.max_sge
= 1;
2378 attr
.attr
.max_wr
= 1;
2379 attr
.srq_type
= IB_SRQT_XRC
;
2380 attr
.ext
.xrc
.cq
= devr
->c0
;
2381 attr
.ext
.xrc
.xrcd
= devr
->x0
;
2383 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2384 if (IS_ERR(devr
->s0
)) {
2385 ret
= PTR_ERR(devr
->s0
);
2388 devr
->s0
->device
= &dev
->ib_dev
;
2389 devr
->s0
->pd
= devr
->p0
;
2390 devr
->s0
->uobject
= NULL
;
2391 devr
->s0
->event_handler
= NULL
;
2392 devr
->s0
->srq_context
= NULL
;
2393 devr
->s0
->srq_type
= IB_SRQT_XRC
;
2394 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
2395 devr
->s0
->ext
.xrc
.cq
= devr
->c0
;
2396 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
2397 atomic_inc(&devr
->s0
->ext
.xrc
.cq
->usecnt
);
2398 atomic_inc(&devr
->p0
->usecnt
);
2399 atomic_set(&devr
->s0
->usecnt
, 0);
2401 memset(&attr
, 0, sizeof(attr
));
2402 attr
.attr
.max_sge
= 1;
2403 attr
.attr
.max_wr
= 1;
2404 attr
.srq_type
= IB_SRQT_BASIC
;
2405 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2406 if (IS_ERR(devr
->s1
)) {
2407 ret
= PTR_ERR(devr
->s1
);
2410 devr
->s1
->device
= &dev
->ib_dev
;
2411 devr
->s1
->pd
= devr
->p0
;
2412 devr
->s1
->uobject
= NULL
;
2413 devr
->s1
->event_handler
= NULL
;
2414 devr
->s1
->srq_context
= NULL
;
2415 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
2416 devr
->s1
->ext
.xrc
.cq
= devr
->c0
;
2417 atomic_inc(&devr
->p0
->usecnt
);
2418 atomic_set(&devr
->s0
->usecnt
, 0);
2420 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
2421 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
2422 pkey_change_handler
);
2423 devr
->ports
[port
].devr
= devr
;
2429 mlx5_ib_destroy_srq(devr
->s0
);
2431 mlx5_ib_dealloc_xrcd(devr
->x1
);
2433 mlx5_ib_dealloc_xrcd(devr
->x0
);
2435 mlx5_ib_destroy_cq(devr
->c0
);
2437 mlx5_ib_dealloc_pd(devr
->p0
);
2442 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
2444 struct mlx5_ib_dev
*dev
=
2445 container_of(devr
, struct mlx5_ib_dev
, devr
);
2448 mlx5_ib_destroy_srq(devr
->s1
);
2449 mlx5_ib_destroy_srq(devr
->s0
);
2450 mlx5_ib_dealloc_xrcd(devr
->x0
);
2451 mlx5_ib_dealloc_xrcd(devr
->x1
);
2452 mlx5_ib_destroy_cq(devr
->c0
);
2453 mlx5_ib_dealloc_pd(devr
->p0
);
2455 /* Make sure no change P_Key work items are still executing */
2456 for (port
= 0; port
< dev
->num_ports
; ++port
)
2457 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
2460 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
2462 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2463 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
2464 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
2465 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
2468 if (ll
== IB_LINK_LAYER_INFINIBAND
)
2469 return RDMA_CORE_PORT_IBA_IB
;
2471 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
2474 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
2477 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
2478 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
2480 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
2481 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
2486 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
2487 struct ib_port_immutable
*immutable
)
2489 struct ib_port_attr attr
;
2492 err
= mlx5_ib_query_port(ibdev
, port_num
, &attr
);
2496 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
2497 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
2498 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
2499 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
2504 static void get_dev_fw_str(struct ib_device
*ibdev
, char *str
,
2507 struct mlx5_ib_dev
*dev
=
2508 container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
2509 snprintf(str
, str_len
, "%d.%d.%04d", fw_rev_maj(dev
->mdev
),
2510 fw_rev_min(dev
->mdev
), fw_rev_sub(dev
->mdev
));
2513 static int mlx5_enable_roce(struct mlx5_ib_dev
*dev
)
2517 dev
->roce
.nb
.notifier_call
= mlx5_netdev_event
;
2518 err
= register_netdevice_notifier(&dev
->roce
.nb
);
2522 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
2524 goto err_unregister_netdevice_notifier
;
2528 err_unregister_netdevice_notifier
:
2529 unregister_netdevice_notifier(&dev
->roce
.nb
);
2533 static void mlx5_disable_roce(struct mlx5_ib_dev
*dev
)
2535 mlx5_nic_vport_disable_roce(dev
->mdev
);
2536 unregister_netdevice_notifier(&dev
->roce
.nb
);
2539 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev
*dev
)
2543 for (i
= 0; i
< dev
->num_ports
; i
++)
2544 mlx5_core_dealloc_q_counter(dev
->mdev
,
2545 dev
->port
[i
].q_cnt_id
);
2548 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev
*dev
)
2553 for (i
= 0; i
< dev
->num_ports
; i
++) {
2554 ret
= mlx5_core_alloc_q_counter(dev
->mdev
,
2555 &dev
->port
[i
].q_cnt_id
);
2558 "couldn't allocate queue counter for port %d, err %d\n",
2560 goto dealloc_counters
;
2568 mlx5_core_dealloc_q_counter(dev
->mdev
,
2569 dev
->port
[i
].q_cnt_id
);
2574 static const char * const names
[] = {
2575 "rx_write_requests",
2577 "rx_atomic_requests",
2580 "duplicate_request",
2581 "rnr_nak_retry_err",
2583 "implied_nak_seq_err",
2584 "local_ack_timeout_err",
2587 static const size_t stats_offsets
[] = {
2588 MLX5_BYTE_OFF(query_q_counter_out
, rx_write_requests
),
2589 MLX5_BYTE_OFF(query_q_counter_out
, rx_read_requests
),
2590 MLX5_BYTE_OFF(query_q_counter_out
, rx_atomic_requests
),
2591 MLX5_BYTE_OFF(query_q_counter_out
, out_of_buffer
),
2592 MLX5_BYTE_OFF(query_q_counter_out
, out_of_sequence
),
2593 MLX5_BYTE_OFF(query_q_counter_out
, duplicate_request
),
2594 MLX5_BYTE_OFF(query_q_counter_out
, rnr_nak_retry_err
),
2595 MLX5_BYTE_OFF(query_q_counter_out
, packet_seq_err
),
2596 MLX5_BYTE_OFF(query_q_counter_out
, implied_nak_seq_err
),
2597 MLX5_BYTE_OFF(query_q_counter_out
, local_ack_timeout_err
),
2600 static struct rdma_hw_stats
*mlx5_ib_alloc_hw_stats(struct ib_device
*ibdev
,
2603 BUILD_BUG_ON(ARRAY_SIZE(names
) != ARRAY_SIZE(stats_offsets
));
2605 /* We support only per port stats */
2609 return rdma_alloc_hw_stats_struct(names
, ARRAY_SIZE(names
),
2610 RDMA_HW_STATS_DEFAULT_LIFESPAN
);
2613 static int mlx5_ib_get_hw_stats(struct ib_device
*ibdev
,
2614 struct rdma_hw_stats
*stats
,
2617 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2618 int outlen
= MLX5_ST_SZ_BYTES(query_q_counter_out
);
2624 if (!port
|| !stats
)
2627 out
= mlx5_vzalloc(outlen
);
2631 ret
= mlx5_core_query_q_counter(dev
->mdev
,
2632 dev
->port
[port
- 1].q_cnt_id
, 0,
2637 for (i
= 0; i
< ARRAY_SIZE(names
); i
++) {
2638 val
= *(__be32
*)(out
+ stats_offsets
[i
]);
2639 stats
->value
[i
] = (u64
)be32_to_cpu(val
);
2643 return ARRAY_SIZE(names
);
2646 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
2648 struct mlx5_ib_dev
*dev
;
2649 enum rdma_link_layer ll
;
2654 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
2655 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
2657 if ((ll
== IB_LINK_LAYER_ETHERNET
) && !MLX5_CAP_GEN(mdev
, roce
))
2660 printk_once(KERN_INFO
"%s", mlx5_version
);
2662 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
2668 dev
->port
= kcalloc(MLX5_CAP_GEN(mdev
, num_ports
), sizeof(*dev
->port
),
2673 rwlock_init(&dev
->roce
.netdev_lock
);
2674 err
= get_port_caps(dev
);
2678 if (mlx5_use_mad_ifc(dev
))
2679 get_ext_port_caps(dev
);
2681 MLX5_INIT_DOORBELL_LOCK(&dev
->uar_lock
);
2683 strlcpy(dev
->ib_dev
.name
, "mlx5_%d", IB_DEVICE_NAME_MAX
);
2684 dev
->ib_dev
.owner
= THIS_MODULE
;
2685 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
2686 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
2687 dev
->num_ports
= MLX5_CAP_GEN(mdev
, num_ports
);
2688 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
2689 dev
->ib_dev
.num_comp_vectors
=
2690 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
2691 dev
->ib_dev
.dma_device
= &mdev
->pdev
->dev
;
2693 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
2694 dev
->ib_dev
.uverbs_cmd_mask
=
2695 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
2696 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
2697 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
2698 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
2699 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
2700 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
2701 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
2702 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
2703 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
2704 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
2705 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
2706 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
2707 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
2708 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
2709 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
2710 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
2711 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
2712 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
2713 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
2714 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
2715 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
2716 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
2717 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
2718 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
2719 dev
->ib_dev
.uverbs_ex_cmd_mask
=
2720 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
2721 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
2722 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
);
2724 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
2725 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
2726 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
2727 if (ll
== IB_LINK_LAYER_ETHERNET
)
2728 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
2729 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
2730 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
2731 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
2732 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
2733 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
2734 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
2735 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
2736 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
2737 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
2738 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
2739 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
2740 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
2741 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
2742 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
2743 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
2744 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
2745 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
2746 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
2747 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
2748 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
2749 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
2750 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
2751 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
2752 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
2753 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
2754 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
2755 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
2756 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
2757 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
2758 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
2759 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
2760 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
2761 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
2762 dev
->ib_dev
.rereg_user_mr
= mlx5_ib_rereg_user_mr
;
2763 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
2764 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
2765 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
2766 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
2767 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
2768 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
2769 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
2770 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
2771 dev
->ib_dev
.get_dev_fw_str
= get_dev_fw_str
;
2772 if (mlx5_core_is_pf(mdev
)) {
2773 dev
->ib_dev
.get_vf_config
= mlx5_ib_get_vf_config
;
2774 dev
->ib_dev
.set_vf_link_state
= mlx5_ib_set_vf_link_state
;
2775 dev
->ib_dev
.get_vf_stats
= mlx5_ib_get_vf_stats
;
2776 dev
->ib_dev
.set_vf_guid
= mlx5_ib_set_vf_guid
;
2779 dev
->ib_dev
.disassociate_ucontext
= mlx5_ib_disassociate_ucontext
;
2781 mlx5_ib_internal_fill_odp_caps(dev
);
2783 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
2784 dev
->ib_dev
.alloc_mw
= mlx5_ib_alloc_mw
;
2785 dev
->ib_dev
.dealloc_mw
= mlx5_ib_dealloc_mw
;
2786 dev
->ib_dev
.uverbs_cmd_mask
|=
2787 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
2788 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
2791 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
) &&
2792 MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
)) {
2793 dev
->ib_dev
.get_hw_stats
= mlx5_ib_get_hw_stats
;
2794 dev
->ib_dev
.alloc_hw_stats
= mlx5_ib_alloc_hw_stats
;
2797 if (MLX5_CAP_GEN(mdev
, xrc
)) {
2798 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
2799 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
2800 dev
->ib_dev
.uverbs_cmd_mask
|=
2801 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
2802 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
2805 if (mlx5_ib_port_link_layer(&dev
->ib_dev
, 1) ==
2806 IB_LINK_LAYER_ETHERNET
) {
2807 dev
->ib_dev
.create_flow
= mlx5_ib_create_flow
;
2808 dev
->ib_dev
.destroy_flow
= mlx5_ib_destroy_flow
;
2809 dev
->ib_dev
.create_wq
= mlx5_ib_create_wq
;
2810 dev
->ib_dev
.modify_wq
= mlx5_ib_modify_wq
;
2811 dev
->ib_dev
.destroy_wq
= mlx5_ib_destroy_wq
;
2812 dev
->ib_dev
.create_rwq_ind_table
= mlx5_ib_create_rwq_ind_table
;
2813 dev
->ib_dev
.destroy_rwq_ind_table
= mlx5_ib_destroy_rwq_ind_table
;
2814 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
2815 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
2816 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
) |
2817 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ
) |
2818 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ
) |
2819 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ
) |
2820 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
) |
2821 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
);
2823 err
= init_node_data(dev
);
2827 mutex_init(&dev
->flow_db
.lock
);
2828 mutex_init(&dev
->cap_mask_mutex
);
2829 INIT_LIST_HEAD(&dev
->qp_list
);
2830 spin_lock_init(&dev
->reset_flow_resource_lock
);
2832 if (ll
== IB_LINK_LAYER_ETHERNET
) {
2833 err
= mlx5_enable_roce(dev
);
2838 err
= create_dev_resources(&dev
->devr
);
2840 goto err_disable_roce
;
2842 err
= mlx5_ib_odp_init_one(dev
);
2846 err
= mlx5_ib_alloc_q_counters(dev
);
2850 err
= ib_register_device(&dev
->ib_dev
, NULL
);
2854 err
= create_umr_res(dev
);
2858 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
2859 err
= device_create_file(&dev
->ib_dev
.dev
,
2860 mlx5_class_attributes
[i
]);
2865 dev
->ib_active
= true;
2870 destroy_umrc_res(dev
);
2873 ib_unregister_device(&dev
->ib_dev
);
2876 mlx5_ib_dealloc_q_counters(dev
);
2879 mlx5_ib_odp_remove_one(dev
);
2882 destroy_dev_resources(&dev
->devr
);
2885 if (ll
== IB_LINK_LAYER_ETHERNET
)
2886 mlx5_disable_roce(dev
);
2892 ib_dealloc_device((struct ib_device
*)dev
);
2897 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
2899 struct mlx5_ib_dev
*dev
= context
;
2900 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
, 1);
2902 ib_unregister_device(&dev
->ib_dev
);
2903 mlx5_ib_dealloc_q_counters(dev
);
2904 destroy_umrc_res(dev
);
2905 mlx5_ib_odp_remove_one(dev
);
2906 destroy_dev_resources(&dev
->devr
);
2907 if (ll
== IB_LINK_LAYER_ETHERNET
)
2908 mlx5_disable_roce(dev
);
2910 ib_dealloc_device(&dev
->ib_dev
);
2913 static struct mlx5_interface mlx5_ib_interface
= {
2915 .remove
= mlx5_ib_remove
,
2916 .event
= mlx5_ib_event
,
2917 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
2920 static int __init
mlx5_ib_init(void)
2924 if (deprecated_prof_sel
!= 2)
2925 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2927 err
= mlx5_ib_odp_init();
2931 err
= mlx5_register_interface(&mlx5_ib_interface
);
2938 mlx5_ib_odp_cleanup();
2942 static void __exit
mlx5_ib_cleanup(void)
2944 mlx5_unregister_interface(&mlx5_ib_interface
);
2945 mlx5_ib_odp_cleanup();
2948 module_init(mlx5_ib_init
);
2949 module_exit(mlx5_ib_cleanup
);