2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
40 /* not supported currently */
41 static int wq_signature
;
44 MLX5_IB_ACK_REQ_FREQ
= 8,
48 MLX5_IB_DEFAULT_SCHED_QUEUE
= 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE
= 0x3f,
50 MLX5_IB_LINK_TYPE_IB
= 0,
51 MLX5_IB_LINK_TYPE_ETH
= 1
55 MLX5_IB_SQ_STRIDE
= 6,
56 MLX5_IB_CACHE_LINE_SIZE
= 64,
59 static const u32 mlx5_ib_opcode
[] = {
60 [IB_WR_SEND
] = MLX5_OPCODE_SEND
,
61 [IB_WR_LSO
] = MLX5_OPCODE_LSO
,
62 [IB_WR_SEND_WITH_IMM
] = MLX5_OPCODE_SEND_IMM
,
63 [IB_WR_RDMA_WRITE
] = MLX5_OPCODE_RDMA_WRITE
,
64 [IB_WR_RDMA_WRITE_WITH_IMM
] = MLX5_OPCODE_RDMA_WRITE_IMM
,
65 [IB_WR_RDMA_READ
] = MLX5_OPCODE_RDMA_READ
,
66 [IB_WR_ATOMIC_CMP_AND_SWP
] = MLX5_OPCODE_ATOMIC_CS
,
67 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MLX5_OPCODE_ATOMIC_FA
,
68 [IB_WR_SEND_WITH_INV
] = MLX5_OPCODE_SEND_INVAL
,
69 [IB_WR_LOCAL_INV
] = MLX5_OPCODE_UMR
,
70 [IB_WR_REG_MR
] = MLX5_OPCODE_UMR
,
71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP
] = MLX5_OPCODE_ATOMIC_MASKED_CS
,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
] = MLX5_OPCODE_ATOMIC_MASKED_FA
,
73 [MLX5_IB_WR_UMR
] = MLX5_OPCODE_UMR
,
76 struct mlx5_wqe_eth_pad
{
80 static void get_cqs(enum ib_qp_type qp_type
,
81 struct ib_cq
*ib_send_cq
, struct ib_cq
*ib_recv_cq
,
82 struct mlx5_ib_cq
**send_cq
, struct mlx5_ib_cq
**recv_cq
);
84 static int is_qp0(enum ib_qp_type qp_type
)
86 return qp_type
== IB_QPT_SMI
;
89 static int is_sqp(enum ib_qp_type qp_type
)
91 return is_qp0(qp_type
) || is_qp1(qp_type
);
94 static void *get_wqe(struct mlx5_ib_qp
*qp
, int offset
)
96 return mlx5_buf_offset(&qp
->buf
, offset
);
99 static void *get_recv_wqe(struct mlx5_ib_qp
*qp
, int n
)
101 return get_wqe(qp
, qp
->rq
.offset
+ (n
<< qp
->rq
.wqe_shift
));
104 void *mlx5_get_send_wqe(struct mlx5_ib_qp
*qp
, int n
)
106 return get_wqe(qp
, qp
->sq
.offset
+ (n
<< MLX5_IB_SQ_STRIDE
));
110 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
112 * @qp: QP to copy from.
113 * @send: copy from the send queue when non-zero, use the receive queue
115 * @wqe_index: index to start copying from. For send work queues, the
116 * wqe_index is in units of MLX5_SEND_WQE_BB.
117 * For receive work queue, it is the number of work queue
118 * element in the queue.
119 * @buffer: destination buffer.
120 * @length: maximum number of bytes to copy.
122 * Copies at least a single WQE, but may copy more data.
124 * Return: the number of bytes copied, or an error code.
126 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp
*qp
, int send
, int wqe_index
,
127 void *buffer
, u32 length
,
128 struct mlx5_ib_qp_base
*base
)
130 struct ib_device
*ibdev
= qp
->ibqp
.device
;
131 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
132 struct mlx5_ib_wq
*wq
= send
? &qp
->sq
: &qp
->rq
;
135 struct ib_umem
*umem
= base
->ubuffer
.umem
;
136 u32 first_copy_length
;
140 if (wq
->wqe_cnt
== 0) {
141 mlx5_ib_dbg(dev
, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
146 offset
= wq
->offset
+ ((wqe_index
% wq
->wqe_cnt
) << wq
->wqe_shift
);
147 wq_end
= wq
->offset
+ (wq
->wqe_cnt
<< wq
->wqe_shift
);
149 if (send
&& length
< sizeof(struct mlx5_wqe_ctrl_seg
))
152 if (offset
> umem
->length
||
153 (send
&& offset
+ sizeof(struct mlx5_wqe_ctrl_seg
) > umem
->length
))
156 first_copy_length
= min_t(u32
, offset
+ length
, wq_end
) - offset
;
157 ret
= ib_umem_copy_from(buffer
, umem
, offset
, first_copy_length
);
162 struct mlx5_wqe_ctrl_seg
*ctrl
= buffer
;
163 int ds
= be32_to_cpu(ctrl
->qpn_ds
) & MLX5_WQE_CTRL_DS_MASK
;
165 wqe_length
= ds
* MLX5_WQE_DS_UNITS
;
167 wqe_length
= 1 << wq
->wqe_shift
;
170 if (wqe_length
<= first_copy_length
)
171 return first_copy_length
;
173 ret
= ib_umem_copy_from(buffer
+ first_copy_length
, umem
, wq
->offset
,
174 wqe_length
- first_copy_length
);
181 static void mlx5_ib_qp_event(struct mlx5_core_qp
*qp
, int type
)
183 struct ib_qp
*ibqp
= &to_mibqp(qp
)->ibqp
;
184 struct ib_event event
;
186 if (type
== MLX5_EVENT_TYPE_PATH_MIG
) {
187 /* This event is only valid for trans_qps */
188 to_mibqp(qp
)->port
= to_mibqp(qp
)->trans_qp
.alt_port
;
191 if (ibqp
->event_handler
) {
192 event
.device
= ibqp
->device
;
193 event
.element
.qp
= ibqp
;
195 case MLX5_EVENT_TYPE_PATH_MIG
:
196 event
.event
= IB_EVENT_PATH_MIG
;
198 case MLX5_EVENT_TYPE_COMM_EST
:
199 event
.event
= IB_EVENT_COMM_EST
;
201 case MLX5_EVENT_TYPE_SQ_DRAINED
:
202 event
.event
= IB_EVENT_SQ_DRAINED
;
204 case MLX5_EVENT_TYPE_SRQ_LAST_WQE
:
205 event
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
207 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR
:
208 event
.event
= IB_EVENT_QP_FATAL
;
210 case MLX5_EVENT_TYPE_PATH_MIG_FAILED
:
211 event
.event
= IB_EVENT_PATH_MIG_ERR
;
213 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
214 event
.event
= IB_EVENT_QP_REQ_ERR
;
216 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR
:
217 event
.event
= IB_EVENT_QP_ACCESS_ERR
;
220 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type
, qp
->qpn
);
224 ibqp
->event_handler(&event
, ibqp
->qp_context
);
228 static int set_rq_size(struct mlx5_ib_dev
*dev
, struct ib_qp_cap
*cap
,
229 int has_rq
, struct mlx5_ib_qp
*qp
, struct mlx5_ib_create_qp
*ucmd
)
234 /* Sanity check RQ size before proceeding */
235 if (cap
->max_recv_wr
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
)))
241 qp
->rq
.wqe_shift
= 0;
242 cap
->max_recv_wr
= 0;
243 cap
->max_recv_sge
= 0;
246 qp
->rq
.wqe_cnt
= ucmd
->rq_wqe_count
;
247 qp
->rq
.wqe_shift
= ucmd
->rq_wqe_shift
;
248 qp
->rq
.max_gs
= (1 << qp
->rq
.wqe_shift
) / sizeof(struct mlx5_wqe_data_seg
) - qp
->wq_sig
;
249 qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
251 wqe_size
= qp
->wq_sig
? sizeof(struct mlx5_wqe_signature_seg
) : 0;
252 wqe_size
+= cap
->max_recv_sge
* sizeof(struct mlx5_wqe_data_seg
);
253 wqe_size
= roundup_pow_of_two(wqe_size
);
254 wq_size
= roundup_pow_of_two(cap
->max_recv_wr
) * wqe_size
;
255 wq_size
= max_t(int, wq_size
, MLX5_SEND_WQE_BB
);
256 qp
->rq
.wqe_cnt
= wq_size
/ wqe_size
;
257 if (wqe_size
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
)) {
258 mlx5_ib_dbg(dev
, "wqe_size %d, max %d\n",
260 MLX5_CAP_GEN(dev
->mdev
,
264 qp
->rq
.wqe_shift
= ilog2(wqe_size
);
265 qp
->rq
.max_gs
= (1 << qp
->rq
.wqe_shift
) / sizeof(struct mlx5_wqe_data_seg
) - qp
->wq_sig
;
266 qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
273 static int sq_overhead(struct ib_qp_init_attr
*attr
)
277 switch (attr
->qp_type
) {
279 size
+= sizeof(struct mlx5_wqe_xrc_seg
);
282 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
283 max(sizeof(struct mlx5_wqe_atomic_seg
) +
284 sizeof(struct mlx5_wqe_raddr_seg
),
285 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
286 sizeof(struct mlx5_mkey_seg
));
293 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
294 max(sizeof(struct mlx5_wqe_raddr_seg
),
295 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
296 sizeof(struct mlx5_mkey_seg
));
300 if (attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)
301 size
+= sizeof(struct mlx5_wqe_eth_pad
) +
302 sizeof(struct mlx5_wqe_eth_seg
);
305 case MLX5_IB_QPT_HW_GSI
:
306 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
307 sizeof(struct mlx5_wqe_datagram_seg
);
310 case MLX5_IB_QPT_REG_UMR
:
311 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
312 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
313 sizeof(struct mlx5_mkey_seg
);
323 static int calc_send_wqe(struct ib_qp_init_attr
*attr
)
328 size
= sq_overhead(attr
);
332 if (attr
->cap
.max_inline_data
) {
333 inl_size
= size
+ sizeof(struct mlx5_wqe_inline_seg
) +
334 attr
->cap
.max_inline_data
;
337 size
+= attr
->cap
.max_send_sge
* sizeof(struct mlx5_wqe_data_seg
);
338 if (attr
->create_flags
& IB_QP_CREATE_SIGNATURE_EN
&&
339 ALIGN(max_t(int, inl_size
, size
), MLX5_SEND_WQE_BB
) < MLX5_SIG_WQE_SIZE
)
340 return MLX5_SIG_WQE_SIZE
;
342 return ALIGN(max_t(int, inl_size
, size
), MLX5_SEND_WQE_BB
);
345 static int calc_sq_size(struct mlx5_ib_dev
*dev
, struct ib_qp_init_attr
*attr
,
346 struct mlx5_ib_qp
*qp
)
351 if (!attr
->cap
.max_send_wr
)
354 wqe_size
= calc_send_wqe(attr
);
355 mlx5_ib_dbg(dev
, "wqe_size %d\n", wqe_size
);
359 if (wqe_size
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
)) {
360 mlx5_ib_dbg(dev
, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
361 wqe_size
, MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
));
365 qp
->max_inline_data
= wqe_size
- sq_overhead(attr
) -
366 sizeof(struct mlx5_wqe_inline_seg
);
367 attr
->cap
.max_inline_data
= qp
->max_inline_data
;
369 if (attr
->create_flags
& IB_QP_CREATE_SIGNATURE_EN
)
370 qp
->signature_en
= true;
372 wq_size
= roundup_pow_of_two(attr
->cap
.max_send_wr
* wqe_size
);
373 qp
->sq
.wqe_cnt
= wq_size
/ MLX5_SEND_WQE_BB
;
374 if (qp
->sq
.wqe_cnt
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
))) {
375 mlx5_ib_dbg(dev
, "wqe count(%d) exceeds limits(%d)\n",
377 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
));
380 qp
->sq
.wqe_shift
= ilog2(MLX5_SEND_WQE_BB
);
381 qp
->sq
.max_gs
= attr
->cap
.max_send_sge
;
382 qp
->sq
.max_post
= wq_size
/ wqe_size
;
383 attr
->cap
.max_send_wr
= qp
->sq
.max_post
;
388 static int set_user_buf_size(struct mlx5_ib_dev
*dev
,
389 struct mlx5_ib_qp
*qp
,
390 struct mlx5_ib_create_qp
*ucmd
,
391 struct mlx5_ib_qp_base
*base
,
392 struct ib_qp_init_attr
*attr
)
394 int desc_sz
= 1 << qp
->sq
.wqe_shift
;
396 if (desc_sz
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
)) {
397 mlx5_ib_warn(dev
, "desc_sz %d, max_sq_desc_sz %d\n",
398 desc_sz
, MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
));
402 if (ucmd
->sq_wqe_count
&& ((1 << ilog2(ucmd
->sq_wqe_count
)) != ucmd
->sq_wqe_count
)) {
403 mlx5_ib_warn(dev
, "sq_wqe_count %d, sq_wqe_count %d\n",
404 ucmd
->sq_wqe_count
, ucmd
->sq_wqe_count
);
408 qp
->sq
.wqe_cnt
= ucmd
->sq_wqe_count
;
410 if (qp
->sq
.wqe_cnt
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
))) {
411 mlx5_ib_warn(dev
, "wqe_cnt %d, max_wqes %d\n",
413 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
));
417 if (attr
->qp_type
== IB_QPT_RAW_PACKET
) {
418 base
->ubuffer
.buf_size
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
419 qp
->raw_packet_qp
.sq
.ubuffer
.buf_size
= qp
->sq
.wqe_cnt
<< 6;
421 base
->ubuffer
.buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
422 (qp
->sq
.wqe_cnt
<< 6);
428 static int qp_has_rq(struct ib_qp_init_attr
*attr
)
430 if (attr
->qp_type
== IB_QPT_XRC_INI
||
431 attr
->qp_type
== IB_QPT_XRC_TGT
|| attr
->srq
||
432 attr
->qp_type
== MLX5_IB_QPT_REG_UMR
||
433 !attr
->cap
.max_recv_wr
)
439 static int first_med_uuar(void)
444 static int next_uuar(int n
)
448 while (((n
% 4) & 2))
454 static int num_med_uuar(struct mlx5_uuar_info
*uuari
)
458 n
= uuari
->num_uars
* MLX5_NON_FP_BF_REGS_PER_PAGE
-
459 uuari
->num_low_latency_uuars
- 1;
461 return n
>= 0 ? n
: 0;
464 static int max_uuari(struct mlx5_uuar_info
*uuari
)
466 return uuari
->num_uars
* 4;
469 static int first_hi_uuar(struct mlx5_uuar_info
*uuari
)
475 med
= num_med_uuar(uuari
);
476 for (t
= 0, i
= first_med_uuar();; i
= next_uuar(i
)) {
485 static int alloc_high_class_uuar(struct mlx5_uuar_info
*uuari
)
489 for (i
= first_hi_uuar(uuari
); i
< max_uuari(uuari
); i
= next_uuar(i
)) {
490 if (!test_bit(i
, uuari
->bitmap
)) {
491 set_bit(i
, uuari
->bitmap
);
500 static int alloc_med_class_uuar(struct mlx5_uuar_info
*uuari
)
502 int minidx
= first_med_uuar();
505 for (i
= first_med_uuar(); i
< first_hi_uuar(uuari
); i
= next_uuar(i
)) {
506 if (uuari
->count
[i
] < uuari
->count
[minidx
])
510 uuari
->count
[minidx
]++;
514 static int alloc_uuar(struct mlx5_uuar_info
*uuari
,
515 enum mlx5_ib_latency_class lat
)
519 mutex_lock(&uuari
->lock
);
521 case MLX5_IB_LATENCY_CLASS_LOW
:
523 uuari
->count
[uuarn
]++;
526 case MLX5_IB_LATENCY_CLASS_MEDIUM
:
530 uuarn
= alloc_med_class_uuar(uuari
);
533 case MLX5_IB_LATENCY_CLASS_HIGH
:
537 uuarn
= alloc_high_class_uuar(uuari
);
540 case MLX5_IB_LATENCY_CLASS_FAST_PATH
:
544 mutex_unlock(&uuari
->lock
);
549 static void free_med_class_uuar(struct mlx5_uuar_info
*uuari
, int uuarn
)
551 clear_bit(uuarn
, uuari
->bitmap
);
552 --uuari
->count
[uuarn
];
555 static void free_high_class_uuar(struct mlx5_uuar_info
*uuari
, int uuarn
)
557 clear_bit(uuarn
, uuari
->bitmap
);
558 --uuari
->count
[uuarn
];
561 static void free_uuar(struct mlx5_uuar_info
*uuari
, int uuarn
)
563 int nuuars
= uuari
->num_uars
* MLX5_BF_REGS_PER_PAGE
;
564 int high_uuar
= nuuars
- uuari
->num_low_latency_uuars
;
566 mutex_lock(&uuari
->lock
);
568 --uuari
->count
[uuarn
];
572 if (uuarn
< high_uuar
) {
573 free_med_class_uuar(uuari
, uuarn
);
577 free_high_class_uuar(uuari
, uuarn
);
580 mutex_unlock(&uuari
->lock
);
583 static enum mlx5_qp_state
to_mlx5_state(enum ib_qp_state state
)
586 case IB_QPS_RESET
: return MLX5_QP_STATE_RST
;
587 case IB_QPS_INIT
: return MLX5_QP_STATE_INIT
;
588 case IB_QPS_RTR
: return MLX5_QP_STATE_RTR
;
589 case IB_QPS_RTS
: return MLX5_QP_STATE_RTS
;
590 case IB_QPS_SQD
: return MLX5_QP_STATE_SQD
;
591 case IB_QPS_SQE
: return MLX5_QP_STATE_SQER
;
592 case IB_QPS_ERR
: return MLX5_QP_STATE_ERR
;
597 static int to_mlx5_st(enum ib_qp_type type
)
600 case IB_QPT_RC
: return MLX5_QP_ST_RC
;
601 case IB_QPT_UC
: return MLX5_QP_ST_UC
;
602 case IB_QPT_UD
: return MLX5_QP_ST_UD
;
603 case MLX5_IB_QPT_REG_UMR
: return MLX5_QP_ST_REG_UMR
;
605 case IB_QPT_XRC_TGT
: return MLX5_QP_ST_XRC
;
606 case IB_QPT_SMI
: return MLX5_QP_ST_QP0
;
607 case MLX5_IB_QPT_HW_GSI
: return MLX5_QP_ST_QP1
;
608 case IB_QPT_RAW_IPV6
: return MLX5_QP_ST_RAW_IPV6
;
609 case IB_QPT_RAW_PACKET
:
610 case IB_QPT_RAW_ETHERTYPE
: return MLX5_QP_ST_RAW_ETHERTYPE
;
612 default: return -EINVAL
;
616 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq
*send_cq
,
617 struct mlx5_ib_cq
*recv_cq
);
618 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq
*send_cq
,
619 struct mlx5_ib_cq
*recv_cq
);
621 static int uuarn_to_uar_index(struct mlx5_uuar_info
*uuari
, int uuarn
)
623 return uuari
->uars
[uuarn
/ MLX5_BF_REGS_PER_PAGE
].index
;
626 static int mlx5_ib_umem_get(struct mlx5_ib_dev
*dev
,
628 unsigned long addr
, size_t size
,
629 struct ib_umem
**umem
,
630 int *npages
, int *page_shift
, int *ncont
,
635 *umem
= ib_umem_get(pd
->uobject
->context
, addr
, size
, 0, 0);
637 mlx5_ib_dbg(dev
, "umem_get failed\n");
638 return PTR_ERR(*umem
);
641 mlx5_ib_cont_pages(*umem
, addr
, npages
, page_shift
, ncont
, NULL
);
643 err
= mlx5_ib_get_buf_offset(addr
, *page_shift
, offset
);
645 mlx5_ib_warn(dev
, "bad offset\n");
649 mlx5_ib_dbg(dev
, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
650 addr
, size
, *npages
, *page_shift
, *ncont
, *offset
);
655 ib_umem_release(*umem
);
661 static void destroy_user_rq(struct ib_pd
*pd
, struct mlx5_ib_rwq
*rwq
)
663 struct mlx5_ib_ucontext
*context
;
665 context
= to_mucontext(pd
->uobject
->context
);
666 mlx5_ib_db_unmap_user(context
, &rwq
->db
);
668 ib_umem_release(rwq
->umem
);
671 static int create_user_rq(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
672 struct mlx5_ib_rwq
*rwq
,
673 struct mlx5_ib_create_wq
*ucmd
)
675 struct mlx5_ib_ucontext
*context
;
685 context
= to_mucontext(pd
->uobject
->context
);
686 rwq
->umem
= ib_umem_get(pd
->uobject
->context
, ucmd
->buf_addr
,
687 rwq
->buf_size
, 0, 0);
688 if (IS_ERR(rwq
->umem
)) {
689 mlx5_ib_dbg(dev
, "umem_get failed\n");
690 err
= PTR_ERR(rwq
->umem
);
694 mlx5_ib_cont_pages(rwq
->umem
, ucmd
->buf_addr
, &npages
, &page_shift
,
696 err
= mlx5_ib_get_buf_offset(ucmd
->buf_addr
, page_shift
,
697 &rwq
->rq_page_offset
);
699 mlx5_ib_warn(dev
, "bad offset\n");
703 rwq
->rq_num_pas
= ncont
;
704 rwq
->page_shift
= page_shift
;
705 rwq
->log_page_size
= page_shift
- MLX5_ADAPTER_PAGE_SHIFT
;
706 rwq
->wq_sig
= !!(ucmd
->flags
& MLX5_WQ_FLAG_SIGNATURE
);
708 mlx5_ib_dbg(dev
, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
709 (unsigned long long)ucmd
->buf_addr
, rwq
->buf_size
,
710 npages
, page_shift
, ncont
, offset
);
712 err
= mlx5_ib_db_map_user(context
, ucmd
->db_addr
, &rwq
->db
);
714 mlx5_ib_dbg(dev
, "map failed\n");
718 rwq
->create_type
= MLX5_WQ_USER
;
722 ib_umem_release(rwq
->umem
);
726 static int create_user_qp(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
727 struct mlx5_ib_qp
*qp
, struct ib_udata
*udata
,
728 struct ib_qp_init_attr
*attr
,
730 struct mlx5_ib_create_qp_resp
*resp
, int *inlen
,
731 struct mlx5_ib_qp_base
*base
)
733 struct mlx5_ib_ucontext
*context
;
734 struct mlx5_ib_create_qp ucmd
;
735 struct mlx5_ib_ubuffer
*ubuffer
= &base
->ubuffer
;
746 err
= ib_copy_from_udata(&ucmd
, udata
, sizeof(ucmd
));
748 mlx5_ib_dbg(dev
, "copy failed\n");
752 context
= to_mucontext(pd
->uobject
->context
);
754 * TBD: should come from the verbs when we have the API
756 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
757 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
758 uuarn
= MLX5_CROSS_CHANNEL_UUAR
;
760 uuarn
= alloc_uuar(&context
->uuari
, MLX5_IB_LATENCY_CLASS_HIGH
);
762 mlx5_ib_dbg(dev
, "failed to allocate low latency UUAR\n");
763 mlx5_ib_dbg(dev
, "reverting to medium latency\n");
764 uuarn
= alloc_uuar(&context
->uuari
, MLX5_IB_LATENCY_CLASS_MEDIUM
);
766 mlx5_ib_dbg(dev
, "failed to allocate medium latency UUAR\n");
767 mlx5_ib_dbg(dev
, "reverting to high latency\n");
768 uuarn
= alloc_uuar(&context
->uuari
, MLX5_IB_LATENCY_CLASS_LOW
);
770 mlx5_ib_warn(dev
, "uuar allocation failed\n");
777 uar_index
= uuarn_to_uar_index(&context
->uuari
, uuarn
);
778 mlx5_ib_dbg(dev
, "uuarn 0x%x, uar_index 0x%x\n", uuarn
, uar_index
);
781 qp
->sq
.wqe_shift
= ilog2(MLX5_SEND_WQE_BB
);
782 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
784 err
= set_user_buf_size(dev
, qp
, &ucmd
, base
, attr
);
788 if (ucmd
.buf_addr
&& ubuffer
->buf_size
) {
789 ubuffer
->buf_addr
= ucmd
.buf_addr
;
790 err
= mlx5_ib_umem_get(dev
, pd
, ubuffer
->buf_addr
,
792 &ubuffer
->umem
, &npages
, &page_shift
,
797 ubuffer
->umem
= NULL
;
800 *inlen
= MLX5_ST_SZ_BYTES(create_qp_in
) +
801 MLX5_FLD_SZ_BYTES(create_qp_in
, pas
[0]) * ncont
;
802 *in
= mlx5_vzalloc(*inlen
);
808 pas
= (__be64
*)MLX5_ADDR_OF(create_qp_in
, *in
, pas
);
810 mlx5_ib_populate_pas(dev
, ubuffer
->umem
, page_shift
, pas
, 0);
812 qpc
= MLX5_ADDR_OF(create_qp_in
, *in
, qpc
);
814 MLX5_SET(qpc
, qpc
, log_page_size
, page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
815 MLX5_SET(qpc
, qpc
, page_offset
, offset
);
817 MLX5_SET(qpc
, qpc
, uar_page
, uar_index
);
818 resp
->uuar_index
= uuarn
;
821 err
= mlx5_ib_db_map_user(context
, ucmd
.db_addr
, &qp
->db
);
823 mlx5_ib_dbg(dev
, "map failed\n");
827 err
= ib_copy_to_udata(udata
, resp
, sizeof(*resp
));
829 mlx5_ib_dbg(dev
, "copy failed\n");
832 qp
->create_type
= MLX5_QP_USER
;
837 mlx5_ib_db_unmap_user(context
, &qp
->db
);
844 ib_umem_release(ubuffer
->umem
);
847 free_uuar(&context
->uuari
, uuarn
);
851 static void destroy_qp_user(struct ib_pd
*pd
, struct mlx5_ib_qp
*qp
,
852 struct mlx5_ib_qp_base
*base
)
854 struct mlx5_ib_ucontext
*context
;
856 context
= to_mucontext(pd
->uobject
->context
);
857 mlx5_ib_db_unmap_user(context
, &qp
->db
);
858 if (base
->ubuffer
.umem
)
859 ib_umem_release(base
->ubuffer
.umem
);
860 free_uuar(&context
->uuari
, qp
->uuarn
);
863 static int create_kernel_qp(struct mlx5_ib_dev
*dev
,
864 struct ib_qp_init_attr
*init_attr
,
865 struct mlx5_ib_qp
*qp
,
866 u32
**in
, int *inlen
,
867 struct mlx5_ib_qp_base
*base
)
869 enum mlx5_ib_latency_class lc
= MLX5_IB_LATENCY_CLASS_LOW
;
870 struct mlx5_uuar_info
*uuari
;
876 uuari
= &dev
->mdev
->priv
.uuari
;
877 if (init_attr
->create_flags
& ~(IB_QP_CREATE_SIGNATURE_EN
|
878 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
|
879 IB_QP_CREATE_IPOIB_UD_LSO
|
880 mlx5_ib_create_qp_sqpn_qp1()))
883 if (init_attr
->qp_type
== MLX5_IB_QPT_REG_UMR
)
884 lc
= MLX5_IB_LATENCY_CLASS_FAST_PATH
;
886 uuarn
= alloc_uuar(uuari
, lc
);
888 mlx5_ib_dbg(dev
, "\n");
892 qp
->bf
= &uuari
->bfs
[uuarn
];
893 uar_index
= qp
->bf
->uar
->index
;
895 err
= calc_sq_size(dev
, init_attr
, qp
);
897 mlx5_ib_dbg(dev
, "err %d\n", err
);
902 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
903 base
->ubuffer
.buf_size
= err
+ (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
);
905 err
= mlx5_buf_alloc(dev
->mdev
, base
->ubuffer
.buf_size
, &qp
->buf
);
907 mlx5_ib_dbg(dev
, "err %d\n", err
);
911 qp
->sq
.qend
= mlx5_get_send_wqe(qp
, qp
->sq
.wqe_cnt
);
912 *inlen
= MLX5_ST_SZ_BYTES(create_qp_in
) +
913 MLX5_FLD_SZ_BYTES(create_qp_in
, pas
[0]) * qp
->buf
.npages
;
914 *in
= mlx5_vzalloc(*inlen
);
920 qpc
= MLX5_ADDR_OF(create_qp_in
, *in
, qpc
);
921 MLX5_SET(qpc
, qpc
, uar_page
, uar_index
);
922 MLX5_SET(qpc
, qpc
, log_page_size
, qp
->buf
.page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
924 /* Set "fast registration enabled" for all kernel QPs */
925 MLX5_SET(qpc
, qpc
, fre
, 1);
926 MLX5_SET(qpc
, qpc
, rlky
, 1);
928 if (init_attr
->create_flags
& mlx5_ib_create_qp_sqpn_qp1()) {
929 MLX5_SET(qpc
, qpc
, deth_sqpn
, 1);
930 qp
->flags
|= MLX5_IB_QP_SQPN_QP1
;
933 mlx5_fill_page_array(&qp
->buf
,
934 (__be64
*)MLX5_ADDR_OF(create_qp_in
, *in
, pas
));
936 err
= mlx5_db_alloc(dev
->mdev
, &qp
->db
);
938 mlx5_ib_dbg(dev
, "err %d\n", err
);
942 qp
->sq
.wrid
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.wrid
), GFP_KERNEL
);
943 qp
->sq
.wr_data
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.wr_data
), GFP_KERNEL
);
944 qp
->rq
.wrid
= kmalloc(qp
->rq
.wqe_cnt
* sizeof(*qp
->rq
.wrid
), GFP_KERNEL
);
945 qp
->sq
.w_list
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.w_list
), GFP_KERNEL
);
946 qp
->sq
.wqe_head
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.wqe_head
), GFP_KERNEL
);
948 if (!qp
->sq
.wrid
|| !qp
->sq
.wr_data
|| !qp
->rq
.wrid
||
949 !qp
->sq
.w_list
|| !qp
->sq
.wqe_head
) {
953 qp
->create_type
= MLX5_QP_KERNEL
;
958 mlx5_db_free(dev
->mdev
, &qp
->db
);
959 kfree(qp
->sq
.wqe_head
);
960 kfree(qp
->sq
.w_list
);
962 kfree(qp
->sq
.wr_data
);
969 mlx5_buf_free(dev
->mdev
, &qp
->buf
);
972 free_uuar(&dev
->mdev
->priv
.uuari
, uuarn
);
976 static void destroy_qp_kernel(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
978 mlx5_db_free(dev
->mdev
, &qp
->db
);
979 kfree(qp
->sq
.wqe_head
);
980 kfree(qp
->sq
.w_list
);
982 kfree(qp
->sq
.wr_data
);
984 mlx5_buf_free(dev
->mdev
, &qp
->buf
);
985 free_uuar(&dev
->mdev
->priv
.uuari
, qp
->bf
->uuarn
);
988 static u32
get_rx_type(struct mlx5_ib_qp
*qp
, struct ib_qp_init_attr
*attr
)
990 if (attr
->srq
|| (attr
->qp_type
== IB_QPT_XRC_TGT
) ||
991 (attr
->qp_type
== IB_QPT_XRC_INI
))
993 else if (!qp
->has_rq
)
994 return MLX5_ZERO_LEN_RQ
;
996 return MLX5_NON_ZERO_RQ
;
999 static int is_connected(enum ib_qp_type qp_type
)
1001 if (qp_type
== IB_QPT_RC
|| qp_type
== IB_QPT_UC
)
1007 static int create_raw_packet_qp_tis(struct mlx5_ib_dev
*dev
,
1008 struct mlx5_ib_sq
*sq
, u32 tdn
)
1010 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)] = {0};
1011 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
1013 MLX5_SET(tisc
, tisc
, transport_domain
, tdn
);
1014 return mlx5_core_create_tis(dev
->mdev
, in
, sizeof(in
), &sq
->tisn
);
1017 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev
*dev
,
1018 struct mlx5_ib_sq
*sq
)
1020 mlx5_core_destroy_tis(dev
->mdev
, sq
->tisn
);
1023 static int create_raw_packet_qp_sq(struct mlx5_ib_dev
*dev
,
1024 struct mlx5_ib_sq
*sq
, void *qpin
,
1027 struct mlx5_ib_ubuffer
*ubuffer
= &sq
->ubuffer
;
1031 void *qpc
= MLX5_ADDR_OF(create_qp_in
, qpin
, qpc
);
1040 err
= mlx5_ib_umem_get(dev
, pd
, ubuffer
->buf_addr
, ubuffer
->buf_size
,
1041 &sq
->ubuffer
.umem
, &npages
, &page_shift
,
1046 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) + sizeof(u64
) * ncont
;
1047 in
= mlx5_vzalloc(inlen
);
1053 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
1054 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
1055 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
1056 MLX5_SET(sqc
, sqc
, user_index
, MLX5_GET(qpc
, qpc
, user_index
));
1057 MLX5_SET(sqc
, sqc
, cqn
, MLX5_GET(qpc
, qpc
, cqn_snd
));
1058 MLX5_SET(sqc
, sqc
, tis_lst_sz
, 1);
1059 MLX5_SET(sqc
, sqc
, tis_num_0
, sq
->tisn
);
1061 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1062 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1063 MLX5_SET(wq
, wq
, pd
, MLX5_GET(qpc
, qpc
, pd
));
1064 MLX5_SET(wq
, wq
, uar_page
, MLX5_GET(qpc
, qpc
, uar_page
));
1065 MLX5_SET64(wq
, wq
, dbr_addr
, MLX5_GET64(qpc
, qpc
, dbr_addr
));
1066 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1067 MLX5_SET(wq
, wq
, log_wq_sz
, MLX5_GET(qpc
, qpc
, log_sq_size
));
1068 MLX5_SET(wq
, wq
, log_wq_pg_sz
, page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
1069 MLX5_SET(wq
, wq
, page_offset
, offset
);
1071 pas
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
1072 mlx5_ib_populate_pas(dev
, sq
->ubuffer
.umem
, page_shift
, pas
, 0);
1074 err
= mlx5_core_create_sq_tracked(dev
->mdev
, in
, inlen
, &sq
->base
.mqp
);
1084 ib_umem_release(sq
->ubuffer
.umem
);
1085 sq
->ubuffer
.umem
= NULL
;
1090 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev
*dev
,
1091 struct mlx5_ib_sq
*sq
)
1093 mlx5_core_destroy_sq_tracked(dev
->mdev
, &sq
->base
.mqp
);
1094 ib_umem_release(sq
->ubuffer
.umem
);
1097 static int get_rq_pas_size(void *qpc
)
1099 u32 log_page_size
= MLX5_GET(qpc
, qpc
, log_page_size
) + 12;
1100 u32 log_rq_stride
= MLX5_GET(qpc
, qpc
, log_rq_stride
);
1101 u32 log_rq_size
= MLX5_GET(qpc
, qpc
, log_rq_size
);
1102 u32 page_offset
= MLX5_GET(qpc
, qpc
, page_offset
);
1103 u32 po_quanta
= 1 << (log_page_size
- 6);
1104 u32 rq_sz
= 1 << (log_rq_size
+ 4 + log_rq_stride
);
1105 u32 page_size
= 1 << log_page_size
;
1106 u32 rq_sz_po
= rq_sz
+ (page_offset
* po_quanta
);
1107 u32 rq_num_pas
= (rq_sz_po
+ page_size
- 1) / page_size
;
1109 return rq_num_pas
* sizeof(u64
);
1112 static int create_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
1113 struct mlx5_ib_rq
*rq
, void *qpin
)
1115 struct mlx5_ib_qp
*mqp
= rq
->base
.container_mibqp
;
1121 void *qpc
= MLX5_ADDR_OF(create_qp_in
, qpin
, qpc
);
1124 u32 rq_pas_size
= get_rq_pas_size(qpc
);
1126 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) + rq_pas_size
;
1127 in
= mlx5_vzalloc(inlen
);
1131 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
1132 MLX5_SET(rqc
, rqc
, vsd
, 1);
1133 MLX5_SET(rqc
, rqc
, mem_rq_type
, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
);
1134 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
1135 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
1136 MLX5_SET(rqc
, rqc
, user_index
, MLX5_GET(qpc
, qpc
, user_index
));
1137 MLX5_SET(rqc
, rqc
, cqn
, MLX5_GET(qpc
, qpc
, cqn_rcv
));
1139 if (mqp
->flags
& MLX5_IB_QP_CAP_SCATTER_FCS
)
1140 MLX5_SET(rqc
, rqc
, scatter_fcs
, 1);
1142 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1143 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1144 MLX5_SET(wq
, wq
, end_padding_mode
,
1145 MLX5_GET(qpc
, qpc
, end_padding_mode
));
1146 MLX5_SET(wq
, wq
, page_offset
, MLX5_GET(qpc
, qpc
, page_offset
));
1147 MLX5_SET(wq
, wq
, pd
, MLX5_GET(qpc
, qpc
, pd
));
1148 MLX5_SET64(wq
, wq
, dbr_addr
, MLX5_GET64(qpc
, qpc
, dbr_addr
));
1149 MLX5_SET(wq
, wq
, log_wq_stride
, MLX5_GET(qpc
, qpc
, log_rq_stride
) + 4);
1150 MLX5_SET(wq
, wq
, log_wq_pg_sz
, MLX5_GET(qpc
, qpc
, log_page_size
));
1151 MLX5_SET(wq
, wq
, log_wq_sz
, MLX5_GET(qpc
, qpc
, log_rq_size
));
1153 pas
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
1154 qp_pas
= (__be64
*)MLX5_ADDR_OF(create_qp_in
, qpin
, pas
);
1155 memcpy(pas
, qp_pas
, rq_pas_size
);
1157 err
= mlx5_core_create_rq_tracked(dev
->mdev
, in
, inlen
, &rq
->base
.mqp
);
1164 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
1165 struct mlx5_ib_rq
*rq
)
1167 mlx5_core_destroy_rq_tracked(dev
->mdev
, &rq
->base
.mqp
);
1170 static int create_raw_packet_qp_tir(struct mlx5_ib_dev
*dev
,
1171 struct mlx5_ib_rq
*rq
, u32 tdn
)
1178 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1179 in
= mlx5_vzalloc(inlen
);
1183 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1184 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_DIRECT
);
1185 MLX5_SET(tirc
, tirc
, inline_rqn
, rq
->base
.mqp
.qpn
);
1186 MLX5_SET(tirc
, tirc
, transport_domain
, tdn
);
1188 err
= mlx5_core_create_tir(dev
->mdev
, in
, inlen
, &rq
->tirn
);
1195 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev
*dev
,
1196 struct mlx5_ib_rq
*rq
)
1198 mlx5_core_destroy_tir(dev
->mdev
, rq
->tirn
);
1201 static int create_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1205 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
1206 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1207 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1208 struct ib_uobject
*uobj
= pd
->uobject
;
1209 struct ib_ucontext
*ucontext
= uobj
->context
;
1210 struct mlx5_ib_ucontext
*mucontext
= to_mucontext(ucontext
);
1212 u32 tdn
= mucontext
->tdn
;
1214 if (qp
->sq
.wqe_cnt
) {
1215 err
= create_raw_packet_qp_tis(dev
, sq
, tdn
);
1219 err
= create_raw_packet_qp_sq(dev
, sq
, in
, pd
);
1221 goto err_destroy_tis
;
1223 sq
->base
.container_mibqp
= qp
;
1226 if (qp
->rq
.wqe_cnt
) {
1227 rq
->base
.container_mibqp
= qp
;
1229 err
= create_raw_packet_qp_rq(dev
, rq
, in
);
1231 goto err_destroy_sq
;
1234 err
= create_raw_packet_qp_tir(dev
, rq
, tdn
);
1236 goto err_destroy_rq
;
1239 qp
->trans_qp
.base
.mqp
.qpn
= qp
->sq
.wqe_cnt
? sq
->base
.mqp
.qpn
:
1245 destroy_raw_packet_qp_rq(dev
, rq
);
1247 if (!qp
->sq
.wqe_cnt
)
1249 destroy_raw_packet_qp_sq(dev
, sq
);
1251 destroy_raw_packet_qp_tis(dev
, sq
);
1256 static void destroy_raw_packet_qp(struct mlx5_ib_dev
*dev
,
1257 struct mlx5_ib_qp
*qp
)
1259 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
1260 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1261 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1263 if (qp
->rq
.wqe_cnt
) {
1264 destroy_raw_packet_qp_tir(dev
, rq
);
1265 destroy_raw_packet_qp_rq(dev
, rq
);
1268 if (qp
->sq
.wqe_cnt
) {
1269 destroy_raw_packet_qp_sq(dev
, sq
);
1270 destroy_raw_packet_qp_tis(dev
, sq
);
1274 static void raw_packet_qp_copy_info(struct mlx5_ib_qp
*qp
,
1275 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
)
1277 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1278 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1282 sq
->doorbell
= &qp
->db
;
1283 rq
->doorbell
= &qp
->db
;
1286 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
1288 mlx5_core_destroy_tir(dev
->mdev
, qp
->rss_qp
.tirn
);
1291 static int create_rss_raw_qp_tir(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1293 struct ib_qp_init_attr
*init_attr
,
1294 struct ib_udata
*udata
)
1296 struct ib_uobject
*uobj
= pd
->uobject
;
1297 struct ib_ucontext
*ucontext
= uobj
->context
;
1298 struct mlx5_ib_ucontext
*mucontext
= to_mucontext(ucontext
);
1299 struct mlx5_ib_create_qp_resp resp
= {};
1305 u32 selected_fields
= 0;
1306 size_t min_resp_len
;
1307 u32 tdn
= mucontext
->tdn
;
1308 struct mlx5_ib_create_qp_rss ucmd
= {};
1309 size_t required_cmd_sz
;
1311 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
)
1314 if (init_attr
->create_flags
|| init_attr
->send_cq
)
1317 min_resp_len
= offsetof(typeof(resp
), uuar_index
) + sizeof(resp
.uuar_index
);
1318 if (udata
->outlen
< min_resp_len
)
1321 required_cmd_sz
= offsetof(typeof(ucmd
), reserved1
) + sizeof(ucmd
.reserved1
);
1322 if (udata
->inlen
< required_cmd_sz
) {
1323 mlx5_ib_dbg(dev
, "invalid inlen\n");
1327 if (udata
->inlen
> sizeof(ucmd
) &&
1328 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
1329 udata
->inlen
- sizeof(ucmd
))) {
1330 mlx5_ib_dbg(dev
, "inlen is not supported\n");
1334 if (ib_copy_from_udata(&ucmd
, udata
, min(sizeof(ucmd
), udata
->inlen
))) {
1335 mlx5_ib_dbg(dev
, "copy failed\n");
1339 if (ucmd
.comp_mask
) {
1340 mlx5_ib_dbg(dev
, "invalid comp mask\n");
1344 if (memchr_inv(ucmd
.reserved
, 0, sizeof(ucmd
.reserved
)) || ucmd
.reserved1
) {
1345 mlx5_ib_dbg(dev
, "invalid reserved\n");
1349 err
= ib_copy_to_udata(udata
, &resp
, min_resp_len
);
1351 mlx5_ib_dbg(dev
, "copy failed\n");
1355 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1356 in
= mlx5_vzalloc(inlen
);
1360 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1361 MLX5_SET(tirc
, tirc
, disp_type
,
1362 MLX5_TIRC_DISP_TYPE_INDIRECT
);
1363 MLX5_SET(tirc
, tirc
, indirect_table
,
1364 init_attr
->rwq_ind_tbl
->ind_tbl_num
);
1365 MLX5_SET(tirc
, tirc
, transport_domain
, tdn
);
1367 hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
1368 switch (ucmd
.rx_hash_function
) {
1369 case MLX5_RX_HASH_FUNC_TOEPLITZ
:
1371 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_toeplitz_key
);
1372 size_t len
= MLX5_FLD_SZ_BYTES(tirc
, rx_hash_toeplitz_key
);
1374 if (len
!= ucmd
.rx_key_len
) {
1379 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_TOEPLITZ
);
1380 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
1381 memcpy(rss_key
, ucmd
.rx_hash_key
, len
);
1389 if (!ucmd
.rx_hash_fields_mask
) {
1390 /* special case when this TIR serves as steering entry without hashing */
1391 if (!init_attr
->rwq_ind_tbl
->log_ind_tbl_size
)
1397 if (((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV4
) ||
1398 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV4
)) &&
1399 ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV6
) ||
1400 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV6
))) {
1405 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1406 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV4
) ||
1407 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV4
))
1408 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1409 MLX5_L3_PROT_TYPE_IPV4
);
1410 else if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV6
) ||
1411 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV6
))
1412 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1413 MLX5_L3_PROT_TYPE_IPV6
);
1415 if (((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_TCP
) ||
1416 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_TCP
)) &&
1417 ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_UDP
) ||
1418 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_UDP
))) {
1423 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1424 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_TCP
) ||
1425 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_TCP
))
1426 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1427 MLX5_L4_PROT_TYPE_TCP
);
1428 else if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_UDP
) ||
1429 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_UDP
))
1430 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1431 MLX5_L4_PROT_TYPE_UDP
);
1433 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV4
) ||
1434 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV6
))
1435 selected_fields
|= MLX5_HASH_FIELD_SEL_SRC_IP
;
1437 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV4
) ||
1438 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV6
))
1439 selected_fields
|= MLX5_HASH_FIELD_SEL_DST_IP
;
1441 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_TCP
) ||
1442 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_UDP
))
1443 selected_fields
|= MLX5_HASH_FIELD_SEL_L4_SPORT
;
1445 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_TCP
) ||
1446 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_UDP
))
1447 selected_fields
|= MLX5_HASH_FIELD_SEL_L4_DPORT
;
1449 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
, selected_fields
);
1452 err
= mlx5_core_create_tir(dev
->mdev
, in
, inlen
, &qp
->rss_qp
.tirn
);
1458 /* qpn is reserved for that QP */
1459 qp
->trans_qp
.base
.mqp
.qpn
= 0;
1460 qp
->flags
|= MLX5_IB_QP_RSS
;
1468 static int create_qp_common(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
1469 struct ib_qp_init_attr
*init_attr
,
1470 struct ib_udata
*udata
, struct mlx5_ib_qp
*qp
)
1472 struct mlx5_ib_resources
*devr
= &dev
->devr
;
1473 int inlen
= MLX5_ST_SZ_BYTES(create_qp_in
);
1474 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1475 struct mlx5_ib_create_qp_resp resp
;
1476 struct mlx5_ib_cq
*send_cq
;
1477 struct mlx5_ib_cq
*recv_cq
;
1478 unsigned long flags
;
1479 u32 uidx
= MLX5_IB_DEFAULT_UIDX
;
1480 struct mlx5_ib_create_qp ucmd
;
1481 struct mlx5_ib_qp_base
*base
;
1486 base
= init_attr
->qp_type
== IB_QPT_RAW_PACKET
?
1487 &qp
->raw_packet_qp
.rq
.base
:
1490 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
)
1491 mlx5_ib_odp_create_qp(qp
);
1493 mutex_init(&qp
->mutex
);
1494 spin_lock_init(&qp
->sq
.lock
);
1495 spin_lock_init(&qp
->rq
.lock
);
1497 if (init_attr
->rwq_ind_tbl
) {
1501 err
= create_rss_raw_qp_tir(dev
, qp
, pd
, init_attr
, udata
);
1505 if (init_attr
->create_flags
& IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
) {
1506 if (!MLX5_CAP_GEN(mdev
, block_lb_mc
)) {
1507 mlx5_ib_dbg(dev
, "block multicast loopback isn't supported\n");
1510 qp
->flags
|= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
;
1514 if (init_attr
->create_flags
&
1515 (IB_QP_CREATE_CROSS_CHANNEL
|
1516 IB_QP_CREATE_MANAGED_SEND
|
1517 IB_QP_CREATE_MANAGED_RECV
)) {
1518 if (!MLX5_CAP_GEN(mdev
, cd
)) {
1519 mlx5_ib_dbg(dev
, "cross-channel isn't supported\n");
1522 if (init_attr
->create_flags
& IB_QP_CREATE_CROSS_CHANNEL
)
1523 qp
->flags
|= MLX5_IB_QP_CROSS_CHANNEL
;
1524 if (init_attr
->create_flags
& IB_QP_CREATE_MANAGED_SEND
)
1525 qp
->flags
|= MLX5_IB_QP_MANAGED_SEND
;
1526 if (init_attr
->create_flags
& IB_QP_CREATE_MANAGED_RECV
)
1527 qp
->flags
|= MLX5_IB_QP_MANAGED_RECV
;
1530 if (init_attr
->qp_type
== IB_QPT_UD
&&
1531 (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
))
1532 if (!MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
1533 mlx5_ib_dbg(dev
, "ipoib UD lso qp isn't supported\n");
1537 if (init_attr
->create_flags
& IB_QP_CREATE_SCATTER_FCS
) {
1538 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
) {
1539 mlx5_ib_dbg(dev
, "Scatter FCS is supported only for Raw Packet QPs");
1542 if (!MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) ||
1543 !MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
)) {
1544 mlx5_ib_dbg(dev
, "Scatter FCS isn't supported\n");
1547 qp
->flags
|= MLX5_IB_QP_CAP_SCATTER_FCS
;
1550 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
)
1551 qp
->sq_signal_bits
= MLX5_WQE_CTRL_CQ_UPDATE
;
1553 if (pd
&& pd
->uobject
) {
1554 if (ib_copy_from_udata(&ucmd
, udata
, sizeof(ucmd
))) {
1555 mlx5_ib_dbg(dev
, "copy failed\n");
1559 err
= get_qp_user_index(to_mucontext(pd
->uobject
->context
),
1560 &ucmd
, udata
->inlen
, &uidx
);
1564 qp
->wq_sig
= !!(ucmd
.flags
& MLX5_QP_FLAG_SIGNATURE
);
1565 qp
->scat_cqe
= !!(ucmd
.flags
& MLX5_QP_FLAG_SCATTER_CQE
);
1567 qp
->wq_sig
= !!wq_signature
;
1570 qp
->has_rq
= qp_has_rq(init_attr
);
1571 err
= set_rq_size(dev
, &init_attr
->cap
, qp
->has_rq
,
1572 qp
, (pd
&& pd
->uobject
) ? &ucmd
: NULL
);
1574 mlx5_ib_dbg(dev
, "err %d\n", err
);
1581 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
1582 mlx5_ib_dbg(dev
, "requested sq_wqe_count (%d)\n", ucmd
.sq_wqe_count
);
1583 if (ucmd
.rq_wqe_shift
!= qp
->rq
.wqe_shift
||
1584 ucmd
.rq_wqe_count
!= qp
->rq
.wqe_cnt
) {
1585 mlx5_ib_dbg(dev
, "invalid rq params\n");
1588 if (ucmd
.sq_wqe_count
> max_wqes
) {
1589 mlx5_ib_dbg(dev
, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1590 ucmd
.sq_wqe_count
, max_wqes
);
1593 if (init_attr
->create_flags
&
1594 mlx5_ib_create_qp_sqpn_qp1()) {
1595 mlx5_ib_dbg(dev
, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1598 err
= create_user_qp(dev
, pd
, qp
, udata
, init_attr
, &in
,
1599 &resp
, &inlen
, base
);
1601 mlx5_ib_dbg(dev
, "err %d\n", err
);
1603 err
= create_kernel_qp(dev
, init_attr
, qp
, &in
, &inlen
,
1606 mlx5_ib_dbg(dev
, "err %d\n", err
);
1612 in
= mlx5_vzalloc(inlen
);
1616 qp
->create_type
= MLX5_QP_EMPTY
;
1619 if (is_sqp(init_attr
->qp_type
))
1620 qp
->port
= init_attr
->port_num
;
1622 qpc
= MLX5_ADDR_OF(create_qp_in
, in
, qpc
);
1624 MLX5_SET(qpc
, qpc
, st
, to_mlx5_st(init_attr
->qp_type
));
1625 MLX5_SET(qpc
, qpc
, pm_state
, MLX5_QP_PM_MIGRATED
);
1627 if (init_attr
->qp_type
!= MLX5_IB_QPT_REG_UMR
)
1628 MLX5_SET(qpc
, qpc
, pd
, to_mpd(pd
? pd
: devr
->p0
)->pdn
);
1630 MLX5_SET(qpc
, qpc
, latency_sensitive
, 1);
1634 MLX5_SET(qpc
, qpc
, wq_signature
, 1);
1636 if (qp
->flags
& MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
1637 MLX5_SET(qpc
, qpc
, block_lb_mc
, 1);
1639 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
1640 MLX5_SET(qpc
, qpc
, cd_master
, 1);
1641 if (qp
->flags
& MLX5_IB_QP_MANAGED_SEND
)
1642 MLX5_SET(qpc
, qpc
, cd_slave_send
, 1);
1643 if (qp
->flags
& MLX5_IB_QP_MANAGED_RECV
)
1644 MLX5_SET(qpc
, qpc
, cd_slave_receive
, 1);
1646 if (qp
->scat_cqe
&& is_connected(init_attr
->qp_type
)) {
1650 rcqe_sz
= mlx5_ib_get_cqe_size(dev
, init_attr
->recv_cq
);
1651 scqe_sz
= mlx5_ib_get_cqe_size(dev
, init_attr
->send_cq
);
1654 MLX5_SET(qpc
, qpc
, cs_res
, MLX5_RES_SCAT_DATA64_CQE
);
1656 MLX5_SET(qpc
, qpc
, cs_res
, MLX5_RES_SCAT_DATA32_CQE
);
1658 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
) {
1660 MLX5_SET(qpc
, qpc
, cs_req
, MLX5_REQ_SCAT_DATA64_CQE
);
1662 MLX5_SET(qpc
, qpc
, cs_req
, MLX5_REQ_SCAT_DATA32_CQE
);
1666 if (qp
->rq
.wqe_cnt
) {
1667 MLX5_SET(qpc
, qpc
, log_rq_stride
, qp
->rq
.wqe_shift
- 4);
1668 MLX5_SET(qpc
, qpc
, log_rq_size
, ilog2(qp
->rq
.wqe_cnt
));
1671 MLX5_SET(qpc
, qpc
, rq_type
, get_rx_type(qp
, init_attr
));
1674 MLX5_SET(qpc
, qpc
, log_sq_size
, ilog2(qp
->sq
.wqe_cnt
));
1676 MLX5_SET(qpc
, qpc
, no_sq
, 1);
1678 /* Set default resources */
1679 switch (init_attr
->qp_type
) {
1680 case IB_QPT_XRC_TGT
:
1681 MLX5_SET(qpc
, qpc
, cqn_rcv
, to_mcq(devr
->c0
)->mcq
.cqn
);
1682 MLX5_SET(qpc
, qpc
, cqn_snd
, to_mcq(devr
->c0
)->mcq
.cqn
);
1683 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(devr
->s0
)->msrq
.srqn
);
1684 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(init_attr
->xrcd
)->xrcdn
);
1686 case IB_QPT_XRC_INI
:
1687 MLX5_SET(qpc
, qpc
, cqn_rcv
, to_mcq(devr
->c0
)->mcq
.cqn
);
1688 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(devr
->x1
)->xrcdn
);
1689 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(devr
->s0
)->msrq
.srqn
);
1692 if (init_attr
->srq
) {
1693 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(devr
->x0
)->xrcdn
);
1694 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(init_attr
->srq
)->msrq
.srqn
);
1696 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(devr
->x1
)->xrcdn
);
1697 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(devr
->s1
)->msrq
.srqn
);
1701 if (init_attr
->send_cq
)
1702 MLX5_SET(qpc
, qpc
, cqn_snd
, to_mcq(init_attr
->send_cq
)->mcq
.cqn
);
1704 if (init_attr
->recv_cq
)
1705 MLX5_SET(qpc
, qpc
, cqn_rcv
, to_mcq(init_attr
->recv_cq
)->mcq
.cqn
);
1707 MLX5_SET64(qpc
, qpc
, dbr_addr
, qp
->db
.dma
);
1709 /* 0xffffff means we ask to work with cqe version 0 */
1710 if (MLX5_CAP_GEN(mdev
, cqe_version
) == MLX5_CQE_VERSION_V1
)
1711 MLX5_SET(qpc
, qpc
, user_index
, uidx
);
1713 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1714 if (init_attr
->qp_type
== IB_QPT_UD
&&
1715 (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)) {
1716 MLX5_SET(qpc
, qpc
, ulp_stateless_offload_mode
, 1);
1717 qp
->flags
|= MLX5_IB_QP_LSO
;
1720 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
) {
1721 qp
->raw_packet_qp
.sq
.ubuffer
.buf_addr
= ucmd
.sq_buf_addr
;
1722 raw_packet_qp_copy_info(qp
, &qp
->raw_packet_qp
);
1723 err
= create_raw_packet_qp(dev
, qp
, in
, pd
);
1725 err
= mlx5_core_create_qp(dev
->mdev
, &base
->mqp
, in
, inlen
);
1729 mlx5_ib_dbg(dev
, "create qp failed\n");
1735 base
->container_mibqp
= qp
;
1736 base
->mqp
.event
= mlx5_ib_qp_event
;
1738 get_cqs(init_attr
->qp_type
, init_attr
->send_cq
, init_attr
->recv_cq
,
1739 &send_cq
, &recv_cq
);
1740 spin_lock_irqsave(&dev
->reset_flow_resource_lock
, flags
);
1741 mlx5_ib_lock_cqs(send_cq
, recv_cq
);
1742 /* Maintain device to QPs access, needed for further handling via reset
1745 list_add_tail(&qp
->qps_list
, &dev
->qp_list
);
1746 /* Maintain CQ to QPs access, needed for further handling via reset flow
1749 list_add_tail(&qp
->cq_send_list
, &send_cq
->list_send_qp
);
1751 list_add_tail(&qp
->cq_recv_list
, &recv_cq
->list_recv_qp
);
1752 mlx5_ib_unlock_cqs(send_cq
, recv_cq
);
1753 spin_unlock_irqrestore(&dev
->reset_flow_resource_lock
, flags
);
1758 if (qp
->create_type
== MLX5_QP_USER
)
1759 destroy_qp_user(pd
, qp
, base
);
1760 else if (qp
->create_type
== MLX5_QP_KERNEL
)
1761 destroy_qp_kernel(dev
, qp
);
1767 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq
*send_cq
, struct mlx5_ib_cq
*recv_cq
)
1768 __acquires(&send_cq
->lock
) __acquires(&recv_cq
->lock
)
1772 if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
1773 spin_lock(&send_cq
->lock
);
1774 spin_lock_nested(&recv_cq
->lock
,
1775 SINGLE_DEPTH_NESTING
);
1776 } else if (send_cq
->mcq
.cqn
== recv_cq
->mcq
.cqn
) {
1777 spin_lock(&send_cq
->lock
);
1778 __acquire(&recv_cq
->lock
);
1780 spin_lock(&recv_cq
->lock
);
1781 spin_lock_nested(&send_cq
->lock
,
1782 SINGLE_DEPTH_NESTING
);
1785 spin_lock(&send_cq
->lock
);
1786 __acquire(&recv_cq
->lock
);
1788 } else if (recv_cq
) {
1789 spin_lock(&recv_cq
->lock
);
1790 __acquire(&send_cq
->lock
);
1792 __acquire(&send_cq
->lock
);
1793 __acquire(&recv_cq
->lock
);
1797 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq
*send_cq
, struct mlx5_ib_cq
*recv_cq
)
1798 __releases(&send_cq
->lock
) __releases(&recv_cq
->lock
)
1802 if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
1803 spin_unlock(&recv_cq
->lock
);
1804 spin_unlock(&send_cq
->lock
);
1805 } else if (send_cq
->mcq
.cqn
== recv_cq
->mcq
.cqn
) {
1806 __release(&recv_cq
->lock
);
1807 spin_unlock(&send_cq
->lock
);
1809 spin_unlock(&send_cq
->lock
);
1810 spin_unlock(&recv_cq
->lock
);
1813 __release(&recv_cq
->lock
);
1814 spin_unlock(&send_cq
->lock
);
1816 } else if (recv_cq
) {
1817 __release(&send_cq
->lock
);
1818 spin_unlock(&recv_cq
->lock
);
1820 __release(&recv_cq
->lock
);
1821 __release(&send_cq
->lock
);
1825 static struct mlx5_ib_pd
*get_pd(struct mlx5_ib_qp
*qp
)
1827 return to_mpd(qp
->ibqp
.pd
);
1830 static void get_cqs(enum ib_qp_type qp_type
,
1831 struct ib_cq
*ib_send_cq
, struct ib_cq
*ib_recv_cq
,
1832 struct mlx5_ib_cq
**send_cq
, struct mlx5_ib_cq
**recv_cq
)
1835 case IB_QPT_XRC_TGT
:
1839 case MLX5_IB_QPT_REG_UMR
:
1840 case IB_QPT_XRC_INI
:
1841 *send_cq
= ib_send_cq
? to_mcq(ib_send_cq
) : NULL
;
1846 case MLX5_IB_QPT_HW_GSI
:
1850 case IB_QPT_RAW_IPV6
:
1851 case IB_QPT_RAW_ETHERTYPE
:
1852 case IB_QPT_RAW_PACKET
:
1853 *send_cq
= ib_send_cq
? to_mcq(ib_send_cq
) : NULL
;
1854 *recv_cq
= ib_recv_cq
? to_mcq(ib_recv_cq
) : NULL
;
1865 static int modify_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1868 static void destroy_qp_common(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
1870 struct mlx5_ib_cq
*send_cq
, *recv_cq
;
1871 struct mlx5_ib_qp_base
*base
= &qp
->trans_qp
.base
;
1872 unsigned long flags
;
1875 if (qp
->ibqp
.rwq_ind_tbl
) {
1876 destroy_rss_raw_qp_tir(dev
, qp
);
1880 base
= qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
?
1881 &qp
->raw_packet_qp
.rq
.base
:
1884 if (qp
->state
!= IB_QPS_RESET
) {
1885 if (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
) {
1886 mlx5_ib_qp_disable_pagefaults(qp
);
1887 err
= mlx5_core_qp_modify(dev
->mdev
,
1888 MLX5_CMD_OP_2RST_QP
, 0,
1891 err
= modify_raw_packet_qp(dev
, qp
,
1892 MLX5_CMD_OP_2RST_QP
);
1895 mlx5_ib_warn(dev
, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1899 get_cqs(qp
->ibqp
.qp_type
, qp
->ibqp
.send_cq
, qp
->ibqp
.recv_cq
,
1900 &send_cq
, &recv_cq
);
1902 spin_lock_irqsave(&dev
->reset_flow_resource_lock
, flags
);
1903 mlx5_ib_lock_cqs(send_cq
, recv_cq
);
1904 /* del from lists under both locks above to protect reset flow paths */
1905 list_del(&qp
->qps_list
);
1907 list_del(&qp
->cq_send_list
);
1910 list_del(&qp
->cq_recv_list
);
1912 if (qp
->create_type
== MLX5_QP_KERNEL
) {
1913 __mlx5_ib_cq_clean(recv_cq
, base
->mqp
.qpn
,
1914 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1915 if (send_cq
!= recv_cq
)
1916 __mlx5_ib_cq_clean(send_cq
, base
->mqp
.qpn
,
1919 mlx5_ib_unlock_cqs(send_cq
, recv_cq
);
1920 spin_unlock_irqrestore(&dev
->reset_flow_resource_lock
, flags
);
1922 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) {
1923 destroy_raw_packet_qp(dev
, qp
);
1925 err
= mlx5_core_destroy_qp(dev
->mdev
, &base
->mqp
);
1927 mlx5_ib_warn(dev
, "failed to destroy QP 0x%x\n",
1931 if (qp
->create_type
== MLX5_QP_KERNEL
)
1932 destroy_qp_kernel(dev
, qp
);
1933 else if (qp
->create_type
== MLX5_QP_USER
)
1934 destroy_qp_user(&get_pd(qp
)->ibpd
, qp
, base
);
1937 static const char *ib_qp_type_str(enum ib_qp_type type
)
1941 return "IB_QPT_SMI";
1943 return "IB_QPT_GSI";
1950 case IB_QPT_RAW_IPV6
:
1951 return "IB_QPT_RAW_IPV6";
1952 case IB_QPT_RAW_ETHERTYPE
:
1953 return "IB_QPT_RAW_ETHERTYPE";
1954 case IB_QPT_XRC_INI
:
1955 return "IB_QPT_XRC_INI";
1956 case IB_QPT_XRC_TGT
:
1957 return "IB_QPT_XRC_TGT";
1958 case IB_QPT_RAW_PACKET
:
1959 return "IB_QPT_RAW_PACKET";
1960 case MLX5_IB_QPT_REG_UMR
:
1961 return "MLX5_IB_QPT_REG_UMR";
1964 return "Invalid QP type";
1968 struct ib_qp
*mlx5_ib_create_qp(struct ib_pd
*pd
,
1969 struct ib_qp_init_attr
*init_attr
,
1970 struct ib_udata
*udata
)
1972 struct mlx5_ib_dev
*dev
;
1973 struct mlx5_ib_qp
*qp
;
1978 dev
= to_mdev(pd
->device
);
1980 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
) {
1982 mlx5_ib_dbg(dev
, "Raw Packet QP is not supported for kernel consumers\n");
1983 return ERR_PTR(-EINVAL
);
1984 } else if (!to_mucontext(pd
->uobject
->context
)->cqe_version
) {
1985 mlx5_ib_dbg(dev
, "Raw Packet QP is only supported for CQE version > 0\n");
1986 return ERR_PTR(-EINVAL
);
1990 /* being cautious here */
1991 if (init_attr
->qp_type
!= IB_QPT_XRC_TGT
&&
1992 init_attr
->qp_type
!= MLX5_IB_QPT_REG_UMR
) {
1993 pr_warn("%s: no PD for transport %s\n", __func__
,
1994 ib_qp_type_str(init_attr
->qp_type
));
1995 return ERR_PTR(-EINVAL
);
1997 dev
= to_mdev(to_mxrcd(init_attr
->xrcd
)->ibxrcd
.device
);
2000 switch (init_attr
->qp_type
) {
2001 case IB_QPT_XRC_TGT
:
2002 case IB_QPT_XRC_INI
:
2003 if (!MLX5_CAP_GEN(dev
->mdev
, xrc
)) {
2004 mlx5_ib_dbg(dev
, "XRC not supported\n");
2005 return ERR_PTR(-ENOSYS
);
2007 init_attr
->recv_cq
= NULL
;
2008 if (init_attr
->qp_type
== IB_QPT_XRC_TGT
) {
2009 xrcdn
= to_mxrcd(init_attr
->xrcd
)->xrcdn
;
2010 init_attr
->send_cq
= NULL
;
2014 case IB_QPT_RAW_PACKET
:
2019 case MLX5_IB_QPT_HW_GSI
:
2020 case MLX5_IB_QPT_REG_UMR
:
2021 qp
= kzalloc(sizeof(*qp
), GFP_KERNEL
);
2023 return ERR_PTR(-ENOMEM
);
2025 err
= create_qp_common(dev
, pd
, init_attr
, udata
, qp
);
2027 mlx5_ib_dbg(dev
, "create_qp_common failed\n");
2029 return ERR_PTR(err
);
2032 if (is_qp0(init_attr
->qp_type
))
2033 qp
->ibqp
.qp_num
= 0;
2034 else if (is_qp1(init_attr
->qp_type
))
2035 qp
->ibqp
.qp_num
= 1;
2037 qp
->ibqp
.qp_num
= qp
->trans_qp
.base
.mqp
.qpn
;
2039 mlx5_ib_dbg(dev
, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2040 qp
->ibqp
.qp_num
, qp
->trans_qp
.base
.mqp
.qpn
,
2041 to_mcq(init_attr
->recv_cq
)->mcq
.cqn
,
2042 to_mcq(init_attr
->send_cq
)->mcq
.cqn
);
2044 qp
->trans_qp
.xrcdn
= xrcdn
;
2049 return mlx5_ib_gsi_create_qp(pd
, init_attr
);
2051 case IB_QPT_RAW_IPV6
:
2052 case IB_QPT_RAW_ETHERTYPE
:
2055 mlx5_ib_dbg(dev
, "unsupported qp type %d\n",
2056 init_attr
->qp_type
);
2057 /* Don't support raw QPs */
2058 return ERR_PTR(-EINVAL
);
2064 int mlx5_ib_destroy_qp(struct ib_qp
*qp
)
2066 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
2067 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
2069 if (unlikely(qp
->qp_type
== IB_QPT_GSI
))
2070 return mlx5_ib_gsi_destroy_qp(qp
);
2072 destroy_qp_common(dev
, mqp
);
2079 static __be32
to_mlx5_access_flags(struct mlx5_ib_qp
*qp
, const struct ib_qp_attr
*attr
,
2082 u32 hw_access_flags
= 0;
2086 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
2087 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
2089 dest_rd_atomic
= qp
->trans_qp
.resp_depth
;
2091 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
2092 access_flags
= attr
->qp_access_flags
;
2094 access_flags
= qp
->trans_qp
.atomic_rd_en
;
2096 if (!dest_rd_atomic
)
2097 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
2099 if (access_flags
& IB_ACCESS_REMOTE_READ
)
2100 hw_access_flags
|= MLX5_QP_BIT_RRE
;
2101 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
2102 hw_access_flags
|= (MLX5_QP_BIT_RAE
| MLX5_ATOMIC_MODE_CX
);
2103 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
2104 hw_access_flags
|= MLX5_QP_BIT_RWE
;
2106 return cpu_to_be32(hw_access_flags
);
2110 MLX5_PATH_FLAG_FL
= 1 << 0,
2111 MLX5_PATH_FLAG_FREE_AR
= 1 << 1,
2112 MLX5_PATH_FLAG_COUNTER
= 1 << 2,
2115 static int ib_rate_to_mlx5(struct mlx5_ib_dev
*dev
, u8 rate
)
2117 if (rate
== IB_RATE_PORT_CURRENT
) {
2119 } else if (rate
< IB_RATE_2_5_GBPS
|| rate
> IB_RATE_300_GBPS
) {
2122 while (rate
!= IB_RATE_2_5_GBPS
&&
2123 !(1 << (rate
+ MLX5_STAT_RATE_OFFSET
) &
2124 MLX5_CAP_GEN(dev
->mdev
, stat_rate_support
)))
2128 return rate
+ MLX5_STAT_RATE_OFFSET
;
2131 static int modify_raw_packet_eth_prio(struct mlx5_core_dev
*dev
,
2132 struct mlx5_ib_sq
*sq
, u8 sl
)
2139 inlen
= MLX5_ST_SZ_BYTES(modify_tis_in
);
2140 in
= mlx5_vzalloc(inlen
);
2144 MLX5_SET(modify_tis_in
, in
, bitmask
.prio
, 1);
2146 tisc
= MLX5_ADDR_OF(modify_tis_in
, in
, ctx
);
2147 MLX5_SET(tisc
, tisc
, prio
, ((sl
& 0x7) << 1));
2149 err
= mlx5_core_modify_tis(dev
, sq
->tisn
, in
, inlen
);
2156 static int mlx5_set_path(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
2157 const struct ib_ah_attr
*ah
,
2158 struct mlx5_qp_path
*path
, u8 port
, int attr_mask
,
2159 u32 path_flags
, const struct ib_qp_attr
*attr
,
2162 enum rdma_link_layer ll
= rdma_port_get_link_layer(&dev
->ib_dev
, port
);
2165 if (attr_mask
& IB_QP_PKEY_INDEX
)
2166 path
->pkey_index
= cpu_to_be16(alt
? attr
->alt_pkey_index
:
2169 if (ah
->ah_flags
& IB_AH_GRH
) {
2170 if (ah
->grh
.sgid_index
>=
2171 dev
->mdev
->port_caps
[port
- 1].gid_table_len
) {
2172 pr_err("sgid_index (%u) too large. max is %d\n",
2174 dev
->mdev
->port_caps
[port
- 1].gid_table_len
);
2179 if (ll
== IB_LINK_LAYER_ETHERNET
) {
2180 if (!(ah
->ah_flags
& IB_AH_GRH
))
2182 memcpy(path
->rmac
, ah
->dmac
, sizeof(ah
->dmac
));
2183 path
->udp_sport
= mlx5_get_roce_udp_sport(dev
, port
,
2184 ah
->grh
.sgid_index
);
2185 path
->dci_cfi_prio_sl
= (ah
->sl
& 0x7) << 4;
2187 path
->fl_free_ar
= (path_flags
& MLX5_PATH_FLAG_FL
) ? 0x80 : 0;
2189 (path_flags
& MLX5_PATH_FLAG_FREE_AR
) ? 0x40 : 0;
2190 path
->rlid
= cpu_to_be16(ah
->dlid
);
2191 path
->grh_mlid
= ah
->src_path_bits
& 0x7f;
2192 if (ah
->ah_flags
& IB_AH_GRH
)
2193 path
->grh_mlid
|= 1 << 7;
2194 path
->dci_cfi_prio_sl
= ah
->sl
& 0xf;
2197 if (ah
->ah_flags
& IB_AH_GRH
) {
2198 path
->mgid_index
= ah
->grh
.sgid_index
;
2199 path
->hop_limit
= ah
->grh
.hop_limit
;
2200 path
->tclass_flowlabel
=
2201 cpu_to_be32((ah
->grh
.traffic_class
<< 20) |
2202 (ah
->grh
.flow_label
));
2203 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
2206 err
= ib_rate_to_mlx5(dev
, ah
->static_rate
);
2209 path
->static_rate
= err
;
2212 if (attr_mask
& IB_QP_TIMEOUT
)
2213 path
->ackto_lt
= (alt
? attr
->alt_timeout
: attr
->timeout
) << 3;
2215 if ((qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) && qp
->sq
.wqe_cnt
)
2216 return modify_raw_packet_eth_prio(dev
->mdev
,
2217 &qp
->raw_packet_qp
.sq
,
2223 static enum mlx5_qp_optpar opt_mask
[MLX5_QP_NUM_STATE
][MLX5_QP_NUM_STATE
][MLX5_QP_ST_MAX
] = {
2224 [MLX5_QP_STATE_INIT
] = {
2225 [MLX5_QP_STATE_INIT
] = {
2226 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RRE
|
2227 MLX5_QP_OPTPAR_RAE
|
2228 MLX5_QP_OPTPAR_RWE
|
2229 MLX5_QP_OPTPAR_PKEY_INDEX
|
2230 MLX5_QP_OPTPAR_PRI_PORT
,
2231 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
|
2232 MLX5_QP_OPTPAR_PKEY_INDEX
|
2233 MLX5_QP_OPTPAR_PRI_PORT
,
2234 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
2235 MLX5_QP_OPTPAR_Q_KEY
|
2236 MLX5_QP_OPTPAR_PRI_PORT
,
2238 [MLX5_QP_STATE_RTR
] = {
2239 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2240 MLX5_QP_OPTPAR_RRE
|
2241 MLX5_QP_OPTPAR_RAE
|
2242 MLX5_QP_OPTPAR_RWE
|
2243 MLX5_QP_OPTPAR_PKEY_INDEX
,
2244 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2245 MLX5_QP_OPTPAR_RWE
|
2246 MLX5_QP_OPTPAR_PKEY_INDEX
,
2247 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
2248 MLX5_QP_OPTPAR_Q_KEY
,
2249 [MLX5_QP_ST_MLX
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
2250 MLX5_QP_OPTPAR_Q_KEY
,
2251 [MLX5_QP_ST_XRC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2252 MLX5_QP_OPTPAR_RRE
|
2253 MLX5_QP_OPTPAR_RAE
|
2254 MLX5_QP_OPTPAR_RWE
|
2255 MLX5_QP_OPTPAR_PKEY_INDEX
,
2258 [MLX5_QP_STATE_RTR
] = {
2259 [MLX5_QP_STATE_RTS
] = {
2260 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2261 MLX5_QP_OPTPAR_RRE
|
2262 MLX5_QP_OPTPAR_RAE
|
2263 MLX5_QP_OPTPAR_RWE
|
2264 MLX5_QP_OPTPAR_PM_STATE
|
2265 MLX5_QP_OPTPAR_RNR_TIMEOUT
,
2266 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2267 MLX5_QP_OPTPAR_RWE
|
2268 MLX5_QP_OPTPAR_PM_STATE
,
2269 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
,
2272 [MLX5_QP_STATE_RTS
] = {
2273 [MLX5_QP_STATE_RTS
] = {
2274 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RRE
|
2275 MLX5_QP_OPTPAR_RAE
|
2276 MLX5_QP_OPTPAR_RWE
|
2277 MLX5_QP_OPTPAR_RNR_TIMEOUT
|
2278 MLX5_QP_OPTPAR_PM_STATE
|
2279 MLX5_QP_OPTPAR_ALT_ADDR_PATH
,
2280 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
|
2281 MLX5_QP_OPTPAR_PM_STATE
|
2282 MLX5_QP_OPTPAR_ALT_ADDR_PATH
,
2283 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
|
2284 MLX5_QP_OPTPAR_SRQN
|
2285 MLX5_QP_OPTPAR_CQN_RCV
,
2288 [MLX5_QP_STATE_SQER
] = {
2289 [MLX5_QP_STATE_RTS
] = {
2290 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
,
2291 [MLX5_QP_ST_MLX
] = MLX5_QP_OPTPAR_Q_KEY
,
2292 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
,
2293 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RNR_TIMEOUT
|
2294 MLX5_QP_OPTPAR_RWE
|
2295 MLX5_QP_OPTPAR_RAE
|
2301 static int ib_nr_to_mlx5_nr(int ib_mask
)
2306 case IB_QP_CUR_STATE
:
2308 case IB_QP_EN_SQD_ASYNC_NOTIFY
:
2310 case IB_QP_ACCESS_FLAGS
:
2311 return MLX5_QP_OPTPAR_RWE
| MLX5_QP_OPTPAR_RRE
|
2313 case IB_QP_PKEY_INDEX
:
2314 return MLX5_QP_OPTPAR_PKEY_INDEX
;
2316 return MLX5_QP_OPTPAR_PRI_PORT
;
2318 return MLX5_QP_OPTPAR_Q_KEY
;
2320 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH
|
2321 MLX5_QP_OPTPAR_PRI_PORT
;
2322 case IB_QP_PATH_MTU
:
2325 return MLX5_QP_OPTPAR_ACK_TIMEOUT
;
2326 case IB_QP_RETRY_CNT
:
2327 return MLX5_QP_OPTPAR_RETRY_COUNT
;
2328 case IB_QP_RNR_RETRY
:
2329 return MLX5_QP_OPTPAR_RNR_RETRY
;
2332 case IB_QP_MAX_QP_RD_ATOMIC
:
2333 return MLX5_QP_OPTPAR_SRA_MAX
;
2334 case IB_QP_ALT_PATH
:
2335 return MLX5_QP_OPTPAR_ALT_ADDR_PATH
;
2336 case IB_QP_MIN_RNR_TIMER
:
2337 return MLX5_QP_OPTPAR_RNR_TIMEOUT
;
2340 case IB_QP_MAX_DEST_RD_ATOMIC
:
2341 return MLX5_QP_OPTPAR_RRA_MAX
| MLX5_QP_OPTPAR_RWE
|
2342 MLX5_QP_OPTPAR_RRE
| MLX5_QP_OPTPAR_RAE
;
2343 case IB_QP_PATH_MIG_STATE
:
2344 return MLX5_QP_OPTPAR_PM_STATE
;
2347 case IB_QP_DEST_QPN
:
2353 static int ib_mask_to_mlx5_opt(int ib_mask
)
2358 for (i
= 0; i
< 8 * sizeof(int); i
++) {
2359 if ((1 << i
) & ib_mask
)
2360 result
|= ib_nr_to_mlx5_nr(1 << i
);
2366 static int modify_raw_packet_qp_rq(struct mlx5_core_dev
*dev
,
2367 struct mlx5_ib_rq
*rq
, int new_state
)
2374 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
2375 in
= mlx5_vzalloc(inlen
);
2379 MLX5_SET(modify_rq_in
, in
, rq_state
, rq
->state
);
2381 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
2382 MLX5_SET(rqc
, rqc
, state
, new_state
);
2384 err
= mlx5_core_modify_rq(dev
, rq
->base
.mqp
.qpn
, in
, inlen
);
2388 rq
->state
= new_state
;
2395 static int modify_raw_packet_qp_sq(struct mlx5_core_dev
*dev
,
2396 struct mlx5_ib_sq
*sq
, int new_state
)
2403 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
2404 in
= mlx5_vzalloc(inlen
);
2408 MLX5_SET(modify_sq_in
, in
, sq_state
, sq
->state
);
2410 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
2411 MLX5_SET(sqc
, sqc
, state
, new_state
);
2413 err
= mlx5_core_modify_sq(dev
, sq
->base
.mqp
.qpn
, in
, inlen
);
2417 sq
->state
= new_state
;
2424 static int modify_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
2427 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
2428 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
2429 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
2434 switch (operation
) {
2435 case MLX5_CMD_OP_RST2INIT_QP
:
2436 rq_state
= MLX5_RQC_STATE_RDY
;
2437 sq_state
= MLX5_SQC_STATE_RDY
;
2439 case MLX5_CMD_OP_2ERR_QP
:
2440 rq_state
= MLX5_RQC_STATE_ERR
;
2441 sq_state
= MLX5_SQC_STATE_ERR
;
2443 case MLX5_CMD_OP_2RST_QP
:
2444 rq_state
= MLX5_RQC_STATE_RST
;
2445 sq_state
= MLX5_SQC_STATE_RST
;
2447 case MLX5_CMD_OP_INIT2INIT_QP
:
2448 case MLX5_CMD_OP_INIT2RTR_QP
:
2449 case MLX5_CMD_OP_RTR2RTS_QP
:
2450 case MLX5_CMD_OP_RTS2RTS_QP
:
2451 /* Nothing to do here... */
2458 if (qp
->rq
.wqe_cnt
) {
2459 err
= modify_raw_packet_qp_rq(dev
->mdev
, rq
, rq_state
);
2465 return modify_raw_packet_qp_sq(dev
->mdev
, sq
, sq_state
);
2470 static int __mlx5_ib_modify_qp(struct ib_qp
*ibqp
,
2471 const struct ib_qp_attr
*attr
, int attr_mask
,
2472 enum ib_qp_state cur_state
, enum ib_qp_state new_state
)
2474 static const u16 optab
[MLX5_QP_NUM_STATE
][MLX5_QP_NUM_STATE
] = {
2475 [MLX5_QP_STATE_RST
] = {
2476 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2477 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2478 [MLX5_QP_STATE_INIT
] = MLX5_CMD_OP_RST2INIT_QP
,
2480 [MLX5_QP_STATE_INIT
] = {
2481 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2482 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2483 [MLX5_QP_STATE_INIT
] = MLX5_CMD_OP_INIT2INIT_QP
,
2484 [MLX5_QP_STATE_RTR
] = MLX5_CMD_OP_INIT2RTR_QP
,
2486 [MLX5_QP_STATE_RTR
] = {
2487 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2488 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2489 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_RTR2RTS_QP
,
2491 [MLX5_QP_STATE_RTS
] = {
2492 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2493 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2494 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_RTS2RTS_QP
,
2496 [MLX5_QP_STATE_SQD
] = {
2497 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2498 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2500 [MLX5_QP_STATE_SQER
] = {
2501 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2502 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2503 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_SQERR2RTS_QP
,
2505 [MLX5_QP_STATE_ERR
] = {
2506 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2507 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2511 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2512 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
2513 struct mlx5_ib_qp_base
*base
= &qp
->trans_qp
.base
;
2514 struct mlx5_ib_cq
*send_cq
, *recv_cq
;
2515 struct mlx5_qp_context
*context
;
2516 struct mlx5_ib_pd
*pd
;
2517 enum mlx5_qp_state mlx5_cur
, mlx5_new
;
2518 enum mlx5_qp_optpar optpar
;
2524 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
2528 err
= to_mlx5_st(ibqp
->qp_type
);
2530 mlx5_ib_dbg(dev
, "unsupported qp type %d\n", ibqp
->qp_type
);
2534 context
->flags
= cpu_to_be32(err
<< 16);
2536 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
)) {
2537 context
->flags
|= cpu_to_be32(MLX5_QP_PM_MIGRATED
<< 11);
2539 switch (attr
->path_mig_state
) {
2540 case IB_MIG_MIGRATED
:
2541 context
->flags
|= cpu_to_be32(MLX5_QP_PM_MIGRATED
<< 11);
2544 context
->flags
|= cpu_to_be32(MLX5_QP_PM_REARM
<< 11);
2547 context
->flags
|= cpu_to_be32(MLX5_QP_PM_ARMED
<< 11);
2552 if (is_sqp(ibqp
->qp_type
)) {
2553 context
->mtu_msgmax
= (IB_MTU_256
<< 5) | 8;
2554 } else if (ibqp
->qp_type
== IB_QPT_UD
||
2555 ibqp
->qp_type
== MLX5_IB_QPT_REG_UMR
) {
2556 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 12;
2557 } else if (attr_mask
& IB_QP_PATH_MTU
) {
2558 if (attr
->path_mtu
< IB_MTU_256
||
2559 attr
->path_mtu
> IB_MTU_4096
) {
2560 mlx5_ib_warn(dev
, "invalid mtu %d\n", attr
->path_mtu
);
2564 context
->mtu_msgmax
= (attr
->path_mtu
<< 5) |
2565 (u8
)MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
2568 if (attr_mask
& IB_QP_DEST_QPN
)
2569 context
->log_pg_sz_remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
2571 if (attr_mask
& IB_QP_PKEY_INDEX
)
2572 context
->pri_path
.pkey_index
= cpu_to_be16(attr
->pkey_index
);
2574 /* todo implement counter_index functionality */
2576 if (is_sqp(ibqp
->qp_type
))
2577 context
->pri_path
.port
= qp
->port
;
2579 if (attr_mask
& IB_QP_PORT
)
2580 context
->pri_path
.port
= attr
->port_num
;
2582 if (attr_mask
& IB_QP_AV
) {
2583 err
= mlx5_set_path(dev
, qp
, &attr
->ah_attr
, &context
->pri_path
,
2584 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
,
2585 attr_mask
, 0, attr
, false);
2590 if (attr_mask
& IB_QP_TIMEOUT
)
2591 context
->pri_path
.ackto_lt
|= attr
->timeout
<< 3;
2593 if (attr_mask
& IB_QP_ALT_PATH
) {
2594 err
= mlx5_set_path(dev
, qp
, &attr
->alt_ah_attr
,
2597 attr_mask
| IB_QP_PKEY_INDEX
| IB_QP_TIMEOUT
,
2604 get_cqs(qp
->ibqp
.qp_type
, qp
->ibqp
.send_cq
, qp
->ibqp
.recv_cq
,
2605 &send_cq
, &recv_cq
);
2607 context
->flags_pd
= cpu_to_be32(pd
? pd
->pdn
: to_mpd(dev
->devr
.p0
)->pdn
);
2608 context
->cqn_send
= send_cq
? cpu_to_be32(send_cq
->mcq
.cqn
) : 0;
2609 context
->cqn_recv
= recv_cq
? cpu_to_be32(recv_cq
->mcq
.cqn
) : 0;
2610 context
->params1
= cpu_to_be32(MLX5_IB_ACK_REQ_FREQ
<< 28);
2612 if (attr_mask
& IB_QP_RNR_RETRY
)
2613 context
->params1
|= cpu_to_be32(attr
->rnr_retry
<< 13);
2615 if (attr_mask
& IB_QP_RETRY_CNT
)
2616 context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
2618 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
2619 if (attr
->max_rd_atomic
)
2621 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
2624 if (attr_mask
& IB_QP_SQ_PSN
)
2625 context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
2627 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
2628 if (attr
->max_dest_rd_atomic
)
2630 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
2633 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
))
2634 context
->params2
|= to_mlx5_access_flags(qp
, attr
, attr_mask
);
2636 if (attr_mask
& IB_QP_MIN_RNR_TIMER
)
2637 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
2639 if (attr_mask
& IB_QP_RQ_PSN
)
2640 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
2642 if (attr_mask
& IB_QP_QKEY
)
2643 context
->qkey
= cpu_to_be32(attr
->qkey
);
2645 if (qp
->rq
.wqe_cnt
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
2646 context
->db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
2648 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
2649 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&& attr
->en_sqd_async_notify
)
2654 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
2655 u8 port_num
= (attr_mask
& IB_QP_PORT
? attr
->port_num
:
2657 struct mlx5_ib_port
*mibport
= &dev
->port
[port_num
];
2659 context
->qp_counter_set_usr_page
|=
2660 cpu_to_be32((u32
)(mibport
->q_cnt_id
) << 24);
2663 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
2664 context
->sq_crq_size
|= cpu_to_be16(1 << 4);
2666 if (qp
->flags
& MLX5_IB_QP_SQPN_QP1
)
2667 context
->deth_sqpn
= cpu_to_be32(1);
2669 mlx5_cur
= to_mlx5_state(cur_state
);
2670 mlx5_new
= to_mlx5_state(new_state
);
2671 mlx5_st
= to_mlx5_st(ibqp
->qp_type
);
2675 /* If moving to a reset or error state, we must disable page faults on
2676 * this QP and flush all current page faults. Otherwise a stale page
2677 * fault may attempt to work on this QP after it is reset and moved
2678 * again to RTS, and may cause the driver and the device to get out of
2680 if (cur_state
!= IB_QPS_RESET
&& cur_state
!= IB_QPS_ERR
&&
2681 (new_state
== IB_QPS_RESET
|| new_state
== IB_QPS_ERR
) &&
2682 (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
))
2683 mlx5_ib_qp_disable_pagefaults(qp
);
2685 if (mlx5_cur
>= MLX5_QP_NUM_STATE
|| mlx5_new
>= MLX5_QP_NUM_STATE
||
2686 !optab
[mlx5_cur
][mlx5_new
])
2689 op
= optab
[mlx5_cur
][mlx5_new
];
2690 optpar
= ib_mask_to_mlx5_opt(attr_mask
);
2691 optpar
&= opt_mask
[mlx5_cur
][mlx5_new
][mlx5_st
];
2693 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
)
2694 err
= modify_raw_packet_qp(dev
, qp
, op
);
2696 err
= mlx5_core_qp_modify(dev
->mdev
, op
, optpar
, context
,
2701 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
&&
2702 (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
))
2703 mlx5_ib_qp_enable_pagefaults(qp
);
2705 qp
->state
= new_state
;
2707 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
2708 qp
->trans_qp
.atomic_rd_en
= attr
->qp_access_flags
;
2709 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
2710 qp
->trans_qp
.resp_depth
= attr
->max_dest_rd_atomic
;
2711 if (attr_mask
& IB_QP_PORT
)
2712 qp
->port
= attr
->port_num
;
2713 if (attr_mask
& IB_QP_ALT_PATH
)
2714 qp
->trans_qp
.alt_port
= attr
->alt_port_num
;
2717 * If we moved a kernel QP to RESET, clean up all old CQ
2718 * entries and reinitialize the QP.
2720 if (new_state
== IB_QPS_RESET
&& !ibqp
->uobject
) {
2721 mlx5_ib_cq_clean(recv_cq
, base
->mqp
.qpn
,
2722 ibqp
->srq
? to_msrq(ibqp
->srq
) : NULL
);
2723 if (send_cq
!= recv_cq
)
2724 mlx5_ib_cq_clean(send_cq
, base
->mqp
.qpn
, NULL
);
2730 qp
->sq
.cur_post
= 0;
2731 qp
->sq
.last_poll
= 0;
2732 qp
->db
.db
[MLX5_RCV_DBR
] = 0;
2733 qp
->db
.db
[MLX5_SND_DBR
] = 0;
2741 int mlx5_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
2742 int attr_mask
, struct ib_udata
*udata
)
2744 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2745 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
2746 enum ib_qp_type qp_type
;
2747 enum ib_qp_state cur_state
, new_state
;
2750 enum rdma_link_layer ll
= IB_LINK_LAYER_UNSPECIFIED
;
2752 if (ibqp
->rwq_ind_tbl
)
2755 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
2756 return mlx5_ib_gsi_modify_qp(ibqp
, attr
, attr_mask
);
2758 qp_type
= (unlikely(ibqp
->qp_type
== MLX5_IB_QPT_HW_GSI
)) ?
2759 IB_QPT_GSI
: ibqp
->qp_type
;
2761 mutex_lock(&qp
->mutex
);
2763 cur_state
= attr_mask
& IB_QP_CUR_STATE
? attr
->cur_qp_state
: qp
->state
;
2764 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
2766 if (!(cur_state
== new_state
&& cur_state
== IB_QPS_RESET
)) {
2767 port
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
2768 ll
= dev
->ib_dev
.get_link_layer(&dev
->ib_dev
, port
);
2771 if (qp_type
!= MLX5_IB_QPT_REG_UMR
&&
2772 !ib_modify_qp_is_ok(cur_state
, new_state
, qp_type
, attr_mask
, ll
)) {
2773 mlx5_ib_dbg(dev
, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2774 cur_state
, new_state
, ibqp
->qp_type
, attr_mask
);
2778 if ((attr_mask
& IB_QP_PORT
) &&
2779 (attr
->port_num
== 0 ||
2780 attr
->port_num
> MLX5_CAP_GEN(dev
->mdev
, num_ports
))) {
2781 mlx5_ib_dbg(dev
, "invalid port number %d. number of ports is %d\n",
2782 attr
->port_num
, dev
->num_ports
);
2786 if (attr_mask
& IB_QP_PKEY_INDEX
) {
2787 port
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
2788 if (attr
->pkey_index
>=
2789 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
) {
2790 mlx5_ib_dbg(dev
, "invalid pkey index %d\n",
2796 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
2797 attr
->max_rd_atomic
>
2798 (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_ra_res_qp
))) {
2799 mlx5_ib_dbg(dev
, "invalid max_rd_atomic value %d\n",
2800 attr
->max_rd_atomic
);
2804 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
2805 attr
->max_dest_rd_atomic
>
2806 (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_ra_req_qp
))) {
2807 mlx5_ib_dbg(dev
, "invalid max_dest_rd_atomic value %d\n",
2808 attr
->max_dest_rd_atomic
);
2812 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
2817 err
= __mlx5_ib_modify_qp(ibqp
, attr
, attr_mask
, cur_state
, new_state
);
2820 mutex_unlock(&qp
->mutex
);
2824 static int mlx5_wq_overflow(struct mlx5_ib_wq
*wq
, int nreq
, struct ib_cq
*ib_cq
)
2826 struct mlx5_ib_cq
*cq
;
2829 cur
= wq
->head
- wq
->tail
;
2830 if (likely(cur
+ nreq
< wq
->max_post
))
2834 spin_lock(&cq
->lock
);
2835 cur
= wq
->head
- wq
->tail
;
2836 spin_unlock(&cq
->lock
);
2838 return cur
+ nreq
>= wq
->max_post
;
2841 static __always_inline
void set_raddr_seg(struct mlx5_wqe_raddr_seg
*rseg
,
2842 u64 remote_addr
, u32 rkey
)
2844 rseg
->raddr
= cpu_to_be64(remote_addr
);
2845 rseg
->rkey
= cpu_to_be32(rkey
);
2849 static void *set_eth_seg(struct mlx5_wqe_eth_seg
*eseg
,
2850 struct ib_send_wr
*wr
, void *qend
,
2851 struct mlx5_ib_qp
*qp
, int *size
)
2855 memset(eseg
, 0, sizeof(struct mlx5_wqe_eth_seg
));
2857 if (wr
->send_flags
& IB_SEND_IP_CSUM
)
2858 eseg
->cs_flags
= MLX5_ETH_WQE_L3_CSUM
|
2859 MLX5_ETH_WQE_L4_CSUM
;
2861 seg
+= sizeof(struct mlx5_wqe_eth_seg
);
2862 *size
+= sizeof(struct mlx5_wqe_eth_seg
) / 16;
2864 if (wr
->opcode
== IB_WR_LSO
) {
2865 struct ib_ud_wr
*ud_wr
= container_of(wr
, struct ib_ud_wr
, wr
);
2866 int size_of_inl_hdr_start
= sizeof(eseg
->inline_hdr_start
);
2867 u64 left
, leftlen
, copysz
;
2868 void *pdata
= ud_wr
->header
;
2871 eseg
->mss
= cpu_to_be16(ud_wr
->mss
);
2872 eseg
->inline_hdr_sz
= cpu_to_be16(left
);
2875 * check if there is space till the end of queue, if yes,
2876 * copy all in one shot, otherwise copy till the end of queue,
2877 * rollback and than the copy the left
2879 leftlen
= qend
- (void *)eseg
->inline_hdr_start
;
2880 copysz
= min_t(u64
, leftlen
, left
);
2882 memcpy(seg
- size_of_inl_hdr_start
, pdata
, copysz
);
2884 if (likely(copysz
> size_of_inl_hdr_start
)) {
2885 seg
+= ALIGN(copysz
- size_of_inl_hdr_start
, 16);
2886 *size
+= ALIGN(copysz
- size_of_inl_hdr_start
, 16) / 16;
2889 if (unlikely(copysz
< left
)) { /* the last wqe in the queue */
2890 seg
= mlx5_get_send_wqe(qp
, 0);
2893 memcpy(seg
, pdata
, left
);
2894 seg
+= ALIGN(left
, 16);
2895 *size
+= ALIGN(left
, 16) / 16;
2902 static void set_datagram_seg(struct mlx5_wqe_datagram_seg
*dseg
,
2903 struct ib_send_wr
*wr
)
2905 memcpy(&dseg
->av
, &to_mah(ud_wr(wr
)->ah
)->av
, sizeof(struct mlx5_av
));
2906 dseg
->av
.dqp_dct
= cpu_to_be32(ud_wr(wr
)->remote_qpn
| MLX5_EXTENDED_UD_AV
);
2907 dseg
->av
.key
.qkey
.qkey
= cpu_to_be32(ud_wr(wr
)->remote_qkey
);
2910 static void set_data_ptr_seg(struct mlx5_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
2912 dseg
->byte_count
= cpu_to_be32(sg
->length
);
2913 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
2914 dseg
->addr
= cpu_to_be64(sg
->addr
);
2917 static __be16
get_klm_octo(int npages
)
2919 return cpu_to_be16(ALIGN(npages
, 8) / 2);
2922 static __be64
frwr_mkey_mask(void)
2926 result
= MLX5_MKEY_MASK_LEN
|
2927 MLX5_MKEY_MASK_PAGE_SIZE
|
2928 MLX5_MKEY_MASK_START_ADDR
|
2929 MLX5_MKEY_MASK_EN_RINVAL
|
2930 MLX5_MKEY_MASK_KEY
|
2936 MLX5_MKEY_MASK_SMALL_FENCE
|
2937 MLX5_MKEY_MASK_FREE
;
2939 return cpu_to_be64(result
);
2942 static __be64
sig_mkey_mask(void)
2946 result
= MLX5_MKEY_MASK_LEN
|
2947 MLX5_MKEY_MASK_PAGE_SIZE
|
2948 MLX5_MKEY_MASK_START_ADDR
|
2949 MLX5_MKEY_MASK_EN_SIGERR
|
2950 MLX5_MKEY_MASK_EN_RINVAL
|
2951 MLX5_MKEY_MASK_KEY
|
2956 MLX5_MKEY_MASK_SMALL_FENCE
|
2957 MLX5_MKEY_MASK_FREE
|
2958 MLX5_MKEY_MASK_BSF_EN
;
2960 return cpu_to_be64(result
);
2963 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg
*umr
,
2964 struct mlx5_ib_mr
*mr
)
2966 int ndescs
= mr
->ndescs
;
2968 memset(umr
, 0, sizeof(*umr
));
2970 if (mr
->access_mode
== MLX5_MKC_ACCESS_MODE_KLMS
)
2971 /* KLMs take twice the size of MTTs */
2974 umr
->flags
= MLX5_UMR_CHECK_NOT_FREE
;
2975 umr
->klm_octowords
= get_klm_octo(ndescs
);
2976 umr
->mkey_mask
= frwr_mkey_mask();
2979 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg
*umr
)
2981 memset(umr
, 0, sizeof(*umr
));
2982 umr
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
2983 umr
->flags
= 1 << 7;
2986 static __be64
get_umr_reg_mr_mask(void)
2990 result
= MLX5_MKEY_MASK_LEN
|
2991 MLX5_MKEY_MASK_PAGE_SIZE
|
2992 MLX5_MKEY_MASK_START_ADDR
|
2996 MLX5_MKEY_MASK_KEY
|
3000 MLX5_MKEY_MASK_FREE
;
3002 return cpu_to_be64(result
);
3005 static __be64
get_umr_unreg_mr_mask(void)
3009 result
= MLX5_MKEY_MASK_FREE
;
3011 return cpu_to_be64(result
);
3014 static __be64
get_umr_update_mtt_mask(void)
3018 result
= MLX5_MKEY_MASK_FREE
;
3020 return cpu_to_be64(result
);
3023 static __be64
get_umr_update_translation_mask(void)
3027 result
= MLX5_MKEY_MASK_LEN
|
3028 MLX5_MKEY_MASK_PAGE_SIZE
|
3029 MLX5_MKEY_MASK_START_ADDR
|
3030 MLX5_MKEY_MASK_KEY
|
3031 MLX5_MKEY_MASK_FREE
;
3033 return cpu_to_be64(result
);
3036 static __be64
get_umr_update_access_mask(void)
3040 result
= MLX5_MKEY_MASK_LW
|
3044 MLX5_MKEY_MASK_KEY
|
3045 MLX5_MKEY_MASK_FREE
;
3047 return cpu_to_be64(result
);
3050 static __be64
get_umr_update_pd_mask(void)
3054 result
= MLX5_MKEY_MASK_PD
|
3055 MLX5_MKEY_MASK_KEY
|
3056 MLX5_MKEY_MASK_FREE
;
3058 return cpu_to_be64(result
);
3061 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg
*umr
,
3062 struct ib_send_wr
*wr
)
3064 struct mlx5_umr_wr
*umrwr
= umr_wr(wr
);
3066 memset(umr
, 0, sizeof(*umr
));
3068 if (wr
->send_flags
& MLX5_IB_SEND_UMR_FAIL_IF_FREE
)
3069 umr
->flags
= MLX5_UMR_CHECK_FREE
; /* fail if free */
3071 umr
->flags
= MLX5_UMR_CHECK_NOT_FREE
; /* fail if not free */
3073 if (!(wr
->send_flags
& MLX5_IB_SEND_UMR_UNREG
)) {
3074 umr
->klm_octowords
= get_klm_octo(umrwr
->npages
);
3075 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_MTT
) {
3076 umr
->mkey_mask
= get_umr_update_mtt_mask();
3077 umr
->bsf_octowords
= get_klm_octo(umrwr
->target
.offset
);
3078 umr
->flags
|= MLX5_UMR_TRANSLATION_OFFSET_EN
;
3080 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
)
3081 umr
->mkey_mask
|= get_umr_update_translation_mask();
3082 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_ACCESS
)
3083 umr
->mkey_mask
|= get_umr_update_access_mask();
3084 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_PD
)
3085 umr
->mkey_mask
|= get_umr_update_pd_mask();
3086 if (!umr
->mkey_mask
)
3087 umr
->mkey_mask
= get_umr_reg_mr_mask();
3089 umr
->mkey_mask
= get_umr_unreg_mr_mask();
3093 umr
->flags
|= MLX5_UMR_INLINE
;
3096 static u8
get_umr_flags(int acc
)
3098 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? MLX5_PERM_ATOMIC
: 0) |
3099 (acc
& IB_ACCESS_REMOTE_WRITE
? MLX5_PERM_REMOTE_WRITE
: 0) |
3100 (acc
& IB_ACCESS_REMOTE_READ
? MLX5_PERM_REMOTE_READ
: 0) |
3101 (acc
& IB_ACCESS_LOCAL_WRITE
? MLX5_PERM_LOCAL_WRITE
: 0) |
3102 MLX5_PERM_LOCAL_READ
| MLX5_PERM_UMR_EN
;
3105 static void set_reg_mkey_seg(struct mlx5_mkey_seg
*seg
,
3106 struct mlx5_ib_mr
*mr
,
3107 u32 key
, int access
)
3109 int ndescs
= ALIGN(mr
->ndescs
, 8) >> 1;
3111 memset(seg
, 0, sizeof(*seg
));
3113 if (mr
->access_mode
== MLX5_MKC_ACCESS_MODE_MTT
)
3114 seg
->log2_page_size
= ilog2(mr
->ibmr
.page_size
);
3115 else if (mr
->access_mode
== MLX5_MKC_ACCESS_MODE_KLMS
)
3116 /* KLMs take twice the size of MTTs */
3119 seg
->flags
= get_umr_flags(access
) | mr
->access_mode
;
3120 seg
->qpn_mkey7_0
= cpu_to_be32((key
& 0xff) | 0xffffff00);
3121 seg
->flags_pd
= cpu_to_be32(MLX5_MKEY_REMOTE_INVAL
);
3122 seg
->start_addr
= cpu_to_be64(mr
->ibmr
.iova
);
3123 seg
->len
= cpu_to_be64(mr
->ibmr
.length
);
3124 seg
->xlt_oct_size
= cpu_to_be32(ndescs
);
3127 static void set_linv_mkey_seg(struct mlx5_mkey_seg
*seg
)
3129 memset(seg
, 0, sizeof(*seg
));
3130 seg
->status
= MLX5_MKEY_STATUS_FREE
;
3133 static void set_reg_mkey_segment(struct mlx5_mkey_seg
*seg
, struct ib_send_wr
*wr
)
3135 struct mlx5_umr_wr
*umrwr
= umr_wr(wr
);
3137 memset(seg
, 0, sizeof(*seg
));
3138 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UNREG
) {
3139 seg
->status
= MLX5_MKEY_STATUS_FREE
;
3143 seg
->flags
= convert_access(umrwr
->access_flags
);
3144 if (!(wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_MTT
)) {
3146 seg
->flags_pd
= cpu_to_be32(to_mpd(umrwr
->pd
)->pdn
);
3147 seg
->start_addr
= cpu_to_be64(umrwr
->target
.virt_addr
);
3149 seg
->len
= cpu_to_be64(umrwr
->length
);
3150 seg
->log2_page_size
= umrwr
->page_shift
;
3151 seg
->qpn_mkey7_0
= cpu_to_be32(0xffffff00 |
3152 mlx5_mkey_variant(umrwr
->mkey
));
3155 static void set_reg_data_seg(struct mlx5_wqe_data_seg
*dseg
,
3156 struct mlx5_ib_mr
*mr
,
3157 struct mlx5_ib_pd
*pd
)
3159 int bcount
= mr
->desc_size
* mr
->ndescs
;
3161 dseg
->addr
= cpu_to_be64(mr
->desc_map
);
3162 dseg
->byte_count
= cpu_to_be32(ALIGN(bcount
, 64));
3163 dseg
->lkey
= cpu_to_be32(pd
->ibpd
.local_dma_lkey
);
3166 static __be32
send_ieth(struct ib_send_wr
*wr
)
3168 switch (wr
->opcode
) {
3169 case IB_WR_SEND_WITH_IMM
:
3170 case IB_WR_RDMA_WRITE_WITH_IMM
:
3171 return wr
->ex
.imm_data
;
3173 case IB_WR_SEND_WITH_INV
:
3174 return cpu_to_be32(wr
->ex
.invalidate_rkey
);
3181 static u8
calc_sig(void *wqe
, int size
)
3187 for (i
= 0; i
< size
; i
++)
3193 static u8
wq_sig(void *wqe
)
3195 return calc_sig(wqe
, (*((u8
*)wqe
+ 8) & 0x3f) << 4);
3198 static int set_data_inl_seg(struct mlx5_ib_qp
*qp
, struct ib_send_wr
*wr
,
3201 struct mlx5_wqe_inline_seg
*seg
;
3202 void *qend
= qp
->sq
.qend
;
3210 wqe
+= sizeof(*seg
);
3211 for (i
= 0; i
< wr
->num_sge
; i
++) {
3212 addr
= (void *)(unsigned long)(wr
->sg_list
[i
].addr
);
3213 len
= wr
->sg_list
[i
].length
;
3216 if (unlikely(inl
> qp
->max_inline_data
))
3219 if (unlikely(wqe
+ len
> qend
)) {
3221 memcpy(wqe
, addr
, copy
);
3224 wqe
= mlx5_get_send_wqe(qp
, 0);
3226 memcpy(wqe
, addr
, len
);
3230 seg
->byte_count
= cpu_to_be32(inl
| MLX5_INLINE_SEG
);
3232 *sz
= ALIGN(inl
+ sizeof(seg
->byte_count
), 16) / 16;
3237 static u16
prot_field_size(enum ib_signature_type type
)
3240 case IB_SIG_TYPE_T10_DIF
:
3241 return MLX5_DIF_SIZE
;
3247 static u8
bs_selector(int block_size
)
3249 switch (block_size
) {
3250 case 512: return 0x1;
3251 case 520: return 0x2;
3252 case 4096: return 0x3;
3253 case 4160: return 0x4;
3254 case 1073741824: return 0x5;
3259 static void mlx5_fill_inl_bsf(struct ib_sig_domain
*domain
,
3260 struct mlx5_bsf_inl
*inl
)
3262 /* Valid inline section and allow BSF refresh */
3263 inl
->vld_refresh
= cpu_to_be16(MLX5_BSF_INL_VALID
|
3264 MLX5_BSF_REFRESH_DIF
);
3265 inl
->dif_apptag
= cpu_to_be16(domain
->sig
.dif
.app_tag
);
3266 inl
->dif_reftag
= cpu_to_be32(domain
->sig
.dif
.ref_tag
);
3267 /* repeating block */
3268 inl
->rp_inv_seed
= MLX5_BSF_REPEAT_BLOCK
;
3269 inl
->sig_type
= domain
->sig
.dif
.bg_type
== IB_T10DIF_CRC
?
3270 MLX5_DIF_CRC
: MLX5_DIF_IPCS
;
3272 if (domain
->sig
.dif
.ref_remap
)
3273 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_INC_REFTAG
;
3275 if (domain
->sig
.dif
.app_escape
) {
3276 if (domain
->sig
.dif
.ref_escape
)
3277 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_APPREF_ESCAPE
;
3279 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_APPTAG_ESCAPE
;
3282 inl
->dif_app_bitmask_check
=
3283 cpu_to_be16(domain
->sig
.dif
.apptag_check_mask
);
3286 static int mlx5_set_bsf(struct ib_mr
*sig_mr
,
3287 struct ib_sig_attrs
*sig_attrs
,
3288 struct mlx5_bsf
*bsf
, u32 data_size
)
3290 struct mlx5_core_sig_ctx
*msig
= to_mmr(sig_mr
)->sig
;
3291 struct mlx5_bsf_basic
*basic
= &bsf
->basic
;
3292 struct ib_sig_domain
*mem
= &sig_attrs
->mem
;
3293 struct ib_sig_domain
*wire
= &sig_attrs
->wire
;
3295 memset(bsf
, 0, sizeof(*bsf
));
3297 /* Basic + Extended + Inline */
3298 basic
->bsf_size_sbs
= 1 << 7;
3299 /* Input domain check byte mask */
3300 basic
->check_byte_mask
= sig_attrs
->check_mask
;
3301 basic
->raw_data_size
= cpu_to_be32(data_size
);
3304 switch (sig_attrs
->mem
.sig_type
) {
3305 case IB_SIG_TYPE_NONE
:
3307 case IB_SIG_TYPE_T10_DIF
:
3308 basic
->mem
.bs_selector
= bs_selector(mem
->sig
.dif
.pi_interval
);
3309 basic
->m_bfs_psv
= cpu_to_be32(msig
->psv_memory
.psv_idx
);
3310 mlx5_fill_inl_bsf(mem
, &bsf
->m_inl
);
3317 switch (sig_attrs
->wire
.sig_type
) {
3318 case IB_SIG_TYPE_NONE
:
3320 case IB_SIG_TYPE_T10_DIF
:
3321 if (mem
->sig
.dif
.pi_interval
== wire
->sig
.dif
.pi_interval
&&
3322 mem
->sig_type
== wire
->sig_type
) {
3323 /* Same block structure */
3324 basic
->bsf_size_sbs
|= 1 << 4;
3325 if (mem
->sig
.dif
.bg_type
== wire
->sig
.dif
.bg_type
)
3326 basic
->wire
.copy_byte_mask
|= MLX5_CPY_GRD_MASK
;
3327 if (mem
->sig
.dif
.app_tag
== wire
->sig
.dif
.app_tag
)
3328 basic
->wire
.copy_byte_mask
|= MLX5_CPY_APP_MASK
;
3329 if (mem
->sig
.dif
.ref_tag
== wire
->sig
.dif
.ref_tag
)
3330 basic
->wire
.copy_byte_mask
|= MLX5_CPY_REF_MASK
;
3332 basic
->wire
.bs_selector
= bs_selector(wire
->sig
.dif
.pi_interval
);
3334 basic
->w_bfs_psv
= cpu_to_be32(msig
->psv_wire
.psv_idx
);
3335 mlx5_fill_inl_bsf(wire
, &bsf
->w_inl
);
3344 static int set_sig_data_segment(struct ib_sig_handover_wr
*wr
,
3345 struct mlx5_ib_qp
*qp
, void **seg
, int *size
)
3347 struct ib_sig_attrs
*sig_attrs
= wr
->sig_attrs
;
3348 struct ib_mr
*sig_mr
= wr
->sig_mr
;
3349 struct mlx5_bsf
*bsf
;
3350 u32 data_len
= wr
->wr
.sg_list
->length
;
3351 u32 data_key
= wr
->wr
.sg_list
->lkey
;
3352 u64 data_va
= wr
->wr
.sg_list
->addr
;
3357 (data_key
== wr
->prot
->lkey
&&
3358 data_va
== wr
->prot
->addr
&&
3359 data_len
== wr
->prot
->length
)) {
3361 * Source domain doesn't contain signature information
3362 * or data and protection are interleaved in memory.
3363 * So need construct:
3364 * ------------------
3366 * ------------------
3368 * ------------------
3370 struct mlx5_klm
*data_klm
= *seg
;
3372 data_klm
->bcount
= cpu_to_be32(data_len
);
3373 data_klm
->key
= cpu_to_be32(data_key
);
3374 data_klm
->va
= cpu_to_be64(data_va
);
3375 wqe_size
= ALIGN(sizeof(*data_klm
), 64);
3378 * Source domain contains signature information
3379 * So need construct a strided block format:
3380 * ---------------------------
3381 * | stride_block_ctrl |
3382 * ---------------------------
3384 * ---------------------------
3386 * ---------------------------
3388 * ---------------------------
3390 struct mlx5_stride_block_ctrl_seg
*sblock_ctrl
;
3391 struct mlx5_stride_block_entry
*data_sentry
;
3392 struct mlx5_stride_block_entry
*prot_sentry
;
3393 u32 prot_key
= wr
->prot
->lkey
;
3394 u64 prot_va
= wr
->prot
->addr
;
3395 u16 block_size
= sig_attrs
->mem
.sig
.dif
.pi_interval
;
3399 data_sentry
= (void *)sblock_ctrl
+ sizeof(*sblock_ctrl
);
3400 prot_sentry
= (void *)data_sentry
+ sizeof(*data_sentry
);
3402 prot_size
= prot_field_size(sig_attrs
->mem
.sig_type
);
3404 pr_err("Bad block size given: %u\n", block_size
);
3407 sblock_ctrl
->bcount_per_cycle
= cpu_to_be32(block_size
+
3409 sblock_ctrl
->op
= cpu_to_be32(MLX5_STRIDE_BLOCK_OP
);
3410 sblock_ctrl
->repeat_count
= cpu_to_be32(data_len
/ block_size
);
3411 sblock_ctrl
->num_entries
= cpu_to_be16(2);
3413 data_sentry
->bcount
= cpu_to_be16(block_size
);
3414 data_sentry
->key
= cpu_to_be32(data_key
);
3415 data_sentry
->va
= cpu_to_be64(data_va
);
3416 data_sentry
->stride
= cpu_to_be16(block_size
);
3418 prot_sentry
->bcount
= cpu_to_be16(prot_size
);
3419 prot_sentry
->key
= cpu_to_be32(prot_key
);
3420 prot_sentry
->va
= cpu_to_be64(prot_va
);
3421 prot_sentry
->stride
= cpu_to_be16(prot_size
);
3423 wqe_size
= ALIGN(sizeof(*sblock_ctrl
) + sizeof(*data_sentry
) +
3424 sizeof(*prot_sentry
), 64);
3428 *size
+= wqe_size
/ 16;
3429 if (unlikely((*seg
== qp
->sq
.qend
)))
3430 *seg
= mlx5_get_send_wqe(qp
, 0);
3433 ret
= mlx5_set_bsf(sig_mr
, sig_attrs
, bsf
, data_len
);
3437 *seg
+= sizeof(*bsf
);
3438 *size
+= sizeof(*bsf
) / 16;
3439 if (unlikely((*seg
== qp
->sq
.qend
)))
3440 *seg
= mlx5_get_send_wqe(qp
, 0);
3445 static void set_sig_mkey_segment(struct mlx5_mkey_seg
*seg
,
3446 struct ib_sig_handover_wr
*wr
, u32 nelements
,
3447 u32 length
, u32 pdn
)
3449 struct ib_mr
*sig_mr
= wr
->sig_mr
;
3450 u32 sig_key
= sig_mr
->rkey
;
3451 u8 sigerr
= to_mmr(sig_mr
)->sig
->sigerr_count
& 1;
3453 memset(seg
, 0, sizeof(*seg
));
3455 seg
->flags
= get_umr_flags(wr
->access_flags
) |
3456 MLX5_MKC_ACCESS_MODE_KLMS
;
3457 seg
->qpn_mkey7_0
= cpu_to_be32((sig_key
& 0xff) | 0xffffff00);
3458 seg
->flags_pd
= cpu_to_be32(MLX5_MKEY_REMOTE_INVAL
| sigerr
<< 26 |
3459 MLX5_MKEY_BSF_EN
| pdn
);
3460 seg
->len
= cpu_to_be64(length
);
3461 seg
->xlt_oct_size
= cpu_to_be32(be16_to_cpu(get_klm_octo(nelements
)));
3462 seg
->bsfs_octo_size
= cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE
);
3465 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg
*umr
,
3468 memset(umr
, 0, sizeof(*umr
));
3470 umr
->flags
= MLX5_FLAGS_INLINE
| MLX5_FLAGS_CHECK_FREE
;
3471 umr
->klm_octowords
= get_klm_octo(nelements
);
3472 umr
->bsf_octowords
= cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE
);
3473 umr
->mkey_mask
= sig_mkey_mask();
3477 static int set_sig_umr_wr(struct ib_send_wr
*send_wr
, struct mlx5_ib_qp
*qp
,
3478 void **seg
, int *size
)
3480 struct ib_sig_handover_wr
*wr
= sig_handover_wr(send_wr
);
3481 struct mlx5_ib_mr
*sig_mr
= to_mmr(wr
->sig_mr
);
3482 u32 pdn
= get_pd(qp
)->pdn
;
3484 int region_len
, ret
;
3486 if (unlikely(wr
->wr
.num_sge
!= 1) ||
3487 unlikely(wr
->access_flags
& IB_ACCESS_REMOTE_ATOMIC
) ||
3488 unlikely(!sig_mr
->sig
) || unlikely(!qp
->signature_en
) ||
3489 unlikely(!sig_mr
->sig
->sig_status_checked
))
3492 /* length of the protected region, data + protection */
3493 region_len
= wr
->wr
.sg_list
->length
;
3495 (wr
->prot
->lkey
!= wr
->wr
.sg_list
->lkey
||
3496 wr
->prot
->addr
!= wr
->wr
.sg_list
->addr
||
3497 wr
->prot
->length
!= wr
->wr
.sg_list
->length
))
3498 region_len
+= wr
->prot
->length
;
3501 * KLM octoword size - if protection was provided
3502 * then we use strided block format (3 octowords),
3503 * else we use single KLM (1 octoword)
3505 klm_oct_size
= wr
->prot
? 3 : 1;
3507 set_sig_umr_segment(*seg
, klm_oct_size
);
3508 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3509 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3510 if (unlikely((*seg
== qp
->sq
.qend
)))
3511 *seg
= mlx5_get_send_wqe(qp
, 0);
3513 set_sig_mkey_segment(*seg
, wr
, klm_oct_size
, region_len
, pdn
);
3514 *seg
+= sizeof(struct mlx5_mkey_seg
);
3515 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3516 if (unlikely((*seg
== qp
->sq
.qend
)))
3517 *seg
= mlx5_get_send_wqe(qp
, 0);
3519 ret
= set_sig_data_segment(wr
, qp
, seg
, size
);
3523 sig_mr
->sig
->sig_status_checked
= false;
3527 static int set_psv_wr(struct ib_sig_domain
*domain
,
3528 u32 psv_idx
, void **seg
, int *size
)
3530 struct mlx5_seg_set_psv
*psv_seg
= *seg
;
3532 memset(psv_seg
, 0, sizeof(*psv_seg
));
3533 psv_seg
->psv_num
= cpu_to_be32(psv_idx
);
3534 switch (domain
->sig_type
) {
3535 case IB_SIG_TYPE_NONE
:
3537 case IB_SIG_TYPE_T10_DIF
:
3538 psv_seg
->transient_sig
= cpu_to_be32(domain
->sig
.dif
.bg
<< 16 |
3539 domain
->sig
.dif
.app_tag
);
3540 psv_seg
->ref_tag
= cpu_to_be32(domain
->sig
.dif
.ref_tag
);
3543 pr_err("Bad signature type given.\n");
3547 *seg
+= sizeof(*psv_seg
);
3548 *size
+= sizeof(*psv_seg
) / 16;
3553 static int set_reg_wr(struct mlx5_ib_qp
*qp
,
3554 struct ib_reg_wr
*wr
,
3555 void **seg
, int *size
)
3557 struct mlx5_ib_mr
*mr
= to_mmr(wr
->mr
);
3558 struct mlx5_ib_pd
*pd
= to_mpd(qp
->ibqp
.pd
);
3560 if (unlikely(wr
->wr
.send_flags
& IB_SEND_INLINE
)) {
3561 mlx5_ib_warn(to_mdev(qp
->ibqp
.device
),
3562 "Invalid IB_SEND_INLINE send flag\n");
3566 set_reg_umr_seg(*seg
, mr
);
3567 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3568 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3569 if (unlikely((*seg
== qp
->sq
.qend
)))
3570 *seg
= mlx5_get_send_wqe(qp
, 0);
3572 set_reg_mkey_seg(*seg
, mr
, wr
->key
, wr
->access
);
3573 *seg
+= sizeof(struct mlx5_mkey_seg
);
3574 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3575 if (unlikely((*seg
== qp
->sq
.qend
)))
3576 *seg
= mlx5_get_send_wqe(qp
, 0);
3578 set_reg_data_seg(*seg
, mr
, pd
);
3579 *seg
+= sizeof(struct mlx5_wqe_data_seg
);
3580 *size
+= (sizeof(struct mlx5_wqe_data_seg
) / 16);
3585 static void set_linv_wr(struct mlx5_ib_qp
*qp
, void **seg
, int *size
)
3587 set_linv_umr_seg(*seg
);
3588 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3589 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3590 if (unlikely((*seg
== qp
->sq
.qend
)))
3591 *seg
= mlx5_get_send_wqe(qp
, 0);
3592 set_linv_mkey_seg(*seg
);
3593 *seg
+= sizeof(struct mlx5_mkey_seg
);
3594 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3595 if (unlikely((*seg
== qp
->sq
.qend
)))
3596 *seg
= mlx5_get_send_wqe(qp
, 0);
3599 static void dump_wqe(struct mlx5_ib_qp
*qp
, int idx
, int size_16
)
3605 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp
, tidx
));
3606 for (i
= 0, j
= 0; i
< size_16
* 4; i
+= 4, j
+= 4) {
3607 if ((i
& 0xf) == 0) {
3608 void *buf
= mlx5_get_send_wqe(qp
, tidx
);
3609 tidx
= (tidx
+ 1) & (qp
->sq
.wqe_cnt
- 1);
3613 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p
[j
]),
3614 be32_to_cpu(p
[j
+ 1]), be32_to_cpu(p
[j
+ 2]),
3615 be32_to_cpu(p
[j
+ 3]));
3619 static void mlx5_bf_copy(u64 __iomem
*dst
, u64
*src
,
3620 unsigned bytecnt
, struct mlx5_ib_qp
*qp
)
3622 while (bytecnt
> 0) {
3623 __iowrite64_copy(dst
++, src
++, 8);
3624 __iowrite64_copy(dst
++, src
++, 8);
3625 __iowrite64_copy(dst
++, src
++, 8);
3626 __iowrite64_copy(dst
++, src
++, 8);
3627 __iowrite64_copy(dst
++, src
++, 8);
3628 __iowrite64_copy(dst
++, src
++, 8);
3629 __iowrite64_copy(dst
++, src
++, 8);
3630 __iowrite64_copy(dst
++, src
++, 8);
3632 if (unlikely(src
== qp
->sq
.qend
))
3633 src
= mlx5_get_send_wqe(qp
, 0);
3637 static u8
get_fence(u8 fence
, struct ib_send_wr
*wr
)
3639 if (unlikely(wr
->opcode
== IB_WR_LOCAL_INV
&&
3640 wr
->send_flags
& IB_SEND_FENCE
))
3641 return MLX5_FENCE_MODE_STRONG_ORDERING
;
3643 if (unlikely(fence
)) {
3644 if (wr
->send_flags
& IB_SEND_FENCE
)
3645 return MLX5_FENCE_MODE_SMALL_AND_FENCE
;
3648 } else if (unlikely(wr
->send_flags
& IB_SEND_FENCE
)) {
3649 return MLX5_FENCE_MODE_FENCE
;
3655 static int begin_wqe(struct mlx5_ib_qp
*qp
, void **seg
,
3656 struct mlx5_wqe_ctrl_seg
**ctrl
,
3657 struct ib_send_wr
*wr
, unsigned *idx
,
3658 int *size
, int nreq
)
3660 if (unlikely(mlx5_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)))
3663 *idx
= qp
->sq
.cur_post
& (qp
->sq
.wqe_cnt
- 1);
3664 *seg
= mlx5_get_send_wqe(qp
, *idx
);
3666 *(uint32_t *)(*seg
+ 8) = 0;
3667 (*ctrl
)->imm
= send_ieth(wr
);
3668 (*ctrl
)->fm_ce_se
= qp
->sq_signal_bits
|
3669 (wr
->send_flags
& IB_SEND_SIGNALED
?
3670 MLX5_WQE_CTRL_CQ_UPDATE
: 0) |
3671 (wr
->send_flags
& IB_SEND_SOLICITED
?
3672 MLX5_WQE_CTRL_SOLICITED
: 0);
3674 *seg
+= sizeof(**ctrl
);
3675 *size
= sizeof(**ctrl
) / 16;
3680 static void finish_wqe(struct mlx5_ib_qp
*qp
,
3681 struct mlx5_wqe_ctrl_seg
*ctrl
,
3682 u8 size
, unsigned idx
, u64 wr_id
,
3683 int nreq
, u8 fence
, u8 next_fence
,
3688 ctrl
->opmod_idx_opcode
= cpu_to_be32(((u32
)(qp
->sq
.cur_post
) << 8) |
3689 mlx5_opcode
| ((u32
)opmod
<< 24));
3690 ctrl
->qpn_ds
= cpu_to_be32(size
| (qp
->trans_qp
.base
.mqp
.qpn
<< 8));
3691 ctrl
->fm_ce_se
|= fence
;
3692 qp
->fm_cache
= next_fence
;
3693 if (unlikely(qp
->wq_sig
))
3694 ctrl
->signature
= wq_sig(ctrl
);
3696 qp
->sq
.wrid
[idx
] = wr_id
;
3697 qp
->sq
.w_list
[idx
].opcode
= mlx5_opcode
;
3698 qp
->sq
.wqe_head
[idx
] = qp
->sq
.head
+ nreq
;
3699 qp
->sq
.cur_post
+= DIV_ROUND_UP(size
* 16, MLX5_SEND_WQE_BB
);
3700 qp
->sq
.w_list
[idx
].next
= qp
->sq
.cur_post
;
3704 int mlx5_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
3705 struct ib_send_wr
**bad_wr
)
3707 struct mlx5_wqe_ctrl_seg
*ctrl
= NULL
; /* compiler warning */
3708 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3709 struct mlx5_core_dev
*mdev
= dev
->mdev
;
3710 struct mlx5_ib_qp
*qp
;
3711 struct mlx5_ib_mr
*mr
;
3712 struct mlx5_wqe_data_seg
*dpseg
;
3713 struct mlx5_wqe_xrc_seg
*xrc
;
3715 int uninitialized_var(size
);
3717 unsigned long flags
;
3728 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
3729 return mlx5_ib_gsi_post_send(ibqp
, wr
, bad_wr
);
3735 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
3737 if (mdev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
3744 for (nreq
= 0; wr
; nreq
++, wr
= wr
->next
) {
3745 if (unlikely(wr
->opcode
>= ARRAY_SIZE(mlx5_ib_opcode
))) {
3746 mlx5_ib_warn(dev
, "\n");
3752 fence
= qp
->fm_cache
;
3753 num_sge
= wr
->num_sge
;
3754 if (unlikely(num_sge
> qp
->sq
.max_gs
)) {
3755 mlx5_ib_warn(dev
, "\n");
3761 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
, &idx
, &size
, nreq
);
3763 mlx5_ib_warn(dev
, "\n");
3769 switch (ibqp
->qp_type
) {
3770 case IB_QPT_XRC_INI
:
3772 seg
+= sizeof(*xrc
);
3773 size
+= sizeof(*xrc
) / 16;
3776 switch (wr
->opcode
) {
3777 case IB_WR_RDMA_READ
:
3778 case IB_WR_RDMA_WRITE
:
3779 case IB_WR_RDMA_WRITE_WITH_IMM
:
3780 set_raddr_seg(seg
, rdma_wr(wr
)->remote_addr
,
3782 seg
+= sizeof(struct mlx5_wqe_raddr_seg
);
3783 size
+= sizeof(struct mlx5_wqe_raddr_seg
) / 16;
3786 case IB_WR_ATOMIC_CMP_AND_SWP
:
3787 case IB_WR_ATOMIC_FETCH_AND_ADD
:
3788 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP
:
3789 mlx5_ib_warn(dev
, "Atomic operations are not supported yet\n");
3794 case IB_WR_LOCAL_INV
:
3795 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
3796 qp
->sq
.wr_data
[idx
] = IB_WR_LOCAL_INV
;
3797 ctrl
->imm
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
3798 set_linv_wr(qp
, &seg
, &size
);
3803 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
3804 qp
->sq
.wr_data
[idx
] = IB_WR_REG_MR
;
3805 ctrl
->imm
= cpu_to_be32(reg_wr(wr
)->key
);
3806 err
= set_reg_wr(qp
, reg_wr(wr
), &seg
, &size
);
3814 case IB_WR_REG_SIG_MR
:
3815 qp
->sq
.wr_data
[idx
] = IB_WR_REG_SIG_MR
;
3816 mr
= to_mmr(sig_handover_wr(wr
)->sig_mr
);
3818 ctrl
->imm
= cpu_to_be32(mr
->ibmr
.rkey
);
3819 err
= set_sig_umr_wr(wr
, qp
, &seg
, &size
);
3821 mlx5_ib_warn(dev
, "\n");
3826 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
,
3827 nreq
, get_fence(fence
, wr
),
3828 next_fence
, MLX5_OPCODE_UMR
);
3830 * SET_PSV WQEs are not signaled and solicited
3833 wr
->send_flags
&= ~IB_SEND_SIGNALED
;
3834 wr
->send_flags
|= IB_SEND_SOLICITED
;
3835 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
,
3838 mlx5_ib_warn(dev
, "\n");
3844 err
= set_psv_wr(&sig_handover_wr(wr
)->sig_attrs
->mem
,
3845 mr
->sig
->psv_memory
.psv_idx
, &seg
,
3848 mlx5_ib_warn(dev
, "\n");
3853 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
,
3854 nreq
, get_fence(fence
, wr
),
3855 next_fence
, MLX5_OPCODE_SET_PSV
);
3856 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
,
3859 mlx5_ib_warn(dev
, "\n");
3865 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
3866 err
= set_psv_wr(&sig_handover_wr(wr
)->sig_attrs
->wire
,
3867 mr
->sig
->psv_wire
.psv_idx
, &seg
,
3870 mlx5_ib_warn(dev
, "\n");
3875 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
,
3876 nreq
, get_fence(fence
, wr
),
3877 next_fence
, MLX5_OPCODE_SET_PSV
);
3887 switch (wr
->opcode
) {
3888 case IB_WR_RDMA_WRITE
:
3889 case IB_WR_RDMA_WRITE_WITH_IMM
:
3890 set_raddr_seg(seg
, rdma_wr(wr
)->remote_addr
,
3892 seg
+= sizeof(struct mlx5_wqe_raddr_seg
);
3893 size
+= sizeof(struct mlx5_wqe_raddr_seg
) / 16;
3902 case MLX5_IB_QPT_HW_GSI
:
3903 set_datagram_seg(seg
, wr
);
3904 seg
+= sizeof(struct mlx5_wqe_datagram_seg
);
3905 size
+= sizeof(struct mlx5_wqe_datagram_seg
) / 16;
3906 if (unlikely((seg
== qend
)))
3907 seg
= mlx5_get_send_wqe(qp
, 0);
3910 set_datagram_seg(seg
, wr
);
3911 seg
+= sizeof(struct mlx5_wqe_datagram_seg
);
3912 size
+= sizeof(struct mlx5_wqe_datagram_seg
) / 16;
3914 if (unlikely((seg
== qend
)))
3915 seg
= mlx5_get_send_wqe(qp
, 0);
3917 /* handle qp that supports ud offload */
3918 if (qp
->flags
& IB_QP_CREATE_IPOIB_UD_LSO
) {
3919 struct mlx5_wqe_eth_pad
*pad
;
3922 memset(pad
, 0, sizeof(struct mlx5_wqe_eth_pad
));
3923 seg
+= sizeof(struct mlx5_wqe_eth_pad
);
3924 size
+= sizeof(struct mlx5_wqe_eth_pad
) / 16;
3926 seg
= set_eth_seg(seg
, wr
, qend
, qp
, &size
);
3928 if (unlikely((seg
== qend
)))
3929 seg
= mlx5_get_send_wqe(qp
, 0);
3932 case MLX5_IB_QPT_REG_UMR
:
3933 if (wr
->opcode
!= MLX5_IB_WR_UMR
) {
3935 mlx5_ib_warn(dev
, "bad opcode\n");
3938 qp
->sq
.wr_data
[idx
] = MLX5_IB_WR_UMR
;
3939 ctrl
->imm
= cpu_to_be32(umr_wr(wr
)->mkey
);
3940 set_reg_umr_segment(seg
, wr
);
3941 seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3942 size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3943 if (unlikely((seg
== qend
)))
3944 seg
= mlx5_get_send_wqe(qp
, 0);
3945 set_reg_mkey_segment(seg
, wr
);
3946 seg
+= sizeof(struct mlx5_mkey_seg
);
3947 size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3948 if (unlikely((seg
== qend
)))
3949 seg
= mlx5_get_send_wqe(qp
, 0);
3956 if (wr
->send_flags
& IB_SEND_INLINE
&& num_sge
) {
3957 int uninitialized_var(sz
);
3959 err
= set_data_inl_seg(qp
, wr
, seg
, &sz
);
3960 if (unlikely(err
)) {
3961 mlx5_ib_warn(dev
, "\n");
3969 for (i
= 0; i
< num_sge
; i
++) {
3970 if (unlikely(dpseg
== qend
)) {
3971 seg
= mlx5_get_send_wqe(qp
, 0);
3974 if (likely(wr
->sg_list
[i
].length
)) {
3975 set_data_ptr_seg(dpseg
, wr
->sg_list
+ i
);
3976 size
+= sizeof(struct mlx5_wqe_data_seg
) / 16;
3982 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
, nreq
,
3983 get_fence(fence
, wr
), next_fence
,
3984 mlx5_ib_opcode
[wr
->opcode
]);
3987 dump_wqe(qp
, idx
, size
);
3992 qp
->sq
.head
+= nreq
;
3994 /* Make sure that descriptors are written before
3995 * updating doorbell record and ringing the doorbell
3999 qp
->db
.db
[MLX5_SND_DBR
] = cpu_to_be32(qp
->sq
.cur_post
);
4001 /* Make sure doorbell record is visible to the HCA before
4002 * we hit doorbell */
4006 spin_lock(&bf
->lock
);
4008 __acquire(&bf
->lock
);
4011 if (0 && nreq
== 1 && bf
->uuarn
&& inl
&& size
> 1 && size
<= bf
->buf_size
/ 16) {
4012 mlx5_bf_copy(bf
->reg
+ bf
->offset
, (u64
*)ctrl
, ALIGN(size
* 16, 64), qp
);
4015 mlx5_write64((__be32
*)ctrl
, bf
->regreg
+ bf
->offset
,
4016 MLX5_GET_DOORBELL_LOCK(&bf
->lock32
));
4017 /* Make sure doorbells don't leak out of SQ spinlock
4018 * and reach the HCA out of order.
4022 bf
->offset
^= bf
->buf_size
;
4024 spin_unlock(&bf
->lock
);
4026 __release(&bf
->lock
);
4029 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
4034 static void set_sig_seg(struct mlx5_rwqe_sig
*sig
, int size
)
4036 sig
->signature
= calc_sig(sig
, size
);
4039 int mlx5_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
4040 struct ib_recv_wr
**bad_wr
)
4042 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
4043 struct mlx5_wqe_data_seg
*scat
;
4044 struct mlx5_rwqe_sig
*sig
;
4045 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
4046 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4047 unsigned long flags
;
4053 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
4054 return mlx5_ib_gsi_post_recv(ibqp
, wr
, bad_wr
);
4056 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
4058 if (mdev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
4065 ind
= qp
->rq
.head
& (qp
->rq
.wqe_cnt
- 1);
4067 for (nreq
= 0; wr
; nreq
++, wr
= wr
->next
) {
4068 if (mlx5_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
4074 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
4080 scat
= get_recv_wqe(qp
, ind
);
4084 for (i
= 0; i
< wr
->num_sge
; i
++)
4085 set_data_ptr_seg(scat
+ i
, wr
->sg_list
+ i
);
4087 if (i
< qp
->rq
.max_gs
) {
4088 scat
[i
].byte_count
= 0;
4089 scat
[i
].lkey
= cpu_to_be32(MLX5_INVALID_LKEY
);
4094 sig
= (struct mlx5_rwqe_sig
*)scat
;
4095 set_sig_seg(sig
, (qp
->rq
.max_gs
+ 1) << 2);
4098 qp
->rq
.wrid
[ind
] = wr
->wr_id
;
4100 ind
= (ind
+ 1) & (qp
->rq
.wqe_cnt
- 1);
4105 qp
->rq
.head
+= nreq
;
4107 /* Make sure that descriptors are written before
4112 *qp
->db
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
4115 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
4120 static inline enum ib_qp_state
to_ib_qp_state(enum mlx5_qp_state mlx5_state
)
4122 switch (mlx5_state
) {
4123 case MLX5_QP_STATE_RST
: return IB_QPS_RESET
;
4124 case MLX5_QP_STATE_INIT
: return IB_QPS_INIT
;
4125 case MLX5_QP_STATE_RTR
: return IB_QPS_RTR
;
4126 case MLX5_QP_STATE_RTS
: return IB_QPS_RTS
;
4127 case MLX5_QP_STATE_SQ_DRAINING
:
4128 case MLX5_QP_STATE_SQD
: return IB_QPS_SQD
;
4129 case MLX5_QP_STATE_SQER
: return IB_QPS_SQE
;
4130 case MLX5_QP_STATE_ERR
: return IB_QPS_ERR
;
4135 static inline enum ib_mig_state
to_ib_mig_state(int mlx5_mig_state
)
4137 switch (mlx5_mig_state
) {
4138 case MLX5_QP_PM_ARMED
: return IB_MIG_ARMED
;
4139 case MLX5_QP_PM_REARM
: return IB_MIG_REARM
;
4140 case MLX5_QP_PM_MIGRATED
: return IB_MIG_MIGRATED
;
4145 static int to_ib_qp_access_flags(int mlx5_flags
)
4149 if (mlx5_flags
& MLX5_QP_BIT_RRE
)
4150 ib_flags
|= IB_ACCESS_REMOTE_READ
;
4151 if (mlx5_flags
& MLX5_QP_BIT_RWE
)
4152 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
4153 if (mlx5_flags
& MLX5_QP_BIT_RAE
)
4154 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
4159 static void to_ib_ah_attr(struct mlx5_ib_dev
*ibdev
, struct ib_ah_attr
*ib_ah_attr
,
4160 struct mlx5_qp_path
*path
)
4162 struct mlx5_core_dev
*dev
= ibdev
->mdev
;
4164 memset(ib_ah_attr
, 0, sizeof(*ib_ah_attr
));
4165 ib_ah_attr
->port_num
= path
->port
;
4167 if (ib_ah_attr
->port_num
== 0 ||
4168 ib_ah_attr
->port_num
> MLX5_CAP_GEN(dev
, num_ports
))
4171 ib_ah_attr
->sl
= path
->dci_cfi_prio_sl
& 0xf;
4173 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
4174 ib_ah_attr
->src_path_bits
= path
->grh_mlid
& 0x7f;
4175 ib_ah_attr
->static_rate
= path
->static_rate
? path
->static_rate
- 5 : 0;
4176 ib_ah_attr
->ah_flags
= (path
->grh_mlid
& (1 << 7)) ? IB_AH_GRH
: 0;
4177 if (ib_ah_attr
->ah_flags
) {
4178 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
;
4179 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
4180 ib_ah_attr
->grh
.traffic_class
=
4181 (be32_to_cpu(path
->tclass_flowlabel
) >> 20) & 0xff;
4182 ib_ah_attr
->grh
.flow_label
=
4183 be32_to_cpu(path
->tclass_flowlabel
) & 0xfffff;
4184 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
4185 path
->rgid
, sizeof(ib_ah_attr
->grh
.dgid
.raw
));
4189 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev
*dev
,
4190 struct mlx5_ib_sq
*sq
,
4198 inlen
= MLX5_ST_SZ_BYTES(query_sq_out
);
4199 out
= mlx5_vzalloc(inlen
);
4203 err
= mlx5_core_query_sq(dev
->mdev
, sq
->base
.mqp
.qpn
, out
);
4207 sqc
= MLX5_ADDR_OF(query_sq_out
, out
, sq_context
);
4208 *sq_state
= MLX5_GET(sqc
, sqc
, state
);
4209 sq
->state
= *sq_state
;
4216 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev
*dev
,
4217 struct mlx5_ib_rq
*rq
,
4225 inlen
= MLX5_ST_SZ_BYTES(query_rq_out
);
4226 out
= mlx5_vzalloc(inlen
);
4230 err
= mlx5_core_query_rq(dev
->mdev
, rq
->base
.mqp
.qpn
, out
);
4234 rqc
= MLX5_ADDR_OF(query_rq_out
, out
, rq_context
);
4235 *rq_state
= MLX5_GET(rqc
, rqc
, state
);
4236 rq
->state
= *rq_state
;
4243 static int sqrq_state_to_qp_state(u8 sq_state
, u8 rq_state
,
4244 struct mlx5_ib_qp
*qp
, u8
*qp_state
)
4246 static const u8 sqrq_trans
[MLX5_RQ_NUM_STATE
][MLX5_SQ_NUM_STATE
] = {
4247 [MLX5_RQC_STATE_RST
] = {
4248 [MLX5_SQC_STATE_RST
] = IB_QPS_RESET
,
4249 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE_BAD
,
4250 [MLX5_SQC_STATE_ERR
] = MLX5_QP_STATE_BAD
,
4251 [MLX5_SQ_STATE_NA
] = IB_QPS_RESET
,
4253 [MLX5_RQC_STATE_RDY
] = {
4254 [MLX5_SQC_STATE_RST
] = MLX5_QP_STATE_BAD
,
4255 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE
,
4256 [MLX5_SQC_STATE_ERR
] = IB_QPS_SQE
,
4257 [MLX5_SQ_STATE_NA
] = MLX5_QP_STATE
,
4259 [MLX5_RQC_STATE_ERR
] = {
4260 [MLX5_SQC_STATE_RST
] = MLX5_QP_STATE_BAD
,
4261 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE_BAD
,
4262 [MLX5_SQC_STATE_ERR
] = IB_QPS_ERR
,
4263 [MLX5_SQ_STATE_NA
] = IB_QPS_ERR
,
4265 [MLX5_RQ_STATE_NA
] = {
4266 [MLX5_SQC_STATE_RST
] = IB_QPS_RESET
,
4267 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE
,
4268 [MLX5_SQC_STATE_ERR
] = MLX5_QP_STATE
,
4269 [MLX5_SQ_STATE_NA
] = MLX5_QP_STATE_BAD
,
4273 *qp_state
= sqrq_trans
[rq_state
][sq_state
];
4275 if (*qp_state
== MLX5_QP_STATE_BAD
) {
4276 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4277 qp
->raw_packet_qp
.sq
.base
.mqp
.qpn
, sq_state
,
4278 qp
->raw_packet_qp
.rq
.base
.mqp
.qpn
, rq_state
);
4282 if (*qp_state
== MLX5_QP_STATE
)
4283 *qp_state
= qp
->state
;
4288 static int query_raw_packet_qp_state(struct mlx5_ib_dev
*dev
,
4289 struct mlx5_ib_qp
*qp
,
4290 u8
*raw_packet_qp_state
)
4292 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
4293 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
4294 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
4296 u8 sq_state
= MLX5_SQ_STATE_NA
;
4297 u8 rq_state
= MLX5_RQ_STATE_NA
;
4299 if (qp
->sq
.wqe_cnt
) {
4300 err
= query_raw_packet_qp_sq_state(dev
, sq
, &sq_state
);
4305 if (qp
->rq
.wqe_cnt
) {
4306 err
= query_raw_packet_qp_rq_state(dev
, rq
, &rq_state
);
4311 return sqrq_state_to_qp_state(sq_state
, rq_state
, qp
,
4312 raw_packet_qp_state
);
4315 static int query_qp_attr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
4316 struct ib_qp_attr
*qp_attr
)
4318 int outlen
= MLX5_ST_SZ_BYTES(query_qp_out
);
4319 struct mlx5_qp_context
*context
;
4324 outb
= kzalloc(outlen
, GFP_KERNEL
);
4328 err
= mlx5_core_qp_query(dev
->mdev
, &qp
->trans_qp
.base
.mqp
, outb
,
4333 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4334 context
= (struct mlx5_qp_context
*)MLX5_ADDR_OF(query_qp_out
, outb
, qpc
);
4336 mlx5_state
= be32_to_cpu(context
->flags
) >> 28;
4338 qp
->state
= to_ib_qp_state(mlx5_state
);
4339 qp_attr
->path_mtu
= context
->mtu_msgmax
>> 5;
4340 qp_attr
->path_mig_state
=
4341 to_ib_mig_state((be32_to_cpu(context
->flags
) >> 11) & 0x3);
4342 qp_attr
->qkey
= be32_to_cpu(context
->qkey
);
4343 qp_attr
->rq_psn
= be32_to_cpu(context
->rnr_nextrecvpsn
) & 0xffffff;
4344 qp_attr
->sq_psn
= be32_to_cpu(context
->next_send_psn
) & 0xffffff;
4345 qp_attr
->dest_qp_num
= be32_to_cpu(context
->log_pg_sz_remote_qpn
) & 0xffffff;
4346 qp_attr
->qp_access_flags
=
4347 to_ib_qp_access_flags(be32_to_cpu(context
->params2
));
4349 if (qp
->ibqp
.qp_type
== IB_QPT_RC
|| qp
->ibqp
.qp_type
== IB_QPT_UC
) {
4350 to_ib_ah_attr(dev
, &qp_attr
->ah_attr
, &context
->pri_path
);
4351 to_ib_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
->alt_path
);
4352 qp_attr
->alt_pkey_index
=
4353 be16_to_cpu(context
->alt_path
.pkey_index
);
4354 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
4357 qp_attr
->pkey_index
= be16_to_cpu(context
->pri_path
.pkey_index
);
4358 qp_attr
->port_num
= context
->pri_path
.port
;
4360 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4361 qp_attr
->sq_draining
= mlx5_state
== MLX5_QP_STATE_SQ_DRAINING
;
4363 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
->params1
) >> 21) & 0x7);
4365 qp_attr
->max_dest_rd_atomic
=
4366 1 << ((be32_to_cpu(context
->params2
) >> 21) & 0x7);
4367 qp_attr
->min_rnr_timer
=
4368 (be32_to_cpu(context
->rnr_nextrecvpsn
) >> 24) & 0x1f;
4369 qp_attr
->timeout
= context
->pri_path
.ackto_lt
>> 3;
4370 qp_attr
->retry_cnt
= (be32_to_cpu(context
->params1
) >> 16) & 0x7;
4371 qp_attr
->rnr_retry
= (be32_to_cpu(context
->params1
) >> 13) & 0x7;
4372 qp_attr
->alt_timeout
= context
->alt_path
.ackto_lt
>> 3;
4379 int mlx5_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
,
4380 int qp_attr_mask
, struct ib_qp_init_attr
*qp_init_attr
)
4382 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
4383 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
4385 u8 raw_packet_qp_state
;
4387 if (ibqp
->rwq_ind_tbl
)
4390 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
4391 return mlx5_ib_gsi_query_qp(ibqp
, qp_attr
, qp_attr_mask
,
4394 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4396 * Wait for any outstanding page faults, in case the user frees memory
4397 * based upon this query's result.
4399 flush_workqueue(mlx5_ib_page_fault_wq
);
4402 mutex_lock(&qp
->mutex
);
4404 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) {
4405 err
= query_raw_packet_qp_state(dev
, qp
, &raw_packet_qp_state
);
4408 qp
->state
= raw_packet_qp_state
;
4409 qp_attr
->port_num
= 1;
4411 err
= query_qp_attr(dev
, qp
, qp_attr
);
4416 qp_attr
->qp_state
= qp
->state
;
4417 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
4418 qp_attr
->cap
.max_recv_wr
= qp
->rq
.wqe_cnt
;
4419 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
4421 if (!ibqp
->uobject
) {
4422 qp_attr
->cap
.max_send_wr
= qp
->sq
.max_post
;
4423 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
4424 qp_init_attr
->qp_context
= ibqp
->qp_context
;
4426 qp_attr
->cap
.max_send_wr
= 0;
4427 qp_attr
->cap
.max_send_sge
= 0;
4430 qp_init_attr
->qp_type
= ibqp
->qp_type
;
4431 qp_init_attr
->recv_cq
= ibqp
->recv_cq
;
4432 qp_init_attr
->send_cq
= ibqp
->send_cq
;
4433 qp_init_attr
->srq
= ibqp
->srq
;
4434 qp_attr
->cap
.max_inline_data
= qp
->max_inline_data
;
4436 qp_init_attr
->cap
= qp_attr
->cap
;
4438 qp_init_attr
->create_flags
= 0;
4439 if (qp
->flags
& MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
4440 qp_init_attr
->create_flags
|= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
;
4442 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
4443 qp_init_attr
->create_flags
|= IB_QP_CREATE_CROSS_CHANNEL
;
4444 if (qp
->flags
& MLX5_IB_QP_MANAGED_SEND
)
4445 qp_init_attr
->create_flags
|= IB_QP_CREATE_MANAGED_SEND
;
4446 if (qp
->flags
& MLX5_IB_QP_MANAGED_RECV
)
4447 qp_init_attr
->create_flags
|= IB_QP_CREATE_MANAGED_RECV
;
4448 if (qp
->flags
& MLX5_IB_QP_SQPN_QP1
)
4449 qp_init_attr
->create_flags
|= mlx5_ib_create_qp_sqpn_qp1();
4451 qp_init_attr
->sq_sig_type
= qp
->sq_signal_bits
& MLX5_WQE_CTRL_CQ_UPDATE
?
4452 IB_SIGNAL_ALL_WR
: IB_SIGNAL_REQ_WR
;
4455 mutex_unlock(&qp
->mutex
);
4459 struct ib_xrcd
*mlx5_ib_alloc_xrcd(struct ib_device
*ibdev
,
4460 struct ib_ucontext
*context
,
4461 struct ib_udata
*udata
)
4463 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
4464 struct mlx5_ib_xrcd
*xrcd
;
4467 if (!MLX5_CAP_GEN(dev
->mdev
, xrc
))
4468 return ERR_PTR(-ENOSYS
);
4470 xrcd
= kmalloc(sizeof(*xrcd
), GFP_KERNEL
);
4472 return ERR_PTR(-ENOMEM
);
4474 err
= mlx5_core_xrcd_alloc(dev
->mdev
, &xrcd
->xrcdn
);
4477 return ERR_PTR(-ENOMEM
);
4480 return &xrcd
->ibxrcd
;
4483 int mlx5_ib_dealloc_xrcd(struct ib_xrcd
*xrcd
)
4485 struct mlx5_ib_dev
*dev
= to_mdev(xrcd
->device
);
4486 u32 xrcdn
= to_mxrcd(xrcd
)->xrcdn
;
4489 err
= mlx5_core_xrcd_dealloc(dev
->mdev
, xrcdn
);
4491 mlx5_ib_warn(dev
, "failed to dealloc xrcdn 0x%x\n", xrcdn
);
4500 static int create_rq(struct mlx5_ib_rwq
*rwq
, struct ib_pd
*pd
,
4501 struct ib_wq_init_attr
*init_attr
)
4503 struct mlx5_ib_dev
*dev
;
4511 dev
= to_mdev(pd
->device
);
4513 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) + sizeof(u64
) * rwq
->rq_num_pas
;
4514 in
= mlx5_vzalloc(inlen
);
4518 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
4519 MLX5_SET(rqc
, rqc
, mem_rq_type
,
4520 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
);
4521 MLX5_SET(rqc
, rqc
, user_index
, rwq
->user_index
);
4522 MLX5_SET(rqc
, rqc
, cqn
, to_mcq(init_attr
->cq
)->mcq
.cqn
);
4523 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
4524 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
4525 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
4526 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
4527 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
4528 MLX5_SET(wq
, wq
, log_wq_stride
, rwq
->log_rq_stride
);
4529 MLX5_SET(wq
, wq
, log_wq_sz
, rwq
->log_rq_size
);
4530 MLX5_SET(wq
, wq
, pd
, to_mpd(pd
)->pdn
);
4531 MLX5_SET(wq
, wq
, page_offset
, rwq
->rq_page_offset
);
4532 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rwq
->log_page_size
);
4533 MLX5_SET(wq
, wq
, wq_signature
, rwq
->wq_sig
);
4534 MLX5_SET64(wq
, wq
, dbr_addr
, rwq
->db
.dma
);
4535 rq_pas0
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
4536 mlx5_ib_populate_pas(dev
, rwq
->umem
, rwq
->page_shift
, rq_pas0
, 0);
4537 err
= mlx5_core_create_rq(dev
->mdev
, in
, inlen
, &rwq
->rqn
);
4542 static int set_user_rq_size(struct mlx5_ib_dev
*dev
,
4543 struct ib_wq_init_attr
*wq_init_attr
,
4544 struct mlx5_ib_create_wq
*ucmd
,
4545 struct mlx5_ib_rwq
*rwq
)
4547 /* Sanity check RQ size before proceeding */
4548 if (wq_init_attr
->max_wr
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_wq_sz
)))
4551 if (!ucmd
->rq_wqe_count
)
4554 rwq
->wqe_count
= ucmd
->rq_wqe_count
;
4555 rwq
->wqe_shift
= ucmd
->rq_wqe_shift
;
4556 rwq
->buf_size
= (rwq
->wqe_count
<< rwq
->wqe_shift
);
4557 rwq
->log_rq_stride
= rwq
->wqe_shift
;
4558 rwq
->log_rq_size
= ilog2(rwq
->wqe_count
);
4562 static int prepare_user_rq(struct ib_pd
*pd
,
4563 struct ib_wq_init_attr
*init_attr
,
4564 struct ib_udata
*udata
,
4565 struct mlx5_ib_rwq
*rwq
)
4567 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
4568 struct mlx5_ib_create_wq ucmd
= {};
4570 size_t required_cmd_sz
;
4572 required_cmd_sz
= offsetof(typeof(ucmd
), reserved
) + sizeof(ucmd
.reserved
);
4573 if (udata
->inlen
< required_cmd_sz
) {
4574 mlx5_ib_dbg(dev
, "invalid inlen\n");
4578 if (udata
->inlen
> sizeof(ucmd
) &&
4579 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
4580 udata
->inlen
- sizeof(ucmd
))) {
4581 mlx5_ib_dbg(dev
, "inlen is not supported\n");
4585 if (ib_copy_from_udata(&ucmd
, udata
, min(sizeof(ucmd
), udata
->inlen
))) {
4586 mlx5_ib_dbg(dev
, "copy failed\n");
4590 if (ucmd
.comp_mask
) {
4591 mlx5_ib_dbg(dev
, "invalid comp mask\n");
4595 if (ucmd
.reserved
) {
4596 mlx5_ib_dbg(dev
, "invalid reserved\n");
4600 err
= set_user_rq_size(dev
, init_attr
, &ucmd
, rwq
);
4602 mlx5_ib_dbg(dev
, "err %d\n", err
);
4606 err
= create_user_rq(dev
, pd
, rwq
, &ucmd
);
4608 mlx5_ib_dbg(dev
, "err %d\n", err
);
4613 rwq
->user_index
= ucmd
.user_index
;
4617 struct ib_wq
*mlx5_ib_create_wq(struct ib_pd
*pd
,
4618 struct ib_wq_init_attr
*init_attr
,
4619 struct ib_udata
*udata
)
4621 struct mlx5_ib_dev
*dev
;
4622 struct mlx5_ib_rwq
*rwq
;
4623 struct mlx5_ib_create_wq_resp resp
= {};
4624 size_t min_resp_len
;
4628 return ERR_PTR(-ENOSYS
);
4630 min_resp_len
= offsetof(typeof(resp
), reserved
) + sizeof(resp
.reserved
);
4631 if (udata
->outlen
&& udata
->outlen
< min_resp_len
)
4632 return ERR_PTR(-EINVAL
);
4634 dev
= to_mdev(pd
->device
);
4635 switch (init_attr
->wq_type
) {
4637 rwq
= kzalloc(sizeof(*rwq
), GFP_KERNEL
);
4639 return ERR_PTR(-ENOMEM
);
4640 err
= prepare_user_rq(pd
, init_attr
, udata
, rwq
);
4643 err
= create_rq(rwq
, pd
, init_attr
);
4648 mlx5_ib_dbg(dev
, "unsupported wq type %d\n",
4649 init_attr
->wq_type
);
4650 return ERR_PTR(-EINVAL
);
4653 rwq
->ibwq
.wq_num
= rwq
->rqn
;
4654 rwq
->ibwq
.state
= IB_WQS_RESET
;
4655 if (udata
->outlen
) {
4656 resp
.response_length
= offsetof(typeof(resp
), response_length
) +
4657 sizeof(resp
.response_length
);
4658 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
4666 mlx5_core_destroy_rq(dev
->mdev
, rwq
->rqn
);
4668 destroy_user_rq(pd
, rwq
);
4671 return ERR_PTR(err
);
4674 int mlx5_ib_destroy_wq(struct ib_wq
*wq
)
4676 struct mlx5_ib_dev
*dev
= to_mdev(wq
->device
);
4677 struct mlx5_ib_rwq
*rwq
= to_mrwq(wq
);
4679 mlx5_core_destroy_rq(dev
->mdev
, rwq
->rqn
);
4680 destroy_user_rq(wq
->pd
, rwq
);
4686 struct ib_rwq_ind_table
*mlx5_ib_create_rwq_ind_table(struct ib_device
*device
,
4687 struct ib_rwq_ind_table_init_attr
*init_attr
,
4688 struct ib_udata
*udata
)
4690 struct mlx5_ib_dev
*dev
= to_mdev(device
);
4691 struct mlx5_ib_rwq_ind_table
*rwq_ind_tbl
;
4692 int sz
= 1 << init_attr
->log_ind_tbl_size
;
4693 struct mlx5_ib_create_rwq_ind_tbl_resp resp
= {};
4694 size_t min_resp_len
;
4701 if (udata
->inlen
> 0 &&
4702 !ib_is_udata_cleared(udata
, 0,
4704 return ERR_PTR(-EOPNOTSUPP
);
4706 min_resp_len
= offsetof(typeof(resp
), reserved
) + sizeof(resp
.reserved
);
4707 if (udata
->outlen
&& udata
->outlen
< min_resp_len
)
4708 return ERR_PTR(-EINVAL
);
4710 rwq_ind_tbl
= kzalloc(sizeof(*rwq_ind_tbl
), GFP_KERNEL
);
4712 return ERR_PTR(-ENOMEM
);
4714 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
4715 in
= mlx5_vzalloc(inlen
);
4721 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
4723 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
4724 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
4726 for (i
= 0; i
< sz
; i
++)
4727 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], init_attr
->ind_tbl
[i
]->wq_num
);
4729 err
= mlx5_core_create_rqt(dev
->mdev
, in
, inlen
, &rwq_ind_tbl
->rqtn
);
4735 rwq_ind_tbl
->ib_rwq_ind_tbl
.ind_tbl_num
= rwq_ind_tbl
->rqtn
;
4736 if (udata
->outlen
) {
4737 resp
.response_length
= offsetof(typeof(resp
), response_length
) +
4738 sizeof(resp
.response_length
);
4739 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
4744 return &rwq_ind_tbl
->ib_rwq_ind_tbl
;
4747 mlx5_core_destroy_rqt(dev
->mdev
, rwq_ind_tbl
->rqtn
);
4750 return ERR_PTR(err
);
4753 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table
*ib_rwq_ind_tbl
)
4755 struct mlx5_ib_rwq_ind_table
*rwq_ind_tbl
= to_mrwq_ind_table(ib_rwq_ind_tbl
);
4756 struct mlx5_ib_dev
*dev
= to_mdev(ib_rwq_ind_tbl
->device
);
4758 mlx5_core_destroy_rqt(dev
->mdev
, rwq_ind_tbl
->rqtn
);
4764 int mlx5_ib_modify_wq(struct ib_wq
*wq
, struct ib_wq_attr
*wq_attr
,
4765 u32 wq_attr_mask
, struct ib_udata
*udata
)
4767 struct mlx5_ib_dev
*dev
= to_mdev(wq
->device
);
4768 struct mlx5_ib_rwq
*rwq
= to_mrwq(wq
);
4769 struct mlx5_ib_modify_wq ucmd
= {};
4770 size_t required_cmd_sz
;
4778 required_cmd_sz
= offsetof(typeof(ucmd
), reserved
) + sizeof(ucmd
.reserved
);
4779 if (udata
->inlen
< required_cmd_sz
)
4782 if (udata
->inlen
> sizeof(ucmd
) &&
4783 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
4784 udata
->inlen
- sizeof(ucmd
)))
4787 if (ib_copy_from_udata(&ucmd
, udata
, min(sizeof(ucmd
), udata
->inlen
)))
4790 if (ucmd
.comp_mask
|| ucmd
.reserved
)
4793 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
4794 in
= mlx5_vzalloc(inlen
);
4798 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
4800 curr_wq_state
= (wq_attr_mask
& IB_WQ_CUR_STATE
) ?
4801 wq_attr
->curr_wq_state
: wq
->state
;
4802 wq_state
= (wq_attr_mask
& IB_WQ_STATE
) ?
4803 wq_attr
->wq_state
: curr_wq_state
;
4804 if (curr_wq_state
== IB_WQS_ERR
)
4805 curr_wq_state
= MLX5_RQC_STATE_ERR
;
4806 if (wq_state
== IB_WQS_ERR
)
4807 wq_state
= MLX5_RQC_STATE_ERR
;
4808 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_wq_state
);
4809 MLX5_SET(rqc
, rqc
, state
, wq_state
);
4811 err
= mlx5_core_modify_rq(dev
->mdev
, rwq
->rqn
, in
, inlen
);
4814 rwq
->ibwq
.state
= (wq_state
== MLX5_RQC_STATE_ERR
) ? IB_WQS_ERR
: wq_state
;