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Merge remote-tracking branch 'vfio/next'
[deliverable/linux.git] / drivers / iommu / amd_iommu_init.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/iommu.h>
30 #include <asm/pci-direct.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 #include <asm/io_apic.h>
36 #include <asm/irq_remapping.h>
37
38 #include "amd_iommu_proto.h"
39 #include "amd_iommu_types.h"
40 #include "irq_remapping.h"
41
42 /*
43 * definitions for the ACPI scanning code
44 */
45 #define IVRS_HEADER_LENGTH 48
46
47 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
48 #define ACPI_IVMD_TYPE_ALL 0x20
49 #define ACPI_IVMD_TYPE 0x21
50 #define ACPI_IVMD_TYPE_RANGE 0x22
51
52 #define IVHD_DEV_ALL 0x01
53 #define IVHD_DEV_SELECT 0x02
54 #define IVHD_DEV_SELECT_RANGE_START 0x03
55 #define IVHD_DEV_RANGE_END 0x04
56 #define IVHD_DEV_ALIAS 0x42
57 #define IVHD_DEV_ALIAS_RANGE 0x43
58 #define IVHD_DEV_EXT_SELECT 0x46
59 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
60 #define IVHD_DEV_SPECIAL 0x48
61 #define IVHD_DEV_ACPI_HID 0xf0
62
63 #define UID_NOT_PRESENT 0
64 #define UID_IS_INTEGER 1
65 #define UID_IS_CHARACTER 2
66
67 #define IVHD_SPECIAL_IOAPIC 1
68 #define IVHD_SPECIAL_HPET 2
69
70 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
71 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
72 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
73 #define IVHD_FLAG_ISOC_EN_MASK 0x08
74
75 #define IVMD_FLAG_EXCL_RANGE 0x08
76 #define IVMD_FLAG_UNITY_MAP 0x01
77
78 #define ACPI_DEVFLAG_INITPASS 0x01
79 #define ACPI_DEVFLAG_EXTINT 0x02
80 #define ACPI_DEVFLAG_NMI 0x04
81 #define ACPI_DEVFLAG_SYSMGT1 0x10
82 #define ACPI_DEVFLAG_SYSMGT2 0x20
83 #define ACPI_DEVFLAG_LINT0 0x40
84 #define ACPI_DEVFLAG_LINT1 0x80
85 #define ACPI_DEVFLAG_ATSDIS 0x10000000
86
87 #define LOOP_TIMEOUT 100000
88 /*
89 * ACPI table definitions
90 *
91 * These data structures are laid over the table to parse the important values
92 * out of it.
93 */
94
95 /*
96 * structure describing one IOMMU in the ACPI table. Typically followed by one
97 * or more ivhd_entrys.
98 */
99 struct ivhd_header {
100 u8 type;
101 u8 flags;
102 u16 length;
103 u16 devid;
104 u16 cap_ptr;
105 u64 mmio_phys;
106 u16 pci_seg;
107 u16 info;
108 u32 efr_attr;
109
110 /* Following only valid on IVHD type 11h and 40h */
111 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
112 u64 res;
113 } __attribute__((packed));
114
115 /*
116 * A device entry describing which devices a specific IOMMU translates and
117 * which requestor ids they use.
118 */
119 struct ivhd_entry {
120 u8 type;
121 u16 devid;
122 u8 flags;
123 u32 ext;
124 u32 hidh;
125 u64 cid;
126 u8 uidf;
127 u8 uidl;
128 u8 uid;
129 } __attribute__((packed));
130
131 /*
132 * An AMD IOMMU memory definition structure. It defines things like exclusion
133 * ranges for devices and regions that should be unity mapped.
134 */
135 struct ivmd_header {
136 u8 type;
137 u8 flags;
138 u16 length;
139 u16 devid;
140 u16 aux;
141 u64 resv;
142 u64 range_start;
143 u64 range_length;
144 } __attribute__((packed));
145
146 bool amd_iommu_dump;
147 bool amd_iommu_irq_remap __read_mostly;
148
149 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
150
151 static bool amd_iommu_detected;
152 static bool __initdata amd_iommu_disabled;
153 static int amd_iommu_target_ivhd_type;
154
155 u16 amd_iommu_last_bdf; /* largest PCI device id we have
156 to handle */
157 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
158 we find in ACPI */
159 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
160
161 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
162 system */
163
164 /* Array to assign indices to IOMMUs*/
165 struct amd_iommu *amd_iommus[MAX_IOMMUS];
166 int amd_iommus_present;
167
168 /* IOMMUs have a non-present cache? */
169 bool amd_iommu_np_cache __read_mostly;
170 bool amd_iommu_iotlb_sup __read_mostly = true;
171
172 u32 amd_iommu_max_pasid __read_mostly = ~0;
173
174 bool amd_iommu_v2_present __read_mostly;
175 static bool amd_iommu_pc_present __read_mostly;
176
177 bool amd_iommu_force_isolation __read_mostly;
178
179 /*
180 * List of protection domains - used during resume
181 */
182 LIST_HEAD(amd_iommu_pd_list);
183 spinlock_t amd_iommu_pd_lock;
184
185 /*
186 * Pointer to the device table which is shared by all AMD IOMMUs
187 * it is indexed by the PCI device id or the HT unit id and contains
188 * information about the domain the device belongs to as well as the
189 * page table root pointer.
190 */
191 struct dev_table_entry *amd_iommu_dev_table;
192
193 /*
194 * The alias table is a driver specific data structure which contains the
195 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
196 * More than one device can share the same requestor id.
197 */
198 u16 *amd_iommu_alias_table;
199
200 /*
201 * The rlookup table is used to find the IOMMU which is responsible
202 * for a specific device. It is also indexed by the PCI device id.
203 */
204 struct amd_iommu **amd_iommu_rlookup_table;
205
206 /*
207 * This table is used to find the irq remapping table for a given device id
208 * quickly.
209 */
210 struct irq_remap_table **irq_lookup_table;
211
212 /*
213 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
214 * to know which ones are already in use.
215 */
216 unsigned long *amd_iommu_pd_alloc_bitmap;
217
218 static u32 dev_table_size; /* size of the device table */
219 static u32 alias_table_size; /* size of the alias table */
220 static u32 rlookup_table_size; /* size if the rlookup table */
221
222 enum iommu_init_state {
223 IOMMU_START_STATE,
224 IOMMU_IVRS_DETECTED,
225 IOMMU_ACPI_FINISHED,
226 IOMMU_ENABLED,
227 IOMMU_PCI_INIT,
228 IOMMU_INTERRUPTS_EN,
229 IOMMU_DMA_OPS,
230 IOMMU_INITIALIZED,
231 IOMMU_NOT_FOUND,
232 IOMMU_INIT_ERROR,
233 };
234
235 /* Early ioapic and hpet maps from kernel command line */
236 #define EARLY_MAP_SIZE 4
237 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
238 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
239 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
240
241 static int __initdata early_ioapic_map_size;
242 static int __initdata early_hpet_map_size;
243 static int __initdata early_acpihid_map_size;
244
245 static bool __initdata cmdline_maps;
246
247 static enum iommu_init_state init_state = IOMMU_START_STATE;
248
249 static int amd_iommu_enable_interrupts(void);
250 static int __init iommu_go_to_state(enum iommu_init_state state);
251 static void init_device_table_dma(void);
252
253 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
254 u8 bank, u8 cntr, u8 fxn,
255 u64 *value, bool is_write);
256
257 static inline void update_last_devid(u16 devid)
258 {
259 if (devid > amd_iommu_last_bdf)
260 amd_iommu_last_bdf = devid;
261 }
262
263 static inline unsigned long tbl_size(int entry_size)
264 {
265 unsigned shift = PAGE_SHIFT +
266 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
267
268 return 1UL << shift;
269 }
270
271 /* Access to l1 and l2 indexed register spaces */
272
273 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
274 {
275 u32 val;
276
277 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
278 pci_read_config_dword(iommu->dev, 0xfc, &val);
279 return val;
280 }
281
282 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
283 {
284 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
285 pci_write_config_dword(iommu->dev, 0xfc, val);
286 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
287 }
288
289 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
290 {
291 u32 val;
292
293 pci_write_config_dword(iommu->dev, 0xf0, address);
294 pci_read_config_dword(iommu->dev, 0xf4, &val);
295 return val;
296 }
297
298 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
299 {
300 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
301 pci_write_config_dword(iommu->dev, 0xf4, val);
302 }
303
304 /****************************************************************************
305 *
306 * AMD IOMMU MMIO register space handling functions
307 *
308 * These functions are used to program the IOMMU device registers in
309 * MMIO space required for that driver.
310 *
311 ****************************************************************************/
312
313 /*
314 * This function set the exclusion range in the IOMMU. DMA accesses to the
315 * exclusion range are passed through untranslated
316 */
317 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
318 {
319 u64 start = iommu->exclusion_start & PAGE_MASK;
320 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
321 u64 entry;
322
323 if (!iommu->exclusion_start)
324 return;
325
326 entry = start | MMIO_EXCL_ENABLE_MASK;
327 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
328 &entry, sizeof(entry));
329
330 entry = limit;
331 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
332 &entry, sizeof(entry));
333 }
334
335 /* Programs the physical address of the device table into the IOMMU hardware */
336 static void iommu_set_device_table(struct amd_iommu *iommu)
337 {
338 u64 entry;
339
340 BUG_ON(iommu->mmio_base == NULL);
341
342 entry = virt_to_phys(amd_iommu_dev_table);
343 entry |= (dev_table_size >> 12) - 1;
344 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
345 &entry, sizeof(entry));
346 }
347
348 /* Generic functions to enable/disable certain features of the IOMMU. */
349 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
350 {
351 u32 ctrl;
352
353 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
354 ctrl |= (1 << bit);
355 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
356 }
357
358 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
359 {
360 u32 ctrl;
361
362 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
363 ctrl &= ~(1 << bit);
364 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
365 }
366
367 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
368 {
369 u32 ctrl;
370
371 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
372 ctrl &= ~CTRL_INV_TO_MASK;
373 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
374 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
375 }
376
377 /* Function to enable the hardware */
378 static void iommu_enable(struct amd_iommu *iommu)
379 {
380 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
381 }
382
383 static void iommu_disable(struct amd_iommu *iommu)
384 {
385 /* Disable command buffer */
386 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
387
388 /* Disable event logging and event interrupts */
389 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
390 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
391
392 /* Disable IOMMU GA_LOG */
393 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
394 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
395
396 /* Disable IOMMU hardware itself */
397 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
398 }
399
400 /*
401 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
402 * the system has one.
403 */
404 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
405 {
406 if (!request_mem_region(address, end, "amd_iommu")) {
407 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
408 address, end);
409 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
410 return NULL;
411 }
412
413 return (u8 __iomem *)ioremap_nocache(address, end);
414 }
415
416 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
417 {
418 if (iommu->mmio_base)
419 iounmap(iommu->mmio_base);
420 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
421 }
422
423 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
424 {
425 u32 size = 0;
426
427 switch (h->type) {
428 case 0x10:
429 size = 24;
430 break;
431 case 0x11:
432 case 0x40:
433 size = 40;
434 break;
435 }
436 return size;
437 }
438
439 /****************************************************************************
440 *
441 * The functions below belong to the first pass of AMD IOMMU ACPI table
442 * parsing. In this pass we try to find out the highest device id this
443 * code has to handle. Upon this information the size of the shared data
444 * structures is determined later.
445 *
446 ****************************************************************************/
447
448 /*
449 * This function calculates the length of a given IVHD entry
450 */
451 static inline int ivhd_entry_length(u8 *ivhd)
452 {
453 u32 type = ((struct ivhd_entry *)ivhd)->type;
454
455 if (type < 0x80) {
456 return 0x04 << (*ivhd >> 6);
457 } else if (type == IVHD_DEV_ACPI_HID) {
458 /* For ACPI_HID, offset 21 is uid len */
459 return *((u8 *)ivhd + 21) + 22;
460 }
461 return 0;
462 }
463
464 /*
465 * After reading the highest device id from the IOMMU PCI capability header
466 * this function looks if there is a higher device id defined in the ACPI table
467 */
468 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
469 {
470 u8 *p = (void *)h, *end = (void *)h;
471 struct ivhd_entry *dev;
472
473 u32 ivhd_size = get_ivhd_header_size(h);
474
475 if (!ivhd_size) {
476 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
477 return -EINVAL;
478 }
479
480 p += ivhd_size;
481 end += h->length;
482
483 while (p < end) {
484 dev = (struct ivhd_entry *)p;
485 switch (dev->type) {
486 case IVHD_DEV_ALL:
487 /* Use maximum BDF value for DEV_ALL */
488 update_last_devid(0xffff);
489 break;
490 case IVHD_DEV_SELECT:
491 case IVHD_DEV_RANGE_END:
492 case IVHD_DEV_ALIAS:
493 case IVHD_DEV_EXT_SELECT:
494 /* all the above subfield types refer to device ids */
495 update_last_devid(dev->devid);
496 break;
497 default:
498 break;
499 }
500 p += ivhd_entry_length(p);
501 }
502
503 WARN_ON(p != end);
504
505 return 0;
506 }
507
508 static int __init check_ivrs_checksum(struct acpi_table_header *table)
509 {
510 int i;
511 u8 checksum = 0, *p = (u8 *)table;
512
513 for (i = 0; i < table->length; ++i)
514 checksum += p[i];
515 if (checksum != 0) {
516 /* ACPI table corrupt */
517 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
518 return -ENODEV;
519 }
520
521 return 0;
522 }
523
524 /*
525 * Iterate over all IVHD entries in the ACPI table and find the highest device
526 * id which we need to handle. This is the first of three functions which parse
527 * the ACPI table. So we check the checksum here.
528 */
529 static int __init find_last_devid_acpi(struct acpi_table_header *table)
530 {
531 u8 *p = (u8 *)table, *end = (u8 *)table;
532 struct ivhd_header *h;
533
534 p += IVRS_HEADER_LENGTH;
535
536 end += table->length;
537 while (p < end) {
538 h = (struct ivhd_header *)p;
539 if (h->type == amd_iommu_target_ivhd_type) {
540 int ret = find_last_devid_from_ivhd(h);
541
542 if (ret)
543 return ret;
544 }
545 p += h->length;
546 }
547 WARN_ON(p != end);
548
549 return 0;
550 }
551
552 /****************************************************************************
553 *
554 * The following functions belong to the code path which parses the ACPI table
555 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
556 * data structures, initialize the device/alias/rlookup table and also
557 * basically initialize the hardware.
558 *
559 ****************************************************************************/
560
561 /*
562 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
563 * write commands to that buffer later and the IOMMU will execute them
564 * asynchronously
565 */
566 static int __init alloc_command_buffer(struct amd_iommu *iommu)
567 {
568 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
569 get_order(CMD_BUFFER_SIZE));
570
571 return iommu->cmd_buf ? 0 : -ENOMEM;
572 }
573
574 /*
575 * This function resets the command buffer if the IOMMU stopped fetching
576 * commands from it.
577 */
578 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
579 {
580 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
581
582 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
583 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
584
585 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
586 }
587
588 /*
589 * This function writes the command buffer address to the hardware and
590 * enables it.
591 */
592 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
593 {
594 u64 entry;
595
596 BUG_ON(iommu->cmd_buf == NULL);
597
598 entry = (u64)virt_to_phys(iommu->cmd_buf);
599 entry |= MMIO_CMD_SIZE_512;
600
601 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
602 &entry, sizeof(entry));
603
604 amd_iommu_reset_cmd_buffer(iommu);
605 }
606
607 static void __init free_command_buffer(struct amd_iommu *iommu)
608 {
609 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
610 }
611
612 /* allocates the memory where the IOMMU will log its events to */
613 static int __init alloc_event_buffer(struct amd_iommu *iommu)
614 {
615 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
616 get_order(EVT_BUFFER_SIZE));
617
618 return iommu->evt_buf ? 0 : -ENOMEM;
619 }
620
621 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
622 {
623 u64 entry;
624
625 BUG_ON(iommu->evt_buf == NULL);
626
627 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
628
629 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
630 &entry, sizeof(entry));
631
632 /* set head and tail to zero manually */
633 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
634 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
635
636 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
637 }
638
639 static void __init free_event_buffer(struct amd_iommu *iommu)
640 {
641 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
642 }
643
644 /* allocates the memory where the IOMMU will log its events to */
645 static int __init alloc_ppr_log(struct amd_iommu *iommu)
646 {
647 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
648 get_order(PPR_LOG_SIZE));
649
650 return iommu->ppr_log ? 0 : -ENOMEM;
651 }
652
653 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
654 {
655 u64 entry;
656
657 if (iommu->ppr_log == NULL)
658 return;
659
660 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
661
662 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
663 &entry, sizeof(entry));
664
665 /* set head and tail to zero manually */
666 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
667 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
668
669 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
670 iommu_feature_enable(iommu, CONTROL_PPR_EN);
671 }
672
673 static void __init free_ppr_log(struct amd_iommu *iommu)
674 {
675 if (iommu->ppr_log == NULL)
676 return;
677
678 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
679 }
680
681 static void free_ga_log(struct amd_iommu *iommu)
682 {
683 #ifdef CONFIG_IRQ_REMAP
684 if (iommu->ga_log)
685 free_pages((unsigned long)iommu->ga_log,
686 get_order(GA_LOG_SIZE));
687 if (iommu->ga_log_tail)
688 free_pages((unsigned long)iommu->ga_log_tail,
689 get_order(8));
690 #endif
691 }
692
693 static int iommu_ga_log_enable(struct amd_iommu *iommu)
694 {
695 #ifdef CONFIG_IRQ_REMAP
696 u32 status, i;
697
698 if (!iommu->ga_log)
699 return -EINVAL;
700
701 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
702
703 /* Check if already running */
704 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
705 return 0;
706
707 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
708 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
709
710 for (i = 0; i < LOOP_TIMEOUT; ++i) {
711 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
712 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
713 break;
714 }
715
716 if (i >= LOOP_TIMEOUT)
717 return -EINVAL;
718 #endif /* CONFIG_IRQ_REMAP */
719 return 0;
720 }
721
722 #ifdef CONFIG_IRQ_REMAP
723 static int iommu_init_ga_log(struct amd_iommu *iommu)
724 {
725 u64 entry;
726
727 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
728 return 0;
729
730 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
731 get_order(GA_LOG_SIZE));
732 if (!iommu->ga_log)
733 goto err_out;
734
735 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
736 get_order(8));
737 if (!iommu->ga_log_tail)
738 goto err_out;
739
740 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
741 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
742 &entry, sizeof(entry));
743 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
744 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
745 &entry, sizeof(entry));
746 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
747 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
748
749 return 0;
750 err_out:
751 free_ga_log(iommu);
752 return -EINVAL;
753 }
754 #endif /* CONFIG_IRQ_REMAP */
755
756 static int iommu_init_ga(struct amd_iommu *iommu)
757 {
758 int ret = 0;
759
760 #ifdef CONFIG_IRQ_REMAP
761 /* Note: We have already checked GASup from IVRS table.
762 * Now, we need to make sure that GAMSup is set.
763 */
764 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
765 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
766 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
767
768 ret = iommu_init_ga_log(iommu);
769 #endif /* CONFIG_IRQ_REMAP */
770
771 return ret;
772 }
773
774 static void iommu_enable_gt(struct amd_iommu *iommu)
775 {
776 if (!iommu_feature(iommu, FEATURE_GT))
777 return;
778
779 iommu_feature_enable(iommu, CONTROL_GT_EN);
780 }
781
782 /* sets a specific bit in the device table entry. */
783 static void set_dev_entry_bit(u16 devid, u8 bit)
784 {
785 int i = (bit >> 6) & 0x03;
786 int _bit = bit & 0x3f;
787
788 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
789 }
790
791 static int get_dev_entry_bit(u16 devid, u8 bit)
792 {
793 int i = (bit >> 6) & 0x03;
794 int _bit = bit & 0x3f;
795
796 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
797 }
798
799
800 void amd_iommu_apply_erratum_63(u16 devid)
801 {
802 int sysmgt;
803
804 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
805 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
806
807 if (sysmgt == 0x01)
808 set_dev_entry_bit(devid, DEV_ENTRY_IW);
809 }
810
811 /* Writes the specific IOMMU for a device into the rlookup table */
812 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
813 {
814 amd_iommu_rlookup_table[devid] = iommu;
815 }
816
817 /*
818 * This function takes the device specific flags read from the ACPI
819 * table and sets up the device table entry with that information
820 */
821 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
822 u16 devid, u32 flags, u32 ext_flags)
823 {
824 if (flags & ACPI_DEVFLAG_INITPASS)
825 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
826 if (flags & ACPI_DEVFLAG_EXTINT)
827 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
828 if (flags & ACPI_DEVFLAG_NMI)
829 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
830 if (flags & ACPI_DEVFLAG_SYSMGT1)
831 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
832 if (flags & ACPI_DEVFLAG_SYSMGT2)
833 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
834 if (flags & ACPI_DEVFLAG_LINT0)
835 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
836 if (flags & ACPI_DEVFLAG_LINT1)
837 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
838
839 amd_iommu_apply_erratum_63(devid);
840
841 set_iommu_for_device(iommu, devid);
842 }
843
844 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
845 {
846 struct devid_map *entry;
847 struct list_head *list;
848
849 if (type == IVHD_SPECIAL_IOAPIC)
850 list = &ioapic_map;
851 else if (type == IVHD_SPECIAL_HPET)
852 list = &hpet_map;
853 else
854 return -EINVAL;
855
856 list_for_each_entry(entry, list, list) {
857 if (!(entry->id == id && entry->cmd_line))
858 continue;
859
860 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
861 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
862
863 *devid = entry->devid;
864
865 return 0;
866 }
867
868 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
869 if (!entry)
870 return -ENOMEM;
871
872 entry->id = id;
873 entry->devid = *devid;
874 entry->cmd_line = cmd_line;
875
876 list_add_tail(&entry->list, list);
877
878 return 0;
879 }
880
881 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
882 bool cmd_line)
883 {
884 struct acpihid_map_entry *entry;
885 struct list_head *list = &acpihid_map;
886
887 list_for_each_entry(entry, list, list) {
888 if (strcmp(entry->hid, hid) ||
889 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
890 !entry->cmd_line)
891 continue;
892
893 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
894 hid, uid);
895 *devid = entry->devid;
896 return 0;
897 }
898
899 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
900 if (!entry)
901 return -ENOMEM;
902
903 memcpy(entry->uid, uid, strlen(uid));
904 memcpy(entry->hid, hid, strlen(hid));
905 entry->devid = *devid;
906 entry->cmd_line = cmd_line;
907 entry->root_devid = (entry->devid & (~0x7));
908
909 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
910 entry->cmd_line ? "cmd" : "ivrs",
911 entry->hid, entry->uid, entry->root_devid);
912
913 list_add_tail(&entry->list, list);
914 return 0;
915 }
916
917 static int __init add_early_maps(void)
918 {
919 int i, ret;
920
921 for (i = 0; i < early_ioapic_map_size; ++i) {
922 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
923 early_ioapic_map[i].id,
924 &early_ioapic_map[i].devid,
925 early_ioapic_map[i].cmd_line);
926 if (ret)
927 return ret;
928 }
929
930 for (i = 0; i < early_hpet_map_size; ++i) {
931 ret = add_special_device(IVHD_SPECIAL_HPET,
932 early_hpet_map[i].id,
933 &early_hpet_map[i].devid,
934 early_hpet_map[i].cmd_line);
935 if (ret)
936 return ret;
937 }
938
939 for (i = 0; i < early_acpihid_map_size; ++i) {
940 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
941 early_acpihid_map[i].uid,
942 &early_acpihid_map[i].devid,
943 early_acpihid_map[i].cmd_line);
944 if (ret)
945 return ret;
946 }
947
948 return 0;
949 }
950
951 /*
952 * Reads the device exclusion range from ACPI and initializes the IOMMU with
953 * it
954 */
955 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
956 {
957 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
958
959 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
960 return;
961
962 if (iommu) {
963 /*
964 * We only can configure exclusion ranges per IOMMU, not
965 * per device. But we can enable the exclusion range per
966 * device. This is done here
967 */
968 set_dev_entry_bit(devid, DEV_ENTRY_EX);
969 iommu->exclusion_start = m->range_start;
970 iommu->exclusion_length = m->range_length;
971 }
972 }
973
974 /*
975 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
976 * initializes the hardware and our data structures with it.
977 */
978 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
979 struct ivhd_header *h)
980 {
981 u8 *p = (u8 *)h;
982 u8 *end = p, flags = 0;
983 u16 devid = 0, devid_start = 0, devid_to = 0;
984 u32 dev_i, ext_flags = 0;
985 bool alias = false;
986 struct ivhd_entry *e;
987 u32 ivhd_size;
988 int ret;
989
990
991 ret = add_early_maps();
992 if (ret)
993 return ret;
994
995 /*
996 * First save the recommended feature enable bits from ACPI
997 */
998 iommu->acpi_flags = h->flags;
999
1000 /*
1001 * Done. Now parse the device entries
1002 */
1003 ivhd_size = get_ivhd_header_size(h);
1004 if (!ivhd_size) {
1005 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1006 return -EINVAL;
1007 }
1008
1009 p += ivhd_size;
1010
1011 end += h->length;
1012
1013
1014 while (p < end) {
1015 e = (struct ivhd_entry *)p;
1016 switch (e->type) {
1017 case IVHD_DEV_ALL:
1018
1019 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1020
1021 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1022 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1023 break;
1024 case IVHD_DEV_SELECT:
1025
1026 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1027 "flags: %02x\n",
1028 PCI_BUS_NUM(e->devid),
1029 PCI_SLOT(e->devid),
1030 PCI_FUNC(e->devid),
1031 e->flags);
1032
1033 devid = e->devid;
1034 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1035 break;
1036 case IVHD_DEV_SELECT_RANGE_START:
1037
1038 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1039 "devid: %02x:%02x.%x flags: %02x\n",
1040 PCI_BUS_NUM(e->devid),
1041 PCI_SLOT(e->devid),
1042 PCI_FUNC(e->devid),
1043 e->flags);
1044
1045 devid_start = e->devid;
1046 flags = e->flags;
1047 ext_flags = 0;
1048 alias = false;
1049 break;
1050 case IVHD_DEV_ALIAS:
1051
1052 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1053 "flags: %02x devid_to: %02x:%02x.%x\n",
1054 PCI_BUS_NUM(e->devid),
1055 PCI_SLOT(e->devid),
1056 PCI_FUNC(e->devid),
1057 e->flags,
1058 PCI_BUS_NUM(e->ext >> 8),
1059 PCI_SLOT(e->ext >> 8),
1060 PCI_FUNC(e->ext >> 8));
1061
1062 devid = e->devid;
1063 devid_to = e->ext >> 8;
1064 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1065 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1066 amd_iommu_alias_table[devid] = devid_to;
1067 break;
1068 case IVHD_DEV_ALIAS_RANGE:
1069
1070 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1071 "devid: %02x:%02x.%x flags: %02x "
1072 "devid_to: %02x:%02x.%x\n",
1073 PCI_BUS_NUM(e->devid),
1074 PCI_SLOT(e->devid),
1075 PCI_FUNC(e->devid),
1076 e->flags,
1077 PCI_BUS_NUM(e->ext >> 8),
1078 PCI_SLOT(e->ext >> 8),
1079 PCI_FUNC(e->ext >> 8));
1080
1081 devid_start = e->devid;
1082 flags = e->flags;
1083 devid_to = e->ext >> 8;
1084 ext_flags = 0;
1085 alias = true;
1086 break;
1087 case IVHD_DEV_EXT_SELECT:
1088
1089 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1090 "flags: %02x ext: %08x\n",
1091 PCI_BUS_NUM(e->devid),
1092 PCI_SLOT(e->devid),
1093 PCI_FUNC(e->devid),
1094 e->flags, e->ext);
1095
1096 devid = e->devid;
1097 set_dev_entry_from_acpi(iommu, devid, e->flags,
1098 e->ext);
1099 break;
1100 case IVHD_DEV_EXT_SELECT_RANGE:
1101
1102 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1103 "%02x:%02x.%x flags: %02x ext: %08x\n",
1104 PCI_BUS_NUM(e->devid),
1105 PCI_SLOT(e->devid),
1106 PCI_FUNC(e->devid),
1107 e->flags, e->ext);
1108
1109 devid_start = e->devid;
1110 flags = e->flags;
1111 ext_flags = e->ext;
1112 alias = false;
1113 break;
1114 case IVHD_DEV_RANGE_END:
1115
1116 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1117 PCI_BUS_NUM(e->devid),
1118 PCI_SLOT(e->devid),
1119 PCI_FUNC(e->devid));
1120
1121 devid = e->devid;
1122 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1123 if (alias) {
1124 amd_iommu_alias_table[dev_i] = devid_to;
1125 set_dev_entry_from_acpi(iommu,
1126 devid_to, flags, ext_flags);
1127 }
1128 set_dev_entry_from_acpi(iommu, dev_i,
1129 flags, ext_flags);
1130 }
1131 break;
1132 case IVHD_DEV_SPECIAL: {
1133 u8 handle, type;
1134 const char *var;
1135 u16 devid;
1136 int ret;
1137
1138 handle = e->ext & 0xff;
1139 devid = (e->ext >> 8) & 0xffff;
1140 type = (e->ext >> 24) & 0xff;
1141
1142 if (type == IVHD_SPECIAL_IOAPIC)
1143 var = "IOAPIC";
1144 else if (type == IVHD_SPECIAL_HPET)
1145 var = "HPET";
1146 else
1147 var = "UNKNOWN";
1148
1149 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1150 var, (int)handle,
1151 PCI_BUS_NUM(devid),
1152 PCI_SLOT(devid),
1153 PCI_FUNC(devid));
1154
1155 ret = add_special_device(type, handle, &devid, false);
1156 if (ret)
1157 return ret;
1158
1159 /*
1160 * add_special_device might update the devid in case a
1161 * command-line override is present. So call
1162 * set_dev_entry_from_acpi after add_special_device.
1163 */
1164 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1165
1166 break;
1167 }
1168 case IVHD_DEV_ACPI_HID: {
1169 u16 devid;
1170 u8 hid[ACPIHID_HID_LEN] = {0};
1171 u8 uid[ACPIHID_UID_LEN] = {0};
1172 int ret;
1173
1174 if (h->type != 0x40) {
1175 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1176 e->type);
1177 break;
1178 }
1179
1180 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1181 hid[ACPIHID_HID_LEN - 1] = '\0';
1182
1183 if (!(*hid)) {
1184 pr_err(FW_BUG "Invalid HID.\n");
1185 break;
1186 }
1187
1188 switch (e->uidf) {
1189 case UID_NOT_PRESENT:
1190
1191 if (e->uidl != 0)
1192 pr_warn(FW_BUG "Invalid UID length.\n");
1193
1194 break;
1195 case UID_IS_INTEGER:
1196
1197 sprintf(uid, "%d", e->uid);
1198
1199 break;
1200 case UID_IS_CHARACTER:
1201
1202 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1203 uid[ACPIHID_UID_LEN - 1] = '\0';
1204
1205 break;
1206 default:
1207 break;
1208 }
1209
1210 devid = e->devid;
1211 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1212 hid, uid,
1213 PCI_BUS_NUM(devid),
1214 PCI_SLOT(devid),
1215 PCI_FUNC(devid));
1216
1217 flags = e->flags;
1218
1219 ret = add_acpi_hid_device(hid, uid, &devid, false);
1220 if (ret)
1221 return ret;
1222
1223 /*
1224 * add_special_device might update the devid in case a
1225 * command-line override is present. So call
1226 * set_dev_entry_from_acpi after add_special_device.
1227 */
1228 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1229
1230 break;
1231 }
1232 default:
1233 break;
1234 }
1235
1236 p += ivhd_entry_length(p);
1237 }
1238
1239 return 0;
1240 }
1241
1242 static void __init free_iommu_one(struct amd_iommu *iommu)
1243 {
1244 free_command_buffer(iommu);
1245 free_event_buffer(iommu);
1246 free_ppr_log(iommu);
1247 free_ga_log(iommu);
1248 iommu_unmap_mmio_space(iommu);
1249 }
1250
1251 static void __init free_iommu_all(void)
1252 {
1253 struct amd_iommu *iommu, *next;
1254
1255 for_each_iommu_safe(iommu, next) {
1256 list_del(&iommu->list);
1257 free_iommu_one(iommu);
1258 kfree(iommu);
1259 }
1260 }
1261
1262 /*
1263 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1264 * Workaround:
1265 * BIOS should disable L2B micellaneous clock gating by setting
1266 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1267 */
1268 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1269 {
1270 u32 value;
1271
1272 if ((boot_cpu_data.x86 != 0x15) ||
1273 (boot_cpu_data.x86_model < 0x10) ||
1274 (boot_cpu_data.x86_model > 0x1f))
1275 return;
1276
1277 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1278 pci_read_config_dword(iommu->dev, 0xf4, &value);
1279
1280 if (value & BIT(2))
1281 return;
1282
1283 /* Select NB indirect register 0x90 and enable writing */
1284 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1285
1286 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1287 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1288 dev_name(&iommu->dev->dev));
1289
1290 /* Clear the enable writing bit */
1291 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1292 }
1293
1294 /*
1295 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1296 * Workaround:
1297 * BIOS should enable ATS write permission check by setting
1298 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1299 */
1300 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1301 {
1302 u32 value;
1303
1304 if ((boot_cpu_data.x86 != 0x15) ||
1305 (boot_cpu_data.x86_model < 0x30) ||
1306 (boot_cpu_data.x86_model > 0x3f))
1307 return;
1308
1309 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1310 value = iommu_read_l2(iommu, 0x47);
1311
1312 if (value & BIT(0))
1313 return;
1314
1315 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1316 iommu_write_l2(iommu, 0x47, value | BIT(0));
1317
1318 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1319 dev_name(&iommu->dev->dev));
1320 }
1321
1322 /*
1323 * This function clues the initialization function for one IOMMU
1324 * together and also allocates the command buffer and programs the
1325 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1326 */
1327 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1328 {
1329 int ret;
1330
1331 spin_lock_init(&iommu->lock);
1332
1333 /* Add IOMMU to internal data structures */
1334 list_add_tail(&iommu->list, &amd_iommu_list);
1335 iommu->index = amd_iommus_present++;
1336
1337 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1338 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1339 return -ENOSYS;
1340 }
1341
1342 /* Index is fine - add IOMMU to the array */
1343 amd_iommus[iommu->index] = iommu;
1344
1345 /*
1346 * Copy data from ACPI table entry to the iommu struct
1347 */
1348 iommu->devid = h->devid;
1349 iommu->cap_ptr = h->cap_ptr;
1350 iommu->pci_seg = h->pci_seg;
1351 iommu->mmio_phys = h->mmio_phys;
1352
1353 switch (h->type) {
1354 case 0x10:
1355 /* Check if IVHD EFR contains proper max banks/counters */
1356 if ((h->efr_attr != 0) &&
1357 ((h->efr_attr & (0xF << 13)) != 0) &&
1358 ((h->efr_attr & (0x3F << 17)) != 0))
1359 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1360 else
1361 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1362 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1363 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1364 break;
1365 case 0x11:
1366 case 0x40:
1367 if (h->efr_reg & (1 << 9))
1368 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1369 else
1370 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1371 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1372 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1373 break;
1374 default:
1375 return -EINVAL;
1376 }
1377
1378 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1379 iommu->mmio_phys_end);
1380 if (!iommu->mmio_base)
1381 return -ENOMEM;
1382
1383 if (alloc_command_buffer(iommu))
1384 return -ENOMEM;
1385
1386 if (alloc_event_buffer(iommu))
1387 return -ENOMEM;
1388
1389 iommu->int_enabled = false;
1390
1391 ret = init_iommu_from_acpi(iommu, h);
1392 if (ret)
1393 return ret;
1394
1395 ret = amd_iommu_create_irq_domain(iommu);
1396 if (ret)
1397 return ret;
1398
1399 /*
1400 * Make sure IOMMU is not considered to translate itself. The IVRS
1401 * table tells us so, but this is a lie!
1402 */
1403 amd_iommu_rlookup_table[iommu->devid] = NULL;
1404
1405 return 0;
1406 }
1407
1408 /**
1409 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1410 * @ivrs Pointer to the IVRS header
1411 *
1412 * This function search through all IVDB of the maximum supported IVHD
1413 */
1414 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1415 {
1416 u8 *base = (u8 *)ivrs;
1417 struct ivhd_header *ivhd = (struct ivhd_header *)
1418 (base + IVRS_HEADER_LENGTH);
1419 u8 last_type = ivhd->type;
1420 u16 devid = ivhd->devid;
1421
1422 while (((u8 *)ivhd - base < ivrs->length) &&
1423 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1424 u8 *p = (u8 *) ivhd;
1425
1426 if (ivhd->devid == devid)
1427 last_type = ivhd->type;
1428 ivhd = (struct ivhd_header *)(p + ivhd->length);
1429 }
1430
1431 return last_type;
1432 }
1433
1434 /*
1435 * Iterates over all IOMMU entries in the ACPI table, allocates the
1436 * IOMMU structure and initializes it with init_iommu_one()
1437 */
1438 static int __init init_iommu_all(struct acpi_table_header *table)
1439 {
1440 u8 *p = (u8 *)table, *end = (u8 *)table;
1441 struct ivhd_header *h;
1442 struct amd_iommu *iommu;
1443 int ret;
1444
1445 end += table->length;
1446 p += IVRS_HEADER_LENGTH;
1447
1448 while (p < end) {
1449 h = (struct ivhd_header *)p;
1450 if (*p == amd_iommu_target_ivhd_type) {
1451
1452 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1453 "seg: %d flags: %01x info %04x\n",
1454 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1455 PCI_FUNC(h->devid), h->cap_ptr,
1456 h->pci_seg, h->flags, h->info);
1457 DUMP_printk(" mmio-addr: %016llx\n",
1458 h->mmio_phys);
1459
1460 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1461 if (iommu == NULL)
1462 return -ENOMEM;
1463
1464 ret = init_iommu_one(iommu, h);
1465 if (ret)
1466 return ret;
1467 }
1468 p += h->length;
1469
1470 }
1471 WARN_ON(p != end);
1472
1473 return 0;
1474 }
1475
1476
1477 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1478 {
1479 u64 val = 0xabcd, val2 = 0;
1480
1481 if (!iommu_feature(iommu, FEATURE_PC))
1482 return;
1483
1484 amd_iommu_pc_present = true;
1485
1486 /* Check if the performance counters can be written to */
1487 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1488 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
1489 (val != val2)) {
1490 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1491 amd_iommu_pc_present = false;
1492 return;
1493 }
1494
1495 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1496
1497 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1498 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1499 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1500 }
1501
1502 static ssize_t amd_iommu_show_cap(struct device *dev,
1503 struct device_attribute *attr,
1504 char *buf)
1505 {
1506 struct amd_iommu *iommu = dev_get_drvdata(dev);
1507 return sprintf(buf, "%x\n", iommu->cap);
1508 }
1509 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1510
1511 static ssize_t amd_iommu_show_features(struct device *dev,
1512 struct device_attribute *attr,
1513 char *buf)
1514 {
1515 struct amd_iommu *iommu = dev_get_drvdata(dev);
1516 return sprintf(buf, "%llx\n", iommu->features);
1517 }
1518 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1519
1520 static struct attribute *amd_iommu_attrs[] = {
1521 &dev_attr_cap.attr,
1522 &dev_attr_features.attr,
1523 NULL,
1524 };
1525
1526 static struct attribute_group amd_iommu_group = {
1527 .name = "amd-iommu",
1528 .attrs = amd_iommu_attrs,
1529 };
1530
1531 static const struct attribute_group *amd_iommu_groups[] = {
1532 &amd_iommu_group,
1533 NULL,
1534 };
1535
1536 static int iommu_init_pci(struct amd_iommu *iommu)
1537 {
1538 int cap_ptr = iommu->cap_ptr;
1539 u32 range, misc, low, high;
1540 int ret;
1541
1542 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1543 iommu->devid & 0xff);
1544 if (!iommu->dev)
1545 return -ENODEV;
1546
1547 /* Prevent binding other PCI device drivers to IOMMU devices */
1548 iommu->dev->match_driver = false;
1549
1550 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1551 &iommu->cap);
1552 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1553 &range);
1554 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1555 &misc);
1556
1557 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1558 amd_iommu_iotlb_sup = false;
1559
1560 /* read extended feature bits */
1561 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1562 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1563
1564 iommu->features = ((u64)high << 32) | low;
1565
1566 if (iommu_feature(iommu, FEATURE_GT)) {
1567 int glxval;
1568 u32 max_pasid;
1569 u64 pasmax;
1570
1571 pasmax = iommu->features & FEATURE_PASID_MASK;
1572 pasmax >>= FEATURE_PASID_SHIFT;
1573 max_pasid = (1 << (pasmax + 1)) - 1;
1574
1575 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1576
1577 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1578
1579 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1580 glxval >>= FEATURE_GLXVAL_SHIFT;
1581
1582 if (amd_iommu_max_glx_val == -1)
1583 amd_iommu_max_glx_val = glxval;
1584 else
1585 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1586 }
1587
1588 if (iommu_feature(iommu, FEATURE_GT) &&
1589 iommu_feature(iommu, FEATURE_PPR)) {
1590 iommu->is_iommu_v2 = true;
1591 amd_iommu_v2_present = true;
1592 }
1593
1594 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1595 return -ENOMEM;
1596
1597 ret = iommu_init_ga(iommu);
1598 if (ret)
1599 return ret;
1600
1601 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1602 amd_iommu_np_cache = true;
1603
1604 init_iommu_perf_ctr(iommu);
1605
1606 if (is_rd890_iommu(iommu->dev)) {
1607 int i, j;
1608
1609 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1610 PCI_DEVFN(0, 0));
1611
1612 /*
1613 * Some rd890 systems may not be fully reconfigured by the
1614 * BIOS, so it's necessary for us to store this information so
1615 * it can be reprogrammed on resume
1616 */
1617 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1618 &iommu->stored_addr_lo);
1619 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1620 &iommu->stored_addr_hi);
1621
1622 /* Low bit locks writes to configuration space */
1623 iommu->stored_addr_lo &= ~1;
1624
1625 for (i = 0; i < 6; i++)
1626 for (j = 0; j < 0x12; j++)
1627 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1628
1629 for (i = 0; i < 0x83; i++)
1630 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1631 }
1632
1633 amd_iommu_erratum_746_workaround(iommu);
1634 amd_iommu_ats_write_check_workaround(iommu);
1635
1636 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1637 amd_iommu_groups, "ivhd%d",
1638 iommu->index);
1639
1640 return pci_enable_device(iommu->dev);
1641 }
1642
1643 static void print_iommu_info(void)
1644 {
1645 static const char * const feat_str[] = {
1646 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1647 "IA", "GA", "HE", "PC"
1648 };
1649 struct amd_iommu *iommu;
1650
1651 for_each_iommu(iommu) {
1652 int i;
1653
1654 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1655 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1656
1657 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1658 pr_info("AMD-Vi: Extended features (%#llx):\n",
1659 iommu->features);
1660 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1661 if (iommu_feature(iommu, (1ULL << i)))
1662 pr_cont(" %s", feat_str[i]);
1663 }
1664
1665 if (iommu->features & FEATURE_GAM_VAPIC)
1666 pr_cont(" GA_vAPIC");
1667
1668 pr_cont("\n");
1669 }
1670 }
1671 if (irq_remapping_enabled) {
1672 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1673 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1674 pr_info("AMD-Vi: virtual APIC enabled\n");
1675 }
1676 }
1677
1678 static int __init amd_iommu_init_pci(void)
1679 {
1680 struct amd_iommu *iommu;
1681 int ret = 0;
1682
1683 for_each_iommu(iommu) {
1684 ret = iommu_init_pci(iommu);
1685 if (ret)
1686 break;
1687 }
1688
1689 /*
1690 * Order is important here to make sure any unity map requirements are
1691 * fulfilled. The unity mappings are created and written to the device
1692 * table during the amd_iommu_init_api() call.
1693 *
1694 * After that we call init_device_table_dma() to make sure any
1695 * uninitialized DTE will block DMA, and in the end we flush the caches
1696 * of all IOMMUs to make sure the changes to the device table are
1697 * active.
1698 */
1699 ret = amd_iommu_init_api();
1700
1701 init_device_table_dma();
1702
1703 for_each_iommu(iommu)
1704 iommu_flush_all_caches(iommu);
1705
1706 if (!ret)
1707 print_iommu_info();
1708
1709 return ret;
1710 }
1711
1712 /****************************************************************************
1713 *
1714 * The following functions initialize the MSI interrupts for all IOMMUs
1715 * in the system. It's a bit challenging because there could be multiple
1716 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1717 * pci_dev.
1718 *
1719 ****************************************************************************/
1720
1721 static int iommu_setup_msi(struct amd_iommu *iommu)
1722 {
1723 int r;
1724
1725 r = pci_enable_msi(iommu->dev);
1726 if (r)
1727 return r;
1728
1729 r = request_threaded_irq(iommu->dev->irq,
1730 amd_iommu_int_handler,
1731 amd_iommu_int_thread,
1732 0, "AMD-Vi",
1733 iommu);
1734
1735 if (r) {
1736 pci_disable_msi(iommu->dev);
1737 return r;
1738 }
1739
1740 iommu->int_enabled = true;
1741
1742 return 0;
1743 }
1744
1745 static int iommu_init_msi(struct amd_iommu *iommu)
1746 {
1747 int ret;
1748
1749 if (iommu->int_enabled)
1750 goto enable_faults;
1751
1752 if (iommu->dev->msi_cap)
1753 ret = iommu_setup_msi(iommu);
1754 else
1755 ret = -ENODEV;
1756
1757 if (ret)
1758 return ret;
1759
1760 enable_faults:
1761 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1762
1763 if (iommu->ppr_log != NULL)
1764 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1765
1766 iommu_ga_log_enable(iommu);
1767
1768 return 0;
1769 }
1770
1771 /****************************************************************************
1772 *
1773 * The next functions belong to the third pass of parsing the ACPI
1774 * table. In this last pass the memory mapping requirements are
1775 * gathered (like exclusion and unity mapping ranges).
1776 *
1777 ****************************************************************************/
1778
1779 static void __init free_unity_maps(void)
1780 {
1781 struct unity_map_entry *entry, *next;
1782
1783 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1784 list_del(&entry->list);
1785 kfree(entry);
1786 }
1787 }
1788
1789 /* called when we find an exclusion range definition in ACPI */
1790 static int __init init_exclusion_range(struct ivmd_header *m)
1791 {
1792 int i;
1793
1794 switch (m->type) {
1795 case ACPI_IVMD_TYPE:
1796 set_device_exclusion_range(m->devid, m);
1797 break;
1798 case ACPI_IVMD_TYPE_ALL:
1799 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1800 set_device_exclusion_range(i, m);
1801 break;
1802 case ACPI_IVMD_TYPE_RANGE:
1803 for (i = m->devid; i <= m->aux; ++i)
1804 set_device_exclusion_range(i, m);
1805 break;
1806 default:
1807 break;
1808 }
1809
1810 return 0;
1811 }
1812
1813 /* called for unity map ACPI definition */
1814 static int __init init_unity_map_range(struct ivmd_header *m)
1815 {
1816 struct unity_map_entry *e = NULL;
1817 char *s;
1818
1819 e = kzalloc(sizeof(*e), GFP_KERNEL);
1820 if (e == NULL)
1821 return -ENOMEM;
1822
1823 switch (m->type) {
1824 default:
1825 kfree(e);
1826 return 0;
1827 case ACPI_IVMD_TYPE:
1828 s = "IVMD_TYPEi\t\t\t";
1829 e->devid_start = e->devid_end = m->devid;
1830 break;
1831 case ACPI_IVMD_TYPE_ALL:
1832 s = "IVMD_TYPE_ALL\t\t";
1833 e->devid_start = 0;
1834 e->devid_end = amd_iommu_last_bdf;
1835 break;
1836 case ACPI_IVMD_TYPE_RANGE:
1837 s = "IVMD_TYPE_RANGE\t\t";
1838 e->devid_start = m->devid;
1839 e->devid_end = m->aux;
1840 break;
1841 }
1842 e->address_start = PAGE_ALIGN(m->range_start);
1843 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1844 e->prot = m->flags >> 1;
1845
1846 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1847 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1848 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1849 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1850 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1851 e->address_start, e->address_end, m->flags);
1852
1853 list_add_tail(&e->list, &amd_iommu_unity_map);
1854
1855 return 0;
1856 }
1857
1858 /* iterates over all memory definitions we find in the ACPI table */
1859 static int __init init_memory_definitions(struct acpi_table_header *table)
1860 {
1861 u8 *p = (u8 *)table, *end = (u8 *)table;
1862 struct ivmd_header *m;
1863
1864 end += table->length;
1865 p += IVRS_HEADER_LENGTH;
1866
1867 while (p < end) {
1868 m = (struct ivmd_header *)p;
1869 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1870 init_exclusion_range(m);
1871 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1872 init_unity_map_range(m);
1873
1874 p += m->length;
1875 }
1876
1877 return 0;
1878 }
1879
1880 /*
1881 * Init the device table to not allow DMA access for devices and
1882 * suppress all page faults
1883 */
1884 static void init_device_table_dma(void)
1885 {
1886 u32 devid;
1887
1888 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1889 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1890 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1891 }
1892 }
1893
1894 static void __init uninit_device_table_dma(void)
1895 {
1896 u32 devid;
1897
1898 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1899 amd_iommu_dev_table[devid].data[0] = 0ULL;
1900 amd_iommu_dev_table[devid].data[1] = 0ULL;
1901 }
1902 }
1903
1904 static void init_device_table(void)
1905 {
1906 u32 devid;
1907
1908 if (!amd_iommu_irq_remap)
1909 return;
1910
1911 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1912 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1913 }
1914
1915 static void iommu_init_flags(struct amd_iommu *iommu)
1916 {
1917 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1918 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1919 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1920
1921 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1922 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1923 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1924
1925 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1926 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1927 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1928
1929 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1930 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1931 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1932
1933 /*
1934 * make IOMMU memory accesses cache coherent
1935 */
1936 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1937
1938 /* Set IOTLB invalidation timeout to 1s */
1939 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1940 }
1941
1942 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1943 {
1944 int i, j;
1945 u32 ioc_feature_control;
1946 struct pci_dev *pdev = iommu->root_pdev;
1947
1948 /* RD890 BIOSes may not have completely reconfigured the iommu */
1949 if (!is_rd890_iommu(iommu->dev) || !pdev)
1950 return;
1951
1952 /*
1953 * First, we need to ensure that the iommu is enabled. This is
1954 * controlled by a register in the northbridge
1955 */
1956
1957 /* Select Northbridge indirect register 0x75 and enable writing */
1958 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1959 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1960
1961 /* Enable the iommu */
1962 if (!(ioc_feature_control & 0x1))
1963 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1964
1965 /* Restore the iommu BAR */
1966 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1967 iommu->stored_addr_lo);
1968 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1969 iommu->stored_addr_hi);
1970
1971 /* Restore the l1 indirect regs for each of the 6 l1s */
1972 for (i = 0; i < 6; i++)
1973 for (j = 0; j < 0x12; j++)
1974 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1975
1976 /* Restore the l2 indirect regs */
1977 for (i = 0; i < 0x83; i++)
1978 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1979
1980 /* Lock PCI setup registers */
1981 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1982 iommu->stored_addr_lo | 1);
1983 }
1984
1985 static void iommu_enable_ga(struct amd_iommu *iommu)
1986 {
1987 #ifdef CONFIG_IRQ_REMAP
1988 switch (amd_iommu_guest_ir) {
1989 case AMD_IOMMU_GUEST_IR_VAPIC:
1990 iommu_feature_enable(iommu, CONTROL_GAM_EN);
1991 /* Fall through */
1992 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
1993 iommu_feature_enable(iommu, CONTROL_GA_EN);
1994 iommu->irte_ops = &irte_128_ops;
1995 break;
1996 default:
1997 iommu->irte_ops = &irte_32_ops;
1998 break;
1999 }
2000 #endif
2001 }
2002
2003 /*
2004 * This function finally enables all IOMMUs found in the system after
2005 * they have been initialized
2006 */
2007 static void early_enable_iommus(void)
2008 {
2009 struct amd_iommu *iommu;
2010
2011 for_each_iommu(iommu) {
2012 iommu_disable(iommu);
2013 iommu_init_flags(iommu);
2014 iommu_set_device_table(iommu);
2015 iommu_enable_command_buffer(iommu);
2016 iommu_enable_event_buffer(iommu);
2017 iommu_set_exclusion_range(iommu);
2018 iommu_enable_ga(iommu);
2019 iommu_enable(iommu);
2020 iommu_flush_all_caches(iommu);
2021 }
2022
2023 #ifdef CONFIG_IRQ_REMAP
2024 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2025 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2026 #endif
2027 }
2028
2029 static void enable_iommus_v2(void)
2030 {
2031 struct amd_iommu *iommu;
2032
2033 for_each_iommu(iommu) {
2034 iommu_enable_ppr_log(iommu);
2035 iommu_enable_gt(iommu);
2036 }
2037 }
2038
2039 static void enable_iommus(void)
2040 {
2041 early_enable_iommus();
2042
2043 enable_iommus_v2();
2044 }
2045
2046 static void disable_iommus(void)
2047 {
2048 struct amd_iommu *iommu;
2049
2050 for_each_iommu(iommu)
2051 iommu_disable(iommu);
2052
2053 #ifdef CONFIG_IRQ_REMAP
2054 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2055 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2056 #endif
2057 }
2058
2059 /*
2060 * Suspend/Resume support
2061 * disable suspend until real resume implemented
2062 */
2063
2064 static void amd_iommu_resume(void)
2065 {
2066 struct amd_iommu *iommu;
2067
2068 for_each_iommu(iommu)
2069 iommu_apply_resume_quirks(iommu);
2070
2071 /* re-load the hardware */
2072 enable_iommus();
2073
2074 amd_iommu_enable_interrupts();
2075 }
2076
2077 static int amd_iommu_suspend(void)
2078 {
2079 /* disable IOMMUs to go out of the way for BIOS */
2080 disable_iommus();
2081
2082 return 0;
2083 }
2084
2085 static struct syscore_ops amd_iommu_syscore_ops = {
2086 .suspend = amd_iommu_suspend,
2087 .resume = amd_iommu_resume,
2088 };
2089
2090 static void __init free_on_init_error(void)
2091 {
2092 free_pages((unsigned long)irq_lookup_table,
2093 get_order(rlookup_table_size));
2094
2095 kmem_cache_destroy(amd_iommu_irq_cache);
2096 amd_iommu_irq_cache = NULL;
2097
2098 free_pages((unsigned long)amd_iommu_rlookup_table,
2099 get_order(rlookup_table_size));
2100
2101 free_pages((unsigned long)amd_iommu_alias_table,
2102 get_order(alias_table_size));
2103
2104 free_pages((unsigned long)amd_iommu_dev_table,
2105 get_order(dev_table_size));
2106
2107 free_iommu_all();
2108
2109 #ifdef CONFIG_GART_IOMMU
2110 /*
2111 * We failed to initialize the AMD IOMMU - try fallback to GART
2112 * if possible.
2113 */
2114 gart_iommu_init();
2115
2116 #endif
2117 }
2118
2119 /* SB IOAPIC is always on this device in AMD systems */
2120 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2121
2122 static bool __init check_ioapic_information(void)
2123 {
2124 const char *fw_bug = FW_BUG;
2125 bool ret, has_sb_ioapic;
2126 int idx;
2127
2128 has_sb_ioapic = false;
2129 ret = false;
2130
2131 /*
2132 * If we have map overrides on the kernel command line the
2133 * messages in this function might not describe firmware bugs
2134 * anymore - so be careful
2135 */
2136 if (cmdline_maps)
2137 fw_bug = "";
2138
2139 for (idx = 0; idx < nr_ioapics; idx++) {
2140 int devid, id = mpc_ioapic_id(idx);
2141
2142 devid = get_ioapic_devid(id);
2143 if (devid < 0) {
2144 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2145 fw_bug, id);
2146 ret = false;
2147 } else if (devid == IOAPIC_SB_DEVID) {
2148 has_sb_ioapic = true;
2149 ret = true;
2150 }
2151 }
2152
2153 if (!has_sb_ioapic) {
2154 /*
2155 * We expect the SB IOAPIC to be listed in the IVRS
2156 * table. The system timer is connected to the SB IOAPIC
2157 * and if we don't have it in the list the system will
2158 * panic at boot time. This situation usually happens
2159 * when the BIOS is buggy and provides us the wrong
2160 * device id for the IOAPIC in the system.
2161 */
2162 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2163 }
2164
2165 if (!ret)
2166 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2167
2168 return ret;
2169 }
2170
2171 static void __init free_dma_resources(void)
2172 {
2173 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2174 get_order(MAX_DOMAIN_ID/8));
2175
2176 free_unity_maps();
2177 }
2178
2179 /*
2180 * This is the hardware init function for AMD IOMMU in the system.
2181 * This function is called either from amd_iommu_init or from the interrupt
2182 * remapping setup code.
2183 *
2184 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2185 * four times:
2186 *
2187 * 1 pass) Discover the most comprehensive IVHD type to use.
2188 *
2189 * 2 pass) Find the highest PCI device id the driver has to handle.
2190 * Upon this information the size of the data structures is
2191 * determined that needs to be allocated.
2192 *
2193 * 3 pass) Initialize the data structures just allocated with the
2194 * information in the ACPI table about available AMD IOMMUs
2195 * in the system. It also maps the PCI devices in the
2196 * system to specific IOMMUs
2197 *
2198 * 4 pass) After the basic data structures are allocated and
2199 * initialized we update them with information about memory
2200 * remapping requirements parsed out of the ACPI table in
2201 * this last pass.
2202 *
2203 * After everything is set up the IOMMUs are enabled and the necessary
2204 * hotplug and suspend notifiers are registered.
2205 */
2206 static int __init early_amd_iommu_init(void)
2207 {
2208 struct acpi_table_header *ivrs_base;
2209 acpi_size ivrs_size;
2210 acpi_status status;
2211 int i, remap_cache_sz, ret = 0;
2212
2213 if (!amd_iommu_detected)
2214 return -ENODEV;
2215
2216 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2217 if (status == AE_NOT_FOUND)
2218 return -ENODEV;
2219 else if (ACPI_FAILURE(status)) {
2220 const char *err = acpi_format_exception(status);
2221 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2222 return -EINVAL;
2223 }
2224
2225 /*
2226 * Validate checksum here so we don't need to do it when
2227 * we actually parse the table
2228 */
2229 ret = check_ivrs_checksum(ivrs_base);
2230 if (ret)
2231 return ret;
2232
2233 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2234 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2235
2236 /*
2237 * First parse ACPI tables to find the largest Bus/Dev/Func
2238 * we need to handle. Upon this information the shared data
2239 * structures for the IOMMUs in the system will be allocated
2240 */
2241 ret = find_last_devid_acpi(ivrs_base);
2242 if (ret)
2243 goto out;
2244
2245 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2246 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2247 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2248
2249 /* Device table - directly used by all IOMMUs */
2250 ret = -ENOMEM;
2251 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2252 get_order(dev_table_size));
2253 if (amd_iommu_dev_table == NULL)
2254 goto out;
2255
2256 /*
2257 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2258 * IOMMU see for that device
2259 */
2260 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2261 get_order(alias_table_size));
2262 if (amd_iommu_alias_table == NULL)
2263 goto out;
2264
2265 /* IOMMU rlookup table - find the IOMMU for a specific device */
2266 amd_iommu_rlookup_table = (void *)__get_free_pages(
2267 GFP_KERNEL | __GFP_ZERO,
2268 get_order(rlookup_table_size));
2269 if (amd_iommu_rlookup_table == NULL)
2270 goto out;
2271
2272 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2273 GFP_KERNEL | __GFP_ZERO,
2274 get_order(MAX_DOMAIN_ID/8));
2275 if (amd_iommu_pd_alloc_bitmap == NULL)
2276 goto out;
2277
2278 /*
2279 * let all alias entries point to itself
2280 */
2281 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2282 amd_iommu_alias_table[i] = i;
2283
2284 /*
2285 * never allocate domain 0 because its used as the non-allocated and
2286 * error value placeholder
2287 */
2288 amd_iommu_pd_alloc_bitmap[0] = 1;
2289
2290 spin_lock_init(&amd_iommu_pd_lock);
2291
2292 /*
2293 * now the data structures are allocated and basically initialized
2294 * start the real acpi table scan
2295 */
2296 ret = init_iommu_all(ivrs_base);
2297 if (ret)
2298 goto out;
2299
2300 if (amd_iommu_irq_remap)
2301 amd_iommu_irq_remap = check_ioapic_information();
2302
2303 if (amd_iommu_irq_remap) {
2304 /*
2305 * Interrupt remapping enabled, create kmem_cache for the
2306 * remapping tables.
2307 */
2308 ret = -ENOMEM;
2309 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2310 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2311 else
2312 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2313 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2314 remap_cache_sz,
2315 IRQ_TABLE_ALIGNMENT,
2316 0, NULL);
2317 if (!amd_iommu_irq_cache)
2318 goto out;
2319
2320 irq_lookup_table = (void *)__get_free_pages(
2321 GFP_KERNEL | __GFP_ZERO,
2322 get_order(rlookup_table_size));
2323 if (!irq_lookup_table)
2324 goto out;
2325 }
2326
2327 ret = init_memory_definitions(ivrs_base);
2328 if (ret)
2329 goto out;
2330
2331 /* init the device table */
2332 init_device_table();
2333
2334 out:
2335 /* Don't leak any ACPI memory */
2336 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2337 ivrs_base = NULL;
2338
2339 return ret;
2340 }
2341
2342 static int amd_iommu_enable_interrupts(void)
2343 {
2344 struct amd_iommu *iommu;
2345 int ret = 0;
2346
2347 for_each_iommu(iommu) {
2348 ret = iommu_init_msi(iommu);
2349 if (ret)
2350 goto out;
2351 }
2352
2353 out:
2354 return ret;
2355 }
2356
2357 static bool detect_ivrs(void)
2358 {
2359 struct acpi_table_header *ivrs_base;
2360 acpi_size ivrs_size;
2361 acpi_status status;
2362
2363 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2364 if (status == AE_NOT_FOUND)
2365 return false;
2366 else if (ACPI_FAILURE(status)) {
2367 const char *err = acpi_format_exception(status);
2368 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2369 return false;
2370 }
2371
2372 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2373
2374 /* Make sure ACS will be enabled during PCI probe */
2375 pci_request_acs();
2376
2377 return true;
2378 }
2379
2380 /****************************************************************************
2381 *
2382 * AMD IOMMU Initialization State Machine
2383 *
2384 ****************************************************************************/
2385
2386 static int __init state_next(void)
2387 {
2388 int ret = 0;
2389
2390 switch (init_state) {
2391 case IOMMU_START_STATE:
2392 if (!detect_ivrs()) {
2393 init_state = IOMMU_NOT_FOUND;
2394 ret = -ENODEV;
2395 } else {
2396 init_state = IOMMU_IVRS_DETECTED;
2397 }
2398 break;
2399 case IOMMU_IVRS_DETECTED:
2400 ret = early_amd_iommu_init();
2401 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2402 break;
2403 case IOMMU_ACPI_FINISHED:
2404 early_enable_iommus();
2405 register_syscore_ops(&amd_iommu_syscore_ops);
2406 x86_platform.iommu_shutdown = disable_iommus;
2407 init_state = IOMMU_ENABLED;
2408 break;
2409 case IOMMU_ENABLED:
2410 ret = amd_iommu_init_pci();
2411 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2412 enable_iommus_v2();
2413 break;
2414 case IOMMU_PCI_INIT:
2415 ret = amd_iommu_enable_interrupts();
2416 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2417 break;
2418 case IOMMU_INTERRUPTS_EN:
2419 ret = amd_iommu_init_dma_ops();
2420 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2421 break;
2422 case IOMMU_DMA_OPS:
2423 init_state = IOMMU_INITIALIZED;
2424 break;
2425 case IOMMU_INITIALIZED:
2426 /* Nothing to do */
2427 break;
2428 case IOMMU_NOT_FOUND:
2429 case IOMMU_INIT_ERROR:
2430 /* Error states => do nothing */
2431 ret = -EINVAL;
2432 break;
2433 default:
2434 /* Unknown state */
2435 BUG();
2436 }
2437
2438 return ret;
2439 }
2440
2441 static int __init iommu_go_to_state(enum iommu_init_state state)
2442 {
2443 int ret = 0;
2444
2445 while (init_state != state) {
2446 ret = state_next();
2447 if (init_state == IOMMU_NOT_FOUND ||
2448 init_state == IOMMU_INIT_ERROR)
2449 break;
2450 }
2451
2452 return ret;
2453 }
2454
2455 #ifdef CONFIG_IRQ_REMAP
2456 int __init amd_iommu_prepare(void)
2457 {
2458 int ret;
2459
2460 amd_iommu_irq_remap = true;
2461
2462 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2463 if (ret)
2464 return ret;
2465 return amd_iommu_irq_remap ? 0 : -ENODEV;
2466 }
2467
2468 int __init amd_iommu_enable(void)
2469 {
2470 int ret;
2471
2472 ret = iommu_go_to_state(IOMMU_ENABLED);
2473 if (ret)
2474 return ret;
2475
2476 irq_remapping_enabled = 1;
2477
2478 return 0;
2479 }
2480
2481 void amd_iommu_disable(void)
2482 {
2483 amd_iommu_suspend();
2484 }
2485
2486 int amd_iommu_reenable(int mode)
2487 {
2488 amd_iommu_resume();
2489
2490 return 0;
2491 }
2492
2493 int __init amd_iommu_enable_faulting(void)
2494 {
2495 /* We enable MSI later when PCI is initialized */
2496 return 0;
2497 }
2498 #endif
2499
2500 /*
2501 * This is the core init function for AMD IOMMU hardware in the system.
2502 * This function is called from the generic x86 DMA layer initialization
2503 * code.
2504 */
2505 static int __init amd_iommu_init(void)
2506 {
2507 int ret;
2508
2509 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2510 if (ret) {
2511 free_dma_resources();
2512 if (!irq_remapping_enabled) {
2513 disable_iommus();
2514 free_on_init_error();
2515 } else {
2516 struct amd_iommu *iommu;
2517
2518 uninit_device_table_dma();
2519 for_each_iommu(iommu)
2520 iommu_flush_all_caches(iommu);
2521 }
2522 }
2523
2524 return ret;
2525 }
2526
2527 /****************************************************************************
2528 *
2529 * Early detect code. This code runs at IOMMU detection time in the DMA
2530 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2531 * IOMMUs
2532 *
2533 ****************************************************************************/
2534 int __init amd_iommu_detect(void)
2535 {
2536 int ret;
2537
2538 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2539 return -ENODEV;
2540
2541 if (amd_iommu_disabled)
2542 return -ENODEV;
2543
2544 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2545 if (ret)
2546 return ret;
2547
2548 amd_iommu_detected = true;
2549 iommu_detected = 1;
2550 x86_init.iommu.iommu_init = amd_iommu_init;
2551
2552 return 1;
2553 }
2554
2555 /****************************************************************************
2556 *
2557 * Parsing functions for the AMD IOMMU specific kernel command line
2558 * options.
2559 *
2560 ****************************************************************************/
2561
2562 static int __init parse_amd_iommu_dump(char *str)
2563 {
2564 amd_iommu_dump = true;
2565
2566 return 1;
2567 }
2568
2569 static int __init parse_amd_iommu_intr(char *str)
2570 {
2571 for (; *str; ++str) {
2572 if (strncmp(str, "legacy", 6) == 0) {
2573 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2574 break;
2575 }
2576 if (strncmp(str, "vapic", 5) == 0) {
2577 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2578 break;
2579 }
2580 }
2581 return 1;
2582 }
2583
2584 static int __init parse_amd_iommu_options(char *str)
2585 {
2586 for (; *str; ++str) {
2587 if (strncmp(str, "fullflush", 9) == 0)
2588 amd_iommu_unmap_flush = true;
2589 if (strncmp(str, "off", 3) == 0)
2590 amd_iommu_disabled = true;
2591 if (strncmp(str, "force_isolation", 15) == 0)
2592 amd_iommu_force_isolation = true;
2593 }
2594
2595 return 1;
2596 }
2597
2598 static int __init parse_ivrs_ioapic(char *str)
2599 {
2600 unsigned int bus, dev, fn;
2601 int ret, id, i;
2602 u16 devid;
2603
2604 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2605
2606 if (ret != 4) {
2607 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2608 return 1;
2609 }
2610
2611 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2612 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2613 str);
2614 return 1;
2615 }
2616
2617 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2618
2619 cmdline_maps = true;
2620 i = early_ioapic_map_size++;
2621 early_ioapic_map[i].id = id;
2622 early_ioapic_map[i].devid = devid;
2623 early_ioapic_map[i].cmd_line = true;
2624
2625 return 1;
2626 }
2627
2628 static int __init parse_ivrs_hpet(char *str)
2629 {
2630 unsigned int bus, dev, fn;
2631 int ret, id, i;
2632 u16 devid;
2633
2634 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2635
2636 if (ret != 4) {
2637 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2638 return 1;
2639 }
2640
2641 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2642 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2643 str);
2644 return 1;
2645 }
2646
2647 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2648
2649 cmdline_maps = true;
2650 i = early_hpet_map_size++;
2651 early_hpet_map[i].id = id;
2652 early_hpet_map[i].devid = devid;
2653 early_hpet_map[i].cmd_line = true;
2654
2655 return 1;
2656 }
2657
2658 static int __init parse_ivrs_acpihid(char *str)
2659 {
2660 u32 bus, dev, fn;
2661 char *hid, *uid, *p;
2662 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2663 int ret, i;
2664
2665 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2666 if (ret != 4) {
2667 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2668 return 1;
2669 }
2670
2671 p = acpiid;
2672 hid = strsep(&p, ":");
2673 uid = p;
2674
2675 if (!hid || !(*hid) || !uid) {
2676 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2677 return 1;
2678 }
2679
2680 i = early_acpihid_map_size++;
2681 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2682 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2683 early_acpihid_map[i].devid =
2684 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2685 early_acpihid_map[i].cmd_line = true;
2686
2687 return 1;
2688 }
2689
2690 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2691 __setup("amd_iommu=", parse_amd_iommu_options);
2692 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2693 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2694 __setup("ivrs_hpet", parse_ivrs_hpet);
2695 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2696
2697 IOMMU_INIT_FINISH(amd_iommu_detect,
2698 gart_iommu_hole_init,
2699 NULL,
2700 NULL);
2701
2702 bool amd_iommu_v2_supported(void)
2703 {
2704 return amd_iommu_v2_present;
2705 }
2706 EXPORT_SYMBOL(amd_iommu_v2_supported);
2707
2708 /****************************************************************************
2709 *
2710 * IOMMU EFR Performance Counter support functionality. This code allows
2711 * access to the IOMMU PC functionality.
2712 *
2713 ****************************************************************************/
2714
2715 u8 amd_iommu_pc_get_max_banks(u16 devid)
2716 {
2717 struct amd_iommu *iommu;
2718 u8 ret = 0;
2719
2720 /* locate the iommu governing the devid */
2721 iommu = amd_iommu_rlookup_table[devid];
2722 if (iommu)
2723 ret = iommu->max_banks;
2724
2725 return ret;
2726 }
2727 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2728
2729 bool amd_iommu_pc_supported(void)
2730 {
2731 return amd_iommu_pc_present;
2732 }
2733 EXPORT_SYMBOL(amd_iommu_pc_supported);
2734
2735 u8 amd_iommu_pc_get_max_counters(u16 devid)
2736 {
2737 struct amd_iommu *iommu;
2738 u8 ret = 0;
2739
2740 /* locate the iommu governing the devid */
2741 iommu = amd_iommu_rlookup_table[devid];
2742 if (iommu)
2743 ret = iommu->max_counters;
2744
2745 return ret;
2746 }
2747 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2748
2749 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2750 u8 bank, u8 cntr, u8 fxn,
2751 u64 *value, bool is_write)
2752 {
2753 u32 offset;
2754 u32 max_offset_lim;
2755
2756 /* Check for valid iommu and pc register indexing */
2757 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
2758 return -ENODEV;
2759
2760 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2761
2762 /* Limit the offset to the hw defined mmio region aperture */
2763 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2764 (iommu->max_counters << 8) | 0x28);
2765 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2766 (offset > max_offset_lim))
2767 return -EINVAL;
2768
2769 if (is_write) {
2770 writel((u32)*value, iommu->mmio_base + offset);
2771 writel((*value >> 32), iommu->mmio_base + offset + 4);
2772 } else {
2773 *value = readl(iommu->mmio_base + offset + 4);
2774 *value <<= 32;
2775 *value = readl(iommu->mmio_base + offset);
2776 }
2777
2778 return 0;
2779 }
2780 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
2781
2782 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2783 u64 *value, bool is_write)
2784 {
2785 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2786
2787 /* Make sure the IOMMU PC resource is available */
2788 if (!amd_iommu_pc_present || iommu == NULL)
2789 return -ENODEV;
2790
2791 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
2792 value, is_write);
2793 }
Linux kernel - Deliverables
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