2 * IOMMU API for ARM architected SMMU implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * Copyright (C) 2013 ARM Limited
19 * Author: Will Deacon <will.deacon@arm.com>
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - Context fault reporting
29 #define pr_fmt(fmt) "arm-smmu: " fmt
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
36 #include <linux/iommu.h>
37 #include <linux/iopoll.h>
38 #include <linux/module.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
45 #include <linux/amba/bus.h>
47 #include "io-pgtable.h"
49 /* Maximum number of stream IDs assigned to a single device */
50 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
52 /* Maximum number of context banks per SMMU */
53 #define ARM_SMMU_MAX_CBS 128
55 /* Maximum number of mapping groups per SMMU */
56 #define ARM_SMMU_MAX_SMRS 128
58 /* SMMU global address space */
59 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
60 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
63 * SMMU global address space with conditional offset to access secure
64 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
67 #define ARM_SMMU_GR0_NS(smmu) \
69 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
72 /* Configuration registers */
73 #define ARM_SMMU_GR0_sCR0 0x0
74 #define sCR0_CLIENTPD (1 << 0)
75 #define sCR0_GFRE (1 << 1)
76 #define sCR0_GFIE (1 << 2)
77 #define sCR0_GCFGFRE (1 << 4)
78 #define sCR0_GCFGFIE (1 << 5)
79 #define sCR0_USFCFG (1 << 10)
80 #define sCR0_VMIDPNE (1 << 11)
81 #define sCR0_PTM (1 << 12)
82 #define sCR0_FB (1 << 13)
83 #define sCR0_BSU_SHIFT 14
84 #define sCR0_BSU_MASK 0x3
86 /* Identification registers */
87 #define ARM_SMMU_GR0_ID0 0x20
88 #define ARM_SMMU_GR0_ID1 0x24
89 #define ARM_SMMU_GR0_ID2 0x28
90 #define ARM_SMMU_GR0_ID3 0x2c
91 #define ARM_SMMU_GR0_ID4 0x30
92 #define ARM_SMMU_GR0_ID5 0x34
93 #define ARM_SMMU_GR0_ID6 0x38
94 #define ARM_SMMU_GR0_ID7 0x3c
95 #define ARM_SMMU_GR0_sGFSR 0x48
96 #define ARM_SMMU_GR0_sGFSYNR0 0x50
97 #define ARM_SMMU_GR0_sGFSYNR1 0x54
98 #define ARM_SMMU_GR0_sGFSYNR2 0x58
100 #define ID0_S1TS (1 << 30)
101 #define ID0_S2TS (1 << 29)
102 #define ID0_NTS (1 << 28)
103 #define ID0_SMS (1 << 27)
104 #define ID0_ATOSNS (1 << 26)
105 #define ID0_CTTW (1 << 14)
106 #define ID0_NUMIRPT_SHIFT 16
107 #define ID0_NUMIRPT_MASK 0xff
108 #define ID0_NUMSIDB_SHIFT 9
109 #define ID0_NUMSIDB_MASK 0xf
110 #define ID0_NUMSMRG_SHIFT 0
111 #define ID0_NUMSMRG_MASK 0xff
113 #define ID1_PAGESIZE (1 << 31)
114 #define ID1_NUMPAGENDXB_SHIFT 28
115 #define ID1_NUMPAGENDXB_MASK 7
116 #define ID1_NUMS2CB_SHIFT 16
117 #define ID1_NUMS2CB_MASK 0xff
118 #define ID1_NUMCB_SHIFT 0
119 #define ID1_NUMCB_MASK 0xff
121 #define ID2_OAS_SHIFT 4
122 #define ID2_OAS_MASK 0xf
123 #define ID2_IAS_SHIFT 0
124 #define ID2_IAS_MASK 0xf
125 #define ID2_UBS_SHIFT 8
126 #define ID2_UBS_MASK 0xf
127 #define ID2_PTFS_4K (1 << 12)
128 #define ID2_PTFS_16K (1 << 13)
129 #define ID2_PTFS_64K (1 << 14)
131 /* Global TLB invalidation */
132 #define ARM_SMMU_GR0_TLBIVMID 0x64
133 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
134 #define ARM_SMMU_GR0_TLBIALLH 0x6c
135 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
136 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
137 #define sTLBGSTATUS_GSACTIVE (1 << 0)
138 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
140 /* Stream mapping registers */
141 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
142 #define SMR_VALID (1 << 31)
143 #define SMR_MASK_SHIFT 16
144 #define SMR_MASK_MASK 0x7fff
145 #define SMR_ID_SHIFT 0
146 #define SMR_ID_MASK 0x7fff
148 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
149 #define S2CR_CBNDX_SHIFT 0
150 #define S2CR_CBNDX_MASK 0xff
151 #define S2CR_TYPE_SHIFT 16
152 #define S2CR_TYPE_MASK 0x3
153 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
154 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
155 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
157 /* Context bank attribute registers */
158 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
159 #define CBAR_VMID_SHIFT 0
160 #define CBAR_VMID_MASK 0xff
161 #define CBAR_S1_BPSHCFG_SHIFT 8
162 #define CBAR_S1_BPSHCFG_MASK 3
163 #define CBAR_S1_BPSHCFG_NSH 3
164 #define CBAR_S1_MEMATTR_SHIFT 12
165 #define CBAR_S1_MEMATTR_MASK 0xf
166 #define CBAR_S1_MEMATTR_WB 0xf
167 #define CBAR_TYPE_SHIFT 16
168 #define CBAR_TYPE_MASK 0x3
169 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
170 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
171 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
172 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
173 #define CBAR_IRPTNDX_SHIFT 24
174 #define CBAR_IRPTNDX_MASK 0xff
176 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
177 #define CBA2R_RW64_32BIT (0 << 0)
178 #define CBA2R_RW64_64BIT (1 << 0)
180 /* Translation context bank */
181 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
182 #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
184 #define ARM_SMMU_CB_SCTLR 0x0
185 #define ARM_SMMU_CB_RESUME 0x8
186 #define ARM_SMMU_CB_TTBCR2 0x10
187 #define ARM_SMMU_CB_TTBR0_LO 0x20
188 #define ARM_SMMU_CB_TTBR0_HI 0x24
189 #define ARM_SMMU_CB_TTBR1_LO 0x28
190 #define ARM_SMMU_CB_TTBR1_HI 0x2c
191 #define ARM_SMMU_CB_TTBCR 0x30
192 #define ARM_SMMU_CB_S1_MAIR0 0x38
193 #define ARM_SMMU_CB_S1_MAIR1 0x3c
194 #define ARM_SMMU_CB_PAR_LO 0x50
195 #define ARM_SMMU_CB_PAR_HI 0x54
196 #define ARM_SMMU_CB_FSR 0x58
197 #define ARM_SMMU_CB_FAR_LO 0x60
198 #define ARM_SMMU_CB_FAR_HI 0x64
199 #define ARM_SMMU_CB_FSYNR0 0x68
200 #define ARM_SMMU_CB_S1_TLBIVA 0x600
201 #define ARM_SMMU_CB_S1_TLBIASID 0x610
202 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
203 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
204 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
205 #define ARM_SMMU_CB_ATS1PR_LO 0x800
206 #define ARM_SMMU_CB_ATS1PR_HI 0x804
207 #define ARM_SMMU_CB_ATSR 0x8f0
209 #define SCTLR_S1_ASIDPNE (1 << 12)
210 #define SCTLR_CFCFG (1 << 7)
211 #define SCTLR_CFIE (1 << 6)
212 #define SCTLR_CFRE (1 << 5)
213 #define SCTLR_E (1 << 4)
214 #define SCTLR_AFE (1 << 2)
215 #define SCTLR_TRE (1 << 1)
216 #define SCTLR_M (1 << 0)
217 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
219 #define CB_PAR_F (1 << 0)
221 #define ATSR_ACTIVE (1 << 0)
223 #define RESUME_RETRY (0 << 0)
224 #define RESUME_TERMINATE (1 << 0)
226 #define TTBCR2_SEP_SHIFT 15
227 #define TTBCR2_SEP_MASK 0x7
229 #define TTBCR2_ADDR_32 0
230 #define TTBCR2_ADDR_36 1
231 #define TTBCR2_ADDR_40 2
232 #define TTBCR2_ADDR_42 3
233 #define TTBCR2_ADDR_44 4
234 #define TTBCR2_ADDR_48 5
236 #define TTBRn_HI_ASID_SHIFT 16
238 #define FSR_MULTI (1 << 31)
239 #define FSR_SS (1 << 30)
240 #define FSR_UUT (1 << 8)
241 #define FSR_ASF (1 << 7)
242 #define FSR_TLBLKF (1 << 6)
243 #define FSR_TLBMCF (1 << 5)
244 #define FSR_EF (1 << 4)
245 #define FSR_PF (1 << 3)
246 #define FSR_AFF (1 << 2)
247 #define FSR_TF (1 << 1)
249 #define FSR_IGN (FSR_AFF | FSR_ASF | \
250 FSR_TLBMCF | FSR_TLBLKF)
251 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
252 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
254 #define FSYNR0_WNR (1 << 4)
256 static int force_stage
;
257 module_param_named(force_stage
, force_stage
, int, S_IRUGO
| S_IWUSR
);
258 MODULE_PARM_DESC(force_stage
,
259 "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
261 enum arm_smmu_arch_version
{
266 struct arm_smmu_smr
{
272 struct arm_smmu_master_cfg
{
274 u16 streamids
[MAX_MASTER_STREAMIDS
];
275 struct arm_smmu_smr
*smrs
;
278 struct arm_smmu_master
{
279 struct device_node
*of_node
;
281 struct arm_smmu_master_cfg cfg
;
284 struct arm_smmu_device
{
289 unsigned long pgshift
;
291 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
292 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
293 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
294 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
295 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
296 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
299 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
301 enum arm_smmu_arch_version version
;
303 u32 num_context_banks
;
304 u32 num_s2_context_banks
;
305 DECLARE_BITMAP(context_map
, ARM_SMMU_MAX_CBS
);
308 u32 num_mapping_groups
;
309 DECLARE_BITMAP(smr_map
, ARM_SMMU_MAX_SMRS
);
311 unsigned long va_size
;
312 unsigned long ipa_size
;
313 unsigned long pa_size
;
316 u32 num_context_irqs
;
319 struct list_head list
;
320 struct rb_root masters
;
323 struct arm_smmu_cfg
{
328 #define INVALID_IRPTNDX 0xff
330 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
331 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
333 enum arm_smmu_domain_stage
{
334 ARM_SMMU_DOMAIN_S1
= 0,
336 ARM_SMMU_DOMAIN_NESTED
,
339 struct arm_smmu_domain
{
340 struct arm_smmu_device
*smmu
;
341 struct io_pgtable_ops
*pgtbl_ops
;
342 spinlock_t pgtbl_lock
;
343 struct arm_smmu_cfg cfg
;
344 enum arm_smmu_domain_stage stage
;
345 struct mutex init_mutex
; /* Protects smmu pointer */
348 static struct iommu_ops arm_smmu_ops
;
350 static DEFINE_SPINLOCK(arm_smmu_devices_lock
);
351 static LIST_HEAD(arm_smmu_devices
);
353 struct arm_smmu_option_prop
{
358 static struct arm_smmu_option_prop arm_smmu_options
[] = {
359 { ARM_SMMU_OPT_SECURE_CFG_ACCESS
, "calxeda,smmu-secure-config-access" },
363 static void parse_driver_options(struct arm_smmu_device
*smmu
)
368 if (of_property_read_bool(smmu
->dev
->of_node
,
369 arm_smmu_options
[i
].prop
)) {
370 smmu
->options
|= arm_smmu_options
[i
].opt
;
371 dev_notice(smmu
->dev
, "option %s\n",
372 arm_smmu_options
[i
].prop
);
374 } while (arm_smmu_options
[++i
].opt
);
377 static struct device_node
*dev_get_dev_node(struct device
*dev
)
379 if (dev_is_pci(dev
)) {
380 struct pci_bus
*bus
= to_pci_dev(dev
)->bus
;
382 while (!pci_is_root_bus(bus
))
384 return bus
->bridge
->parent
->of_node
;
390 static struct arm_smmu_master
*find_smmu_master(struct arm_smmu_device
*smmu
,
391 struct device_node
*dev_node
)
393 struct rb_node
*node
= smmu
->masters
.rb_node
;
396 struct arm_smmu_master
*master
;
398 master
= container_of(node
, struct arm_smmu_master
, node
);
400 if (dev_node
< master
->of_node
)
401 node
= node
->rb_left
;
402 else if (dev_node
> master
->of_node
)
403 node
= node
->rb_right
;
411 static struct arm_smmu_master_cfg
*
412 find_smmu_master_cfg(struct device
*dev
)
414 struct arm_smmu_master_cfg
*cfg
= NULL
;
415 struct iommu_group
*group
= iommu_group_get(dev
);
418 cfg
= iommu_group_get_iommudata(group
);
419 iommu_group_put(group
);
425 static int insert_smmu_master(struct arm_smmu_device
*smmu
,
426 struct arm_smmu_master
*master
)
428 struct rb_node
**new, *parent
;
430 new = &smmu
->masters
.rb_node
;
433 struct arm_smmu_master
*this
434 = container_of(*new, struct arm_smmu_master
, node
);
437 if (master
->of_node
< this->of_node
)
438 new = &((*new)->rb_left
);
439 else if (master
->of_node
> this->of_node
)
440 new = &((*new)->rb_right
);
445 rb_link_node(&master
->node
, parent
, new);
446 rb_insert_color(&master
->node
, &smmu
->masters
);
450 static int register_smmu_master(struct arm_smmu_device
*smmu
,
452 struct of_phandle_args
*masterspec
)
455 struct arm_smmu_master
*master
;
457 master
= find_smmu_master(smmu
, masterspec
->np
);
460 "rejecting multiple registrations for master device %s\n",
461 masterspec
->np
->name
);
465 if (masterspec
->args_count
> MAX_MASTER_STREAMIDS
) {
467 "reached maximum number (%d) of stream IDs for master device %s\n",
468 MAX_MASTER_STREAMIDS
, masterspec
->np
->name
);
472 master
= devm_kzalloc(dev
, sizeof(*master
), GFP_KERNEL
);
476 master
->of_node
= masterspec
->np
;
477 master
->cfg
.num_streamids
= masterspec
->args_count
;
479 for (i
= 0; i
< master
->cfg
.num_streamids
; ++i
) {
480 u16 streamid
= masterspec
->args
[i
];
482 if (!(smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
) &&
483 (streamid
>= smmu
->num_mapping_groups
)) {
485 "stream ID for master device %s greater than maximum allowed (%d)\n",
486 masterspec
->np
->name
, smmu
->num_mapping_groups
);
489 master
->cfg
.streamids
[i
] = streamid
;
491 return insert_smmu_master(smmu
, master
);
494 static struct arm_smmu_device
*find_smmu_for_device(struct device
*dev
)
496 struct arm_smmu_device
*smmu
;
497 struct arm_smmu_master
*master
= NULL
;
498 struct device_node
*dev_node
= dev_get_dev_node(dev
);
500 spin_lock(&arm_smmu_devices_lock
);
501 list_for_each_entry(smmu
, &arm_smmu_devices
, list
) {
502 master
= find_smmu_master(smmu
, dev_node
);
506 spin_unlock(&arm_smmu_devices_lock
);
508 return master
? smmu
: NULL
;
511 static int __arm_smmu_alloc_bitmap(unsigned long *map
, int start
, int end
)
516 idx
= find_next_zero_bit(map
, end
, start
);
519 } while (test_and_set_bit(idx
, map
));
524 static void __arm_smmu_free_bitmap(unsigned long *map
, int idx
)
529 /* Wait for any pending TLB invalidations to complete */
530 static void __arm_smmu_tlb_sync(struct arm_smmu_device
*smmu
)
533 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
535 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_sTLBGSYNC
);
536 while (readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sTLBGSTATUS
)
537 & sTLBGSTATUS_GSACTIVE
) {
539 if (++count
== TLB_LOOP_TIMEOUT
) {
540 dev_err_ratelimited(smmu
->dev
,
541 "TLB sync timed out -- SMMU may be deadlocked\n");
548 static void arm_smmu_tlb_sync(void *cookie
)
550 struct arm_smmu_domain
*smmu_domain
= cookie
;
551 __arm_smmu_tlb_sync(smmu_domain
->smmu
);
554 static void arm_smmu_tlb_inv_context(void *cookie
)
556 struct arm_smmu_domain
*smmu_domain
= cookie
;
557 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
558 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
559 bool stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
563 base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
564 writel_relaxed(ARM_SMMU_CB_ASID(cfg
),
565 base
+ ARM_SMMU_CB_S1_TLBIASID
);
567 base
= ARM_SMMU_GR0(smmu
);
568 writel_relaxed(ARM_SMMU_CB_VMID(cfg
),
569 base
+ ARM_SMMU_GR0_TLBIVMID
);
572 __arm_smmu_tlb_sync(smmu
);
575 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova
, size_t size
,
576 bool leaf
, void *cookie
)
578 struct arm_smmu_domain
*smmu_domain
= cookie
;
579 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
580 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
581 bool stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
585 reg
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
586 reg
+= leaf
? ARM_SMMU_CB_S1_TLBIVAL
: ARM_SMMU_CB_S1_TLBIVA
;
588 if (!IS_ENABLED(CONFIG_64BIT
) || smmu
->version
== ARM_SMMU_V1
) {
590 iova
|= ARM_SMMU_CB_ASID(cfg
);
591 writel_relaxed(iova
, reg
);
595 iova
|= (u64
)ARM_SMMU_CB_ASID(cfg
) << 48;
596 writeq_relaxed(iova
, reg
);
600 } else if (smmu
->version
== ARM_SMMU_V2
) {
601 reg
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
602 reg
+= leaf
? ARM_SMMU_CB_S2_TLBIIPAS2L
:
603 ARM_SMMU_CB_S2_TLBIIPAS2
;
604 writeq_relaxed(iova
>> 12, reg
);
607 reg
= ARM_SMMU_GR0(smmu
) + ARM_SMMU_GR0_TLBIVMID
;
608 writel_relaxed(ARM_SMMU_CB_VMID(cfg
), reg
);
612 static void arm_smmu_flush_pgtable(void *addr
, size_t size
, void *cookie
)
614 struct arm_smmu_domain
*smmu_domain
= cookie
;
615 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
616 unsigned long offset
= (unsigned long)addr
& ~PAGE_MASK
;
619 /* Ensure new page tables are visible to the hardware walker */
620 if (smmu
->features
& ARM_SMMU_FEAT_COHERENT_WALK
) {
624 * If the SMMU can't walk tables in the CPU caches, treat them
625 * like non-coherent DMA since we need to flush the new entries
626 * all the way out to memory. There's no possibility of
627 * recursion here as the SMMU table walker will not be wired
628 * through another SMMU.
630 dma_map_page(smmu
->dev
, virt_to_page(addr
), offset
, size
,
635 static struct iommu_gather_ops arm_smmu_gather_ops
= {
636 .tlb_flush_all
= arm_smmu_tlb_inv_context
,
637 .tlb_add_flush
= arm_smmu_tlb_inv_range_nosync
,
638 .tlb_sync
= arm_smmu_tlb_sync
,
639 .flush_pgtable
= arm_smmu_flush_pgtable
,
642 static irqreturn_t
arm_smmu_context_fault(int irq
, void *dev
)
645 u32 fsr
, far
, fsynr
, resume
;
647 struct iommu_domain
*domain
= dev
;
648 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
649 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
650 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
651 void __iomem
*cb_base
;
653 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
654 fsr
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FSR
);
656 if (!(fsr
& FSR_FAULT
))
660 dev_err_ratelimited(smmu
->dev
,
661 "Unexpected context fault (fsr 0x%x)\n",
664 fsynr
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FSYNR0
);
665 flags
= fsynr
& FSYNR0_WNR
? IOMMU_FAULT_WRITE
: IOMMU_FAULT_READ
;
667 far
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FAR_LO
);
670 far
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FAR_HI
);
671 iova
|= ((unsigned long)far
<< 32);
674 if (!report_iommu_fault(domain
, smmu
->dev
, iova
, flags
)) {
676 resume
= RESUME_RETRY
;
678 dev_err_ratelimited(smmu
->dev
,
679 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
680 iova
, fsynr
, cfg
->cbndx
);
682 resume
= RESUME_TERMINATE
;
685 /* Clear the faulting FSR */
686 writel(fsr
, cb_base
+ ARM_SMMU_CB_FSR
);
688 /* Retry or terminate any stalled transactions */
690 writel_relaxed(resume
, cb_base
+ ARM_SMMU_CB_RESUME
);
695 static irqreturn_t
arm_smmu_global_fault(int irq
, void *dev
)
697 u32 gfsr
, gfsynr0
, gfsynr1
, gfsynr2
;
698 struct arm_smmu_device
*smmu
= dev
;
699 void __iomem
*gr0_base
= ARM_SMMU_GR0_NS(smmu
);
701 gfsr
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSR
);
702 gfsynr0
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR0
);
703 gfsynr1
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR1
);
704 gfsynr2
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR2
);
709 dev_err_ratelimited(smmu
->dev
,
710 "Unexpected global fault, this could be serious\n");
711 dev_err_ratelimited(smmu
->dev
,
712 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
713 gfsr
, gfsynr0
, gfsynr1
, gfsynr2
);
715 writel(gfsr
, gr0_base
+ ARM_SMMU_GR0_sGFSR
);
719 static void arm_smmu_init_context_bank(struct arm_smmu_domain
*smmu_domain
,
720 struct io_pgtable_cfg
*pgtbl_cfg
)
724 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
725 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
726 void __iomem
*cb_base
, *gr0_base
, *gr1_base
;
728 gr0_base
= ARM_SMMU_GR0(smmu
);
729 gr1_base
= ARM_SMMU_GR1(smmu
);
730 stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
731 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
733 if (smmu
->version
> ARM_SMMU_V1
) {
736 * *Must* be initialised before CBAR thanks to VMID16
737 * architectural oversight affected some implementations.
740 reg
= CBA2R_RW64_64BIT
;
742 reg
= CBA2R_RW64_32BIT
;
744 writel_relaxed(reg
, gr1_base
+ ARM_SMMU_GR1_CBA2R(cfg
->cbndx
));
749 if (smmu
->version
== ARM_SMMU_V1
)
750 reg
|= cfg
->irptndx
<< CBAR_IRPTNDX_SHIFT
;
753 * Use the weakest shareability/memory types, so they are
754 * overridden by the ttbcr/pte.
757 reg
|= (CBAR_S1_BPSHCFG_NSH
<< CBAR_S1_BPSHCFG_SHIFT
) |
758 (CBAR_S1_MEMATTR_WB
<< CBAR_S1_MEMATTR_SHIFT
);
760 reg
|= ARM_SMMU_CB_VMID(cfg
) << CBAR_VMID_SHIFT
;
762 writel_relaxed(reg
, gr1_base
+ ARM_SMMU_GR1_CBAR(cfg
->cbndx
));
766 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[0];
767 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_LO
);
768 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[0] >> 32;
769 reg
|= ARM_SMMU_CB_ASID(cfg
) << TTBRn_HI_ASID_SHIFT
;
770 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_HI
);
772 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[1];
773 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR1_LO
);
774 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[1] >> 32;
775 reg
|= ARM_SMMU_CB_ASID(cfg
) << TTBRn_HI_ASID_SHIFT
;
776 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR1_HI
);
778 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vttbr
;
779 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_LO
);
780 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vttbr
>> 32;
781 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBR0_HI
);
786 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.tcr
;
787 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR
);
788 if (smmu
->version
> ARM_SMMU_V1
) {
789 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.tcr
>> 32;
790 switch (smmu
->va_size
) {
792 reg
|= (TTBCR2_ADDR_32
<< TTBCR2_SEP_SHIFT
);
795 reg
|= (TTBCR2_ADDR_36
<< TTBCR2_SEP_SHIFT
);
798 reg
|= (TTBCR2_ADDR_40
<< TTBCR2_SEP_SHIFT
);
801 reg
|= (TTBCR2_ADDR_42
<< TTBCR2_SEP_SHIFT
);
804 reg
|= (TTBCR2_ADDR_44
<< TTBCR2_SEP_SHIFT
);
807 reg
|= (TTBCR2_ADDR_48
<< TTBCR2_SEP_SHIFT
);
810 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR2
);
813 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vtcr
;
814 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR
);
817 /* MAIRs (stage-1 only) */
819 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.mair
[0];
820 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_S1_MAIR0
);
821 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.mair
[1];
822 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_S1_MAIR1
);
826 reg
= SCTLR_CFCFG
| SCTLR_CFIE
| SCTLR_CFRE
| SCTLR_M
| SCTLR_EAE_SBOP
;
828 reg
|= SCTLR_S1_ASIDPNE
;
832 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_SCTLR
);
835 static int arm_smmu_init_domain_context(struct iommu_domain
*domain
,
836 struct arm_smmu_device
*smmu
)
838 int irq
, start
, ret
= 0;
839 unsigned long ias
, oas
;
840 struct io_pgtable_ops
*pgtbl_ops
;
841 struct io_pgtable_cfg pgtbl_cfg
;
842 enum io_pgtable_fmt fmt
;
843 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
844 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
846 mutex_lock(&smmu_domain
->init_mutex
);
847 if (smmu_domain
->smmu
)
851 * Mapping the requested stage onto what we support is surprisingly
852 * complicated, mainly because the spec allows S1+S2 SMMUs without
853 * support for nested translation. That means we end up with the
856 * Requested Supported Actual
866 * Note that you can't actually request stage-2 mappings.
868 if (!(smmu
->features
& ARM_SMMU_FEAT_TRANS_S1
))
869 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S2
;
870 if (!(smmu
->features
& ARM_SMMU_FEAT_TRANS_S2
))
871 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S1
;
873 switch (smmu_domain
->stage
) {
874 case ARM_SMMU_DOMAIN_S1
:
875 cfg
->cbar
= CBAR_TYPE_S1_TRANS_S2_BYPASS
;
876 start
= smmu
->num_s2_context_banks
;
878 oas
= smmu
->ipa_size
;
879 if (IS_ENABLED(CONFIG_64BIT
))
880 fmt
= ARM_64_LPAE_S1
;
882 fmt
= ARM_32_LPAE_S1
;
884 case ARM_SMMU_DOMAIN_NESTED
:
886 * We will likely want to change this if/when KVM gets
889 case ARM_SMMU_DOMAIN_S2
:
890 cfg
->cbar
= CBAR_TYPE_S2_TRANS
;
892 ias
= smmu
->ipa_size
;
894 if (IS_ENABLED(CONFIG_64BIT
))
895 fmt
= ARM_64_LPAE_S2
;
897 fmt
= ARM_32_LPAE_S2
;
904 ret
= __arm_smmu_alloc_bitmap(smmu
->context_map
, start
,
905 smmu
->num_context_banks
);
906 if (IS_ERR_VALUE(ret
))
910 if (smmu
->version
== ARM_SMMU_V1
) {
911 cfg
->irptndx
= atomic_inc_return(&smmu
->irptndx
);
912 cfg
->irptndx
%= smmu
->num_context_irqs
;
914 cfg
->irptndx
= cfg
->cbndx
;
917 pgtbl_cfg
= (struct io_pgtable_cfg
) {
918 .pgsize_bitmap
= arm_smmu_ops
.pgsize_bitmap
,
921 .tlb
= &arm_smmu_gather_ops
,
924 smmu_domain
->smmu
= smmu
;
925 pgtbl_ops
= alloc_io_pgtable_ops(fmt
, &pgtbl_cfg
, smmu_domain
);
931 /* Update our support page sizes to reflect the page table format */
932 arm_smmu_ops
.pgsize_bitmap
= pgtbl_cfg
.pgsize_bitmap
;
934 /* Initialise the context bank with our page table cfg */
935 arm_smmu_init_context_bank(smmu_domain
, &pgtbl_cfg
);
938 * Request context fault interrupt. Do this last to avoid the
939 * handler seeing a half-initialised domain state.
941 irq
= smmu
->irqs
[smmu
->num_global_irqs
+ cfg
->irptndx
];
942 ret
= request_irq(irq
, arm_smmu_context_fault
, IRQF_SHARED
,
943 "arm-smmu-context-fault", domain
);
944 if (IS_ERR_VALUE(ret
)) {
945 dev_err(smmu
->dev
, "failed to request context IRQ %d (%u)\n",
947 cfg
->irptndx
= INVALID_IRPTNDX
;
950 mutex_unlock(&smmu_domain
->init_mutex
);
952 /* Publish page table ops for map/unmap */
953 smmu_domain
->pgtbl_ops
= pgtbl_ops
;
957 smmu_domain
->smmu
= NULL
;
959 mutex_unlock(&smmu_domain
->init_mutex
);
963 static void arm_smmu_destroy_domain_context(struct iommu_domain
*domain
)
965 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
966 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
967 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
968 void __iomem
*cb_base
;
975 * Disable the context bank and free the page tables before freeing
978 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
979 writel_relaxed(0, cb_base
+ ARM_SMMU_CB_SCTLR
);
981 if (cfg
->irptndx
!= INVALID_IRPTNDX
) {
982 irq
= smmu
->irqs
[smmu
->num_global_irqs
+ cfg
->irptndx
];
983 free_irq(irq
, domain
);
986 if (smmu_domain
->pgtbl_ops
)
987 free_io_pgtable_ops(smmu_domain
->pgtbl_ops
);
989 __arm_smmu_free_bitmap(smmu
->context_map
, cfg
->cbndx
);
992 static int arm_smmu_domain_init(struct iommu_domain
*domain
)
994 struct arm_smmu_domain
*smmu_domain
;
997 * Allocate the domain and initialise some of its data structures.
998 * We can't really do anything meaningful until we've added a
1001 smmu_domain
= kzalloc(sizeof(*smmu_domain
), GFP_KERNEL
);
1005 mutex_init(&smmu_domain
->init_mutex
);
1006 spin_lock_init(&smmu_domain
->pgtbl_lock
);
1007 domain
->priv
= smmu_domain
;
1011 static void arm_smmu_domain_destroy(struct iommu_domain
*domain
)
1013 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1016 * Free the domain resources. We assume that all devices have
1017 * already been detached.
1019 arm_smmu_destroy_domain_context(domain
);
1023 static int arm_smmu_master_configure_smrs(struct arm_smmu_device
*smmu
,
1024 struct arm_smmu_master_cfg
*cfg
)
1027 struct arm_smmu_smr
*smrs
;
1028 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1030 if (!(smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
))
1036 smrs
= kmalloc_array(cfg
->num_streamids
, sizeof(*smrs
), GFP_KERNEL
);
1038 dev_err(smmu
->dev
, "failed to allocate %d SMRs\n",
1039 cfg
->num_streamids
);
1043 /* Allocate the SMRs on the SMMU */
1044 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1045 int idx
= __arm_smmu_alloc_bitmap(smmu
->smr_map
, 0,
1046 smmu
->num_mapping_groups
);
1047 if (IS_ERR_VALUE(idx
)) {
1048 dev_err(smmu
->dev
, "failed to allocate free SMR\n");
1052 smrs
[i
] = (struct arm_smmu_smr
) {
1054 .mask
= 0, /* We don't currently share SMRs */
1055 .id
= cfg
->streamids
[i
],
1059 /* It worked! Now, poke the actual hardware */
1060 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1061 u32 reg
= SMR_VALID
| smrs
[i
].id
<< SMR_ID_SHIFT
|
1062 smrs
[i
].mask
<< SMR_MASK_SHIFT
;
1063 writel_relaxed(reg
, gr0_base
+ ARM_SMMU_GR0_SMR(smrs
[i
].idx
));
1071 __arm_smmu_free_bitmap(smmu
->smr_map
, smrs
[i
].idx
);
1076 static void arm_smmu_master_free_smrs(struct arm_smmu_device
*smmu
,
1077 struct arm_smmu_master_cfg
*cfg
)
1080 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1081 struct arm_smmu_smr
*smrs
= cfg
->smrs
;
1086 /* Invalidate the SMRs before freeing back to the allocator */
1087 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1088 u8 idx
= smrs
[i
].idx
;
1090 writel_relaxed(~SMR_VALID
, gr0_base
+ ARM_SMMU_GR0_SMR(idx
));
1091 __arm_smmu_free_bitmap(smmu
->smr_map
, idx
);
1098 static int arm_smmu_domain_add_master(struct arm_smmu_domain
*smmu_domain
,
1099 struct arm_smmu_master_cfg
*cfg
)
1102 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1103 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1105 /* Devices in an IOMMU group may already be configured */
1106 ret
= arm_smmu_master_configure_smrs(smmu
, cfg
);
1108 return ret
== -EEXIST
? 0 : ret
;
1110 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1113 idx
= cfg
->smrs
? cfg
->smrs
[i
].idx
: cfg
->streamids
[i
];
1114 s2cr
= S2CR_TYPE_TRANS
|
1115 (smmu_domain
->cfg
.cbndx
<< S2CR_CBNDX_SHIFT
);
1116 writel_relaxed(s2cr
, gr0_base
+ ARM_SMMU_GR0_S2CR(idx
));
1122 static void arm_smmu_domain_remove_master(struct arm_smmu_domain
*smmu_domain
,
1123 struct arm_smmu_master_cfg
*cfg
)
1126 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1127 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1129 /* An IOMMU group is torn down by the first device to be removed */
1130 if ((smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
) && !cfg
->smrs
)
1134 * We *must* clear the S2CR first, because freeing the SMR means
1135 * that it can be re-allocated immediately.
1137 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1138 u32 idx
= cfg
->smrs
? cfg
->smrs
[i
].idx
: cfg
->streamids
[i
];
1140 writel_relaxed(S2CR_TYPE_BYPASS
,
1141 gr0_base
+ ARM_SMMU_GR0_S2CR(idx
));
1144 arm_smmu_master_free_smrs(smmu
, cfg
);
1147 static int arm_smmu_attach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1150 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1151 struct arm_smmu_device
*smmu
;
1152 struct arm_smmu_master_cfg
*cfg
;
1154 smmu
= find_smmu_for_device(dev
);
1156 dev_err(dev
, "cannot attach to SMMU, is it on the same bus?\n");
1160 if (dev
->archdata
.iommu
) {
1161 dev_err(dev
, "already attached to IOMMU domain\n");
1165 /* Ensure that the domain is finalised */
1166 ret
= arm_smmu_init_domain_context(domain
, smmu
);
1167 if (IS_ERR_VALUE(ret
))
1171 * Sanity check the domain. We don't support domains across
1174 if (smmu_domain
->smmu
!= smmu
) {
1176 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1177 dev_name(smmu_domain
->smmu
->dev
), dev_name(smmu
->dev
));
1181 /* Looks ok, so add the device to the domain */
1182 cfg
= find_smmu_master_cfg(dev
);
1186 ret
= arm_smmu_domain_add_master(smmu_domain
, cfg
);
1188 dev
->archdata
.iommu
= domain
;
1192 static void arm_smmu_detach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1194 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1195 struct arm_smmu_master_cfg
*cfg
;
1197 cfg
= find_smmu_master_cfg(dev
);
1201 dev
->archdata
.iommu
= NULL
;
1202 arm_smmu_domain_remove_master(smmu_domain
, cfg
);
1205 static int arm_smmu_map(struct iommu_domain
*domain
, unsigned long iova
,
1206 phys_addr_t paddr
, size_t size
, int prot
)
1209 unsigned long flags
;
1210 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1211 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1216 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1217 ret
= ops
->map(ops
, iova
, paddr
, size
, prot
);
1218 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1222 static size_t arm_smmu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
1226 unsigned long flags
;
1227 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1228 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1233 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1234 ret
= ops
->unmap(ops
, iova
, size
);
1235 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1239 static phys_addr_t
arm_smmu_iova_to_phys_hard(struct iommu_domain
*domain
,
1242 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1243 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1244 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
1245 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1246 struct device
*dev
= smmu
->dev
;
1247 void __iomem
*cb_base
;
1251 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
1253 if (smmu
->version
== 1) {
1254 u32 reg
= iova
& ~0xfff;
1255 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_ATS1PR_LO
);
1257 u32 reg
= iova
& ~0xfff;
1258 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_ATS1PR_LO
);
1259 reg
= ((u64
)iova
& ~0xfff) >> 32;
1260 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_ATS1PR_HI
);
1263 if (readl_poll_timeout_atomic(cb_base
+ ARM_SMMU_CB_ATSR
, tmp
,
1264 !(tmp
& ATSR_ACTIVE
), 5, 50)) {
1266 "iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
1268 return ops
->iova_to_phys(ops
, iova
);
1271 phys
= readl_relaxed(cb_base
+ ARM_SMMU_CB_PAR_LO
);
1272 phys
|= ((u64
)readl_relaxed(cb_base
+ ARM_SMMU_CB_PAR_HI
)) << 32;
1274 if (phys
& CB_PAR_F
) {
1275 dev_err(dev
, "translation fault!\n");
1276 dev_err(dev
, "PAR = 0x%llx\n", phys
);
1280 return (phys
& GENMASK_ULL(39, 12)) | (iova
& 0xfff);
1283 static phys_addr_t
arm_smmu_iova_to_phys(struct iommu_domain
*domain
,
1287 unsigned long flags
;
1288 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1289 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1294 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1295 if (smmu_domain
->smmu
->features
& ARM_SMMU_FEAT_TRANS_OPS
)
1296 ret
= arm_smmu_iova_to_phys_hard(domain
, iova
);
1298 ret
= ops
->iova_to_phys(ops
, iova
);
1299 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1304 static bool arm_smmu_capable(enum iommu_cap cap
)
1307 case IOMMU_CAP_CACHE_COHERENCY
:
1309 * Return true here as the SMMU can always send out coherent
1313 case IOMMU_CAP_INTR_REMAP
:
1314 return true; /* MSIs are just memory writes */
1315 case IOMMU_CAP_NOEXEC
:
1322 static int __arm_smmu_get_pci_sid(struct pci_dev
*pdev
, u16 alias
, void *data
)
1324 *((u16
*)data
) = alias
;
1325 return 0; /* Continue walking */
1328 static void __arm_smmu_release_pci_iommudata(void *data
)
1333 static int arm_smmu_add_device(struct device
*dev
)
1335 struct arm_smmu_device
*smmu
;
1336 struct arm_smmu_master_cfg
*cfg
;
1337 struct iommu_group
*group
;
1338 void (*releasefn
)(void *) = NULL
;
1341 smmu
= find_smmu_for_device(dev
);
1345 group
= iommu_group_alloc();
1346 if (IS_ERR(group
)) {
1347 dev_err(dev
, "Failed to allocate IOMMU group\n");
1348 return PTR_ERR(group
);
1351 if (dev_is_pci(dev
)) {
1352 struct pci_dev
*pdev
= to_pci_dev(dev
);
1354 cfg
= kzalloc(sizeof(*cfg
), GFP_KERNEL
);
1360 cfg
->num_streamids
= 1;
1362 * Assume Stream ID == Requester ID for now.
1363 * We need a way to describe the ID mappings in FDT.
1365 pci_for_each_dma_alias(pdev
, __arm_smmu_get_pci_sid
,
1366 &cfg
->streamids
[0]);
1367 releasefn
= __arm_smmu_release_pci_iommudata
;
1369 struct arm_smmu_master
*master
;
1371 master
= find_smmu_master(smmu
, dev
->of_node
);
1380 iommu_group_set_iommudata(group
, cfg
, releasefn
);
1381 ret
= iommu_group_add_device(group
, dev
);
1384 iommu_group_put(group
);
1388 static void arm_smmu_remove_device(struct device
*dev
)
1390 iommu_group_remove_device(dev
);
1393 static int arm_smmu_domain_get_attr(struct iommu_domain
*domain
,
1394 enum iommu_attr attr
, void *data
)
1396 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1399 case DOMAIN_ATTR_NESTING
:
1400 *(int *)data
= (smmu_domain
->stage
== ARM_SMMU_DOMAIN_NESTED
);
1407 static int arm_smmu_domain_set_attr(struct iommu_domain
*domain
,
1408 enum iommu_attr attr
, void *data
)
1411 struct arm_smmu_domain
*smmu_domain
= domain
->priv
;
1413 mutex_lock(&smmu_domain
->init_mutex
);
1416 case DOMAIN_ATTR_NESTING
:
1417 if (smmu_domain
->smmu
) {
1423 smmu_domain
->stage
= ARM_SMMU_DOMAIN_NESTED
;
1425 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S1
;
1433 mutex_unlock(&smmu_domain
->init_mutex
);
1437 static struct iommu_ops arm_smmu_ops
= {
1438 .capable
= arm_smmu_capable
,
1439 .domain_init
= arm_smmu_domain_init
,
1440 .domain_destroy
= arm_smmu_domain_destroy
,
1441 .attach_dev
= arm_smmu_attach_dev
,
1442 .detach_dev
= arm_smmu_detach_dev
,
1443 .map
= arm_smmu_map
,
1444 .unmap
= arm_smmu_unmap
,
1445 .map_sg
= default_iommu_map_sg
,
1446 .iova_to_phys
= arm_smmu_iova_to_phys
,
1447 .add_device
= arm_smmu_add_device
,
1448 .remove_device
= arm_smmu_remove_device
,
1449 .domain_get_attr
= arm_smmu_domain_get_attr
,
1450 .domain_set_attr
= arm_smmu_domain_set_attr
,
1451 .pgsize_bitmap
= -1UL, /* Restricted during device attach */
1454 static void arm_smmu_device_reset(struct arm_smmu_device
*smmu
)
1456 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1457 void __iomem
*cb_base
;
1461 /* clear global FSR */
1462 reg
= readl_relaxed(ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sGFSR
);
1463 writel(reg
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sGFSR
);
1465 /* Mark all SMRn as invalid and all S2CRn as bypass */
1466 for (i
= 0; i
< smmu
->num_mapping_groups
; ++i
) {
1467 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_SMR(i
));
1468 writel_relaxed(S2CR_TYPE_BYPASS
,
1469 gr0_base
+ ARM_SMMU_GR0_S2CR(i
));
1472 /* Make sure all context banks are disabled and clear CB_FSR */
1473 for (i
= 0; i
< smmu
->num_context_banks
; ++i
) {
1474 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, i
);
1475 writel_relaxed(0, cb_base
+ ARM_SMMU_CB_SCTLR
);
1476 writel_relaxed(FSR_FAULT
, cb_base
+ ARM_SMMU_CB_FSR
);
1479 /* Invalidate the TLB, just in case */
1480 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_TLBIALLH
);
1481 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_TLBIALLNSNH
);
1483 reg
= readl_relaxed(ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1485 /* Enable fault reporting */
1486 reg
|= (sCR0_GFRE
| sCR0_GFIE
| sCR0_GCFGFRE
| sCR0_GCFGFIE
);
1488 /* Disable TLB broadcasting. */
1489 reg
|= (sCR0_VMIDPNE
| sCR0_PTM
);
1491 /* Enable client access, but bypass when no mapping is found */
1492 reg
&= ~(sCR0_CLIENTPD
| sCR0_USFCFG
);
1494 /* Disable forced broadcasting */
1497 /* Don't upgrade barriers */
1498 reg
&= ~(sCR0_BSU_MASK
<< sCR0_BSU_SHIFT
);
1500 /* Push the button */
1501 __arm_smmu_tlb_sync(smmu
);
1502 writel(reg
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1505 static int arm_smmu_id_size_to_bits(int size
)
1524 static int arm_smmu_device_cfg_probe(struct arm_smmu_device
*smmu
)
1527 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1530 dev_notice(smmu
->dev
, "probing hardware configuration...\n");
1531 dev_notice(smmu
->dev
, "SMMUv%d with:\n", smmu
->version
);
1534 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID0
);
1536 /* Restrict available stages based on module parameter */
1537 if (force_stage
== 1)
1538 id
&= ~(ID0_S2TS
| ID0_NTS
);
1539 else if (force_stage
== 2)
1540 id
&= ~(ID0_S1TS
| ID0_NTS
);
1542 if (id
& ID0_S1TS
) {
1543 smmu
->features
|= ARM_SMMU_FEAT_TRANS_S1
;
1544 dev_notice(smmu
->dev
, "\tstage 1 translation\n");
1547 if (id
& ID0_S2TS
) {
1548 smmu
->features
|= ARM_SMMU_FEAT_TRANS_S2
;
1549 dev_notice(smmu
->dev
, "\tstage 2 translation\n");
1553 smmu
->features
|= ARM_SMMU_FEAT_TRANS_NESTED
;
1554 dev_notice(smmu
->dev
, "\tnested translation\n");
1557 if (!(smmu
->features
&
1558 (ARM_SMMU_FEAT_TRANS_S1
| ARM_SMMU_FEAT_TRANS_S2
))) {
1559 dev_err(smmu
->dev
, "\tno translation support!\n");
1563 if (smmu
->version
== 1 || (!(id
& ID0_ATOSNS
) && (id
& ID0_S1TS
))) {
1564 smmu
->features
|= ARM_SMMU_FEAT_TRANS_OPS
;
1565 dev_notice(smmu
->dev
, "\taddress translation ops\n");
1568 if (id
& ID0_CTTW
) {
1569 smmu
->features
|= ARM_SMMU_FEAT_COHERENT_WALK
;
1570 dev_notice(smmu
->dev
, "\tcoherent table walk\n");
1576 smmu
->features
|= ARM_SMMU_FEAT_STREAM_MATCH
;
1577 smmu
->num_mapping_groups
= (id
>> ID0_NUMSMRG_SHIFT
) &
1579 if (smmu
->num_mapping_groups
== 0) {
1581 "stream-matching supported, but no SMRs present!\n");
1585 smr
= SMR_MASK_MASK
<< SMR_MASK_SHIFT
;
1586 smr
|= (SMR_ID_MASK
<< SMR_ID_SHIFT
);
1587 writel_relaxed(smr
, gr0_base
+ ARM_SMMU_GR0_SMR(0));
1588 smr
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_SMR(0));
1590 mask
= (smr
>> SMR_MASK_SHIFT
) & SMR_MASK_MASK
;
1591 sid
= (smr
>> SMR_ID_SHIFT
) & SMR_ID_MASK
;
1592 if ((mask
& sid
) != sid
) {
1594 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1599 dev_notice(smmu
->dev
,
1600 "\tstream matching with %u register groups, mask 0x%x",
1601 smmu
->num_mapping_groups
, mask
);
1603 smmu
->num_mapping_groups
= (id
>> ID0_NUMSIDB_SHIFT
) &
1608 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID1
);
1609 smmu
->pgshift
= (id
& ID1_PAGESIZE
) ? 16 : 12;
1611 /* Check for size mismatch of SMMU address space from mapped region */
1612 size
= 1 << (((id
>> ID1_NUMPAGENDXB_SHIFT
) & ID1_NUMPAGENDXB_MASK
) + 1);
1613 size
*= 2 << smmu
->pgshift
;
1614 if (smmu
->size
!= size
)
1616 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1619 smmu
->num_s2_context_banks
= (id
>> ID1_NUMS2CB_SHIFT
) & ID1_NUMS2CB_MASK
;
1620 smmu
->num_context_banks
= (id
>> ID1_NUMCB_SHIFT
) & ID1_NUMCB_MASK
;
1621 if (smmu
->num_s2_context_banks
> smmu
->num_context_banks
) {
1622 dev_err(smmu
->dev
, "impossible number of S2 context banks!\n");
1625 dev_notice(smmu
->dev
, "\t%u context banks (%u stage-2 only)\n",
1626 smmu
->num_context_banks
, smmu
->num_s2_context_banks
);
1629 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID2
);
1630 size
= arm_smmu_id_size_to_bits((id
>> ID2_IAS_SHIFT
) & ID2_IAS_MASK
);
1631 smmu
->ipa_size
= size
;
1633 /* The output mask is also applied for bypass */
1634 size
= arm_smmu_id_size_to_bits((id
>> ID2_OAS_SHIFT
) & ID2_OAS_MASK
);
1635 smmu
->pa_size
= size
;
1637 if (smmu
->version
== ARM_SMMU_V1
) {
1638 smmu
->va_size
= smmu
->ipa_size
;
1639 size
= SZ_4K
| SZ_2M
| SZ_1G
;
1641 size
= (id
>> ID2_UBS_SHIFT
) & ID2_UBS_MASK
;
1642 smmu
->va_size
= arm_smmu_id_size_to_bits(size
);
1643 #ifndef CONFIG_64BIT
1644 smmu
->va_size
= min(32UL, smmu
->va_size
);
1647 if (id
& ID2_PTFS_4K
)
1648 size
|= SZ_4K
| SZ_2M
| SZ_1G
;
1649 if (id
& ID2_PTFS_16K
)
1650 size
|= SZ_16K
| SZ_32M
;
1651 if (id
& ID2_PTFS_64K
)
1652 size
|= SZ_64K
| SZ_512M
;
1655 arm_smmu_ops
.pgsize_bitmap
&= size
;
1656 dev_notice(smmu
->dev
, "\tSupported page sizes: 0x%08lx\n", size
);
1658 if (smmu
->features
& ARM_SMMU_FEAT_TRANS_S1
)
1659 dev_notice(smmu
->dev
, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1660 smmu
->va_size
, smmu
->ipa_size
);
1662 if (smmu
->features
& ARM_SMMU_FEAT_TRANS_S2
)
1663 dev_notice(smmu
->dev
, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1664 smmu
->ipa_size
, smmu
->pa_size
);
1669 static const struct of_device_id arm_smmu_of_match
[] = {
1670 { .compatible
= "arm,smmu-v1", .data
= (void *)ARM_SMMU_V1
},
1671 { .compatible
= "arm,smmu-v2", .data
= (void *)ARM_SMMU_V2
},
1672 { .compatible
= "arm,mmu-400", .data
= (void *)ARM_SMMU_V1
},
1673 { .compatible
= "arm,mmu-401", .data
= (void *)ARM_SMMU_V1
},
1674 { .compatible
= "arm,mmu-500", .data
= (void *)ARM_SMMU_V2
},
1677 MODULE_DEVICE_TABLE(of
, arm_smmu_of_match
);
1679 static int arm_smmu_device_dt_probe(struct platform_device
*pdev
)
1681 const struct of_device_id
*of_id
;
1682 struct resource
*res
;
1683 struct arm_smmu_device
*smmu
;
1684 struct device
*dev
= &pdev
->dev
;
1685 struct rb_node
*node
;
1686 struct of_phandle_args masterspec
;
1687 int num_irqs
, i
, err
;
1689 smmu
= devm_kzalloc(dev
, sizeof(*smmu
), GFP_KERNEL
);
1691 dev_err(dev
, "failed to allocate arm_smmu_device\n");
1696 of_id
= of_match_node(arm_smmu_of_match
, dev
->of_node
);
1697 smmu
->version
= (enum arm_smmu_arch_version
)of_id
->data
;
1699 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1700 smmu
->base
= devm_ioremap_resource(dev
, res
);
1701 if (IS_ERR(smmu
->base
))
1702 return PTR_ERR(smmu
->base
);
1703 smmu
->size
= resource_size(res
);
1705 if (of_property_read_u32(dev
->of_node
, "#global-interrupts",
1706 &smmu
->num_global_irqs
)) {
1707 dev_err(dev
, "missing #global-interrupts property\n");
1712 while ((res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, num_irqs
))) {
1714 if (num_irqs
> smmu
->num_global_irqs
)
1715 smmu
->num_context_irqs
++;
1718 if (!smmu
->num_context_irqs
) {
1719 dev_err(dev
, "found %d interrupts but expected at least %d\n",
1720 num_irqs
, smmu
->num_global_irqs
+ 1);
1724 smmu
->irqs
= devm_kzalloc(dev
, sizeof(*smmu
->irqs
) * num_irqs
,
1727 dev_err(dev
, "failed to allocate %d irqs\n", num_irqs
);
1731 for (i
= 0; i
< num_irqs
; ++i
) {
1732 int irq
= platform_get_irq(pdev
, i
);
1735 dev_err(dev
, "failed to get irq index %d\n", i
);
1738 smmu
->irqs
[i
] = irq
;
1741 err
= arm_smmu_device_cfg_probe(smmu
);
1746 smmu
->masters
= RB_ROOT
;
1747 while (!of_parse_phandle_with_args(dev
->of_node
, "mmu-masters",
1748 "#stream-id-cells", i
,
1750 err
= register_smmu_master(smmu
, dev
, &masterspec
);
1752 dev_err(dev
, "failed to add master %s\n",
1753 masterspec
.np
->name
);
1754 goto out_put_masters
;
1759 dev_notice(dev
, "registered %d master devices\n", i
);
1761 parse_driver_options(smmu
);
1763 if (smmu
->version
> ARM_SMMU_V1
&&
1764 smmu
->num_context_banks
!= smmu
->num_context_irqs
) {
1766 "found only %d context interrupt(s) but %d required\n",
1767 smmu
->num_context_irqs
, smmu
->num_context_banks
);
1769 goto out_put_masters
;
1772 for (i
= 0; i
< smmu
->num_global_irqs
; ++i
) {
1773 err
= request_irq(smmu
->irqs
[i
],
1774 arm_smmu_global_fault
,
1776 "arm-smmu global fault",
1779 dev_err(dev
, "failed to request global IRQ %d (%u)\n",
1785 INIT_LIST_HEAD(&smmu
->list
);
1786 spin_lock(&arm_smmu_devices_lock
);
1787 list_add(&smmu
->list
, &arm_smmu_devices
);
1788 spin_unlock(&arm_smmu_devices_lock
);
1790 arm_smmu_device_reset(smmu
);
1795 free_irq(smmu
->irqs
[i
], smmu
);
1798 for (node
= rb_first(&smmu
->masters
); node
; node
= rb_next(node
)) {
1799 struct arm_smmu_master
*master
1800 = container_of(node
, struct arm_smmu_master
, node
);
1801 of_node_put(master
->of_node
);
1807 static int arm_smmu_device_remove(struct platform_device
*pdev
)
1810 struct device
*dev
= &pdev
->dev
;
1811 struct arm_smmu_device
*curr
, *smmu
= NULL
;
1812 struct rb_node
*node
;
1814 spin_lock(&arm_smmu_devices_lock
);
1815 list_for_each_entry(curr
, &arm_smmu_devices
, list
) {
1816 if (curr
->dev
== dev
) {
1818 list_del(&smmu
->list
);
1822 spin_unlock(&arm_smmu_devices_lock
);
1827 for (node
= rb_first(&smmu
->masters
); node
; node
= rb_next(node
)) {
1828 struct arm_smmu_master
*master
1829 = container_of(node
, struct arm_smmu_master
, node
);
1830 of_node_put(master
->of_node
);
1833 if (!bitmap_empty(smmu
->context_map
, ARM_SMMU_MAX_CBS
))
1834 dev_err(dev
, "removing device with active domains!\n");
1836 for (i
= 0; i
< smmu
->num_global_irqs
; ++i
)
1837 free_irq(smmu
->irqs
[i
], smmu
);
1839 /* Turn the thing off */
1840 writel(sCR0_CLIENTPD
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1844 static struct platform_driver arm_smmu_driver
= {
1847 .of_match_table
= of_match_ptr(arm_smmu_of_match
),
1849 .probe
= arm_smmu_device_dt_probe
,
1850 .remove
= arm_smmu_device_remove
,
1853 static int __init
arm_smmu_init(void)
1855 struct device_node
*np
;
1859 * Play nice with systems that don't have an ARM SMMU by checking that
1860 * an ARM SMMU exists in the system before proceeding with the driver
1861 * and IOMMU bus operation registration.
1863 np
= of_find_matching_node(NULL
, arm_smmu_of_match
);
1869 ret
= platform_driver_register(&arm_smmu_driver
);
1873 /* Oh, for a proper bus abstraction */
1874 if (!iommu_present(&platform_bus_type
))
1875 bus_set_iommu(&platform_bus_type
, &arm_smmu_ops
);
1877 #ifdef CONFIG_ARM_AMBA
1878 if (!iommu_present(&amba_bustype
))
1879 bus_set_iommu(&amba_bustype
, &arm_smmu_ops
);
1883 if (!iommu_present(&pci_bus_type
))
1884 bus_set_iommu(&pci_bus_type
, &arm_smmu_ops
);
1890 static void __exit
arm_smmu_exit(void)
1892 return platform_driver_unregister(&arm_smmu_driver
);
1895 subsys_initcall(arm_smmu_init
);
1896 module_exit(arm_smmu_exit
);
1898 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1899 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1900 MODULE_LICENSE("GPL v2");