drivers/media/dvb-frontends/stv0297.c

   1 /*
   2     Driver for STV0297 demodulator
   3
   4     Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
   5     Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/delay.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/slab.h>
  29
  30 #include "dvb_frontend.h"
  31 #include "stv0297.h"
  32
  33 struct stv0297_state {
  34         struct i2c_adapter *i2c;
  35         const struct stv0297_config *config;
  36         struct dvb_frontend frontend;
  37
  38         unsigned long last_ber;
  39         unsigned long base_freq;
  40 };
  41
  42 #if 1
  43 #define dprintk(x...) printk(x)
  44 #else
  45 #define dprintk(x...)
  46 #endif
  47
  48 #define STV0297_CLOCK_KHZ   28900
  49
  50
  51 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
  52 {
  53         int ret;
  54         u8 buf[] = { reg, data };
  55         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
  56
  57         ret = i2c_transfer(state->i2c, &msg, 1);
  58
  59         if (ret != 1)
  60                 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
  61                         "ret == %i)\n", __func__, reg, data, ret);
  62
  63         return (ret != 1) ? -1 : 0;
  64 }
  65
  66 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
  67 {
  68         int ret;
  69         u8 b0[] = { reg };
  70         u8 b1[] = { 0 };
  71         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
  72                                  {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  73                                };
  74
  75         // this device needs a STOP between the register and data
  76         if (state->config->stop_during_read) {
  77                 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
  78                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  79                         return -1;
  80                 }
  81                 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
  82                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  83                         return -1;
  84                 }
  85         } else {
  86                 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
  87                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  88                         return -1;
  89                 }
  90         }
  91
  92         return b1[0];
  93 }
  94
  95 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
  96 {
  97         int val;
  98
  99         val = stv0297_readreg(state, reg);
 100         val &= ~mask;
 101         val |= (data & mask);
 102         stv0297_writereg(state, reg, val);
 103
 104         return 0;
 105 }
 106
 107 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
 108 {
 109         int ret;
 110         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
 111                                   &reg1,.len = 1},
 112         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
 113         };
 114
 115         // this device needs a STOP between the register and data
 116         if (state->config->stop_during_read) {
 117                 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
 118                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 119                         return -1;
 120                 }
 121                 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
 122                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 123                         return -1;
 124                 }
 125         } else {
 126                 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
 127                         dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 128                         return -1;
 129                 }
 130         }
 131
 132         return 0;
 133 }
 134
 135 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
 136 {
 137         u64 tmp;
 138
 139         tmp = (u64)(stv0297_readreg(state, 0x55)
 140                     | (stv0297_readreg(state, 0x56) << 8)
 141                     | (stv0297_readreg(state, 0x57) << 16)
 142                     | (stv0297_readreg(state, 0x58) << 24));
 143
 144         tmp *= STV0297_CLOCK_KHZ;
 145         tmp >>= 32;
 146
 147         return (u32) tmp;
 148 }
 149
 150 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
 151 {
 152         long tmp;
 153
 154         tmp = 131072L * srate;  /* 131072 = 2^17  */
 155         tmp = tmp / (STV0297_CLOCK_KHZ / 4);    /* 1/4 = 2^-2 */
 156         tmp = tmp * 8192L;      /* 8192 = 2^13 */
 157
 158         stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
 159         stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
 160         stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
 161         stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
 162 }
 163
 164 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
 165 {
 166         long tmp;
 167
 168         tmp = (long) fshift *262144L;   /* 262144 = 2*18 */
 169         tmp /= symrate;
 170         tmp *= 1024;            /* 1024 = 2*10   */
 171
 172         // adjust
 173         if (tmp >= 0) {
 174                 tmp += 500000;
 175         } else {
 176                 tmp -= 500000;
 177         }
 178         tmp /= 1000000;
 179
 180         stv0297_writereg(state, 0x60, tmp & 0xFF);
 181         stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
 182 }
 183
 184 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
 185 {
 186         long tmp;
 187
 188         /* symrate is hardcoded to 10000 */
 189         tmp = offset * 26844L;  /* (2**28)/10000 */
 190         if (tmp < 0)
 191                 tmp += 0x10000000;
 192         tmp &= 0x0FFFFFFF;
 193
 194         stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
 195         stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
 196         stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
 197         stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
 198 }
 199
 200 /*
 201 static long stv0297_get_carrieroffset(struct stv0297_state *state)
 202 {
 203         s64 tmp;
 204
 205         stv0297_writereg(state, 0x6B, 0x00);
 206
 207         tmp = stv0297_readreg(state, 0x66);
 208         tmp |= (stv0297_readreg(state, 0x67) << 8);
 209         tmp |= (stv0297_readreg(state, 0x68) << 16);
 210         tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
 211
 212         tmp *= stv0297_get_symbolrate(state);
 213         tmp >>= 28;
 214
 215         return (s32) tmp;
 216 }
 217 */
 218
 219 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
 220 {
 221         s32 tmp;
 222
 223         if (freq > 10000)
 224                 freq -= STV0297_CLOCK_KHZ;
 225
 226         tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
 227         tmp = (freq * 1000) / tmp;
 228         if (tmp > 0xffff)
 229                 tmp = 0xffff;
 230
 231         stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
 232         stv0297_writereg(state, 0x21, tmp >> 8);
 233         stv0297_writereg(state, 0x20, tmp);
 234 }
 235
 236 static int stv0297_set_qam(struct stv0297_state *state,
 237                            enum fe_modulation modulation)
 238 {
 239         int val = 0;
 240
 241         switch (modulation) {
 242         case QAM_16:
 243                 val = 0;
 244                 break;
 245
 246         case QAM_32:
 247                 val = 1;
 248                 break;
 249
 250         case QAM_64:
 251                 val = 4;
 252                 break;
 253
 254         case QAM_128:
 255                 val = 2;
 256                 break;
 257
 258         case QAM_256:
 259                 val = 3;
 260                 break;
 261
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
 267
 268         return 0;
 269 }
 270
 271 static int stv0297_set_inversion(struct stv0297_state *state,
 272                                  enum fe_spectral_inversion inversion)
 273 {
 274         int val = 0;
 275
 276         switch (inversion) {
 277         case INVERSION_OFF:
 278                 val = 0;
 279                 break;
 280
 281         case INVERSION_ON:
 282                 val = 1;
 283                 break;
 284
 285         default:
 286                 return -EINVAL;
 287         }
 288
 289         stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
 290
 291         return 0;
 292 }
 293
 294 static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 295 {
 296         struct stv0297_state *state = fe->demodulator_priv;
 297
 298         if (enable) {
 299                 stv0297_writereg(state, 0x87, 0x78);
 300                 stv0297_writereg(state, 0x86, 0xc8);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int stv0297_init(struct dvb_frontend *fe)
 307 {
 308         struct stv0297_state *state = fe->demodulator_priv;
 309         int i;
 310
 311         /* load init table */
 312         for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
 313                 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
 314         msleep(200);
 315
 316         state->last_ber = 0;
 317
 318         return 0;
 319 }
 320
 321 static int stv0297_sleep(struct dvb_frontend *fe)
 322 {
 323         struct stv0297_state *state = fe->demodulator_priv;
 324
 325         stv0297_writereg_mask(state, 0x80, 1, 1);
 326
 327         return 0;
 328 }
 329
 330 static int stv0297_read_status(struct dvb_frontend *fe,
 331                                enum fe_status *status)
 332 {
 333         struct stv0297_state *state = fe->demodulator_priv;
 334
 335         u8 sync = stv0297_readreg(state, 0xDF);
 336
 337         *status = 0;
 338         if (sync & 0x80)
 339                 *status |=
 340                         FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
 341         return 0;
 342 }
 343
 344 static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
 345 {
 346         struct stv0297_state *state = fe->demodulator_priv;
 347         u8 BER[3];
 348
 349         stv0297_readregs(state, 0xA0, BER, 3);
 350         if (!(BER[0] & 0x80)) {
 351                 state->last_ber = BER[2] << 8 | BER[1];
 352                 stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
 353         }
 354
 355         *ber = state->last_ber;
 356
 357         return 0;
 358 }
 359
 360
 361 static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
 362 {
 363         struct stv0297_state *state = fe->demodulator_priv;
 364         u8 STRENGTH[3];
 365         u16 tmp;
 366
 367         stv0297_readregs(state, 0x41, STRENGTH, 3);
 368         tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
 369         if (STRENGTH[2] & 0x20) {
 370                 if (tmp < 0x200)
 371                         tmp = 0;
 372                 else
 373                         tmp = tmp - 0x200;
 374         } else {
 375                 if (tmp > 0x1ff)
 376                         tmp = 0;
 377                 else
 378                         tmp = 0x1ff - tmp;
 379         }
 380         *strength = (tmp << 7) | (tmp >> 2);
 381         return 0;
 382 }
 383
 384 static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
 385 {
 386         struct stv0297_state *state = fe->demodulator_priv;
 387         u8 SNR[2];
 388
 389         stv0297_readregs(state, 0x07, SNR, 2);
 390         *snr = SNR[1] << 8 | SNR[0];
 391
 392         return 0;
 393 }
 394
 395 static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 396 {
 397         struct stv0297_state *state = fe->demodulator_priv;
 398
 399         stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
 400
 401         *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
 402                 | stv0297_readreg(state, 0xD4);
 403
 404         stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
 405         stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
 406
 407         return 0;
 408 }
 409
 410 static int stv0297_set_frontend(struct dvb_frontend *fe)
 411 {
 412         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 413         struct stv0297_state *state = fe->demodulator_priv;
 414         int u_threshold;
 415         int initial_u;
 416         int blind_u;
 417         int delay;
 418         int sweeprate;
 419         int carrieroffset;
 420         unsigned long timeout;
 421         enum fe_spectral_inversion inversion;
 422
 423         switch (p->modulation) {
 424         case QAM_16:
 425         case QAM_32:
 426         case QAM_64:
 427                 delay = 100;
 428                 sweeprate = 1000;
 429                 break;
 430
 431         case QAM_128:
 432         case QAM_256:
 433                 delay = 200;
 434                 sweeprate = 500;
 435                 break;
 436
 437         default:
 438                 return -EINVAL;
 439         }
 440
 441         // determine inversion dependent parameters
 442         inversion = p->inversion;
 443         if (state->config->invert)
 444                 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 445         carrieroffset = -330;
 446         switch (inversion) {
 447         case INVERSION_OFF:
 448                 break;
 449
 450         case INVERSION_ON:
 451                 sweeprate = -sweeprate;
 452                 carrieroffset = -carrieroffset;
 453                 break;
 454
 455         default:
 456                 return -EINVAL;
 457         }
 458
 459         stv0297_init(fe);
 460         if (fe->ops.tuner_ops.set_params) {
 461                 fe->ops.tuner_ops.set_params(fe);
 462                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 463         }
 464
 465         /* clear software interrupts */
 466         stv0297_writereg(state, 0x82, 0x0);
 467
 468         /* set initial demodulation frequency */
 469         stv0297_set_initialdemodfreq(state, 7250);
 470
 471         /* setup AGC */
 472         stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
 473         stv0297_writereg(state, 0x41, 0x00);
 474         stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
 475         stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
 476         stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
 477         stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
 478         stv0297_writereg(state, 0x72, 0x00);
 479         stv0297_writereg(state, 0x73, 0x00);
 480         stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
 481         stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
 482         stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
 483
 484         /* setup STL */
 485         stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
 486         stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
 487         stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
 488         stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
 489         stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
 490
 491         /* disable frequency sweep */
 492         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 493
 494         /* reset deinterleaver */
 495         stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
 496         stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
 497
 498         /* ??? */
 499         stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
 500         stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
 501
 502         /* reset equaliser */
 503         u_threshold = stv0297_readreg(state, 0x00) & 0xf;
 504         initial_u = stv0297_readreg(state, 0x01) >> 4;
 505         blind_u = stv0297_readreg(state, 0x01) & 0xf;
 506         stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
 507         stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
 508         stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
 509         stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
 510         stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
 511
 512         /* data comes from internal A/D */
 513         stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
 514
 515         /* clear phase registers */
 516         stv0297_writereg(state, 0x63, 0x00);
 517         stv0297_writereg(state, 0x64, 0x00);
 518         stv0297_writereg(state, 0x65, 0x00);
 519         stv0297_writereg(state, 0x66, 0x00);
 520         stv0297_writereg(state, 0x67, 0x00);
 521         stv0297_writereg(state, 0x68, 0x00);
 522         stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
 523
 524         /* set parameters */
 525         stv0297_set_qam(state, p->modulation);
 526         stv0297_set_symbolrate(state, p->symbol_rate / 1000);
 527         stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
 528         stv0297_set_carrieroffset(state, carrieroffset);
 529         stv0297_set_inversion(state, inversion);
 530
 531         /* kick off lock */
 532         /* Disable corner detection for higher QAMs */
 533         if (p->modulation == QAM_128 ||
 534                 p->modulation == QAM_256)
 535                 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
 536         else
 537                 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
 538
 539         stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
 540         stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
 541         stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
 542         stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
 543         stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
 544         stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
 545         stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
 546
 547         /* wait for WGAGC lock */
 548         timeout = jiffies + msecs_to_jiffies(2000);
 549         while (time_before(jiffies, timeout)) {
 550                 msleep(10);
 551                 if (stv0297_readreg(state, 0x43) & 0x08)
 552                         break;
 553         }
 554         if (time_after(jiffies, timeout)) {
 555                 goto timeout;
 556         }
 557         msleep(20);
 558
 559         /* wait for equaliser partial convergence */
 560         timeout = jiffies + msecs_to_jiffies(500);
 561         while (time_before(jiffies, timeout)) {
 562                 msleep(10);
 563
 564                 if (stv0297_readreg(state, 0x82) & 0x04) {
 565                         break;
 566                 }
 567         }
 568         if (time_after(jiffies, timeout)) {
 569                 goto timeout;
 570         }
 571
 572         /* wait for equaliser full convergence */
 573         timeout = jiffies + msecs_to_jiffies(delay);
 574         while (time_before(jiffies, timeout)) {
 575                 msleep(10);
 576
 577                 if (stv0297_readreg(state, 0x82) & 0x08) {
 578                         break;
 579                 }
 580         }
 581         if (time_after(jiffies, timeout)) {
 582                 goto timeout;
 583         }
 584
 585         /* disable sweep */
 586         stv0297_writereg_mask(state, 0x6a, 1, 0);
 587         stv0297_writereg_mask(state, 0x88, 8, 0);
 588
 589         /* wait for main lock */
 590         timeout = jiffies + msecs_to_jiffies(20);
 591         while (time_before(jiffies, timeout)) {
 592                 msleep(10);
 593
 594                 if (stv0297_readreg(state, 0xDF) & 0x80) {
 595                         break;
 596                 }
 597         }
 598         if (time_after(jiffies, timeout)) {
 599                 goto timeout;
 600         }
 601         msleep(100);
 602
 603         /* is it still locked after that delay? */
 604         if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
 605                 goto timeout;
 606         }
 607
 608         /* success!! */
 609         stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
 610         state->base_freq = p->frequency;
 611         return 0;
 612
 613 timeout:
 614         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 615         return 0;
 616 }
 617
 618 static int stv0297_get_frontend(struct dvb_frontend *fe)
 619 {
 620         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 621         struct stv0297_state *state = fe->demodulator_priv;
 622         int reg_00, reg_83;
 623
 624         reg_00 = stv0297_readreg(state, 0x00);
 625         reg_83 = stv0297_readreg(state, 0x83);
 626
 627         p->frequency = state->base_freq;
 628         p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
 629         if (state->config->invert)
 630                 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 631         p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
 632         p->fec_inner = FEC_NONE;
 633
 634         switch ((reg_00 >> 4) & 0x7) {
 635         case 0:
 636                 p->modulation = QAM_16;
 637                 break;
 638         case 1:
 639                 p->modulation = QAM_32;
 640                 break;
 641         case 2:
 642                 p->modulation = QAM_128;
 643                 break;
 644         case 3:
 645                 p->modulation = QAM_256;
 646                 break;
 647         case 4:
 648                 p->modulation = QAM_64;
 649                 break;
 650         }
 651
 652         return 0;
 653 }
 654
 655 static void stv0297_release(struct dvb_frontend *fe)
 656 {
 657         struct stv0297_state *state = fe->demodulator_priv;
 658         kfree(state);
 659 }
 660
 661 static struct dvb_frontend_ops stv0297_ops;
 662
 663 struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
 664                                     struct i2c_adapter *i2c)
 665 {
 666         struct stv0297_state *state = NULL;
 667
 668         /* allocate memory for the internal state */
 669         state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
 670         if (state == NULL)
 671                 goto error;
 672
 673         /* setup the state */
 674         state->config = config;
 675         state->i2c = i2c;
 676         state->last_ber = 0;
 677         state->base_freq = 0;
 678
 679         /* check if the demod is there */
 680         if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
 681                 goto error;
 682
 683         /* create dvb_frontend */
 684         memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
 685         state->frontend.demodulator_priv = state;
 686         return &state->frontend;
 687
 688 error:
 689         kfree(state);
 690         return NULL;
 691 }
 692
 693 static struct dvb_frontend_ops stv0297_ops = {
 694         .delsys = { SYS_DVBC_ANNEX_A },
 695         .info = {
 696                  .name = "ST STV0297 DVB-C",
 697                  .frequency_min = 47000000,
 698                  .frequency_max = 862000000,
 699                  .frequency_stepsize = 62500,
 700                  .symbol_rate_min = 870000,
 701                  .symbol_rate_max = 11700000,
 702                  .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
 703                  FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
 704
 705         .release = stv0297_release,
 706
 707         .init = stv0297_init,
 708         .sleep = stv0297_sleep,
 709         .i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
 710
 711         .set_frontend = stv0297_set_frontend,
 712         .get_frontend = stv0297_get_frontend,
 713
 714         .read_status = stv0297_read_status,
 715         .read_ber = stv0297_read_ber,
 716         .read_signal_strength = stv0297_read_signal_strength,
 717         .read_snr = stv0297_read_snr,
 718         .read_ucblocks = stv0297_read_ucblocks,
 719 };
 720
 721 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
 722 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
 723 MODULE_LICENSE("GPL");
 724
 725 EXPORT_SYMBOL(stv0297_attach);