drivers/media/platform/atmel/atmel-isc-regs.h

   1 #ifndef __ATMEL_ISC_REGS_H
   2 #define __ATMEL_ISC_REGS_H
   3
   4 #include <linux/bitops.h>
   5
   6 /* ISC Control Enable Register 0 */
   7 #define ISC_CTRLEN      0x00000000
   8
   9 /* ISC Control Disable Register 0 */
  10 #define ISC_CTRLDIS     0x00000004
  11
  12 /* ISC Control Status Register 0 */
  13 #define ISC_CTRLSR      0x00000008
  14
  15 #define ISC_CTRL_CAPTURE        BIT(0)
  16 #define ISC_CTRL_UPPRO          BIT(1)
  17 #define ISC_CTRL_HISREQ         BIT(2)
  18 #define ISC_CTRL_HISCLR         BIT(3)
  19
  20 /* ISC Parallel Front End Configuration 0 Register */
  21 #define ISC_PFE_CFG0    0x0000000c
  22
  23 #define ISC_PFE_CFG0_HPOL_LOW   BIT(0)
  24 #define ISC_PFE_CFG0_VPOL_LOW   BIT(1)
  25 #define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
  26
  27 #define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
  28 #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
  29
  30 #define ISC_PFE_CFG0_BPS_EIGHT  (0x4 << 28)
  31 #define ISC_PFG_CFG0_BPS_NINE   (0x3 << 28)
  32 #define ISC_PFG_CFG0_BPS_TEN    (0x2 << 28)
  33 #define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
  34 #define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
  35 #define ISC_PFE_CFG0_BPS_MASK   GENMASK(30, 28)
  36
  37 /* ISC Clock Enable Register */
  38 #define ISC_CLKEN               0x00000018
  39
  40 /* ISC Clock Disable Register */
  41 #define ISC_CLKDIS              0x0000001c
  42
  43 /* ISC Clock Status Register */
  44 #define ISC_CLKSR               0x00000020
  45
  46 #define ISC_CLK(n)              BIT(n)
  47
  48 /* ISC Clock Configuration Register */
  49 #define ISC_CLKCFG              0x00000024
  50 #define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
  51 #define ISC_CLKCFG_DIV_MASK(n)  GENMASK(((n)*16 + 7), (n)*16)
  52 #define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
  53 #define ISC_CLKCFG_SEL_MASK(n)  GENMASK(((n)*17 + 8), ((n)*16 + 8))
  54
  55 /* ISC Interrupt Enable Register */
  56 #define ISC_INTEN       0x00000028
  57
  58 /* ISC Interrupt Disable Register */
  59 #define ISC_INTDIS      0x0000002c
  60
  61 /* ISC Interrupt Mask Register */
  62 #define ISC_INTMASK     0x00000030
  63
  64 /* ISC Interrupt Status Register */
  65 #define ISC_INTSR       0x00000034
  66
  67 #define ISC_INT_DDONE           BIT(8)
  68
  69 /* ISC White Balance Control Register */
  70 #define ISC_WB_CTRL     0x00000058
  71
  72 /* ISC White Balance Configuration Register */
  73 #define ISC_WB_CFG      0x0000005c
  74
  75 /* ISC Color Filter Array Control Register */
  76 #define ISC_CFA_CTRL    0x00000070
  77
  78 /* ISC Color Filter Array Configuration Register */
  79 #define ISC_CFA_CFG     0x00000074
  80
  81 #define ISC_BAY_CFG_GRGR        0x0
  82 #define ISC_BAY_CFG_RGRG        0x1
  83 #define ISC_BAY_CFG_GBGB        0x2
  84 #define ISC_BAY_CFG_BGBG        0x3
  85 #define ISC_BAY_CFG_MASK        GENMASK(1, 0)
  86
  87 /* ISC Color Correction Control Register */
  88 #define ISC_CC_CTRL     0x00000078
  89
  90 /* ISC Gamma Correction Control Register */
  91 #define ISC_GAM_CTRL    0x00000094
  92
  93 /* Color Space Conversion Control Register */
  94 #define ISC_CSC_CTRL    0x00000398
  95
  96 /* Contrast And Brightness Control Register */
  97 #define ISC_CBC_CTRL    0x000003b4
  98
  99 /* Subsampling 4:4:4 to 4:2:2 Control Register */
 100 #define ISC_SUB422_CTRL 0x000003c4
 101
 102 /* Subsampling 4:2:2 to 4:2:0 Control Register */
 103 #define ISC_SUB420_CTRL 0x000003cc
 104
 105 /* Rounding, Limiting and Packing Configuration Register */
 106 #define ISC_RLP_CFG     0x000003d0
 107
 108 #define ISC_RLP_CFG_MODE_DAT8           0x0
 109 #define ISC_RLP_CFG_MODE_DAT9           0x1
 110 #define ISC_RLP_CFG_MODE_DAT10          0x2
 111 #define ISC_RLP_CFG_MODE_DAT11          0x3
 112 #define ISC_RLP_CFG_MODE_DAT12          0x4
 113 #define ISC_RLP_CFG_MODE_DATY8          0x5
 114 #define ISC_RLP_CFG_MODE_DATY10         0x6
 115 #define ISC_RLP_CFG_MODE_ARGB444        0x7
 116 #define ISC_RLP_CFG_MODE_ARGB555        0x8
 117 #define ISC_RLP_CFG_MODE_RGB565         0x9
 118 #define ISC_RLP_CFG_MODE_ARGB32         0xa
 119 #define ISC_RLP_CFG_MODE_YYCC           0xb
 120 #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
 121 #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
 122
 123 /* DMA Configuration Register */
 124 #define ISC_DCFG        0x000003e0
 125 #define ISC_DCFG_IMODE_PACKED8          0x0
 126 #define ISC_DCFG_IMODE_PACKED16         0x1
 127 #define ISC_DCFG_IMODE_PACKED32         0x2
 128 #define ISC_DCFG_IMODE_YC422SP          0x3
 129 #define ISC_DCFG_IMODE_YC422P           0x4
 130 #define ISC_DCFG_IMODE_YC420SP          0x5
 131 #define ISC_DCFG_IMODE_YC420P           0x6
 132 #define ISC_DCFG_IMODE_MASK             GENMASK(2, 0)
 133
 134 #define ISC_DCFG_YMBSIZE_SINGLE         (0x0 << 4)
 135 #define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)
 136 #define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)
 137 #define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)
 138 #define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)
 139
 140 #define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)
 141 #define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)
 142 #define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)
 143 #define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)
 144 #define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)
 145
 146 /* DMA Control Register */
 147 #define ISC_DCTRL       0x000003e4
 148
 149 #define ISC_DCTRL_DVIEW_PACKED          (0x0 << 1)
 150 #define ISC_DCTRL_DVIEW_SEMIPLANAR      (0x1 << 1)
 151 #define ISC_DCTRL_DVIEW_PLANAR          (0x2 << 1)
 152 #define ISC_DCTRL_DVIEW_MASK            GENMASK(2, 1)
 153
 154 #define ISC_DCTRL_IE_IS                 (0x0 << 4)
 155
 156 /* DMA Descriptor Address Register */
 157 #define ISC_DNDA        0x000003e8
 158
 159 /* DMA Address 0 Register */
 160 #define ISC_DAD0        0x000003ec
 161
 162 /* DMA Stride 0 Register */
 163 #define ISC_DST0        0x000003f0
 164
 165 #endif