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Merge remote-tracking branch 'regulator/for-next'
[deliverable/linux.git] / drivers / media / platform / pxa_camera.c
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dma/pxa-dma.h>
37
38 #include <media/v4l2-async.h>
39 #include <media/v4l2-clk.h>
40 #include <media/v4l2-common.h>
41 #include <media/v4l2-device.h>
42 #include <media/v4l2-ioctl.h>
43 #include <media/v4l2-of.h>
44
45 #include <media/videobuf2-dma-sg.h>
46
47 #include <linux/videodev2.h>
48
49 #include <linux/platform_data/media/camera-pxa.h>
50
51 #define PXA_CAM_VERSION "0.0.6"
52 #define PXA_CAM_DRV_NAME "pxa27x-camera"
53
54 #define DEFAULT_WIDTH 640
55 #define DEFAULT_HEIGHT 480
56
57 /* Camera Interface */
58 #define CICR0 0x0000
59 #define CICR1 0x0004
60 #define CICR2 0x0008
61 #define CICR3 0x000C
62 #define CICR4 0x0010
63 #define CISR 0x0014
64 #define CIFR 0x0018
65 #define CITOR 0x001C
66 #define CIBR0 0x0028
67 #define CIBR1 0x0030
68 #define CIBR2 0x0038
69
70 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
71 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
72 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
73 #define CICR0_ENB (1 << 28) /* Camera interface enable */
74 #define CICR0_DIS (1 << 27) /* Camera interface disable */
75 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
76 #define CICR0_TOM (1 << 9) /* Time-out mask */
77 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
78 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
79 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
80 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
81 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
82 #define CICR0_CDM (1 << 3) /* Disable-done mask */
83 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
84 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
85 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
86
87 #define CICR1_TBIT (1 << 31) /* Transparency bit */
88 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
89 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
90 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
91 #define CICR1_RGB_F (1 << 11) /* RGB format */
92 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
93 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
94 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
95 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
96 #define CICR1_DW (0x7 << 0) /* Data width mask */
97
98 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
99 wait count mask */
100 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
101 wait count mask */
102 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
103 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
104 wait count mask */
105 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
106 wait count mask */
107
108 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
109 wait count mask */
110 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
111 wait count mask */
112 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
113 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
114 wait count mask */
115 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
116
117 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
118 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
119 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
120 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
121 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
122 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
123 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
124 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
125
126 #define CISR_FTO (1 << 15) /* FIFO time-out */
127 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
128 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
129 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
130 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
131 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
132 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
133 #define CISR_EOL (1 << 8) /* End of line */
134 #define CISR_PAR_ERR (1 << 7) /* Parity error */
135 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
136 #define CISR_CDD (1 << 5) /* Camera interface disable done */
137 #define CISR_SOF (1 << 4) /* Start of frame */
138 #define CISR_EOF (1 << 3) /* End of frame */
139 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
140 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
141 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
142
143 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
144 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
145 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
146 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
147 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
148 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
149 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
150 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
151
152 #define CICR0_SIM_MP (0 << 24)
153 #define CICR0_SIM_SP (1 << 24)
154 #define CICR0_SIM_MS (2 << 24)
155 #define CICR0_SIM_EP (3 << 24)
156 #define CICR0_SIM_ES (4 << 24)
157
158 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
159 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
160 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
161 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
162 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
163
164 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
165 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
166 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
167 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
168 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
169
170 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
171 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
172 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
173 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
174
175 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
176 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
177 CICR0_EOFM | CICR0_FOM)
178
179 #define sensor_call(cam, o, f, args...) \
180 v4l2_subdev_call(cam->sensor, o, f, ##args)
181
182 /*
183 * Format handling
184 */
185
186 /**
187 * enum pxa_mbus_packing - data packing types on the media-bus
188 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
189 * sample represents one pixel
190 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
191 * possibly incomplete byte high bits are padding
192 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
193 * to 16 bits
194 */
195 enum pxa_mbus_packing {
196 PXA_MBUS_PACKING_NONE,
197 PXA_MBUS_PACKING_2X8_PADHI,
198 PXA_MBUS_PACKING_EXTEND16,
199 };
200
201 /**
202 * enum pxa_mbus_order - sample order on the media bus
203 * @PXA_MBUS_ORDER_LE: least significant sample first
204 * @PXA_MBUS_ORDER_BE: most significant sample first
205 */
206 enum pxa_mbus_order {
207 PXA_MBUS_ORDER_LE,
208 PXA_MBUS_ORDER_BE,
209 };
210
211 /**
212 * enum pxa_mbus_layout - planes layout in memory
213 * @PXA_MBUS_LAYOUT_PACKED: color components packed
214 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
215 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
216 * chroma plane (C plane is half the size
217 * of Y plane)
218 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
219 * chroma plane (C plane is the same size
220 * as Y plane)
221 */
222 enum pxa_mbus_layout {
223 PXA_MBUS_LAYOUT_PACKED = 0,
224 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
225 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
226 PXA_MBUS_LAYOUT_PLANAR_Y_C,
227 };
228
229 /**
230 * struct pxa_mbus_pixelfmt - Data format on the media bus
231 * @name: Name of the format
232 * @fourcc: Fourcc code, that will be obtained if the data is
233 * stored in memory in the following way:
234 * @packing: Type of sample-packing, that has to be used
235 * @order: Sample order when storing in memory
236 * @bits_per_sample: How many bits the bridge has to sample
237 */
238 struct pxa_mbus_pixelfmt {
239 const char *name;
240 u32 fourcc;
241 enum pxa_mbus_packing packing;
242 enum pxa_mbus_order order;
243 enum pxa_mbus_layout layout;
244 u8 bits_per_sample;
245 };
246
247 /**
248 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
249 * @code: mediabus pixel-code
250 * @fmt: pixel format description
251 */
252 struct pxa_mbus_lookup {
253 u32 code;
254 struct pxa_mbus_pixelfmt fmt;
255 };
256
257 static const struct pxa_mbus_lookup mbus_fmt[] = {
258 {
259 .code = MEDIA_BUS_FMT_YUYV8_2X8,
260 .fmt = {
261 .fourcc = V4L2_PIX_FMT_YUYV,
262 .name = "YUYV",
263 .bits_per_sample = 8,
264 .packing = PXA_MBUS_PACKING_2X8_PADHI,
265 .order = PXA_MBUS_ORDER_LE,
266 .layout = PXA_MBUS_LAYOUT_PACKED,
267 },
268 }, {
269 .code = MEDIA_BUS_FMT_YVYU8_2X8,
270 .fmt = {
271 .fourcc = V4L2_PIX_FMT_YVYU,
272 .name = "YVYU",
273 .bits_per_sample = 8,
274 .packing = PXA_MBUS_PACKING_2X8_PADHI,
275 .order = PXA_MBUS_ORDER_LE,
276 .layout = PXA_MBUS_LAYOUT_PACKED,
277 },
278 }, {
279 .code = MEDIA_BUS_FMT_UYVY8_2X8,
280 .fmt = {
281 .fourcc = V4L2_PIX_FMT_UYVY,
282 .name = "UYVY",
283 .bits_per_sample = 8,
284 .packing = PXA_MBUS_PACKING_2X8_PADHI,
285 .order = PXA_MBUS_ORDER_LE,
286 .layout = PXA_MBUS_LAYOUT_PACKED,
287 },
288 }, {
289 .code = MEDIA_BUS_FMT_VYUY8_2X8,
290 .fmt = {
291 .fourcc = V4L2_PIX_FMT_VYUY,
292 .name = "VYUY",
293 .bits_per_sample = 8,
294 .packing = PXA_MBUS_PACKING_2X8_PADHI,
295 .order = PXA_MBUS_ORDER_LE,
296 .layout = PXA_MBUS_LAYOUT_PACKED,
297 },
298 }, {
299 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
300 .fmt = {
301 .fourcc = V4L2_PIX_FMT_RGB555,
302 .name = "RGB555",
303 .bits_per_sample = 8,
304 .packing = PXA_MBUS_PACKING_2X8_PADHI,
305 .order = PXA_MBUS_ORDER_LE,
306 .layout = PXA_MBUS_LAYOUT_PACKED,
307 },
308 }, {
309 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
310 .fmt = {
311 .fourcc = V4L2_PIX_FMT_RGB555X,
312 .name = "RGB555X",
313 .bits_per_sample = 8,
314 .packing = PXA_MBUS_PACKING_2X8_PADHI,
315 .order = PXA_MBUS_ORDER_BE,
316 .layout = PXA_MBUS_LAYOUT_PACKED,
317 },
318 }, {
319 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
320 .fmt = {
321 .fourcc = V4L2_PIX_FMT_RGB565,
322 .name = "RGB565",
323 .bits_per_sample = 8,
324 .packing = PXA_MBUS_PACKING_2X8_PADHI,
325 .order = PXA_MBUS_ORDER_LE,
326 .layout = PXA_MBUS_LAYOUT_PACKED,
327 },
328 }, {
329 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
330 .fmt = {
331 .fourcc = V4L2_PIX_FMT_RGB565X,
332 .name = "RGB565X",
333 .bits_per_sample = 8,
334 .packing = PXA_MBUS_PACKING_2X8_PADHI,
335 .order = PXA_MBUS_ORDER_BE,
336 .layout = PXA_MBUS_LAYOUT_PACKED,
337 },
338 }, {
339 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
340 .fmt = {
341 .fourcc = V4L2_PIX_FMT_SBGGR8,
342 .name = "Bayer 8 BGGR",
343 .bits_per_sample = 8,
344 .packing = PXA_MBUS_PACKING_NONE,
345 .order = PXA_MBUS_ORDER_LE,
346 .layout = PXA_MBUS_LAYOUT_PACKED,
347 },
348 }, {
349 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
350 .fmt = {
351 .fourcc = V4L2_PIX_FMT_SBGGR10,
352 .name = "Bayer 10 BGGR",
353 .bits_per_sample = 10,
354 .packing = PXA_MBUS_PACKING_EXTEND16,
355 .order = PXA_MBUS_ORDER_LE,
356 .layout = PXA_MBUS_LAYOUT_PACKED,
357 },
358 }, {
359 .code = MEDIA_BUS_FMT_Y8_1X8,
360 .fmt = {
361 .fourcc = V4L2_PIX_FMT_GREY,
362 .name = "Grey",
363 .bits_per_sample = 8,
364 .packing = PXA_MBUS_PACKING_NONE,
365 .order = PXA_MBUS_ORDER_LE,
366 .layout = PXA_MBUS_LAYOUT_PACKED,
367 },
368 }, {
369 .code = MEDIA_BUS_FMT_Y10_1X10,
370 .fmt = {
371 .fourcc = V4L2_PIX_FMT_Y10,
372 .name = "Grey 10bit",
373 .bits_per_sample = 10,
374 .packing = PXA_MBUS_PACKING_EXTEND16,
375 .order = PXA_MBUS_ORDER_LE,
376 .layout = PXA_MBUS_LAYOUT_PACKED,
377 },
378 }, {
379 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
380 .fmt = {
381 .fourcc = V4L2_PIX_FMT_SBGGR10,
382 .name = "Bayer 10 BGGR",
383 .bits_per_sample = 8,
384 .packing = PXA_MBUS_PACKING_2X8_PADHI,
385 .order = PXA_MBUS_ORDER_LE,
386 .layout = PXA_MBUS_LAYOUT_PACKED,
387 },
388 }, {
389 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
390 .fmt = {
391 .fourcc = V4L2_PIX_FMT_SBGGR10,
392 .name = "Bayer 10 BGGR",
393 .bits_per_sample = 8,
394 .packing = PXA_MBUS_PACKING_2X8_PADHI,
395 .order = PXA_MBUS_ORDER_BE,
396 .layout = PXA_MBUS_LAYOUT_PACKED,
397 },
398 }, {
399 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
400 .fmt = {
401 .fourcc = V4L2_PIX_FMT_RGB444,
402 .name = "RGB444",
403 .bits_per_sample = 8,
404 .packing = PXA_MBUS_PACKING_2X8_PADHI,
405 .order = PXA_MBUS_ORDER_BE,
406 .layout = PXA_MBUS_LAYOUT_PACKED,
407 },
408 }, {
409 .code = MEDIA_BUS_FMT_UYVY8_1X16,
410 .fmt = {
411 .fourcc = V4L2_PIX_FMT_UYVY,
412 .name = "UYVY 16bit",
413 .bits_per_sample = 16,
414 .packing = PXA_MBUS_PACKING_EXTEND16,
415 .order = PXA_MBUS_ORDER_LE,
416 .layout = PXA_MBUS_LAYOUT_PACKED,
417 },
418 }, {
419 .code = MEDIA_BUS_FMT_VYUY8_1X16,
420 .fmt = {
421 .fourcc = V4L2_PIX_FMT_VYUY,
422 .name = "VYUY 16bit",
423 .bits_per_sample = 16,
424 .packing = PXA_MBUS_PACKING_EXTEND16,
425 .order = PXA_MBUS_ORDER_LE,
426 .layout = PXA_MBUS_LAYOUT_PACKED,
427 },
428 }, {
429 .code = MEDIA_BUS_FMT_YUYV8_1X16,
430 .fmt = {
431 .fourcc = V4L2_PIX_FMT_YUYV,
432 .name = "YUYV 16bit",
433 .bits_per_sample = 16,
434 .packing = PXA_MBUS_PACKING_EXTEND16,
435 .order = PXA_MBUS_ORDER_LE,
436 .layout = PXA_MBUS_LAYOUT_PACKED,
437 },
438 }, {
439 .code = MEDIA_BUS_FMT_YVYU8_1X16,
440 .fmt = {
441 .fourcc = V4L2_PIX_FMT_YVYU,
442 .name = "YVYU 16bit",
443 .bits_per_sample = 16,
444 .packing = PXA_MBUS_PACKING_EXTEND16,
445 .order = PXA_MBUS_ORDER_LE,
446 .layout = PXA_MBUS_LAYOUT_PACKED,
447 },
448 }, {
449 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
450 .fmt = {
451 .fourcc = V4L2_PIX_FMT_SGRBG8,
452 .name = "Bayer 8 GRBG",
453 .bits_per_sample = 8,
454 .packing = PXA_MBUS_PACKING_NONE,
455 .order = PXA_MBUS_ORDER_LE,
456 .layout = PXA_MBUS_LAYOUT_PACKED,
457 },
458 }, {
459 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
460 .fmt = {
461 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
462 .name = "Bayer 10 BGGR DPCM 8",
463 .bits_per_sample = 8,
464 .packing = PXA_MBUS_PACKING_NONE,
465 .order = PXA_MBUS_ORDER_LE,
466 .layout = PXA_MBUS_LAYOUT_PACKED,
467 },
468 }, {
469 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
470 .fmt = {
471 .fourcc = V4L2_PIX_FMT_SGBRG10,
472 .name = "Bayer 10 GBRG",
473 .bits_per_sample = 10,
474 .packing = PXA_MBUS_PACKING_EXTEND16,
475 .order = PXA_MBUS_ORDER_LE,
476 .layout = PXA_MBUS_LAYOUT_PACKED,
477 },
478 }, {
479 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
480 .fmt = {
481 .fourcc = V4L2_PIX_FMT_SGRBG10,
482 .name = "Bayer 10 GRBG",
483 .bits_per_sample = 10,
484 .packing = PXA_MBUS_PACKING_EXTEND16,
485 .order = PXA_MBUS_ORDER_LE,
486 .layout = PXA_MBUS_LAYOUT_PACKED,
487 },
488 }, {
489 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
490 .fmt = {
491 .fourcc = V4L2_PIX_FMT_SRGGB10,
492 .name = "Bayer 10 RGGB",
493 .bits_per_sample = 10,
494 .packing = PXA_MBUS_PACKING_EXTEND16,
495 .order = PXA_MBUS_ORDER_LE,
496 .layout = PXA_MBUS_LAYOUT_PACKED,
497 },
498 }, {
499 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
500 .fmt = {
501 .fourcc = V4L2_PIX_FMT_SBGGR12,
502 .name = "Bayer 12 BGGR",
503 .bits_per_sample = 12,
504 .packing = PXA_MBUS_PACKING_EXTEND16,
505 .order = PXA_MBUS_ORDER_LE,
506 .layout = PXA_MBUS_LAYOUT_PACKED,
507 },
508 }, {
509 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
510 .fmt = {
511 .fourcc = V4L2_PIX_FMT_SGBRG12,
512 .name = "Bayer 12 GBRG",
513 .bits_per_sample = 12,
514 .packing = PXA_MBUS_PACKING_EXTEND16,
515 .order = PXA_MBUS_ORDER_LE,
516 .layout = PXA_MBUS_LAYOUT_PACKED,
517 },
518 }, {
519 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
520 .fmt = {
521 .fourcc = V4L2_PIX_FMT_SGRBG12,
522 .name = "Bayer 12 GRBG",
523 .bits_per_sample = 12,
524 .packing = PXA_MBUS_PACKING_EXTEND16,
525 .order = PXA_MBUS_ORDER_LE,
526 .layout = PXA_MBUS_LAYOUT_PACKED,
527 },
528 }, {
529 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
530 .fmt = {
531 .fourcc = V4L2_PIX_FMT_SRGGB12,
532 .name = "Bayer 12 RGGB",
533 .bits_per_sample = 12,
534 .packing = PXA_MBUS_PACKING_EXTEND16,
535 .order = PXA_MBUS_ORDER_LE,
536 .layout = PXA_MBUS_LAYOUT_PACKED,
537 },
538 },
539 };
540
541 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
542 {
543 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
544 return width * mf->bits_per_sample / 8;
545
546 switch (mf->packing) {
547 case PXA_MBUS_PACKING_NONE:
548 return width * mf->bits_per_sample / 8;
549 case PXA_MBUS_PACKING_2X8_PADHI:
550 case PXA_MBUS_PACKING_EXTEND16:
551 return width * 2;
552 }
553 return -EINVAL;
554 }
555
556 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
557 u32 bytes_per_line, u32 height)
558 {
559 switch (mf->packing) {
560 case PXA_MBUS_PACKING_2X8_PADHI:
561 return bytes_per_line * height * 2;
562 default:
563 return -EINVAL;
564 }
565 }
566
567 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
568 u32 code,
569 const struct pxa_mbus_lookup *lookup,
570 int n)
571 {
572 int i;
573
574 for (i = 0; i < n; i++)
575 if (lookup[i].code == code)
576 return &lookup[i].fmt;
577
578 return NULL;
579 }
580
581 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
582 u32 code)
583 {
584 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
585 }
586
587 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
588 unsigned int flags)
589 {
590 unsigned long common_flags;
591 bool hsync = true, vsync = true, pclk, data, mode;
592 bool mipi_lanes, mipi_clock;
593
594 common_flags = cfg->flags & flags;
595
596 switch (cfg->type) {
597 case V4L2_MBUS_PARALLEL:
598 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
599 V4L2_MBUS_HSYNC_ACTIVE_LOW);
600 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
601 V4L2_MBUS_VSYNC_ACTIVE_LOW);
602 /* fall through */
603 case V4L2_MBUS_BT656:
604 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
605 V4L2_MBUS_PCLK_SAMPLE_FALLING);
606 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
607 V4L2_MBUS_DATA_ACTIVE_LOW);
608 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
609 return (!hsync || !vsync || !pclk || !data || !mode) ?
610 0 : common_flags;
611 case V4L2_MBUS_CSI2:
612 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
613 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
614 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
615 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
616 }
617 return 0;
618 }
619
620 /**
621 * struct soc_camera_format_xlate - match between host and sensor formats
622 * @code: code of a sensor provided format
623 * @host_fmt: host format after host translation from code
624 *
625 * Host and sensor translation structure. Used in table of host and sensor
626 * formats matchings in soc_camera_device. A host can override the generic list
627 * generation by implementing get_formats(), and use it for format checks and
628 * format setup.
629 */
630 struct soc_camera_format_xlate {
631 u32 code;
632 const struct pxa_mbus_pixelfmt *host_fmt;
633 };
634
635 /*
636 * Structures
637 */
638 enum pxa_camera_active_dma {
639 DMA_Y = 0x1,
640 DMA_U = 0x2,
641 DMA_V = 0x4,
642 };
643
644 /* buffer for one video frame */
645 struct pxa_buffer {
646 /* common v4l buffer stuff -- must be first */
647 struct vb2_v4l2_buffer vbuf;
648 struct list_head queue;
649 u32 code;
650 int nb_planes;
651 /* our descriptor lists for Y, U and V channels */
652 struct dma_async_tx_descriptor *descs[3];
653 dma_cookie_t cookie[3];
654 struct scatterlist *sg[3];
655 int sg_len[3];
656 size_t plane_sizes[3];
657 int inwork;
658 enum pxa_camera_active_dma active_dma;
659 };
660
661 struct pxa_camera_dev {
662 struct v4l2_device v4l2_dev;
663 struct video_device vdev;
664 struct v4l2_async_notifier notifier;
665 struct vb2_queue vb2_vq;
666 struct v4l2_subdev *sensor;
667 struct soc_camera_format_xlate *user_formats;
668 const struct soc_camera_format_xlate *current_fmt;
669 struct v4l2_pix_format current_pix;
670
671 struct v4l2_async_subdev asd;
672 struct v4l2_async_subdev *asds[1];
673
674 /*
675 * PXA27x is only supposed to handle one camera on its Quick Capture
676 * interface. If anyone ever builds hardware to enable more than
677 * one camera, they will have to modify this driver too
678 */
679 struct clk *clk;
680
681 unsigned int irq;
682 void __iomem *base;
683
684 int channels;
685 struct dma_chan *dma_chans[3];
686
687 struct pxacamera_platform_data *pdata;
688 struct resource *res;
689 unsigned long platform_flags;
690 unsigned long ciclk;
691 unsigned long mclk;
692 u32 mclk_divisor;
693 struct v4l2_clk *mclk_clk;
694 u16 width_flags; /* max 10 bits */
695
696 struct list_head capture;
697
698 spinlock_t lock;
699 struct mutex mlock;
700 unsigned int buf_sequence;
701
702 struct pxa_buffer *active;
703 struct tasklet_struct task_eof;
704
705 u32 save_cicr[5];
706 };
707
708 struct pxa_cam {
709 unsigned long flags;
710 };
711
712 static const char *pxa_cam_driver_description = "PXA_Camera";
713
714 /*
715 * Format translation functions
716 */
717 static const struct soc_camera_format_xlate
718 *pxa_mbus_xlate_by_fourcc(struct soc_camera_format_xlate *user_formats,
719 unsigned int fourcc)
720 {
721 unsigned int i;
722
723 for (i = 0; user_formats[i].code; i++)
724 if (user_formats[i].host_fmt->fourcc == fourcc)
725 return user_formats + i;
726 return NULL;
727 }
728
729 static struct soc_camera_format_xlate *pxa_mbus_build_fmts_xlate(
730 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
731 int (*get_formats)(struct v4l2_device *, unsigned int,
732 struct soc_camera_format_xlate *xlate))
733 {
734 unsigned int i, fmts = 0, raw_fmts = 0;
735 int ret;
736 struct v4l2_subdev_mbus_code_enum code = {
737 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
738 };
739 struct soc_camera_format_xlate *user_formats;
740
741 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
742 raw_fmts++;
743 code.index++;
744 }
745
746 /*
747 * First pass - only count formats this host-sensor
748 * configuration can provide
749 */
750 for (i = 0; i < raw_fmts; i++) {
751 ret = get_formats(v4l2_dev, i, NULL);
752 if (ret < 0)
753 return ERR_PTR(ret);
754 fmts += ret;
755 }
756
757 if (!fmts)
758 return ERR_PTR(-ENXIO);
759
760 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
761 if (!user_formats)
762 return ERR_PTR(-ENOMEM);
763
764 /* Second pass - actually fill data formats */
765 fmts = 0;
766 for (i = 0; i < raw_fmts; i++) {
767 ret = get_formats(v4l2_dev, i, user_formats + fmts);
768 if (ret < 0)
769 goto egfmt;
770 fmts += ret;
771 }
772 user_formats[fmts].code = 0;
773
774 return user_formats;
775 egfmt:
776 kfree(user_formats);
777 return ERR_PTR(ret);
778 }
779
780 /*
781 * Videobuf operations
782 */
783 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
784 {
785 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
786
787 return container_of(vbuf, struct pxa_buffer, vbuf);
788 }
789
790 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
791 {
792 return pcdev->v4l2_dev.dev;
793 }
794
795 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
796 {
797 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
798 }
799
800 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
801 enum pxa_camera_active_dma act_dma);
802
803 static void pxa_camera_dma_irq_y(void *data)
804 {
805 struct pxa_camera_dev *pcdev = data;
806
807 pxa_camera_dma_irq(pcdev, DMA_Y);
808 }
809
810 static void pxa_camera_dma_irq_u(void *data)
811 {
812 struct pxa_camera_dev *pcdev = data;
813
814 pxa_camera_dma_irq(pcdev, DMA_U);
815 }
816
817 static void pxa_camera_dma_irq_v(void *data)
818 {
819 struct pxa_camera_dev *pcdev = data;
820
821 pxa_camera_dma_irq(pcdev, DMA_V);
822 }
823
824 /**
825 * pxa_init_dma_channel - init dma descriptors
826 * @pcdev: pxa camera device
827 * @vb: videobuffer2 buffer
828 * @dma: dma video buffer
829 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
830 * @cibr: camera Receive Buffer Register
831 *
832 * Prepares the pxa dma descriptors to transfer one camera channel.
833 *
834 * Returns 0 if success or -ENOMEM if no memory is available
835 */
836 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
837 struct pxa_buffer *buf, int channel,
838 struct scatterlist *sg, int sglen)
839 {
840 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
841 struct dma_async_tx_descriptor *tx;
842
843 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
844 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
845 if (!tx) {
846 dev_err(pcdev_to_dev(pcdev),
847 "dmaengine_prep_slave_sg failed\n");
848 goto fail;
849 }
850
851 tx->callback_param = pcdev;
852 switch (channel) {
853 case 0:
854 tx->callback = pxa_camera_dma_irq_y;
855 break;
856 case 1:
857 tx->callback = pxa_camera_dma_irq_u;
858 break;
859 case 2:
860 tx->callback = pxa_camera_dma_irq_v;
861 break;
862 }
863
864 buf->descs[channel] = tx;
865 return 0;
866 fail:
867 dev_dbg(pcdev_to_dev(pcdev),
868 "%s (vb=%p) dma_tx=%p\n",
869 __func__, buf, tx);
870
871 return -ENOMEM;
872 }
873
874 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
875 struct pxa_buffer *buf)
876 {
877 buf->active_dma = DMA_Y;
878 if (buf->nb_planes == 3)
879 buf->active_dma |= DMA_U | DMA_V;
880 }
881
882 /**
883 * pxa_dma_start_channels - start DMA channel for active buffer
884 * @pcdev: pxa camera device
885 *
886 * Initialize DMA channels to the beginning of the active video buffer, and
887 * start these channels.
888 */
889 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
890 {
891 int i;
892
893 for (i = 0; i < pcdev->channels; i++) {
894 dev_dbg(pcdev_to_dev(pcdev),
895 "%s (channel=%d)\n", __func__, i);
896 dma_async_issue_pending(pcdev->dma_chans[i]);
897 }
898 }
899
900 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
901 {
902 int i;
903
904 for (i = 0; i < pcdev->channels; i++) {
905 dev_dbg(pcdev_to_dev(pcdev),
906 "%s (channel=%d)\n", __func__, i);
907 dmaengine_terminate_all(pcdev->dma_chans[i]);
908 }
909 }
910
911 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
912 struct pxa_buffer *buf)
913 {
914 int i;
915
916 for (i = 0; i < pcdev->channels; i++) {
917 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
918 dev_dbg(pcdev_to_dev(pcdev),
919 "%s (channel=%d) : submit vb=%p cookie=%d\n",
920 __func__, i, buf, buf->descs[i]->cookie);
921 }
922 }
923
924 /**
925 * pxa_camera_start_capture - start video capturing
926 * @pcdev: camera device
927 *
928 * Launch capturing. DMA channels should not be active yet. They should get
929 * activated at the end of frame interrupt, to capture only whole frames, and
930 * never begin the capture of a partial frame.
931 */
932 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
933 {
934 unsigned long cicr0;
935
936 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
937 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
938 /* Enable End-Of-Frame Interrupt */
939 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
940 cicr0 &= ~CICR0_EOFM;
941 __raw_writel(cicr0, pcdev->base + CICR0);
942 }
943
944 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
945 {
946 unsigned long cicr0;
947
948 pxa_dma_stop_channels(pcdev);
949
950 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
951 __raw_writel(cicr0, pcdev->base + CICR0);
952
953 pcdev->active = NULL;
954 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
955 }
956
957 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
958 struct pxa_buffer *buf,
959 enum vb2_buffer_state state)
960 {
961 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
962 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
963
964 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
965 list_del_init(&buf->queue);
966 vb->timestamp = ktime_get_ns();
967 vbuf->sequence = pcdev->buf_sequence++;
968 vbuf->field = V4L2_FIELD_NONE;
969 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
970 dev_dbg(pcdev_to_dev(pcdev), "%s dequeud buffer (buf=0x%p)\n",
971 __func__, buf);
972
973 if (list_empty(&pcdev->capture)) {
974 pxa_camera_stop_capture(pcdev);
975 return;
976 }
977
978 pcdev->active = list_entry(pcdev->capture.next,
979 struct pxa_buffer, queue);
980 }
981
982 /**
983 * pxa_camera_check_link_miss - check missed DMA linking
984 * @pcdev: camera device
985 *
986 * The DMA chaining is done with DMA running. This means a tiny temporal window
987 * remains, where a buffer is queued on the chain, while the chain is already
988 * stopped. This means the tailed buffer would never be transferred by DMA.
989 * This function restarts the capture for this corner case, where :
990 * - DADR() == DADDR_STOP
991 * - a videobuffer is queued on the pcdev->capture list
992 *
993 * Please check the "DMA hot chaining timeslice issue" in
994 * Documentation/video4linux/pxa_camera.txt
995 *
996 * Context: should only be called within the dma irq handler
997 */
998 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
999 dma_cookie_t last_submitted,
1000 dma_cookie_t last_issued)
1001 {
1002 bool is_dma_stopped = last_submitted != last_issued;
1003
1004 dev_dbg(pcdev_to_dev(pcdev),
1005 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1006 __func__, pcdev->active, is_dma_stopped);
1007
1008 if (pcdev->active && is_dma_stopped)
1009 pxa_camera_start_capture(pcdev);
1010 }
1011
1012 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1013 enum pxa_camera_active_dma act_dma)
1014 {
1015 struct pxa_buffer *buf, *last_buf;
1016 unsigned long flags;
1017 u32 camera_status, overrun;
1018 int chan;
1019 enum dma_status last_status;
1020 dma_cookie_t last_issued;
1021
1022 spin_lock_irqsave(&pcdev->lock, flags);
1023
1024 camera_status = __raw_readl(pcdev->base + CISR);
1025 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1026 camera_status, act_dma);
1027 overrun = CISR_IFO_0;
1028 if (pcdev->channels == 3)
1029 overrun |= CISR_IFO_1 | CISR_IFO_2;
1030
1031 /*
1032 * pcdev->active should not be NULL in DMA irq handler.
1033 *
1034 * But there is one corner case : if capture was stopped due to an
1035 * overrun of channel 1, and at that same channel 2 was completed.
1036 *
1037 * When handling the overrun in DMA irq for channel 1, we'll stop the
1038 * capture and restart it (and thus set pcdev->active to NULL). But the
1039 * DMA irq handler will already be pending for channel 2. So on entering
1040 * the DMA irq handler for channel 2 there will be no active buffer, yet
1041 * that is normal.
1042 */
1043 if (!pcdev->active)
1044 goto out;
1045
1046 buf = pcdev->active;
1047 WARN_ON(buf->inwork || list_empty(&buf->queue));
1048
1049 /*
1050 * It's normal if the last frame creates an overrun, as there
1051 * are no more DMA descriptors to fetch from QCI fifos
1052 */
1053 switch (act_dma) {
1054 case DMA_U:
1055 chan = 1;
1056 break;
1057 case DMA_V:
1058 chan = 2;
1059 break;
1060 default:
1061 chan = 0;
1062 break;
1063 }
1064 last_buf = list_entry(pcdev->capture.prev,
1065 struct pxa_buffer, queue);
1066 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1067 last_buf->cookie[chan],
1068 NULL, &last_issued);
1069 if (camera_status & overrun &&
1070 last_status != DMA_COMPLETE) {
1071 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1072 camera_status);
1073 pxa_camera_stop_capture(pcdev);
1074 list_for_each_entry(buf, &pcdev->capture, queue)
1075 pxa_dma_add_tail_buf(pcdev, buf);
1076 pxa_camera_start_capture(pcdev);
1077 goto out;
1078 }
1079 buf->active_dma &= ~act_dma;
1080 if (!buf->active_dma) {
1081 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1082 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1083 last_issued);
1084 }
1085
1086 out:
1087 spin_unlock_irqrestore(&pcdev->lock, flags);
1088 }
1089
1090 static u32 mclk_get_divisor(struct platform_device *pdev,
1091 struct pxa_camera_dev *pcdev)
1092 {
1093 unsigned long mclk = pcdev->mclk;
1094 u32 div;
1095 unsigned long lcdclk;
1096
1097 lcdclk = clk_get_rate(pcdev->clk);
1098 pcdev->ciclk = lcdclk;
1099
1100 /* mclk <= ciclk / 4 (27.4.2) */
1101 if (mclk > lcdclk / 4) {
1102 mclk = lcdclk / 4;
1103 dev_warn(pcdev_to_dev(pcdev),
1104 "Limiting master clock to %lu\n", mclk);
1105 }
1106
1107 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1108 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1109
1110 /* If we're not supplying MCLK, leave it at 0 */
1111 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1112 pcdev->mclk = lcdclk / (2 * (div + 1));
1113
1114 dev_dbg(pcdev_to_dev(pcdev), "LCD clock %luHz, target freq %luHz, divisor %u\n",
1115 lcdclk, mclk, div);
1116
1117 return div;
1118 }
1119
1120 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1121 unsigned long pclk)
1122 {
1123 /* We want a timeout > 1 pixel time, not ">=" */
1124 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1125
1126 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1127 }
1128
1129 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1130 {
1131 u32 cicr4 = 0;
1132
1133 /* disable all interrupts */
1134 __raw_writel(0x3ff, pcdev->base + CICR0);
1135
1136 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1137 cicr4 |= CICR4_PCLK_EN;
1138 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1139 cicr4 |= CICR4_MCLK_EN;
1140 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1141 cicr4 |= CICR4_PCP;
1142 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1143 cicr4 |= CICR4_HSP;
1144 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1145 cicr4 |= CICR4_VSP;
1146
1147 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1148
1149 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1150 /* Initialise the timeout under the assumption pclk = mclk */
1151 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1152 else
1153 /* "Safe default" - 13MHz */
1154 recalculate_fifo_timeout(pcdev, 13000000);
1155
1156 clk_prepare_enable(pcdev->clk);
1157 }
1158
1159 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1160 {
1161 clk_disable_unprepare(pcdev->clk);
1162 }
1163
1164 static void pxa_camera_eof(unsigned long arg)
1165 {
1166 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1167 unsigned long cifr;
1168 struct pxa_buffer *buf;
1169
1170 dev_dbg(pcdev_to_dev(pcdev),
1171 "Camera interrupt status 0x%x\n",
1172 __raw_readl(pcdev->base + CISR));
1173
1174 /* Reset the FIFOs */
1175 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1176 __raw_writel(cifr, pcdev->base + CIFR);
1177
1178 pcdev->active = list_first_entry(&pcdev->capture,
1179 struct pxa_buffer, queue);
1180 buf = pcdev->active;
1181 pxa_videobuf_set_actdma(pcdev, buf);
1182
1183 pxa_dma_start_channels(pcdev);
1184 }
1185
1186 static irqreturn_t pxa_camera_irq(int irq, void *data)
1187 {
1188 struct pxa_camera_dev *pcdev = data;
1189 unsigned long status, cicr0;
1190
1191 status = __raw_readl(pcdev->base + CISR);
1192 dev_dbg(pcdev_to_dev(pcdev),
1193 "Camera interrupt status 0x%lx\n", status);
1194
1195 if (!status)
1196 return IRQ_NONE;
1197
1198 __raw_writel(status, pcdev->base + CISR);
1199
1200 if (status & CISR_EOF) {
1201 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1202 __raw_writel(cicr0, pcdev->base + CICR0);
1203 tasklet_schedule(&pcdev->task_eof);
1204 }
1205
1206 return IRQ_HANDLED;
1207 }
1208
1209 static int test_platform_param(struct pxa_camera_dev *pcdev,
1210 unsigned char buswidth, unsigned long *flags)
1211 {
1212 /*
1213 * Platform specified synchronization and pixel clock polarities are
1214 * only a recommendation and are only used during probing. The PXA270
1215 * quick capture interface supports both.
1216 */
1217 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1218 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1219 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1220 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1221 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1222 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1223 V4L2_MBUS_DATA_ACTIVE_HIGH |
1224 V4L2_MBUS_PCLK_SAMPLE_RISING |
1225 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1226
1227 /* If requested data width is supported by the platform, use it */
1228 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1229 return 0;
1230
1231 return -EINVAL;
1232 }
1233
1234 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1235 unsigned long flags, __u32 pixfmt)
1236 {
1237 unsigned long dw, bpp;
1238 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1239 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1240
1241 if (ret < 0)
1242 y_skip_top = 0;
1243
1244 /*
1245 * Datawidth is now guaranteed to be equal to one of the three values.
1246 * We fix bit-per-pixel equal to data-width...
1247 */
1248 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1249 case 10:
1250 dw = 4;
1251 bpp = 0x40;
1252 break;
1253 case 9:
1254 dw = 3;
1255 bpp = 0x20;
1256 break;
1257 default:
1258 /*
1259 * Actually it can only be 8 now,
1260 * default is just to silence compiler warnings
1261 */
1262 case 8:
1263 dw = 2;
1264 bpp = 0;
1265 }
1266
1267 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1268 cicr4 |= CICR4_PCLK_EN;
1269 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1270 cicr4 |= CICR4_MCLK_EN;
1271 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1272 cicr4 |= CICR4_PCP;
1273 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1274 cicr4 |= CICR4_HSP;
1275 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1276 cicr4 |= CICR4_VSP;
1277
1278 cicr0 = __raw_readl(pcdev->base + CICR0);
1279 if (cicr0 & CICR0_ENB)
1280 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1281
1282 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1283
1284 switch (pixfmt) {
1285 case V4L2_PIX_FMT_YUV422P:
1286 pcdev->channels = 3;
1287 cicr1 |= CICR1_YCBCR_F;
1288 /*
1289 * Normally, pxa bus wants as input UYVY format. We allow all
1290 * reorderings of the YUV422 format, as no processing is done,
1291 * and the YUV stream is just passed through without any
1292 * transformation. Note that UYVY is the only format that
1293 * should be used if pxa framebuffer Overlay2 is used.
1294 */
1295 case V4L2_PIX_FMT_UYVY:
1296 case V4L2_PIX_FMT_VYUY:
1297 case V4L2_PIX_FMT_YUYV:
1298 case V4L2_PIX_FMT_YVYU:
1299 cicr1 |= CICR1_COLOR_SP_VAL(2);
1300 break;
1301 case V4L2_PIX_FMT_RGB555:
1302 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1303 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1304 break;
1305 case V4L2_PIX_FMT_RGB565:
1306 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1307 break;
1308 }
1309
1310 cicr2 = 0;
1311 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1312 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1313 cicr4 |= pcdev->mclk_divisor;
1314
1315 __raw_writel(cicr1, pcdev->base + CICR1);
1316 __raw_writel(cicr2, pcdev->base + CICR2);
1317 __raw_writel(cicr3, pcdev->base + CICR3);
1318 __raw_writel(cicr4, pcdev->base + CICR4);
1319
1320 /* CIF interrupts are not used, only DMA */
1321 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1322 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1323 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1324 __raw_writel(cicr0, pcdev->base + CICR0);
1325 }
1326
1327 /*
1328 * Videobuf2 section
1329 */
1330 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1331 {
1332 int i;
1333
1334 for (i = 0; i < 3 && buf->descs[i]; i++) {
1335 dmaengine_desc_free(buf->descs[i]);
1336 kfree(buf->sg[i]);
1337 buf->descs[i] = NULL;
1338 buf->sg[i] = NULL;
1339 buf->sg_len[i] = 0;
1340 buf->plane_sizes[i] = 0;
1341 }
1342 buf->nb_planes = 0;
1343 }
1344
1345 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1346 struct pxa_buffer *buf)
1347 {
1348 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1349 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1350 int nb_channels = pcdev->channels;
1351 int i, ret = 0;
1352 unsigned long size = vb2_plane_size(vb, 0);
1353
1354 switch (nb_channels) {
1355 case 1:
1356 buf->plane_sizes[0] = size;
1357 break;
1358 case 3:
1359 buf->plane_sizes[0] = size / 2;
1360 buf->plane_sizes[1] = size / 4;
1361 buf->plane_sizes[2] = size / 4;
1362 break;
1363 default:
1364 return -EINVAL;
1365 };
1366 buf->nb_planes = nb_channels;
1367
1368 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1369 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1370 if (ret < 0) {
1371 dev_err(pcdev_to_dev(pcdev),
1372 "sg_split failed: %d\n", ret);
1373 return ret;
1374 }
1375 for (i = 0; i < nb_channels; i++) {
1376 ret = pxa_init_dma_channel(pcdev, buf, i,
1377 buf->sg[i], buf->sg_len[i]);
1378 if (ret) {
1379 pxa_buffer_cleanup(buf);
1380 return ret;
1381 }
1382 }
1383 INIT_LIST_HEAD(&buf->queue);
1384
1385 return ret;
1386 }
1387
1388 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1389 {
1390 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1391 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1392
1393 dev_dbg(pcdev_to_dev(pcdev),
1394 "%s(vb=%p)\n", __func__, vb);
1395 pxa_buffer_cleanup(buf);
1396 }
1397
1398 static void pxac_vb2_queue(struct vb2_buffer *vb)
1399 {
1400 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1401 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1402
1403 dev_dbg(pcdev_to_dev(pcdev),
1404 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1405 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1406 pcdev->active);
1407
1408 list_add_tail(&buf->queue, &pcdev->capture);
1409
1410 pxa_dma_add_tail_buf(pcdev, buf);
1411 }
1412
1413 /*
1414 * Please check the DMA prepared buffer structure in :
1415 * Documentation/video4linux/pxa_camera.txt
1416 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1417 * modification while DMA chain is running will work anyway.
1418 */
1419 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1420 {
1421 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1422 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1423 int ret = 0;
1424
1425 switch (pcdev->channels) {
1426 case 1:
1427 case 3:
1428 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1429 break;
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 dev_dbg(pcdev_to_dev(pcdev),
1435 "%s (vb=%p) nb_channels=%d size=%lu\n",
1436 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1437
1438 WARN_ON(!pcdev->current_fmt);
1439
1440 #ifdef DEBUG
1441 /*
1442 * This can be useful if you want to see if we actually fill
1443 * the buffer with something
1444 */
1445 for (i = 0; i < vb->num_planes; i++)
1446 memset((void *)vb2_plane_vaddr(vb, i),
1447 0xaa, vb2_get_plane_payload(vb, i));
1448 #endif
1449
1450 /*
1451 * I think, in buf_prepare you only have to protect global data,
1452 * the actual buffer is yours
1453 */
1454 buf->inwork = 0;
1455 pxa_videobuf_set_actdma(pcdev, buf);
1456
1457 return ret;
1458 }
1459
1460 static int pxac_vb2_init(struct vb2_buffer *vb)
1461 {
1462 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1463 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1464
1465 dev_dbg(pcdev_to_dev(pcdev),
1466 "%s(nb_channels=%d)\n",
1467 __func__, pcdev->channels);
1468
1469 return pxa_buffer_init(pcdev, buf);
1470 }
1471
1472 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1473 unsigned int *nbufs,
1474 unsigned int *num_planes, unsigned int sizes[],
1475 struct device *alloc_devs[])
1476 {
1477 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1478 int size = pcdev->current_pix.sizeimage;
1479
1480 dev_dbg(pcdev_to_dev(pcdev),
1481 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1482 __func__, vq, *nbufs, *num_planes, size);
1483 /*
1484 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1485 * format, even if there are 3 planes Y, U and V, we reply there is only
1486 * one plane, containing Y, U and V data, one after the other.
1487 */
1488 if (*num_planes)
1489 return sizes[0] < size ? -EINVAL : 0;
1490
1491 *num_planes = 1;
1492 switch (pcdev->channels) {
1493 case 1:
1494 case 3:
1495 sizes[0] = size;
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 if (!*nbufs)
1502 *nbufs = 1;
1503
1504 return 0;
1505 }
1506
1507 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1508 {
1509 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1510
1511 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1512 __func__, count, pcdev->active);
1513
1514 pcdev->buf_sequence = 0;
1515 if (!pcdev->active)
1516 pxa_camera_start_capture(pcdev);
1517
1518 return 0;
1519 }
1520
1521 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1522 {
1523 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1524 struct pxa_buffer *buf, *tmp;
1525
1526 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1527 __func__, pcdev->active);
1528 pxa_camera_stop_capture(pcdev);
1529
1530 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1531 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1532 }
1533
1534 static struct vb2_ops pxac_vb2_ops = {
1535 .queue_setup = pxac_vb2_queue_setup,
1536 .buf_init = pxac_vb2_init,
1537 .buf_prepare = pxac_vb2_prepare,
1538 .buf_queue = pxac_vb2_queue,
1539 .buf_cleanup = pxac_vb2_cleanup,
1540 .start_streaming = pxac_vb2_start_streaming,
1541 .stop_streaming = pxac_vb2_stop_streaming,
1542 .wait_prepare = vb2_ops_wait_prepare,
1543 .wait_finish = vb2_ops_wait_finish,
1544 };
1545
1546 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1547 {
1548 int ret;
1549 struct vb2_queue *vq = &pcdev->vb2_vq;
1550
1551 memset(vq, 0, sizeof(*vq));
1552 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1553 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1554 vq->drv_priv = pcdev;
1555 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1556 vq->buf_struct_size = sizeof(struct pxa_buffer);
1557 vq->dev = pcdev->v4l2_dev.dev;
1558
1559 vq->ops = &pxac_vb2_ops;
1560 vq->mem_ops = &vb2_dma_sg_memops;
1561 vq->lock = &pcdev->mlock;
1562
1563 ret = vb2_queue_init(vq);
1564 dev_dbg(pcdev_to_dev(pcdev),
1565 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1566
1567 return ret;
1568 }
1569
1570 /*
1571 * Video ioctls section
1572 */
1573 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1574 {
1575 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1576 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1577 unsigned long bus_flags, common_flags;
1578 int ret;
1579
1580 ret = test_platform_param(pcdev,
1581 pcdev->current_fmt->host_fmt->bits_per_sample,
1582 &bus_flags);
1583 if (ret < 0)
1584 return ret;
1585
1586 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1587 if (!ret) {
1588 common_flags = pxa_mbus_config_compatible(&cfg,
1589 bus_flags);
1590 if (!common_flags) {
1591 dev_warn(pcdev_to_dev(pcdev),
1592 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1593 cfg.flags, bus_flags);
1594 return -EINVAL;
1595 }
1596 } else if (ret != -ENOIOCTLCMD) {
1597 return ret;
1598 } else {
1599 common_flags = bus_flags;
1600 }
1601
1602 pcdev->channels = 1;
1603
1604 /* Make choises, based on platform preferences */
1605 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1606 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1607 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1608 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1609 else
1610 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1611 }
1612
1613 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1614 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1615 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1616 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1617 else
1618 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1619 }
1620
1621 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1622 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1623 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1624 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1625 else
1626 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1627 }
1628
1629 cfg.flags = common_flags;
1630 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1631 if (ret < 0 && ret != -ENOIOCTLCMD) {
1632 dev_dbg(pcdev_to_dev(pcdev),
1633 "camera s_mbus_config(0x%lx) returned %d\n",
1634 common_flags, ret);
1635 return ret;
1636 }
1637
1638 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1639
1640 return 0;
1641 }
1642
1643 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1644 unsigned char buswidth)
1645 {
1646 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1647 unsigned long bus_flags, common_flags;
1648 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1649
1650 if (ret < 0)
1651 return ret;
1652
1653 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1654 if (!ret) {
1655 common_flags = pxa_mbus_config_compatible(&cfg,
1656 bus_flags);
1657 if (!common_flags) {
1658 dev_warn(pcdev_to_dev(pcdev),
1659 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1660 cfg.flags, bus_flags);
1661 return -EINVAL;
1662 }
1663 } else if (ret == -ENOIOCTLCMD) {
1664 ret = 0;
1665 }
1666
1667 return ret;
1668 }
1669
1670 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1671 {
1672 .fourcc = V4L2_PIX_FMT_YUV422P,
1673 .name = "Planar YUV422 16 bit",
1674 .bits_per_sample = 8,
1675 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1676 .order = PXA_MBUS_ORDER_LE,
1677 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1678 },
1679 };
1680
1681 /* This will be corrected as we get more formats */
1682 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1683 {
1684 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1685 (fmt->bits_per_sample == 8 &&
1686 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1687 (fmt->bits_per_sample > 8 &&
1688 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1689 }
1690
1691 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1692 unsigned int idx,
1693 struct soc_camera_format_xlate *xlate)
1694 {
1695 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1696 int formats = 0, ret;
1697 struct v4l2_subdev_mbus_code_enum code = {
1698 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1699 .index = idx,
1700 };
1701 const struct pxa_mbus_pixelfmt *fmt;
1702
1703 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1704 if (ret < 0)
1705 /* No more formats */
1706 return 0;
1707
1708 fmt = pxa_mbus_get_fmtdesc(code.code);
1709 if (!fmt) {
1710 dev_err(pcdev_to_dev(pcdev),
1711 "Invalid format code #%u: %d\n", idx, code.code);
1712 return 0;
1713 }
1714
1715 /* This also checks support for the requested bits-per-sample */
1716 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1717 if (ret < 0)
1718 return 0;
1719
1720 switch (code.code) {
1721 case MEDIA_BUS_FMT_UYVY8_2X8:
1722 formats++;
1723 if (xlate) {
1724 xlate->host_fmt = &pxa_camera_formats[0];
1725 xlate->code = code.code;
1726 xlate++;
1727 dev_dbg(pcdev_to_dev(pcdev),
1728 "Providing format %s using code %d\n",
1729 pxa_camera_formats[0].name, code.code);
1730 }
1731 /* fall through */
1732 case MEDIA_BUS_FMT_VYUY8_2X8:
1733 case MEDIA_BUS_FMT_YUYV8_2X8:
1734 case MEDIA_BUS_FMT_YVYU8_2X8:
1735 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1736 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1737 if (xlate)
1738 dev_dbg(pcdev_to_dev(pcdev),
1739 "Providing format %s packed\n",
1740 fmt->name);
1741 break;
1742 default:
1743 if (!pxa_camera_packing_supported(fmt))
1744 return 0;
1745 if (xlate)
1746 dev_dbg(pcdev_to_dev(pcdev),
1747 "Providing format %s in pass-through mode\n",
1748 fmt->name);
1749 break;
1750 }
1751
1752 /* Generic pass-through */
1753 formats++;
1754 if (xlate) {
1755 xlate->host_fmt = fmt;
1756 xlate->code = code.code;
1757 xlate++;
1758 }
1759
1760 return formats;
1761 }
1762
1763 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1764 {
1765 struct soc_camera_format_xlate *xlate;
1766
1767 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1768 pxa_camera_get_formats);
1769 if (IS_ERR(xlate))
1770 return PTR_ERR(xlate);
1771
1772 pcdev->user_formats = xlate;
1773 return 0;
1774 }
1775
1776 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1777 {
1778 kfree(pcdev->user_formats);
1779 }
1780
1781 static int pxa_camera_check_frame(u32 width, u32 height)
1782 {
1783 /* limit to pxa hardware capabilities */
1784 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1785 (width & 0x01);
1786 }
1787
1788 #ifdef CONFIG_VIDEO_ADV_DEBUG
1789 static int pxac_vidioc_g_register(struct file *file, void *priv,
1790 struct v4l2_dbg_register *reg)
1791 {
1792 struct pxa_camera_dev *pcdev = video_drvdata(file);
1793
1794 if (reg->reg > CIBR2)
1795 return -ERANGE;
1796
1797 reg->val = __raw_readl(pcdev->base + reg->reg);
1798 reg->size = sizeof(__u32);
1799 return 0;
1800 }
1801
1802 static int pxac_vidioc_s_register(struct file *file, void *priv,
1803 const struct v4l2_dbg_register *reg)
1804 {
1805 struct pxa_camera_dev *pcdev = video_drvdata(file);
1806
1807 if (reg->reg > CIBR2)
1808 return -ERANGE;
1809 if (reg->size != sizeof(__u32))
1810 return -EINVAL;
1811 __raw_writel(reg->val, pcdev->base + reg->reg);
1812 return 0;
1813 }
1814 #endif
1815
1816 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1817 struct v4l2_fmtdesc *f)
1818 {
1819 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1820 const struct pxa_mbus_pixelfmt *format;
1821 unsigned int idx;
1822
1823 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1824 if (f->index >= idx)
1825 return -EINVAL;
1826
1827 format = pcdev->user_formats[f->index].host_fmt;
1828 f->pixelformat = format->fourcc;
1829 return 0;
1830 }
1831
1832 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1833 struct v4l2_format *f)
1834 {
1835 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1836 struct v4l2_pix_format *pix = &f->fmt.pix;
1837
1838 pix->width = pcdev->current_pix.width;
1839 pix->height = pcdev->current_pix.height;
1840 pix->bytesperline = pcdev->current_pix.bytesperline;
1841 pix->sizeimage = pcdev->current_pix.sizeimage;
1842 pix->field = pcdev->current_pix.field;
1843 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1844 pix->colorspace = pcdev->current_pix.colorspace;
1845 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1846 pcdev->current_fmt->host_fmt->fourcc);
1847 return 0;
1848 }
1849
1850 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1851 struct v4l2_format *f)
1852 {
1853 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1854 const struct soc_camera_format_xlate *xlate;
1855 struct v4l2_pix_format *pix = &f->fmt.pix;
1856 struct v4l2_subdev_pad_config pad_cfg;
1857 struct v4l2_subdev_format format = {
1858 .which = V4L2_SUBDEV_FORMAT_TRY,
1859 };
1860 struct v4l2_mbus_framefmt *mf = &format.format;
1861 __u32 pixfmt = pix->pixelformat;
1862 int ret;
1863
1864 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1865 if (!xlate) {
1866 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1867 return -EINVAL;
1868 }
1869
1870 /*
1871 * Limit to pxa hardware capabilities. YUV422P planar format requires
1872 * images size to be a multiple of 16 bytes. If not, zeros will be
1873 * inserted between Y and U planes, and U and V planes, which violates
1874 * the YUV422P standard.
1875 */
1876 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1877 &pix->height, 32, 2048, 0,
1878 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1879
1880 v4l2_fill_mbus_format(mf, pix, xlate->code);
1881 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1882 if (ret < 0)
1883 return ret;
1884
1885 v4l2_fill_pix_format(pix, mf);
1886
1887 /* Only progressive video supported so far */
1888 switch (mf->field) {
1889 case V4L2_FIELD_ANY:
1890 case V4L2_FIELD_NONE:
1891 pix->field = V4L2_FIELD_NONE;
1892 break;
1893 default:
1894 /* TODO: support interlaced at least in pass-through mode */
1895 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1896 mf->field);
1897 return -EINVAL;
1898 }
1899
1900 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1901 if (ret < 0)
1902 return ret;
1903
1904 pix->bytesperline = ret;
1905 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1906 pix->height);
1907 if (ret < 0)
1908 return ret;
1909
1910 pix->sizeimage = ret;
1911 return 0;
1912 }
1913
1914 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1915 struct v4l2_format *f)
1916 {
1917 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1918 const struct soc_camera_format_xlate *xlate;
1919 struct v4l2_pix_format *pix = &f->fmt.pix;
1920 struct v4l2_subdev_format format = {
1921 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1922 };
1923 unsigned long flags;
1924 int ret, is_busy;
1925
1926 dev_dbg(pcdev_to_dev(pcdev),
1927 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1928 pix->width, pix->height, pix->pixelformat);
1929
1930 spin_lock_irqsave(&pcdev->lock, flags);
1931 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1932 spin_unlock_irqrestore(&pcdev->lock, flags);
1933
1934 if (is_busy)
1935 return -EBUSY;
1936
1937 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1938 if (ret)
1939 return ret;
1940
1941 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1942 pix->pixelformat);
1943 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1944 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1945 if (ret < 0) {
1946 dev_warn(pcdev_to_dev(pcdev),
1947 "Failed to configure for format %x\n",
1948 pix->pixelformat);
1949 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1950 dev_warn(pcdev_to_dev(pcdev),
1951 "Camera driver produced an unsupported frame %dx%d\n",
1952 pix->width, pix->height);
1953 return -EINVAL;
1954 }
1955
1956 pcdev->current_fmt = xlate;
1957 pcdev->current_pix = *pix;
1958
1959 ret = pxa_camera_set_bus_param(pcdev);
1960 return ret;
1961 }
1962
1963 static int pxac_vidioc_querycap(struct file *file, void *priv,
1964 struct v4l2_capability *cap)
1965 {
1966 strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1967 strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1968 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1969 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1970 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1971
1972 return 0;
1973 }
1974
1975 static int pxac_vidioc_enum_input(struct file *file, void *priv,
1976 struct v4l2_input *i)
1977 {
1978 if (i->index > 0)
1979 return -EINVAL;
1980
1981 i->type = V4L2_INPUT_TYPE_CAMERA;
1982 strlcpy(i->name, "Camera", sizeof(i->name));
1983
1984 return 0;
1985 }
1986
1987 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1988 {
1989 *i = 0;
1990
1991 return 0;
1992 }
1993
1994 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1995 {
1996 if (i > 0)
1997 return -EINVAL;
1998
1999 return 0;
2000 }
2001
2002 static int pxac_fops_camera_open(struct file *filp)
2003 {
2004 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2005 int ret;
2006
2007 mutex_lock(&pcdev->mlock);
2008 ret = v4l2_fh_open(filp);
2009 if (ret < 0)
2010 goto out;
2011
2012 ret = sensor_call(pcdev, core, s_power, 1);
2013 if (ret)
2014 v4l2_fh_release(filp);
2015 out:
2016 mutex_unlock(&pcdev->mlock);
2017 return ret;
2018 }
2019
2020 static int pxac_fops_camera_release(struct file *filp)
2021 {
2022 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2023 int ret;
2024
2025 ret = vb2_fop_release(filp);
2026 if (ret < 0)
2027 return ret;
2028
2029 mutex_lock(&pcdev->mlock);
2030 ret = sensor_call(pcdev, core, s_power, 0);
2031 mutex_unlock(&pcdev->mlock);
2032
2033 return ret;
2034 }
2035
2036 static const struct v4l2_file_operations pxa_camera_fops = {
2037 .owner = THIS_MODULE,
2038 .open = pxac_fops_camera_open,
2039 .release = pxac_fops_camera_release,
2040 .read = vb2_fop_read,
2041 .poll = vb2_fop_poll,
2042 .mmap = vb2_fop_mmap,
2043 .unlocked_ioctl = video_ioctl2,
2044 };
2045
2046 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2047 .vidioc_querycap = pxac_vidioc_querycap,
2048
2049 .vidioc_enum_input = pxac_vidioc_enum_input,
2050 .vidioc_g_input = pxac_vidioc_g_input,
2051 .vidioc_s_input = pxac_vidioc_s_input,
2052
2053 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2054 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2055 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2056 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2057
2058 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2059 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2060 .vidioc_querybuf = vb2_ioctl_querybuf,
2061 .vidioc_qbuf = vb2_ioctl_qbuf,
2062 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2063 .vidioc_expbuf = vb2_ioctl_expbuf,
2064 .vidioc_streamon = vb2_ioctl_streamon,
2065 .vidioc_streamoff = vb2_ioctl_streamoff,
2066 #ifdef CONFIG_VIDEO_ADV_DEBUG
2067 .vidioc_g_register = pxac_vidioc_g_register,
2068 .vidioc_s_register = pxac_vidioc_s_register,
2069 #endif
2070 };
2071
2072 static struct v4l2_clk_ops pxa_camera_mclk_ops = {
2073 };
2074
2075 static const struct video_device pxa_camera_videodev_template = {
2076 .name = "pxa-camera",
2077 .minor = -1,
2078 .fops = &pxa_camera_fops,
2079 .ioctl_ops = &pxa_camera_ioctl_ops,
2080 .release = video_device_release_empty,
2081 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2082 };
2083
2084 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2085 struct v4l2_subdev *subdev,
2086 struct v4l2_async_subdev *asd)
2087 {
2088 int err;
2089 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2090 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2091 struct video_device *vdev = &pcdev->vdev;
2092 struct v4l2_pix_format *pix = &pcdev->current_pix;
2093 struct v4l2_subdev_format format = {
2094 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2095 };
2096 struct v4l2_mbus_framefmt *mf = &format.format;
2097
2098 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2099 __func__);
2100 mutex_lock(&pcdev->mlock);
2101 *vdev = pxa_camera_videodev_template;
2102 vdev->v4l2_dev = v4l2_dev;
2103 vdev->lock = &pcdev->mlock;
2104 pcdev->sensor = subdev;
2105 pcdev->vdev.queue = &pcdev->vb2_vq;
2106 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2107 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2108 video_set_drvdata(&pcdev->vdev, pcdev);
2109
2110 err = pxa_camera_build_formats(pcdev);
2111 if (err) {
2112 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2113 err);
2114 goto out;
2115 }
2116
2117 pcdev->current_fmt = pcdev->user_formats;
2118 pix->field = V4L2_FIELD_NONE;
2119 pix->width = DEFAULT_WIDTH;
2120 pix->height = DEFAULT_HEIGHT;
2121 pix->bytesperline =
2122 pxa_mbus_bytes_per_line(pix->width,
2123 pcdev->current_fmt->host_fmt);
2124 pix->sizeimage =
2125 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2126 pix->bytesperline, pix->height);
2127 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2128 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2129 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2130 if (err)
2131 goto out;
2132
2133 v4l2_fill_pix_format(pix, mf);
2134 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2135 __func__, pix->colorspace, pix->pixelformat);
2136
2137 err = pxa_camera_init_videobuf2(pcdev);
2138 if (err)
2139 goto out;
2140
2141 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2142 if (err) {
2143 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2144 pcdev->sensor = NULL;
2145 } else {
2146 dev_info(pcdev_to_dev(pcdev),
2147 "PXA Camera driver attached to camera %s\n",
2148 subdev->name);
2149 }
2150 out:
2151 mutex_unlock(&pcdev->mlock);
2152 return err;
2153 }
2154
2155 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2156 struct v4l2_subdev *subdev,
2157 struct v4l2_async_subdev *asd)
2158 {
2159 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2160
2161 mutex_lock(&pcdev->mlock);
2162 dev_info(pcdev_to_dev(pcdev),
2163 "PXA Camera driver detached from camera %s\n",
2164 subdev->name);
2165
2166 /* disable capture, disable interrupts */
2167 __raw_writel(0x3ff, pcdev->base + CICR0);
2168
2169 /* Stop DMA engine */
2170 pxa_dma_stop_channels(pcdev);
2171
2172 pxa_camera_destroy_formats(pcdev);
2173 video_unregister_device(&pcdev->vdev);
2174 pcdev->sensor = NULL;
2175
2176 mutex_unlock(&pcdev->mlock);
2177 }
2178
2179 /*
2180 * Driver probe, remove, suspend and resume operations
2181 */
2182 static int pxa_camera_suspend(struct device *dev)
2183 {
2184 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2185 int i = 0, ret = 0;
2186
2187 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2188 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2189 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2190 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2191 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2192
2193 if (pcdev->sensor) {
2194 ret = sensor_call(pcdev, core, s_power, 0);
2195 if (ret == -ENOIOCTLCMD)
2196 ret = 0;
2197 }
2198
2199 return ret;
2200 }
2201
2202 static int pxa_camera_resume(struct device *dev)
2203 {
2204 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2205 int i = 0, ret = 0;
2206
2207 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2208 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2209 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2210 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2211 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2212
2213 if (pcdev->sensor) {
2214 ret = sensor_call(pcdev, core, s_power, 1);
2215 if (ret == -ENOIOCTLCMD)
2216 ret = 0;
2217 }
2218
2219 /* Restart frame capture if active buffer exists */
2220 if (!ret && pcdev->active)
2221 pxa_camera_start_capture(pcdev);
2222
2223 return ret;
2224 }
2225
2226 static int pxa_camera_pdata_from_dt(struct device *dev,
2227 struct pxa_camera_dev *pcdev,
2228 struct v4l2_async_subdev *asd)
2229 {
2230 u32 mclk_rate;
2231 struct device_node *remote, *np = dev->of_node;
2232 struct v4l2_of_endpoint ep;
2233 int err = of_property_read_u32(np, "clock-frequency",
2234 &mclk_rate);
2235 if (!err) {
2236 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2237 pcdev->mclk = mclk_rate;
2238 }
2239
2240 np = of_graph_get_next_endpoint(np, NULL);
2241 if (!np) {
2242 dev_err(dev, "could not find endpoint\n");
2243 return -EINVAL;
2244 }
2245
2246 err = v4l2_of_parse_endpoint(np, &ep);
2247 if (err) {
2248 dev_err(dev, "could not parse endpoint\n");
2249 goto out;
2250 }
2251
2252 switch (ep.bus.parallel.bus_width) {
2253 case 4:
2254 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2255 break;
2256 case 5:
2257 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2258 break;
2259 case 8:
2260 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2261 break;
2262 case 9:
2263 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2264 break;
2265 case 10:
2266 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2267 break;
2268 default:
2269 break;
2270 }
2271
2272 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2273 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2274 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2275 pcdev->platform_flags |= PXA_CAMERA_HSP;
2276 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2277 pcdev->platform_flags |= PXA_CAMERA_VSP;
2278 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2279 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2280 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2281 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2282
2283 asd->match_type = V4L2_ASYNC_MATCH_OF;
2284 remote = of_graph_get_remote_port(np);
2285 if (remote) {
2286 asd->match.of.node = remote;
2287 of_node_put(remote);
2288 } else {
2289 dev_notice(dev, "no remote for %s\n", of_node_full_name(np));
2290 }
2291
2292 out:
2293 of_node_put(np);
2294
2295 return err;
2296 }
2297
2298 static int pxa_camera_probe(struct platform_device *pdev)
2299 {
2300 struct pxa_camera_dev *pcdev;
2301 struct resource *res;
2302 void __iomem *base;
2303 struct dma_slave_config config = {
2304 .src_addr_width = 0,
2305 .src_maxburst = 8,
2306 .direction = DMA_DEV_TO_MEM,
2307 };
2308 dma_cap_mask_t mask;
2309 struct pxad_param params;
2310 char clk_name[V4L2_CLK_NAME_SIZE];
2311 int irq;
2312 int err = 0, i;
2313
2314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2315 irq = platform_get_irq(pdev, 0);
2316 if (!res || irq < 0)
2317 return -ENODEV;
2318
2319 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2320 if (!pcdev) {
2321 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2322 return -ENOMEM;
2323 }
2324
2325 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2326 if (IS_ERR(pcdev->clk))
2327 return PTR_ERR(pcdev->clk);
2328
2329 pcdev->res = res;
2330
2331 pcdev->pdata = pdev->dev.platform_data;
2332 if (&pdev->dev.of_node && !pcdev->pdata) {
2333 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2334 } else {
2335 pcdev->platform_flags = pcdev->pdata->flags;
2336 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2337 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2338 pcdev->asd.match.i2c.adapter_id =
2339 pcdev->pdata->sensor_i2c_adapter_id;
2340 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2341 }
2342 if (err < 0)
2343 return err;
2344
2345 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2346 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2347 /*
2348 * Platform hasn't set available data widths. This is bad.
2349 * Warn and use a default.
2350 */
2351 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
2352 "data widths, using default 10 bit\n");
2353 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2354 }
2355 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2356 pcdev->width_flags = 1 << 7;
2357 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2358 pcdev->width_flags |= 1 << 8;
2359 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2360 pcdev->width_flags |= 1 << 9;
2361 if (!pcdev->mclk) {
2362 dev_warn(&pdev->dev,
2363 "mclk == 0! Please, fix your platform data. "
2364 "Using default 20MHz\n");
2365 pcdev->mclk = 20000000;
2366 }
2367
2368 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2369
2370 INIT_LIST_HEAD(&pcdev->capture);
2371 spin_lock_init(&pcdev->lock);
2372 mutex_init(&pcdev->mlock);
2373
2374 /*
2375 * Request the regions.
2376 */
2377 base = devm_ioremap_resource(&pdev->dev, res);
2378 if (IS_ERR(base))
2379 return PTR_ERR(base);
2380
2381 pcdev->irq = irq;
2382 pcdev->base = base;
2383
2384 /* request dma */
2385 dma_cap_zero(mask);
2386 dma_cap_set(DMA_SLAVE, mask);
2387 dma_cap_set(DMA_PRIVATE, mask);
2388
2389 params.prio = 0;
2390 params.drcmr = 68;
2391 pcdev->dma_chans[0] =
2392 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2393 &params, &pdev->dev, "CI_Y");
2394 if (!pcdev->dma_chans[0]) {
2395 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2396 return -ENODEV;
2397 }
2398
2399 params.drcmr = 69;
2400 pcdev->dma_chans[1] =
2401 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2402 &params, &pdev->dev, "CI_U");
2403 if (!pcdev->dma_chans[1]) {
2404 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2405 goto exit_free_dma_y;
2406 }
2407
2408 params.drcmr = 70;
2409 pcdev->dma_chans[2] =
2410 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2411 &params, &pdev->dev, "CI_V");
2412 if (!pcdev->dma_chans[2]) {
2413 dev_err(&pdev->dev, "Can't request DMA for V\n");
2414 goto exit_free_dma_u;
2415 }
2416
2417 for (i = 0; i < 3; i++) {
2418 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2419 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2420 if (err < 0) {
2421 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2422 err);
2423 goto exit_free_dma;
2424 }
2425 }
2426
2427 /* request irq */
2428 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2429 PXA_CAM_DRV_NAME, pcdev);
2430 if (err) {
2431 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2432 goto exit_free_dma;
2433 }
2434
2435 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2436
2437 pxa_camera_activate(pcdev);
2438
2439 dev_set_drvdata(&pdev->dev, pcdev);
2440 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2441 if (err)
2442 goto exit_free_dma;
2443
2444 pcdev->asds[0] = &pcdev->asd;
2445 pcdev->notifier.subdevs = pcdev->asds;
2446 pcdev->notifier.num_subdevs = 1;
2447 pcdev->notifier.bound = pxa_camera_sensor_bound;
2448 pcdev->notifier.unbind = pxa_camera_sensor_unbind;
2449
2450 if (!of_have_populated_dt())
2451 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2452
2453 err = pxa_camera_init_videobuf2(pcdev);
2454 if (err)
2455 goto exit_free_v4l2dev;
2456
2457 if (pcdev->mclk) {
2458 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2459 pcdev->asd.match.i2c.adapter_id,
2460 pcdev->asd.match.i2c.address);
2461
2462 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2463 clk_name, NULL);
2464 if (IS_ERR(pcdev->mclk_clk))
2465 return PTR_ERR(pcdev->mclk_clk);
2466 }
2467
2468 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2469 if (err)
2470 goto exit_free_clk;
2471
2472 return 0;
2473 exit_free_clk:
2474 v4l2_clk_unregister(pcdev->mclk_clk);
2475 exit_free_v4l2dev:
2476 v4l2_device_unregister(&pcdev->v4l2_dev);
2477 exit_free_dma:
2478 dma_release_channel(pcdev->dma_chans[2]);
2479 exit_free_dma_u:
2480 dma_release_channel(pcdev->dma_chans[1]);
2481 exit_free_dma_y:
2482 dma_release_channel(pcdev->dma_chans[0]);
2483 return err;
2484 }
2485
2486 static int pxa_camera_remove(struct platform_device *pdev)
2487 {
2488 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2489
2490 pxa_camera_deactivate(pcdev);
2491 dma_release_channel(pcdev->dma_chans[0]);
2492 dma_release_channel(pcdev->dma_chans[1]);
2493 dma_release_channel(pcdev->dma_chans[2]);
2494
2495 v4l2_clk_unregister(pcdev->mclk_clk);
2496 v4l2_device_unregister(&pcdev->v4l2_dev);
2497
2498 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2499
2500 return 0;
2501 }
2502
2503 static const struct dev_pm_ops pxa_camera_pm = {
2504 .suspend = pxa_camera_suspend,
2505 .resume = pxa_camera_resume,
2506 };
2507
2508 static const struct of_device_id pxa_camera_of_match[] = {
2509 { .compatible = "marvell,pxa270-qci", },
2510 {},
2511 };
2512 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2513
2514 static struct platform_driver pxa_camera_driver = {
2515 .driver = {
2516 .name = PXA_CAM_DRV_NAME,
2517 .pm = &pxa_camera_pm,
2518 .of_match_table = of_match_ptr(pxa_camera_of_match),
2519 },
2520 .probe = pxa_camera_probe,
2521 .remove = pxa_camera_remove,
2522 };
2523
2524 module_platform_driver(pxa_camera_driver);
2525
2526 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2527 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2528 MODULE_LICENSE("GPL");
2529 MODULE_VERSION(PXA_CAM_VERSION);
2530 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux kernel - Deliverables
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