2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
38 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
39 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
42 module_param_named(debug
, mfc_debug_level
, int, S_IRUGO
| S_IWUSR
);
43 MODULE_PARM_DESC(debug
, "Debug level - higher value produces more verbose messages");
45 /* Helper functions for interrupt processing */
47 /* Remove from hw execution round robin */
48 void clear_work_bit(struct s5p_mfc_ctx
*ctx
)
50 struct s5p_mfc_dev
*dev
= ctx
->dev
;
52 spin_lock(&dev
->condlock
);
53 __clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
54 spin_unlock(&dev
->condlock
);
57 /* Add to hw execution round robin */
58 void set_work_bit(struct s5p_mfc_ctx
*ctx
)
60 struct s5p_mfc_dev
*dev
= ctx
->dev
;
62 spin_lock(&dev
->condlock
);
63 __set_bit(ctx
->num
, &dev
->ctx_work_bits
);
64 spin_unlock(&dev
->condlock
);
67 /* Remove from hw execution round robin */
68 void clear_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
)
70 struct s5p_mfc_dev
*dev
= ctx
->dev
;
73 spin_lock_irqsave(&dev
->condlock
, flags
);
74 __clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
75 spin_unlock_irqrestore(&dev
->condlock
, flags
);
78 /* Add to hw execution round robin */
79 void set_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
)
81 struct s5p_mfc_dev
*dev
= ctx
->dev
;
84 spin_lock_irqsave(&dev
->condlock
, flags
);
85 __set_bit(ctx
->num
, &dev
->ctx_work_bits
);
86 spin_unlock_irqrestore(&dev
->condlock
, flags
);
89 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev
*dev
)
94 spin_lock_irqsave(&dev
->condlock
, flags
);
97 ctx
= (ctx
+ 1) % MFC_NUM_CONTEXTS
;
98 if (ctx
== dev
->curr_ctx
) {
99 if (!test_bit(ctx
, &dev
->ctx_work_bits
))
103 } while (!test_bit(ctx
, &dev
->ctx_work_bits
));
104 spin_unlock_irqrestore(&dev
->condlock
, flags
);
109 /* Wake up context wait_queue */
110 static void wake_up_ctx(struct s5p_mfc_ctx
*ctx
, unsigned int reason
,
114 ctx
->int_type
= reason
;
116 wake_up(&ctx
->queue
);
119 /* Wake up device wait_queue */
120 static void wake_up_dev(struct s5p_mfc_dev
*dev
, unsigned int reason
,
124 dev
->int_type
= reason
;
126 wake_up(&dev
->queue
);
129 void s5p_mfc_cleanup_queue(struct list_head
*lh
, struct vb2_queue
*vq
)
131 struct s5p_mfc_buf
*b
;
134 while (!list_empty(lh
)) {
135 b
= list_entry(lh
->next
, struct s5p_mfc_buf
, list
);
136 for (i
= 0; i
< b
->b
->vb2_buf
.num_planes
; i
++)
137 vb2_set_plane_payload(&b
->b
->vb2_buf
, i
, 0);
138 vb2_buffer_done(&b
->b
->vb2_buf
, VB2_BUF_STATE_ERROR
);
143 static void s5p_mfc_watchdog(unsigned long arg
)
145 struct s5p_mfc_dev
*dev
= (struct s5p_mfc_dev
*)arg
;
147 if (test_bit(0, &dev
->hw_lock
))
148 atomic_inc(&dev
->watchdog_cnt
);
149 if (atomic_read(&dev
->watchdog_cnt
) >= MFC_WATCHDOG_CNT
) {
150 /* This means that hw is busy and no interrupts were
151 * generated by hw for the Nth time of running this
152 * watchdog timer. This usually means a serious hw
153 * error. Now it is time to kill all instances and
155 mfc_err("Time out during waiting for HW\n");
156 schedule_work(&dev
->watchdog_work
);
158 dev
->watchdog_timer
.expires
= jiffies
+
159 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
160 add_timer(&dev
->watchdog_timer
);
163 static void s5p_mfc_watchdog_worker(struct work_struct
*work
)
165 struct s5p_mfc_dev
*dev
;
166 struct s5p_mfc_ctx
*ctx
;
171 dev
= container_of(work
, struct s5p_mfc_dev
, watchdog_work
);
173 mfc_err("Driver timeout error handling\n");
174 /* Lock the mutex that protects open and release.
175 * This is necessary as they may load and unload firmware. */
176 mutex_locked
= mutex_trylock(&dev
->mfc_mutex
);
178 mfc_err("Error: some instance may be closing/opening\n");
179 spin_lock_irqsave(&dev
->irqlock
, flags
);
183 for (i
= 0; i
< MFC_NUM_CONTEXTS
; i
++) {
187 ctx
->state
= MFCINST_ERROR
;
188 s5p_mfc_cleanup_queue(&ctx
->dst_queue
, &ctx
->vq_dst
);
189 s5p_mfc_cleanup_queue(&ctx
->src_queue
, &ctx
->vq_src
);
191 wake_up_ctx(ctx
, S5P_MFC_R2H_CMD_ERR_RET
, 0);
193 clear_bit(0, &dev
->hw_lock
);
194 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
197 s5p_mfc_deinit_hw(dev
);
199 /* Double check if there is at least one instance running.
200 * If no instance is in memory than no firmware should be present */
201 if (dev
->num_inst
> 0) {
202 ret
= s5p_mfc_load_firmware(dev
);
204 mfc_err("Failed to reload FW\n");
208 ret
= s5p_mfc_init_hw(dev
);
210 mfc_err("Failed to reinit FW\n");
214 mutex_unlock(&dev
->mfc_mutex
);
217 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx
*ctx
)
219 struct s5p_mfc_buf
*dst_buf
;
220 struct s5p_mfc_dev
*dev
= ctx
->dev
;
222 ctx
->state
= MFCINST_FINISHED
;
224 while (!list_empty(&ctx
->dst_queue
)) {
225 dst_buf
= list_entry(ctx
->dst_queue
.next
,
226 struct s5p_mfc_buf
, list
);
227 mfc_debug(2, "Cleaning up buffer: %d\n",
228 dst_buf
->b
->vb2_buf
.index
);
229 vb2_set_plane_payload(&dst_buf
->b
->vb2_buf
, 0, 0);
230 vb2_set_plane_payload(&dst_buf
->b
->vb2_buf
, 1, 0);
231 list_del(&dst_buf
->list
);
232 dst_buf
->flags
|= MFC_BUF_FLAG_EOS
;
233 ctx
->dst_queue_cnt
--;
234 dst_buf
->b
->sequence
= (ctx
->sequence
++);
236 if (s5p_mfc_hw_call(dev
->mfc_ops
, get_pic_type_top
, ctx
) ==
237 s5p_mfc_hw_call(dev
->mfc_ops
, get_pic_type_bot
, ctx
))
238 dst_buf
->b
->field
= V4L2_FIELD_NONE
;
240 dst_buf
->b
->field
= V4L2_FIELD_INTERLACED
;
241 dst_buf
->b
->flags
|= V4L2_BUF_FLAG_LAST
;
243 ctx
->dec_dst_flag
&= ~(1 << dst_buf
->b
->vb2_buf
.index
);
244 vb2_buffer_done(&dst_buf
->b
->vb2_buf
, VB2_BUF_STATE_DONE
);
248 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx
*ctx
)
250 struct s5p_mfc_dev
*dev
= ctx
->dev
;
251 struct s5p_mfc_buf
*dst_buf
, *src_buf
;
253 unsigned int frame_type
;
255 /* Make sure we actually have a new frame before continuing. */
256 frame_type
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dec_frame_type
, dev
);
257 if (frame_type
== S5P_FIMV_DECODE_FRAME_SKIPPED
)
259 dec_y_addr
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dec_y_adr
, dev
);
261 /* Copy timestamp / timecode from decoded src to dst and set
262 appropriate flags. */
263 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
, list
);
264 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
265 if (vb2_dma_contig_plane_dma_addr(&dst_buf
->b
->vb2_buf
, 0)
267 dst_buf
->b
->timecode
=
268 src_buf
->b
->timecode
;
269 dst_buf
->b
->vb2_buf
.timestamp
=
270 src_buf
->b
->vb2_buf
.timestamp
;
272 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK
;
275 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK
;
276 switch (frame_type
) {
277 case S5P_FIMV_DECODE_FRAME_I_FRAME
:
279 V4L2_BUF_FLAG_KEYFRAME
;
281 case S5P_FIMV_DECODE_FRAME_P_FRAME
:
283 V4L2_BUF_FLAG_PFRAME
;
285 case S5P_FIMV_DECODE_FRAME_B_FRAME
:
287 V4L2_BUF_FLAG_BFRAME
;
290 /* Don't know how to handle
291 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
292 mfc_debug(2, "Unexpected frame type: %d\n",
300 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx
*ctx
, unsigned int err
)
302 struct s5p_mfc_dev
*dev
= ctx
->dev
;
303 struct s5p_mfc_buf
*dst_buf
;
305 unsigned int frame_type
;
307 dspl_y_addr
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dspl_y_adr
, dev
);
308 if (IS_MFCV6_PLUS(dev
))
309 frame_type
= s5p_mfc_hw_call(dev
->mfc_ops
,
310 get_disp_frame_type
, ctx
);
312 frame_type
= s5p_mfc_hw_call(dev
->mfc_ops
,
313 get_dec_frame_type
, dev
);
315 /* If frame is same as previous then skip and do not dequeue */
316 if (frame_type
== S5P_FIMV_DECODE_FRAME_SKIPPED
) {
317 if (!ctx
->after_packed_pb
)
319 ctx
->after_packed_pb
= 0;
323 /* The MFC returns address of the buffer, now we have to
324 * check which videobuf does it correspond to */
325 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
326 /* Check if this is the buffer we're looking for */
327 if (vb2_dma_contig_plane_dma_addr(&dst_buf
->b
->vb2_buf
, 0)
329 list_del(&dst_buf
->list
);
330 ctx
->dst_queue_cnt
--;
331 dst_buf
->b
->sequence
= ctx
->sequence
;
332 if (s5p_mfc_hw_call(dev
->mfc_ops
,
333 get_pic_type_top
, ctx
) ==
334 s5p_mfc_hw_call(dev
->mfc_ops
,
335 get_pic_type_bot
, ctx
))
336 dst_buf
->b
->field
= V4L2_FIELD_NONE
;
339 V4L2_FIELD_INTERLACED
;
340 vb2_set_plane_payload(&dst_buf
->b
->vb2_buf
, 0,
342 vb2_set_plane_payload(&dst_buf
->b
->vb2_buf
, 1,
344 clear_bit(dst_buf
->b
->vb2_buf
.index
,
347 vb2_buffer_done(&dst_buf
->b
->vb2_buf
, err
?
348 VB2_BUF_STATE_ERROR
: VB2_BUF_STATE_DONE
);
355 /* Handle frame decoding interrupt */
356 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx
*ctx
,
357 unsigned int reason
, unsigned int err
)
359 struct s5p_mfc_dev
*dev
= ctx
->dev
;
360 unsigned int dst_frame_status
;
361 unsigned int dec_frame_status
;
362 struct s5p_mfc_buf
*src_buf
;
363 unsigned int res_change
;
365 dst_frame_status
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dspl_status
, dev
)
366 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK
;
367 dec_frame_status
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dec_status
, dev
)
368 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK
;
369 res_change
= (s5p_mfc_hw_call(dev
->mfc_ops
, get_dspl_status
, dev
)
370 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK
)
371 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT
;
372 mfc_debug(2, "Frame Status: %x\n", dst_frame_status
);
373 if (ctx
->state
== MFCINST_RES_CHANGE_INIT
)
374 ctx
->state
= MFCINST_RES_CHANGE_FLUSH
;
375 if (res_change
== S5P_FIMV_RES_INCREASE
||
376 res_change
== S5P_FIMV_RES_DECREASE
) {
377 ctx
->state
= MFCINST_RES_CHANGE_INIT
;
378 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
379 wake_up_ctx(ctx
, reason
, err
);
380 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
382 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
385 if (ctx
->dpb_flush_flag
)
386 ctx
->dpb_flush_flag
= 0;
388 /* All frames remaining in the buffer have been extracted */
389 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_EMPTY
) {
390 if (ctx
->state
== MFCINST_RES_CHANGE_FLUSH
) {
391 static const struct v4l2_event ev_src_ch
= {
392 .type
= V4L2_EVENT_SOURCE_CHANGE
,
393 .u
.src_change
.changes
=
394 V4L2_EVENT_SRC_CH_RESOLUTION
,
397 s5p_mfc_handle_frame_all_extracted(ctx
);
398 ctx
->state
= MFCINST_RES_CHANGE_END
;
399 v4l2_event_queue_fh(&ctx
->fh
, &ev_src_ch
);
401 goto leave_handle_frame
;
403 s5p_mfc_handle_frame_all_extracted(ctx
);
407 if (dec_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
)
408 s5p_mfc_handle_frame_copy_time(ctx
);
410 /* A frame has been decoded and is in the buffer */
411 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
||
412 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
) {
413 s5p_mfc_handle_frame_new(ctx
, err
);
415 mfc_debug(2, "No frame decode\n");
417 /* Mark source buffer as complete */
418 if (dst_frame_status
!= S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
419 && !list_empty(&ctx
->src_queue
)) {
420 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
,
422 ctx
->consumed_stream
+= s5p_mfc_hw_call(dev
->mfc_ops
,
423 get_consumed_stream
, dev
);
424 if (ctx
->codec_mode
!= S5P_MFC_CODEC_H264_DEC
&&
425 ctx
->codec_mode
!= S5P_MFC_CODEC_VP8_DEC
&&
426 ctx
->consumed_stream
+ STUFF_BYTE
<
427 src_buf
->b
->vb2_buf
.planes
[0].bytesused
) {
428 /* Run MFC again on the same buffer */
429 mfc_debug(2, "Running again the same buffer\n");
430 ctx
->after_packed_pb
= 1;
432 mfc_debug(2, "MFC needs next buffer\n");
433 ctx
->consumed_stream
= 0;
434 if (src_buf
->flags
& MFC_BUF_FLAG_EOS
)
435 ctx
->state
= MFCINST_FINISHING
;
436 list_del(&src_buf
->list
);
437 ctx
->src_queue_cnt
--;
438 if (s5p_mfc_hw_call(dev
->mfc_ops
, err_dec
, err
) > 0)
439 vb2_buffer_done(&src_buf
->b
->vb2_buf
,
440 VB2_BUF_STATE_ERROR
);
442 vb2_buffer_done(&src_buf
->b
->vb2_buf
,
447 if ((ctx
->src_queue_cnt
== 0 && ctx
->state
!= MFCINST_FINISHING
)
448 || ctx
->dst_queue_cnt
< ctx
->pb_count
)
450 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
451 wake_up_ctx(ctx
, reason
, err
);
452 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
454 /* if suspending, wake up device and do not try_run again*/
455 if (test_bit(0, &dev
->enter_suspend
))
456 wake_up_dev(dev
, reason
, err
);
458 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
461 /* Error handling for interrupt */
462 static void s5p_mfc_handle_error(struct s5p_mfc_dev
*dev
,
463 struct s5p_mfc_ctx
*ctx
, unsigned int reason
, unsigned int err
)
465 mfc_err("Interrupt Error: %08x\n", err
);
468 /* Error recovery is dependent on the state of context */
469 switch (ctx
->state
) {
470 case MFCINST_RES_CHANGE_INIT
:
471 case MFCINST_RES_CHANGE_FLUSH
:
472 case MFCINST_RES_CHANGE_END
:
473 case MFCINST_FINISHING
:
474 case MFCINST_FINISHED
:
475 case MFCINST_RUNNING
:
476 /* It is highly probable that an error occurred
477 * while decoding a frame */
479 ctx
->state
= MFCINST_ERROR
;
480 /* Mark all dst buffers as having an error */
481 s5p_mfc_cleanup_queue(&ctx
->dst_queue
, &ctx
->vq_dst
);
482 /* Mark all src buffers as having an error */
483 s5p_mfc_cleanup_queue(&ctx
->src_queue
, &ctx
->vq_src
);
484 wake_up_ctx(ctx
, reason
, err
);
488 ctx
->state
= MFCINST_ERROR
;
489 wake_up_ctx(ctx
, reason
, err
);
493 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
494 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
496 wake_up_dev(dev
, reason
, err
);
499 /* Header parsing interrupt handling */
500 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx
*ctx
,
501 unsigned int reason
, unsigned int err
)
503 struct s5p_mfc_dev
*dev
;
508 if (ctx
->c_ops
->post_seq_start
) {
509 if (ctx
->c_ops
->post_seq_start(ctx
))
510 mfc_err("post_seq_start() failed\n");
512 ctx
->img_width
= s5p_mfc_hw_call(dev
->mfc_ops
, get_img_width
,
514 ctx
->img_height
= s5p_mfc_hw_call(dev
->mfc_ops
, get_img_height
,
517 s5p_mfc_hw_call(dev
->mfc_ops
, dec_calc_dpb_size
, ctx
);
519 ctx
->pb_count
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dpb_count
,
521 ctx
->mv_count
= s5p_mfc_hw_call(dev
->mfc_ops
, get_mv_count
,
523 if (ctx
->img_width
== 0 || ctx
->img_height
== 0)
524 ctx
->state
= MFCINST_ERROR
;
526 ctx
->state
= MFCINST_HEAD_PARSED
;
528 if ((ctx
->codec_mode
== S5P_MFC_CODEC_H264_DEC
||
529 ctx
->codec_mode
== S5P_MFC_CODEC_H264_MVC_DEC
) &&
530 !list_empty(&ctx
->src_queue
)) {
531 struct s5p_mfc_buf
*src_buf
;
532 src_buf
= list_entry(ctx
->src_queue
.next
,
533 struct s5p_mfc_buf
, list
);
534 if (s5p_mfc_hw_call(dev
->mfc_ops
, get_consumed_stream
,
536 src_buf
->b
->vb2_buf
.planes
[0].bytesused
)
537 ctx
->head_processed
= 0;
539 ctx
->head_processed
= 1;
541 ctx
->head_processed
= 1;
544 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
546 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
548 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
549 wake_up_ctx(ctx
, reason
, err
);
552 /* Header parsing interrupt handling */
553 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx
*ctx
,
554 unsigned int reason
, unsigned int err
)
556 struct s5p_mfc_buf
*src_buf
;
557 struct s5p_mfc_dev
*dev
;
562 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
563 ctx
->int_type
= reason
;
568 ctx
->state
= MFCINST_RUNNING
;
569 if (!ctx
->dpb_flush_flag
&& ctx
->head_processed
) {
570 if (!list_empty(&ctx
->src_queue
)) {
571 src_buf
= list_entry(ctx
->src_queue
.next
,
572 struct s5p_mfc_buf
, list
);
573 list_del(&src_buf
->list
);
574 ctx
->src_queue_cnt
--;
575 vb2_buffer_done(&src_buf
->b
->vb2_buf
,
579 ctx
->dpb_flush_flag
= 0;
581 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
585 wake_up(&ctx
->queue
);
586 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
588 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
592 wake_up(&ctx
->queue
);
596 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx
*ctx
)
598 struct s5p_mfc_dev
*dev
= ctx
->dev
;
599 struct s5p_mfc_buf
*mb_entry
;
601 mfc_debug(2, "Stream completed\n");
603 ctx
->state
= MFCINST_FINISHED
;
605 if (!list_empty(&ctx
->dst_queue
)) {
606 mb_entry
= list_entry(ctx
->dst_queue
.next
, struct s5p_mfc_buf
,
608 list_del(&mb_entry
->list
);
609 ctx
->dst_queue_cnt
--;
610 vb2_set_plane_payload(&mb_entry
->b
->vb2_buf
, 0, 0);
611 vb2_buffer_done(&mb_entry
->b
->vb2_buf
, VB2_BUF_STATE_DONE
);
616 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
619 wake_up(&ctx
->queue
);
620 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
623 /* Interrupt processing */
624 static irqreturn_t
s5p_mfc_irq(int irq
, void *priv
)
626 struct s5p_mfc_dev
*dev
= priv
;
627 struct s5p_mfc_ctx
*ctx
;
632 /* Reset the timeout watchdog */
633 atomic_set(&dev
->watchdog_cnt
, 0);
634 spin_lock(&dev
->irqlock
);
635 ctx
= dev
->ctx
[dev
->curr_ctx
];
636 /* Get the reason of interrupt and the error code */
637 reason
= s5p_mfc_hw_call(dev
->mfc_ops
, get_int_reason
, dev
);
638 err
= s5p_mfc_hw_call(dev
->mfc_ops
, get_int_err
, dev
);
639 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason
, err
);
641 case S5P_MFC_R2H_CMD_ERR_RET
:
642 /* An error has occurred */
643 if (ctx
->state
== MFCINST_RUNNING
&&
644 s5p_mfc_hw_call(dev
->mfc_ops
, err_dec
, err
) >=
646 s5p_mfc_handle_frame(ctx
, reason
, err
);
648 s5p_mfc_handle_error(dev
, ctx
, reason
, err
);
649 clear_bit(0, &dev
->enter_suspend
);
652 case S5P_MFC_R2H_CMD_SLICE_DONE_RET
:
653 case S5P_MFC_R2H_CMD_FIELD_DONE_RET
:
654 case S5P_MFC_R2H_CMD_FRAME_DONE_RET
:
655 if (ctx
->c_ops
->post_frame_start
) {
656 if (ctx
->c_ops
->post_frame_start(ctx
))
657 mfc_err("post_frame_start() failed\n");
659 if (ctx
->state
== MFCINST_FINISHING
&&
660 list_empty(&ctx
->ref_queue
)) {
661 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
662 s5p_mfc_handle_stream_complete(ctx
);
665 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
666 wake_up_ctx(ctx
, reason
, err
);
667 WARN_ON(test_and_clear_bit(0, &dev
->hw_lock
) == 0);
669 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
671 s5p_mfc_handle_frame(ctx
, reason
, err
);
675 case S5P_MFC_R2H_CMD_SEQ_DONE_RET
:
676 s5p_mfc_handle_seq_done(ctx
, reason
, err
);
679 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET
:
680 ctx
->inst_no
= s5p_mfc_hw_call(dev
->mfc_ops
, get_inst_no
, dev
);
681 ctx
->state
= MFCINST_GOT_INST
;
683 wake_up(&ctx
->queue
);
686 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET
:
688 ctx
->inst_no
= MFC_NO_INSTANCE_SET
;
689 ctx
->state
= MFCINST_FREE
;
690 wake_up(&ctx
->queue
);
693 case S5P_MFC_R2H_CMD_SYS_INIT_RET
:
694 case S5P_MFC_R2H_CMD_FW_STATUS_RET
:
695 case S5P_MFC_R2H_CMD_SLEEP_RET
:
696 case S5P_MFC_R2H_CMD_WAKEUP_RET
:
699 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
700 wake_up_dev(dev
, reason
, err
);
701 clear_bit(0, &dev
->hw_lock
);
702 clear_bit(0, &dev
->enter_suspend
);
705 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET
:
706 s5p_mfc_handle_init_buffers(ctx
, reason
, err
);
709 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET
:
710 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
711 ctx
->int_type
= reason
;
713 s5p_mfc_handle_stream_complete(ctx
);
716 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET
:
718 ctx
->state
= MFCINST_RUNNING
;
719 wake_up(&ctx
->queue
);
723 mfc_debug(2, "Unknown int reason\n");
724 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
726 spin_unlock(&dev
->irqlock
);
730 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
731 ctx
->int_type
= reason
;
734 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
735 mfc_err("Failed to unlock hw\n");
739 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
740 spin_unlock(&dev
->irqlock
);
741 mfc_debug(2, "Exit via irq_cleanup_hw\n");
745 /* Open an MFC node */
746 static int s5p_mfc_open(struct file
*file
)
748 struct video_device
*vdev
= video_devdata(file
);
749 struct s5p_mfc_dev
*dev
= video_drvdata(file
);
750 struct s5p_mfc_ctx
*ctx
= NULL
;
755 if (mutex_lock_interruptible(&dev
->mfc_mutex
))
757 dev
->num_inst
++; /* It is guarded by mfc_mutex in vfd */
758 /* Allocate memory for context */
759 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
764 v4l2_fh_init(&ctx
->fh
, vdev
);
765 file
->private_data
= &ctx
->fh
;
766 v4l2_fh_add(&ctx
->fh
);
768 INIT_LIST_HEAD(&ctx
->src_queue
);
769 INIT_LIST_HEAD(&ctx
->dst_queue
);
770 ctx
->src_queue_cnt
= 0;
771 ctx
->dst_queue_cnt
= 0;
772 /* Get context number */
774 while (dev
->ctx
[ctx
->num
]) {
776 if (ctx
->num
>= MFC_NUM_CONTEXTS
) {
777 mfc_debug(2, "Too many open contexts\n");
782 /* Mark context as idle */
783 clear_work_bit_irqsave(ctx
);
784 dev
->ctx
[ctx
->num
] = ctx
;
785 if (vdev
== dev
->vfd_dec
) {
786 ctx
->type
= MFCINST_DECODER
;
787 ctx
->c_ops
= get_dec_codec_ops();
788 s5p_mfc_dec_init(ctx
);
789 /* Setup ctrl handler */
790 ret
= s5p_mfc_dec_ctrls_setup(ctx
);
792 mfc_err("Failed to setup mfc controls\n");
793 goto err_ctrls_setup
;
795 } else if (vdev
== dev
->vfd_enc
) {
796 ctx
->type
= MFCINST_ENCODER
;
797 ctx
->c_ops
= get_enc_codec_ops();
798 /* only for encoder */
799 INIT_LIST_HEAD(&ctx
->ref_queue
);
800 ctx
->ref_queue_cnt
= 0;
801 s5p_mfc_enc_init(ctx
);
802 /* Setup ctrl handler */
803 ret
= s5p_mfc_enc_ctrls_setup(ctx
);
805 mfc_err("Failed to setup mfc controls\n");
806 goto err_ctrls_setup
;
812 ctx
->fh
.ctrl_handler
= &ctx
->ctrl_handler
;
813 ctx
->inst_no
= MFC_NO_INSTANCE_SET
;
814 /* Load firmware if this is the first instance */
815 if (dev
->num_inst
== 1) {
816 dev
->watchdog_timer
.expires
= jiffies
+
817 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
818 add_timer(&dev
->watchdog_timer
);
819 ret
= s5p_mfc_power_on();
821 mfc_err("power on failed\n");
825 ret
= s5p_mfc_load_firmware(dev
);
831 ret
= s5p_mfc_init_hw(dev
);
836 /* Init videobuf2 queue for CAPTURE */
838 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
;
839 q
->drv_priv
= &ctx
->fh
;
840 q
->lock
= &dev
->mfc_mutex
;
841 if (vdev
== dev
->vfd_dec
) {
842 q
->io_modes
= VB2_MMAP
;
843 q
->ops
= get_dec_queue_ops();
844 } else if (vdev
== dev
->vfd_enc
) {
845 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
846 q
->ops
= get_enc_queue_ops();
851 q
->mem_ops
= &vb2_dma_contig_memops
;
852 q
->timestamp_flags
= V4L2_BUF_FLAG_TIMESTAMP_COPY
;
853 ret
= vb2_queue_init(q
);
855 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
858 /* Init videobuf2 queue for OUTPUT */
860 q
->type
= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
;
861 q
->io_modes
= VB2_MMAP
;
862 q
->drv_priv
= &ctx
->fh
;
863 q
->lock
= &dev
->mfc_mutex
;
864 if (vdev
== dev
->vfd_dec
) {
865 q
->io_modes
= VB2_MMAP
;
866 q
->ops
= get_dec_queue_ops();
867 } else if (vdev
== dev
->vfd_enc
) {
868 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
869 q
->ops
= get_enc_queue_ops();
874 /* One way to indicate end-of-stream for MFC is to set the
875 * bytesused == 0. However by default videobuf2 handles bytesused
876 * equal to 0 as a special case and changes its value to the size
877 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
878 * will keep the value of bytesused intact.
880 q
->allow_zero_bytesused
= 1;
881 q
->mem_ops
= &vb2_dma_contig_memops
;
882 q
->timestamp_flags
= V4L2_BUF_FLAG_TIMESTAMP_COPY
;
883 ret
= vb2_queue_init(q
);
885 mfc_err("Failed to initialize videobuf2 queue(output)\n");
888 init_waitqueue_head(&ctx
->queue
);
889 mutex_unlock(&dev
->mfc_mutex
);
892 /* Deinit when failure occurred */
894 if (dev
->num_inst
== 1)
895 s5p_mfc_deinit_hw(dev
);
899 if (dev
->num_inst
== 1) {
900 if (s5p_mfc_power_off() < 0)
901 mfc_err("power off failed\n");
902 del_timer_sync(&dev
->watchdog_timer
);
905 s5p_mfc_dec_ctrls_delete(ctx
);
907 dev
->ctx
[ctx
->num
] = NULL
;
909 v4l2_fh_del(&ctx
->fh
);
910 v4l2_fh_exit(&ctx
->fh
);
914 mutex_unlock(&dev
->mfc_mutex
);
919 /* Release MFC context */
920 static int s5p_mfc_release(struct file
*file
)
922 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
923 struct s5p_mfc_dev
*dev
= ctx
->dev
;
925 /* if dev is null, do cleanup that doesn't need dev */
928 mutex_lock(&dev
->mfc_mutex
);
930 vb2_queue_release(&ctx
->vq_src
);
931 vb2_queue_release(&ctx
->vq_dst
);
933 /* Mark context as idle */
934 clear_work_bit_irqsave(ctx
);
936 * If instance was initialised and not yet freed,
937 * return instance and free resources
939 if (ctx
->state
!= MFCINST_FREE
&& ctx
->state
!= MFCINST_INIT
) {
940 mfc_debug(2, "Has to free instance\n");
941 s5p_mfc_close_mfc_inst(dev
, ctx
);
943 /* hardware locking scheme */
944 if (dev
->curr_ctx
== ctx
->num
)
945 clear_bit(0, &dev
->hw_lock
);
947 if (dev
->num_inst
== 0) {
948 mfc_debug(2, "Last instance\n");
949 s5p_mfc_deinit_hw(dev
);
950 del_timer_sync(&dev
->watchdog_timer
);
951 if (s5p_mfc_power_off() < 0)
952 mfc_err("Power off failed\n");
955 mfc_debug(2, "Shutting down clock\n");
958 dev
->ctx
[ctx
->num
] = NULL
;
959 s5p_mfc_dec_ctrls_delete(ctx
);
960 v4l2_fh_del(&ctx
->fh
);
961 /* vdev is gone if dev is null */
963 v4l2_fh_exit(&ctx
->fh
);
967 mutex_unlock(&dev
->mfc_mutex
);
973 static unsigned int s5p_mfc_poll(struct file
*file
,
974 struct poll_table_struct
*wait
)
976 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
977 struct s5p_mfc_dev
*dev
= ctx
->dev
;
978 struct vb2_queue
*src_q
, *dst_q
;
979 struct vb2_buffer
*src_vb
= NULL
, *dst_vb
= NULL
;
983 mutex_lock(&dev
->mfc_mutex
);
984 src_q
= &ctx
->vq_src
;
985 dst_q
= &ctx
->vq_dst
;
987 * There has to be at least one buffer queued on each queued_list, which
988 * means either in driver already or waiting for driver to claim it
989 * and start processing.
991 if ((!src_q
->streaming
|| list_empty(&src_q
->queued_list
))
992 && (!dst_q
->streaming
|| list_empty(&dst_q
->queued_list
))) {
996 mutex_unlock(&dev
->mfc_mutex
);
997 poll_wait(file
, &ctx
->fh
.wait
, wait
);
998 poll_wait(file
, &src_q
->done_wq
, wait
);
999 poll_wait(file
, &dst_q
->done_wq
, wait
);
1000 mutex_lock(&dev
->mfc_mutex
);
1001 if (v4l2_event_pending(&ctx
->fh
))
1003 spin_lock_irqsave(&src_q
->done_lock
, flags
);
1004 if (!list_empty(&src_q
->done_list
))
1005 src_vb
= list_first_entry(&src_q
->done_list
, struct vb2_buffer
,
1007 if (src_vb
&& (src_vb
->state
== VB2_BUF_STATE_DONE
1008 || src_vb
->state
== VB2_BUF_STATE_ERROR
))
1009 rc
|= POLLOUT
| POLLWRNORM
;
1010 spin_unlock_irqrestore(&src_q
->done_lock
, flags
);
1011 spin_lock_irqsave(&dst_q
->done_lock
, flags
);
1012 if (!list_empty(&dst_q
->done_list
))
1013 dst_vb
= list_first_entry(&dst_q
->done_list
, struct vb2_buffer
,
1015 if (dst_vb
&& (dst_vb
->state
== VB2_BUF_STATE_DONE
1016 || dst_vb
->state
== VB2_BUF_STATE_ERROR
))
1017 rc
|= POLLIN
| POLLRDNORM
;
1018 spin_unlock_irqrestore(&dst_q
->done_lock
, flags
);
1020 mutex_unlock(&dev
->mfc_mutex
);
1025 static int s5p_mfc_mmap(struct file
*file
, struct vm_area_struct
*vma
)
1027 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
1028 struct s5p_mfc_dev
*dev
= ctx
->dev
;
1029 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
1032 if (mutex_lock_interruptible(&dev
->mfc_mutex
))
1033 return -ERESTARTSYS
;
1034 if (offset
< DST_QUEUE_OFF_BASE
) {
1035 mfc_debug(2, "mmaping source\n");
1036 ret
= vb2_mmap(&ctx
->vq_src
, vma
);
1037 } else { /* capture */
1038 mfc_debug(2, "mmaping destination\n");
1039 vma
->vm_pgoff
-= (DST_QUEUE_OFF_BASE
>> PAGE_SHIFT
);
1040 ret
= vb2_mmap(&ctx
->vq_dst
, vma
);
1042 mutex_unlock(&dev
->mfc_mutex
);
1047 static const struct v4l2_file_operations s5p_mfc_fops
= {
1048 .owner
= THIS_MODULE
,
1049 .open
= s5p_mfc_open
,
1050 .release
= s5p_mfc_release
,
1051 .poll
= s5p_mfc_poll
,
1052 .unlocked_ioctl
= video_ioctl2
,
1053 .mmap
= s5p_mfc_mmap
,
1056 /* DMA memory related helper functions */
1057 static void s5p_mfc_memdev_release(struct device
*dev
)
1059 of_reserved_mem_device_release(dev
);
1062 static struct device
*s5p_mfc_alloc_memdev(struct device
*dev
,
1063 const char *name
, unsigned int idx
)
1065 struct device
*child
;
1068 child
= devm_kzalloc(dev
, sizeof(struct device
), GFP_KERNEL
);
1072 device_initialize(child
);
1073 dev_set_name(child
, "%s:%s", dev_name(dev
), name
);
1074 child
->parent
= dev
;
1075 child
->bus
= dev
->bus
;
1076 child
->coherent_dma_mask
= dev
->coherent_dma_mask
;
1077 child
->dma_mask
= dev
->dma_mask
;
1078 child
->release
= s5p_mfc_memdev_release
;
1080 if (device_add(child
) == 0) {
1081 ret
= of_reserved_mem_device_init_by_idx(child
, dev
->of_node
,
1091 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev
*mfc_dev
)
1093 struct device
*dev
= &mfc_dev
->plat_dev
->dev
;
1096 * When IOMMU is available, we cannot use the default configuration,
1097 * because of MFC firmware requirements: address space limited to
1098 * 256M and non-zero default start address.
1099 * This is still simplified, not optimal configuration, but for now
1100 * IOMMU core doesn't allow to configure device's IOMMUs channel
1103 if (exynos_is_iommu_available(dev
)) {
1104 int ret
= exynos_configure_iommu(dev
, S5P_MFC_IOMMU_DMA_BASE
,
1105 S5P_MFC_IOMMU_DMA_SIZE
);
1107 mfc_dev
->mem_dev_l
= mfc_dev
->mem_dev_r
= dev
;
1112 * Create and initialize virtual devices for accessing
1113 * reserved memory regions.
1115 mfc_dev
->mem_dev_l
= s5p_mfc_alloc_memdev(dev
, "left",
1116 MFC_BANK1_ALLOC_CTX
);
1117 if (!mfc_dev
->mem_dev_l
)
1119 mfc_dev
->mem_dev_r
= s5p_mfc_alloc_memdev(dev
, "right",
1120 MFC_BANK2_ALLOC_CTX
);
1121 if (!mfc_dev
->mem_dev_r
) {
1122 device_unregister(mfc_dev
->mem_dev_l
);
1129 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev
*mfc_dev
)
1131 struct device
*dev
= &mfc_dev
->plat_dev
->dev
;
1133 if (exynos_is_iommu_available(dev
)) {
1134 exynos_unconfigure_iommu(dev
);
1138 device_unregister(mfc_dev
->mem_dev_l
);
1139 device_unregister(mfc_dev
->mem_dev_r
);
1142 static void *mfc_get_drv_data(struct platform_device
*pdev
);
1144 /* MFC probe function */
1145 static int s5p_mfc_probe(struct platform_device
*pdev
)
1147 struct s5p_mfc_dev
*dev
;
1148 struct video_device
*vfd
;
1149 struct resource
*res
;
1152 pr_debug("%s++\n", __func__
);
1153 dev
= devm_kzalloc(&pdev
->dev
, sizeof(*dev
), GFP_KERNEL
);
1155 dev_err(&pdev
->dev
, "Not enough memory for MFC device\n");
1159 spin_lock_init(&dev
->irqlock
);
1160 spin_lock_init(&dev
->condlock
);
1161 dev
->plat_dev
= pdev
;
1162 if (!dev
->plat_dev
) {
1163 dev_err(&pdev
->dev
, "No platform data specified\n");
1167 dev
->variant
= mfc_get_drv_data(pdev
);
1169 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1170 dev
->regs_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1171 if (IS_ERR(dev
->regs_base
))
1172 return PTR_ERR(dev
->regs_base
);
1174 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1176 dev_err(&pdev
->dev
, "failed to get irq resource\n");
1179 dev
->irq
= res
->start
;
1180 ret
= devm_request_irq(&pdev
->dev
, dev
->irq
, s5p_mfc_irq
,
1181 0, pdev
->name
, dev
);
1183 dev_err(&pdev
->dev
, "Failed to install irq (%d)\n", ret
);
1187 ret
= s5p_mfc_configure_dma_memory(dev
);
1189 dev_err(&pdev
->dev
, "failed to configure DMA memory\n");
1193 ret
= s5p_mfc_init_pm(dev
);
1195 dev_err(&pdev
->dev
, "failed to get mfc clock source\n");
1199 vb2_dma_contig_set_max_seg_size(dev
->mem_dev_l
, DMA_BIT_MASK(32));
1200 vb2_dma_contig_set_max_seg_size(dev
->mem_dev_r
, DMA_BIT_MASK(32));
1202 mutex_init(&dev
->mfc_mutex
);
1204 ret
= s5p_mfc_alloc_firmware(dev
);
1208 ret
= v4l2_device_register(&pdev
->dev
, &dev
->v4l2_dev
);
1210 goto err_v4l2_dev_reg
;
1211 init_waitqueue_head(&dev
->queue
);
1214 vfd
= video_device_alloc();
1216 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1220 vfd
->fops
= &s5p_mfc_fops
;
1221 vfd
->ioctl_ops
= get_dec_v4l2_ioctl_ops();
1222 vfd
->release
= video_device_release
;
1223 vfd
->lock
= &dev
->mfc_mutex
;
1224 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1225 vfd
->vfl_dir
= VFL_DIR_M2M
;
1226 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_DEC_NAME
);
1228 video_set_drvdata(vfd
, dev
);
1231 vfd
= video_device_alloc();
1233 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1237 vfd
->fops
= &s5p_mfc_fops
;
1238 vfd
->ioctl_ops
= get_enc_v4l2_ioctl_ops();
1239 vfd
->release
= video_device_release
;
1240 vfd
->lock
= &dev
->mfc_mutex
;
1241 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1242 vfd
->vfl_dir
= VFL_DIR_M2M
;
1243 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_ENC_NAME
);
1245 video_set_drvdata(vfd
, dev
);
1246 platform_set_drvdata(pdev
, dev
);
1249 INIT_WORK(&dev
->watchdog_work
, s5p_mfc_watchdog_worker
);
1250 atomic_set(&dev
->watchdog_cnt
, 0);
1251 init_timer(&dev
->watchdog_timer
);
1252 dev
->watchdog_timer
.data
= (unsigned long)dev
;
1253 dev
->watchdog_timer
.function
= s5p_mfc_watchdog
;
1255 /* Initialize HW ops and commands based on MFC version */
1256 s5p_mfc_init_hw_ops(dev
);
1257 s5p_mfc_init_hw_cmds(dev
);
1258 s5p_mfc_init_regs(dev
);
1260 /* Register decoder and encoder */
1261 ret
= video_register_device(dev
->vfd_dec
, VFL_TYPE_GRABBER
, 0);
1263 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1266 v4l2_info(&dev
->v4l2_dev
,
1267 "decoder registered as /dev/video%d\n", dev
->vfd_dec
->num
);
1269 ret
= video_register_device(dev
->vfd_enc
, VFL_TYPE_GRABBER
, 0);
1271 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1274 v4l2_info(&dev
->v4l2_dev
,
1275 "encoder registered as /dev/video%d\n", dev
->vfd_enc
->num
);
1277 pr_debug("%s--\n", __func__
);
1280 /* Deinit MFC if probe had failed */
1282 video_unregister_device(dev
->vfd_dec
);
1284 video_device_release(dev
->vfd_enc
);
1286 video_device_release(dev
->vfd_dec
);
1288 v4l2_device_unregister(&dev
->v4l2_dev
);
1290 s5p_mfc_release_firmware(dev
);
1292 s5p_mfc_final_pm(dev
);
1294 s5p_mfc_unconfigure_dma_memory(dev
);
1296 pr_debug("%s-- with error\n", __func__
);
1301 /* Remove the driver */
1302 static int s5p_mfc_remove(struct platform_device
*pdev
)
1304 struct s5p_mfc_dev
*dev
= platform_get_drvdata(pdev
);
1305 struct s5p_mfc_ctx
*ctx
;
1308 v4l2_info(&dev
->v4l2_dev
, "Removing %s\n", pdev
->name
);
1311 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1312 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1313 * after s5p_mfc_remove() is run during unbind.
1315 mutex_lock(&dev
->mfc_mutex
);
1316 for (i
= 0; i
< MFC_NUM_CONTEXTS
; i
++) {
1320 /* clear ctx->dev */
1323 mutex_unlock(&dev
->mfc_mutex
);
1325 del_timer_sync(&dev
->watchdog_timer
);
1326 flush_work(&dev
->watchdog_work
);
1328 video_unregister_device(dev
->vfd_enc
);
1329 video_unregister_device(dev
->vfd_dec
);
1330 video_device_release(dev
->vfd_enc
);
1331 video_device_release(dev
->vfd_dec
);
1332 v4l2_device_unregister(&dev
->v4l2_dev
);
1333 s5p_mfc_release_firmware(dev
);
1334 s5p_mfc_unconfigure_dma_memory(dev
);
1335 vb2_dma_contig_clear_max_seg_size(dev
->mem_dev_l
);
1336 vb2_dma_contig_clear_max_seg_size(dev
->mem_dev_r
);
1338 s5p_mfc_final_pm(dev
);
1342 #ifdef CONFIG_PM_SLEEP
1344 static int s5p_mfc_suspend(struct device
*dev
)
1346 struct platform_device
*pdev
= to_platform_device(dev
);
1347 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1350 if (m_dev
->num_inst
== 0)
1353 if (test_and_set_bit(0, &m_dev
->enter_suspend
) != 0) {
1354 mfc_err("Error: going to suspend for a second time\n");
1358 /* Check if we're processing then wait if it necessary. */
1359 while (test_and_set_bit(0, &m_dev
->hw_lock
) != 0) {
1360 /* Try and lock the HW */
1361 /* Wait on the interrupt waitqueue */
1362 ret
= wait_event_interruptible_timeout(m_dev
->queue
,
1363 m_dev
->int_cond
, msecs_to_jiffies(MFC_INT_TIMEOUT
));
1365 mfc_err("Waiting for hardware to finish timed out\n");
1366 clear_bit(0, &m_dev
->enter_suspend
);
1371 ret
= s5p_mfc_sleep(m_dev
);
1373 clear_bit(0, &m_dev
->enter_suspend
);
1374 clear_bit(0, &m_dev
->hw_lock
);
1379 static int s5p_mfc_resume(struct device
*dev
)
1381 struct platform_device
*pdev
= to_platform_device(dev
);
1382 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1384 if (m_dev
->num_inst
== 0)
1386 return s5p_mfc_wakeup(m_dev
);
1391 static int s5p_mfc_runtime_suspend(struct device
*dev
)
1393 struct platform_device
*pdev
= to_platform_device(dev
);
1394 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1396 atomic_set(&m_dev
->pm
.power
, 0);
1400 static int s5p_mfc_runtime_resume(struct device
*dev
)
1402 struct platform_device
*pdev
= to_platform_device(dev
);
1403 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1405 atomic_set(&m_dev
->pm
.power
, 1);
1410 /* Power management */
1411 static const struct dev_pm_ops s5p_mfc_pm_ops
= {
1412 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend
, s5p_mfc_resume
)
1413 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend
, s5p_mfc_runtime_resume
,
1417 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5
= {
1418 .h264_ctx
= MFC_H264_CTX_BUF_SIZE
,
1419 .non_h264_ctx
= MFC_CTX_BUF_SIZE
,
1420 .dsc
= DESC_BUF_SIZE
,
1421 .shm
= SHARED_BUF_SIZE
,
1424 static struct s5p_mfc_buf_size buf_size_v5
= {
1426 .cpb
= MAX_CPB_SIZE
,
1427 .priv
= &mfc_buf_size_v5
,
1430 static struct s5p_mfc_buf_align mfc_buf_align_v5
= {
1431 .base
= MFC_BASE_ALIGN_ORDER
,
1434 static struct s5p_mfc_variant mfc_drvdata_v5
= {
1435 .version
= MFC_VERSION
,
1436 .version_bit
= MFC_V5_BIT
,
1437 .port_num
= MFC_NUM_PORTS
,
1438 .buf_size
= &buf_size_v5
,
1439 .buf_align
= &mfc_buf_align_v5
,
1440 .fw_name
[0] = "s5p-mfc.fw",
1443 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6
= {
1444 .dev_ctx
= MFC_CTX_BUF_SIZE_V6
,
1445 .h264_dec_ctx
= MFC_H264_DEC_CTX_BUF_SIZE_V6
,
1446 .other_dec_ctx
= MFC_OTHER_DEC_CTX_BUF_SIZE_V6
,
1447 .h264_enc_ctx
= MFC_H264_ENC_CTX_BUF_SIZE_V6
,
1448 .other_enc_ctx
= MFC_OTHER_ENC_CTX_BUF_SIZE_V6
,
1451 static struct s5p_mfc_buf_size buf_size_v6
= {
1452 .fw
= MAX_FW_SIZE_V6
,
1453 .cpb
= MAX_CPB_SIZE_V6
,
1454 .priv
= &mfc_buf_size_v6
,
1457 static struct s5p_mfc_buf_align mfc_buf_align_v6
= {
1461 static struct s5p_mfc_variant mfc_drvdata_v6
= {
1462 .version
= MFC_VERSION_V6
,
1463 .version_bit
= MFC_V6_BIT
,
1464 .port_num
= MFC_NUM_PORTS_V6
,
1465 .buf_size
= &buf_size_v6
,
1466 .buf_align
= &mfc_buf_align_v6
,
1467 .fw_name
[0] = "s5p-mfc-v6.fw",
1469 * v6-v2 firmware contains bug fixes and interface change
1470 * for init buffer command
1472 .fw_name
[1] = "s5p-mfc-v6-v2.fw",
1475 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7
= {
1476 .dev_ctx
= MFC_CTX_BUF_SIZE_V7
,
1477 .h264_dec_ctx
= MFC_H264_DEC_CTX_BUF_SIZE_V7
,
1478 .other_dec_ctx
= MFC_OTHER_DEC_CTX_BUF_SIZE_V7
,
1479 .h264_enc_ctx
= MFC_H264_ENC_CTX_BUF_SIZE_V7
,
1480 .other_enc_ctx
= MFC_OTHER_ENC_CTX_BUF_SIZE_V7
,
1483 static struct s5p_mfc_buf_size buf_size_v7
= {
1484 .fw
= MAX_FW_SIZE_V7
,
1485 .cpb
= MAX_CPB_SIZE_V7
,
1486 .priv
= &mfc_buf_size_v7
,
1489 static struct s5p_mfc_buf_align mfc_buf_align_v7
= {
1493 static struct s5p_mfc_variant mfc_drvdata_v7
= {
1494 .version
= MFC_VERSION_V7
,
1495 .version_bit
= MFC_V7_BIT
,
1496 .port_num
= MFC_NUM_PORTS_V7
,
1497 .buf_size
= &buf_size_v7
,
1498 .buf_align
= &mfc_buf_align_v7
,
1499 .fw_name
[0] = "s5p-mfc-v7.fw",
1502 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8
= {
1503 .dev_ctx
= MFC_CTX_BUF_SIZE_V8
,
1504 .h264_dec_ctx
= MFC_H264_DEC_CTX_BUF_SIZE_V8
,
1505 .other_dec_ctx
= MFC_OTHER_DEC_CTX_BUF_SIZE_V8
,
1506 .h264_enc_ctx
= MFC_H264_ENC_CTX_BUF_SIZE_V8
,
1507 .other_enc_ctx
= MFC_OTHER_ENC_CTX_BUF_SIZE_V8
,
1510 static struct s5p_mfc_buf_size buf_size_v8
= {
1511 .fw
= MAX_FW_SIZE_V8
,
1512 .cpb
= MAX_CPB_SIZE_V8
,
1513 .priv
= &mfc_buf_size_v8
,
1516 static struct s5p_mfc_buf_align mfc_buf_align_v8
= {
1520 static struct s5p_mfc_variant mfc_drvdata_v8
= {
1521 .version
= MFC_VERSION_V8
,
1522 .version_bit
= MFC_V8_BIT
,
1523 .port_num
= MFC_NUM_PORTS_V8
,
1524 .buf_size
= &buf_size_v8
,
1525 .buf_align
= &mfc_buf_align_v8
,
1526 .fw_name
[0] = "s5p-mfc-v8.fw",
1529 static const struct of_device_id exynos_mfc_match
[] = {
1531 .compatible
= "samsung,mfc-v5",
1532 .data
= &mfc_drvdata_v5
,
1534 .compatible
= "samsung,mfc-v6",
1535 .data
= &mfc_drvdata_v6
,
1537 .compatible
= "samsung,mfc-v7",
1538 .data
= &mfc_drvdata_v7
,
1540 .compatible
= "samsung,mfc-v8",
1541 .data
= &mfc_drvdata_v8
,
1545 MODULE_DEVICE_TABLE(of
, exynos_mfc_match
);
1547 static void *mfc_get_drv_data(struct platform_device
*pdev
)
1549 struct s5p_mfc_variant
*driver_data
= NULL
;
1550 const struct of_device_id
*match
;
1552 match
= of_match_node(exynos_mfc_match
, pdev
->dev
.of_node
);
1554 driver_data
= (struct s5p_mfc_variant
*)match
->data
;
1559 static struct platform_driver s5p_mfc_driver
= {
1560 .probe
= s5p_mfc_probe
,
1561 .remove
= s5p_mfc_remove
,
1563 .name
= S5P_MFC_NAME
,
1564 .pm
= &s5p_mfc_pm_ops
,
1565 .of_match_table
= exynos_mfc_match
,
1569 module_platform_driver(s5p_mfc_driver
);
1571 MODULE_LICENSE("GPL");
1572 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1573 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");