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[media] media: rc: nuvoton: remove wake states
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
43
44 static const struct nvt_chip nvt_chips[] = {
45 { "w83667hg", NVT_W83667HG },
46 { "NCT6775F", NVT_6775F },
47 { "NCT6776F", NVT_6776F },
48 { "NCT6779D", NVT_6779D },
49 };
50
51 static inline bool is_w83667hg(struct nvt_dev *nvt)
52 {
53 return nvt->chip_ver == NVT_W83667HG;
54 }
55
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 outb(reg, nvt->cr_efir);
60 outb(val, nvt->cr_efdr);
61 }
62
63 /* read val from config reg */
64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
65 {
66 outb(reg, nvt->cr_efir);
67 return inb(nvt->cr_efdr);
68 }
69
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
72 {
73 u8 tmp = nvt_cr_read(nvt, reg) | val;
74 nvt_cr_write(nvt, tmp, reg);
75 }
76
77 /* clear config register bit without changing other bits */
78 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
79 {
80 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
81 nvt_cr_write(nvt, tmp, reg);
82 }
83
84 /* enter extended function mode */
85 static inline int nvt_efm_enable(struct nvt_dev *nvt)
86 {
87 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
88 return -EBUSY;
89
90 /* Enabling Extended Function Mode explicitly requires writing 2x */
91 outb(EFER_EFM_ENABLE, nvt->cr_efir);
92 outb(EFER_EFM_ENABLE, nvt->cr_efir);
93
94 return 0;
95 }
96
97 /* exit extended function mode */
98 static inline void nvt_efm_disable(struct nvt_dev *nvt)
99 {
100 outb(EFER_EFM_DISABLE, nvt->cr_efir);
101
102 release_region(nvt->cr_efir, 2);
103 }
104
105 /*
106 * When you want to address a specific logical device, write its logical
107 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
108 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
109 */
110 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
111 {
112 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
113 }
114
115 /* select and enable logical device with setting EFM mode*/
116 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
117 {
118 nvt_efm_enable(nvt);
119 nvt_select_logical_dev(nvt, ldev);
120 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
121 nvt_efm_disable(nvt);
122 }
123
124 /* select and disable logical device with setting EFM mode*/
125 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
126 {
127 nvt_efm_enable(nvt);
128 nvt_select_logical_dev(nvt, ldev);
129 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
130 nvt_efm_disable(nvt);
131 }
132
133 /* write val to cir config register */
134 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
135 {
136 outb(val, nvt->cir_addr + offset);
137 }
138
139 /* read val from cir config register */
140 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
141 {
142 u8 val;
143
144 val = inb(nvt->cir_addr + offset);
145
146 return val;
147 }
148
149 /* write val to cir wake register */
150 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
151 u8 val, u8 offset)
152 {
153 outb(val, nvt->cir_wake_addr + offset);
154 }
155
156 /* read val from cir wake config register */
157 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
158 {
159 u8 val;
160
161 val = inb(nvt->cir_wake_addr + offset);
162
163 return val;
164 }
165
166 /* don't override io address if one is set already */
167 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
168 {
169 unsigned long old_addr;
170
171 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
172 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
173
174 if (old_addr)
175 *ioaddr = old_addr;
176 else {
177 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
178 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
179 }
180 }
181
182 static ssize_t wakeup_data_show(struct device *dev,
183 struct device_attribute *attr,
184 char *buf)
185 {
186 struct rc_dev *rc_dev = to_rc_dev(dev);
187 struct nvt_dev *nvt = rc_dev->priv;
188 int fifo_len, duration;
189 unsigned long flags;
190 ssize_t buf_len = 0;
191 int i;
192
193 spin_lock_irqsave(&nvt->nvt_lock, flags);
194
195 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
196 fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
197
198 /* go to first element to be read */
199 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
201
202 for (i = 0; i < fifo_len; i++) {
203 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
204 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
205 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
206 "%d ", duration);
207 }
208 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
209
210 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
211
212 return buf_len;
213 }
214
215 static ssize_t wakeup_data_store(struct device *dev,
216 struct device_attribute *attr,
217 const char *buf, size_t len)
218 {
219 struct rc_dev *rc_dev = to_rc_dev(dev);
220 struct nvt_dev *nvt = rc_dev->priv;
221 unsigned long flags;
222 u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE];
223 char **argv;
224 int i, count;
225 unsigned int val;
226 ssize_t ret;
227
228 argv = argv_split(GFP_KERNEL, buf, &count);
229 if (!argv)
230 return -ENOMEM;
231 if (!count || count > WAKEUP_MAX_SIZE) {
232 ret = -EINVAL;
233 goto out;
234 }
235
236 for (i = 0; i < count; i++) {
237 ret = kstrtouint(argv[i], 10, &val);
238 if (ret)
239 goto out;
240 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
241 if (!val || val > 0x7f) {
242 ret = -EINVAL;
243 goto out;
244 }
245 wake_buf[i] = val;
246 /* sequence must start with a pulse */
247 if (i % 2 == 0)
248 wake_buf[i] |= BUF_PULSE_BIT;
249 }
250
251 /* hardcode the tolerance to 10% */
252 tolerance = DIV_ROUND_UP(count, 10);
253
254 spin_lock_irqsave(&nvt->nvt_lock, flags);
255
256 nvt_clear_cir_wake_fifo(nvt);
257 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
258 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
259
260 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
261
262 /* enable writes to wake fifo */
263 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
264 CIR_WAKE_IRCON);
265
266 for (i = 0; i < count; i++)
267 nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA);
268
269 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
270
271 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
272
273 ret = len;
274 out:
275 argv_free(argv);
276 return ret;
277 }
278 static DEVICE_ATTR_RW(wakeup_data);
279
280 /* dump current cir register contents */
281 static void cir_dump_regs(struct nvt_dev *nvt)
282 {
283 nvt_efm_enable(nvt);
284 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
285
286 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
287 pr_info(" * CR CIR ACTIVE : 0x%x\n",
288 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
289 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
290 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
291 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
292 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
293 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
294
295 nvt_efm_disable(nvt);
296
297 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
298 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
299 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
300 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
301 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
302 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
303 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
304 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
305 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
306 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
307 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
308 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
309 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
310 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
311 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
312 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
313 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
314 }
315
316 /* dump current cir wake register contents */
317 static void cir_wake_dump_regs(struct nvt_dev *nvt)
318 {
319 u8 i, fifo_len;
320
321 nvt_efm_enable(nvt);
322 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
323
324 pr_info("%s: Dump CIR WAKE logical device registers:\n",
325 NVT_DRIVER_NAME);
326 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
327 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
328 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
329 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
330 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
331 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
332 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
333
334 nvt_efm_disable(nvt);
335
336 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
337 pr_info(" * IRCON: 0x%x\n",
338 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
339 pr_info(" * IRSTS: 0x%x\n",
340 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
341 pr_info(" * IREN: 0x%x\n",
342 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
343 pr_info(" * FIFO CMP DEEP: 0x%x\n",
344 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
345 pr_info(" * FIFO CMP TOL: 0x%x\n",
346 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
347 pr_info(" * FIFO COUNT: 0x%x\n",
348 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
349 pr_info(" * SLCH: 0x%x\n",
350 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
351 pr_info(" * SLCL: 0x%x\n",
352 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
353 pr_info(" * FIFOCON: 0x%x\n",
354 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
355 pr_info(" * SRXFSTS: 0x%x\n",
356 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
357 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
358 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
359 pr_info(" * WR FIFO DATA: 0x%x\n",
360 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
361 pr_info(" * RD FIFO ONLY: 0x%x\n",
362 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
363 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
364 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
365 pr_info(" * FIFO IGNORE: 0x%x\n",
366 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
367 pr_info(" * IRFSM: 0x%x\n",
368 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
369
370 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
371 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
372 pr_info("* Contents =");
373 for (i = 0; i < fifo_len; i++)
374 pr_cont(" %02x",
375 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
376 pr_cont("\n");
377 }
378
379 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
380 {
381 int i;
382
383 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
384 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
385 nvt->chip_ver = nvt_chips[i].chip_ver;
386 return nvt_chips[i].name;
387 }
388
389 return NULL;
390 }
391
392
393 /* detect hardware features */
394 static int nvt_hw_detect(struct nvt_dev *nvt)
395 {
396 const char *chip_name;
397 int chip_id;
398
399 nvt_efm_enable(nvt);
400
401 /* Check if we're wired for the alternate EFER setup */
402 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
403 if (nvt->chip_major == 0xff) {
404 nvt->cr_efir = CR_EFIR2;
405 nvt->cr_efdr = CR_EFDR2;
406 nvt_efm_enable(nvt);
407 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
408 }
409 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
410
411 nvt_efm_disable(nvt);
412
413 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
414 if (chip_id == NVT_INVALID) {
415 dev_err(&nvt->pdev->dev,
416 "No device found on either EFM port\n");
417 return -ENODEV;
418 }
419
420 chip_name = nvt_find_chip(nvt, chip_id);
421
422 /* warn, but still let the driver load, if we don't know this chip */
423 if (!chip_name)
424 dev_warn(&nvt->pdev->dev,
425 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
426 nvt->chip_major, nvt->chip_minor);
427 else
428 dev_info(&nvt->pdev->dev,
429 "found %s or compatible: chip id: 0x%02x 0x%02x",
430 chip_name, nvt->chip_major, nvt->chip_minor);
431
432 return 0;
433 }
434
435 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
436 {
437 u8 val, psreg, psmask, psval;
438
439 if (is_w83667hg(nvt)) {
440 psreg = CR_MULTIFUNC_PIN_SEL;
441 psmask = MULTIFUNC_PIN_SEL_MASK;
442 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
443 } else {
444 psreg = CR_OUTPUT_PIN_SEL;
445 psmask = OUTPUT_PIN_SEL_MASK;
446 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
447 }
448
449 /* output pin selection: enable CIR, with WB sensor enabled */
450 val = nvt_cr_read(nvt, psreg);
451 val &= psmask;
452 val |= psval;
453 nvt_cr_write(nvt, val, psreg);
454
455 /* Select CIR logical device */
456 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
457
458 nvt_set_ioaddr(nvt, &nvt->cir_addr);
459
460 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
461
462 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
463 nvt->cir_addr, nvt->cir_irq);
464 }
465
466 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
467 {
468 /* Select ACPI logical device and anable it */
469 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
470 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
471
472 /* Enable CIR Wake via PSOUT# (Pin60) */
473 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
474
475 /* enable pme interrupt of cir wakeup event */
476 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
477
478 /* Select CIR Wake logical device */
479 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
480
481 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
482
483 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
484 nvt->cir_wake_addr);
485 }
486
487 /* clear out the hardware's cir rx fifo */
488 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
489 {
490 u8 val;
491
492 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
493 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
494 }
495
496 /* clear out the hardware's cir wake rx fifo */
497 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
498 {
499 u8 val, config;
500
501 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
502
503 /* clearing wake fifo works in learning mode only */
504 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
505 CIR_WAKE_IRCON);
506
507 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
508 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
509 CIR_WAKE_FIFOCON);
510
511 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
512 }
513
514 /* clear out the hardware's cir tx fifo */
515 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
516 {
517 u8 val;
518
519 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
520 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
521 }
522
523 /* enable RX Trigger Level Reach and Packet End interrupts */
524 static void nvt_set_cir_iren(struct nvt_dev *nvt)
525 {
526 u8 iren;
527
528 iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
529 nvt_cir_reg_write(nvt, iren, CIR_IREN);
530 }
531
532 static void nvt_cir_regs_init(struct nvt_dev *nvt)
533 {
534 /* set sample limit count (PE interrupt raised when reached) */
535 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
536 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
537
538 /* set fifo irq trigger levels */
539 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
540 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
541
542 /*
543 * Enable TX and RX, specify carrier on = low, off = high, and set
544 * sample period (currently 50us)
545 */
546 nvt_cir_reg_write(nvt,
547 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
548 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
549 CIR_IRCON);
550
551 /* clear hardware rx and tx fifos */
552 nvt_clear_cir_fifo(nvt);
553 nvt_clear_tx_fifo(nvt);
554
555 /* clear any and all stray interrupts */
556 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
557
558 /* and finally, enable interrupts */
559 nvt_set_cir_iren(nvt);
560
561 /* enable the CIR logical device */
562 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
563 }
564
565 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
566 {
567 /*
568 * Disable RX, set specific carrier on = low, off = high,
569 * and sample period (currently 50us)
570 */
571 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
572 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
573 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
574 CIR_WAKE_IRCON);
575
576 /* clear any and all stray interrupts */
577 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
578
579 /* enable the CIR WAKE logical device */
580 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
581 }
582
583 static void nvt_enable_wake(struct nvt_dev *nvt)
584 {
585 unsigned long flags;
586
587 nvt_efm_enable(nvt);
588
589 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
590 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
591 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
592
593 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
594 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
595
596 nvt_efm_disable(nvt);
597
598 spin_lock_irqsave(&nvt->nvt_lock, flags);
599
600 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
601 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
602 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
603 CIR_WAKE_IRCON);
604 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
605 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
606
607 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
608 }
609
610 #if 0 /* Currently unused */
611 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
612 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
613 {
614 u32 count, carrier, duration = 0;
615 int i;
616
617 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
618 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
619
620 for (i = 0; i < nvt->pkts; i++) {
621 if (nvt->buf[i] & BUF_PULSE_BIT)
622 duration += nvt->buf[i] & BUF_LEN_MASK;
623 }
624
625 duration *= SAMPLE_PERIOD;
626
627 if (!count || !duration) {
628 dev_notice(&nvt->pdev->dev,
629 "Unable to determine carrier! (c:%u, d:%u)",
630 count, duration);
631 return 0;
632 }
633
634 carrier = MS_TO_NS(count) / duration;
635
636 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
637 nvt_dbg("WTF? Carrier frequency out of range!");
638
639 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
640 carrier, count, duration);
641
642 return carrier;
643 }
644 #endif
645 /*
646 * set carrier frequency
647 *
648 * set carrier on 2 registers: CP & CC
649 * always set CP as 0x81
650 * set CC by SPEC, CC = 3MHz/carrier - 1
651 */
652 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
653 {
654 struct nvt_dev *nvt = dev->priv;
655 u16 val;
656
657 if (carrier == 0)
658 return -EINVAL;
659
660 nvt_cir_reg_write(nvt, 1, CIR_CP);
661 val = 3000000 / (carrier) - 1;
662 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
663
664 nvt_dbg("cp: 0x%x cc: 0x%x\n",
665 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
666
667 return 0;
668 }
669
670 /*
671 * nvt_tx_ir
672 *
673 * 1) clean TX fifo first (handled by AP)
674 * 2) copy data from user space
675 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
676 * 4) send 9 packets to TX FIFO to open TTR
677 * in interrupt_handler:
678 * 5) send all data out
679 * go back to write():
680 * 6) disable TX interrupts, re-enable RX interupts
681 *
682 * The key problem of this function is user space data may larger than
683 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
684 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
685 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
686 * set TXFCONT as 0xff, until buf_count less than 0xff.
687 */
688 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
689 {
690 struct nvt_dev *nvt = dev->priv;
691 unsigned long flags;
692 unsigned int i;
693 u8 iren;
694 int ret;
695
696 spin_lock_irqsave(&nvt->tx.lock, flags);
697
698 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
699 nvt->tx.buf_count = (ret * sizeof(unsigned));
700
701 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
702
703 nvt->tx.cur_buf_num = 0;
704
705 /* save currently enabled interrupts */
706 iren = nvt_cir_reg_read(nvt, CIR_IREN);
707
708 /* now disable all interrupts, save TFU & TTR */
709 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
710
711 nvt->tx.tx_state = ST_TX_REPLY;
712
713 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
714 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
715
716 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
717 for (i = 0; i < 9; i++)
718 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
719
720 spin_unlock_irqrestore(&nvt->tx.lock, flags);
721
722 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
723
724 spin_lock_irqsave(&nvt->tx.lock, flags);
725 nvt->tx.tx_state = ST_TX_NONE;
726 spin_unlock_irqrestore(&nvt->tx.lock, flags);
727
728 /* restore enabled interrupts to prior state */
729 nvt_cir_reg_write(nvt, iren, CIR_IREN);
730
731 return ret;
732 }
733
734 /* dump contents of the last rx buffer we got from the hw rx fifo */
735 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
736 {
737 int i;
738
739 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
740 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
741 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
742 printk(KERN_CONT "\n");
743 }
744
745 /*
746 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
747 * trigger decode when appropriate.
748 *
749 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
750 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
751 * (default 50us) intervals for that pulse/space. A discrete signal is
752 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
753 * to signal more IR coming (repeats) or end of IR, respectively. We store
754 * sample data in the raw event kfifo until we see 0x7<something> (except f)
755 * or 0x80, at which time, we trigger a decode operation.
756 */
757 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
758 {
759 DEFINE_IR_RAW_EVENT(rawir);
760 u8 sample;
761 int i;
762
763 nvt_dbg_verbose("%s firing", __func__);
764
765 if (debug)
766 nvt_dump_rx_buf(nvt);
767
768 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
769
770 init_ir_raw_event(&rawir);
771
772 for (i = 0; i < nvt->pkts; i++) {
773 sample = nvt->buf[i];
774
775 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
776 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
777 * SAMPLE_PERIOD);
778
779 nvt_dbg("Storing %s with duration %d",
780 rawir.pulse ? "pulse" : "space", rawir.duration);
781
782 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
783
784 /*
785 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
786 * indicates end of IR signal, but new data incoming. In both
787 * cases, it means we're ready to call ir_raw_event_handle
788 */
789 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
790 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
791 ir_raw_event_handle(nvt->rdev);
792 }
793 }
794
795 nvt->pkts = 0;
796
797 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
798 ir_raw_event_handle(nvt->rdev);
799
800 nvt_dbg_verbose("%s done", __func__);
801 }
802
803 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
804 {
805 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
806
807 nvt->pkts = 0;
808 nvt_clear_cir_fifo(nvt);
809 ir_raw_event_reset(nvt->rdev);
810 }
811
812 /* copy data from hardware rx fifo into driver buffer */
813 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
814 {
815 u8 fifocount, val;
816 unsigned int b_idx;
817 int i;
818
819 /* Get count of how many bytes to read from RX FIFO */
820 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
821 /* if we get 0xff, probably means the logical dev is disabled */
822 if (fifocount == 0xff)
823 return;
824
825 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
826
827 b_idx = nvt->pkts;
828
829 /* This should never happen, but lets check anyway... */
830 if (b_idx + fifocount > RX_BUF_LEN) {
831 nvt_process_rx_ir_data(nvt);
832 b_idx = 0;
833 }
834
835 /* Read fifocount bytes from CIR Sample RX FIFO register */
836 for (i = 0; i < fifocount; i++) {
837 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
838 nvt->buf[b_idx + i] = val;
839 }
840
841 nvt->pkts += fifocount;
842 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
843
844 nvt_process_rx_ir_data(nvt);
845 }
846
847 static void nvt_cir_log_irqs(u8 status, u8 iren)
848 {
849 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
850 status, iren,
851 status & CIR_IRSTS_RDR ? " RDR" : "",
852 status & CIR_IRSTS_RTR ? " RTR" : "",
853 status & CIR_IRSTS_PE ? " PE" : "",
854 status & CIR_IRSTS_RFO ? " RFO" : "",
855 status & CIR_IRSTS_TE ? " TE" : "",
856 status & CIR_IRSTS_TTR ? " TTR" : "",
857 status & CIR_IRSTS_TFU ? " TFU" : "",
858 status & CIR_IRSTS_GH ? " GH" : "",
859 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
860 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
861 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
862 }
863
864 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
865 {
866 unsigned long flags;
867 u8 tx_state;
868
869 spin_lock_irqsave(&nvt->tx.lock, flags);
870 tx_state = nvt->tx.tx_state;
871 spin_unlock_irqrestore(&nvt->tx.lock, flags);
872
873 return tx_state == ST_TX_NONE;
874 }
875
876 /* interrupt service routine for incoming and outgoing CIR data */
877 static irqreturn_t nvt_cir_isr(int irq, void *data)
878 {
879 struct nvt_dev *nvt = data;
880 u8 status, iren, cur_state;
881 unsigned long flags;
882
883 nvt_dbg_verbose("%s firing", __func__);
884
885 spin_lock_irqsave(&nvt->nvt_lock, flags);
886
887 /*
888 * Get IR Status register contents. Write 1 to ack/clear
889 *
890 * bit: reg name - description
891 * 7: CIR_IRSTS_RDR - RX Data Ready
892 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
893 * 5: CIR_IRSTS_PE - Packet End
894 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
895 * 3: CIR_IRSTS_TE - TX FIFO Empty
896 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
897 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
898 * 0: CIR_IRSTS_GH - Min Length Detected
899 */
900 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
901 iren = nvt_cir_reg_read(nvt, CIR_IREN);
902
903 /* IRQ may be shared with CIR WAKE, therefore check for each
904 * status bit whether the related interrupt source is enabled
905 */
906 if (!(status & iren)) {
907 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
908 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
909 return IRQ_NONE;
910 }
911
912 /* ack/clear all irq flags we've got */
913 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
914 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
915
916 nvt_cir_log_irqs(status, iren);
917
918 if (status & CIR_IRSTS_RFO)
919 nvt_handle_rx_fifo_overrun(nvt);
920
921 if (status & CIR_IRSTS_RTR) {
922 /* FIXME: add code for study/learn mode */
923 /* We only do rx if not tx'ing */
924 if (nvt_cir_tx_inactive(nvt))
925 nvt_get_rx_ir_data(nvt);
926 }
927
928 if (status & CIR_IRSTS_PE) {
929 if (nvt_cir_tx_inactive(nvt))
930 nvt_get_rx_ir_data(nvt);
931
932 cur_state = nvt->study_state;
933
934 if (cur_state == ST_STUDY_NONE)
935 nvt_clear_cir_fifo(nvt);
936 }
937
938 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
939
940 if (status & CIR_IRSTS_TE)
941 nvt_clear_tx_fifo(nvt);
942
943 if (status & CIR_IRSTS_TTR) {
944 unsigned int pos, count;
945 u8 tmp;
946
947 spin_lock_irqsave(&nvt->tx.lock, flags);
948
949 pos = nvt->tx.cur_buf_num;
950 count = nvt->tx.buf_count;
951
952 /* Write data into the hardware tx fifo while pos < count */
953 if (pos < count) {
954 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
955 nvt->tx.cur_buf_num++;
956 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
957 } else {
958 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
959 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
960 }
961
962 spin_unlock_irqrestore(&nvt->tx.lock, flags);
963
964 }
965
966 if (status & CIR_IRSTS_TFU) {
967 spin_lock_irqsave(&nvt->tx.lock, flags);
968 if (nvt->tx.tx_state == ST_TX_REPLY) {
969 nvt->tx.tx_state = ST_TX_REQUEST;
970 wake_up(&nvt->tx.queue);
971 }
972 spin_unlock_irqrestore(&nvt->tx.lock, flags);
973 }
974
975 nvt_dbg_verbose("%s done", __func__);
976 return IRQ_HANDLED;
977 }
978
979 static void nvt_disable_cir(struct nvt_dev *nvt)
980 {
981 unsigned long flags;
982
983 spin_lock_irqsave(&nvt->nvt_lock, flags);
984
985 /* disable CIR interrupts */
986 nvt_cir_reg_write(nvt, 0, CIR_IREN);
987
988 /* clear any and all pending interrupts */
989 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
990
991 /* clear all function enable flags */
992 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
993
994 /* clear hardware rx and tx fifos */
995 nvt_clear_cir_fifo(nvt);
996 nvt_clear_tx_fifo(nvt);
997
998 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
999
1000 /* disable the CIR logical device */
1001 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1002 }
1003
1004 static int nvt_open(struct rc_dev *dev)
1005 {
1006 struct nvt_dev *nvt = dev->priv;
1007 unsigned long flags;
1008
1009 spin_lock_irqsave(&nvt->nvt_lock, flags);
1010
1011 /* set function enable flags */
1012 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
1013 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
1014 CIR_IRCON);
1015
1016 /* clear all pending interrupts */
1017 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1018
1019 /* enable interrupts */
1020 nvt_set_cir_iren(nvt);
1021
1022 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1023
1024 /* enable the CIR logical device */
1025 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
1026
1027 return 0;
1028 }
1029
1030 static void nvt_close(struct rc_dev *dev)
1031 {
1032 struct nvt_dev *nvt = dev->priv;
1033
1034 nvt_disable_cir(nvt);
1035 }
1036
1037 /* Allocate memory, probe hardware, and initialize everything */
1038 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1039 {
1040 struct nvt_dev *nvt;
1041 struct rc_dev *rdev;
1042 int ret = -ENOMEM;
1043
1044 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
1045 if (!nvt)
1046 return ret;
1047
1048 /* input device for IR remote (and tx) */
1049 rdev = rc_allocate_device();
1050 if (!rdev)
1051 goto exit_free_dev_rdev;
1052
1053 ret = -ENODEV;
1054 /* activate pnp device */
1055 if (pnp_activate_dev(pdev) < 0) {
1056 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1057 goto exit_free_dev_rdev;
1058 }
1059
1060 /* validate pnp resources */
1061 if (!pnp_port_valid(pdev, 0) ||
1062 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1063 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1064 goto exit_free_dev_rdev;
1065 }
1066
1067 if (!pnp_irq_valid(pdev, 0)) {
1068 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1069 goto exit_free_dev_rdev;
1070 }
1071
1072 if (!pnp_port_valid(pdev, 1) ||
1073 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1074 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1075 goto exit_free_dev_rdev;
1076 }
1077
1078 nvt->cir_addr = pnp_port_start(pdev, 0);
1079 nvt->cir_irq = pnp_irq(pdev, 0);
1080
1081 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1082
1083 nvt->cr_efir = CR_EFIR;
1084 nvt->cr_efdr = CR_EFDR;
1085
1086 spin_lock_init(&nvt->nvt_lock);
1087 spin_lock_init(&nvt->tx.lock);
1088
1089 pnp_set_drvdata(pdev, nvt);
1090 nvt->pdev = pdev;
1091
1092 init_waitqueue_head(&nvt->tx.queue);
1093
1094 ret = nvt_hw_detect(nvt);
1095 if (ret)
1096 goto exit_free_dev_rdev;
1097
1098 /* Initialize CIR & CIR Wake Logical Devices */
1099 nvt_efm_enable(nvt);
1100 nvt_cir_ldev_init(nvt);
1101 nvt_cir_wake_ldev_init(nvt);
1102 nvt_efm_disable(nvt);
1103
1104 /*
1105 * Initialize CIR & CIR Wake Config Registers
1106 * and enable logical devices
1107 */
1108 nvt_cir_regs_init(nvt);
1109 nvt_cir_wake_regs_init(nvt);
1110
1111 /* Set up the rc device */
1112 rdev->priv = nvt;
1113 rdev->driver_type = RC_DRIVER_IR_RAW;
1114 rdev->allowed_protocols = RC_BIT_ALL;
1115 rdev->open = nvt_open;
1116 rdev->close = nvt_close;
1117 rdev->tx_ir = nvt_tx_ir;
1118 rdev->s_tx_carrier = nvt_set_tx_carrier;
1119 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1120 rdev->input_phys = "nuvoton/cir0";
1121 rdev->input_id.bustype = BUS_HOST;
1122 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1123 rdev->input_id.product = nvt->chip_major;
1124 rdev->input_id.version = nvt->chip_minor;
1125 rdev->dev.parent = &pdev->dev;
1126 rdev->driver_name = NVT_DRIVER_NAME;
1127 rdev->map_name = RC_MAP_RC6_MCE;
1128 rdev->timeout = MS_TO_NS(100);
1129 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1130 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1131 #if 0
1132 rdev->min_timeout = XYZ;
1133 rdev->max_timeout = XYZ;
1134 /* tx bits */
1135 rdev->tx_resolution = XYZ;
1136 #endif
1137 nvt->rdev = rdev;
1138
1139 ret = rc_register_device(rdev);
1140 if (ret)
1141 goto exit_free_dev_rdev;
1142
1143 ret = -EBUSY;
1144 /* now claim resources */
1145 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1146 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1147 goto exit_unregister_device;
1148
1149 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1150 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1151 goto exit_unregister_device;
1152
1153 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1154 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1155 goto exit_unregister_device;
1156
1157 ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1158 if (ret)
1159 goto exit_unregister_device;
1160
1161 device_init_wakeup(&pdev->dev, true);
1162
1163 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1164 if (debug) {
1165 cir_dump_regs(nvt);
1166 cir_wake_dump_regs(nvt);
1167 }
1168
1169 return 0;
1170
1171 exit_unregister_device:
1172 rc_unregister_device(rdev);
1173 rdev = NULL;
1174 exit_free_dev_rdev:
1175 rc_free_device(rdev);
1176
1177 return ret;
1178 }
1179
1180 static void nvt_remove(struct pnp_dev *pdev)
1181 {
1182 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1183
1184 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1185
1186 nvt_disable_cir(nvt);
1187
1188 /* enable CIR Wake (for IR power-on) */
1189 nvt_enable_wake(nvt);
1190
1191 rc_unregister_device(nvt->rdev);
1192 }
1193
1194 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1195 {
1196 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1197 unsigned long flags;
1198
1199 nvt_dbg("%s called", __func__);
1200
1201 spin_lock_irqsave(&nvt->tx.lock, flags);
1202 nvt->tx.tx_state = ST_TX_NONE;
1203 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1204
1205 spin_lock_irqsave(&nvt->nvt_lock, flags);
1206
1207 /* zero out misc state tracking */
1208 nvt->study_state = ST_STUDY_NONE;
1209
1210 /* disable all CIR interrupts */
1211 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1212
1213 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1214
1215 /* disable cir logical dev */
1216 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1217
1218 /* make sure wake is enabled */
1219 nvt_enable_wake(nvt);
1220
1221 return 0;
1222 }
1223
1224 static int nvt_resume(struct pnp_dev *pdev)
1225 {
1226 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1227
1228 nvt_dbg("%s called", __func__);
1229
1230 nvt_cir_regs_init(nvt);
1231 nvt_cir_wake_regs_init(nvt);
1232
1233 return 0;
1234 }
1235
1236 static void nvt_shutdown(struct pnp_dev *pdev)
1237 {
1238 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1239
1240 nvt_enable_wake(nvt);
1241 }
1242
1243 static const struct pnp_device_id nvt_ids[] = {
1244 { "WEC0530", 0 }, /* CIR */
1245 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1246 { "", 0 },
1247 };
1248
1249 static struct pnp_driver nvt_driver = {
1250 .name = NVT_DRIVER_NAME,
1251 .id_table = nvt_ids,
1252 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1253 .probe = nvt_probe,
1254 .remove = nvt_remove,
1255 .suspend = nvt_suspend,
1256 .resume = nvt_resume,
1257 .shutdown = nvt_shutdown,
1258 };
1259
1260 module_param(debug, int, S_IRUGO | S_IWUSR);
1261 MODULE_PARM_DESC(debug, "Enable debugging output");
1262
1263 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1264 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1265
1266 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1267 MODULE_LICENSE("GPL");
1268
1269 module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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