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[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
43
44 static const struct nvt_chip nvt_chips[] = {
45 { "w83667hg", NVT_W83667HG },
46 { "NCT6775F", NVT_6775F },
47 { "NCT6776F", NVT_6776F },
48 { "NCT6779D", NVT_6779D },
49 };
50
51 static inline bool is_w83667hg(struct nvt_dev *nvt)
52 {
53 return nvt->chip_ver == NVT_W83667HG;
54 }
55
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 outb(reg, nvt->cr_efir);
60 outb(val, nvt->cr_efdr);
61 }
62
63 /* read val from config reg */
64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
65 {
66 outb(reg, nvt->cr_efir);
67 return inb(nvt->cr_efdr);
68 }
69
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
72 {
73 u8 tmp = nvt_cr_read(nvt, reg) | val;
74 nvt_cr_write(nvt, tmp, reg);
75 }
76
77 /* clear config register bit without changing other bits */
78 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
79 {
80 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
81 nvt_cr_write(nvt, tmp, reg);
82 }
83
84 /* enter extended function mode */
85 static inline int nvt_efm_enable(struct nvt_dev *nvt)
86 {
87 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
88 return -EBUSY;
89
90 /* Enabling Extended Function Mode explicitly requires writing 2x */
91 outb(EFER_EFM_ENABLE, nvt->cr_efir);
92 outb(EFER_EFM_ENABLE, nvt->cr_efir);
93
94 return 0;
95 }
96
97 /* exit extended function mode */
98 static inline void nvt_efm_disable(struct nvt_dev *nvt)
99 {
100 outb(EFER_EFM_DISABLE, nvt->cr_efir);
101
102 release_region(nvt->cr_efir, 2);
103 }
104
105 /*
106 * When you want to address a specific logical device, write its logical
107 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
108 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
109 */
110 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
111 {
112 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
113 }
114
115 /* select and enable logical device with setting EFM mode*/
116 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
117 {
118 nvt_efm_enable(nvt);
119 nvt_select_logical_dev(nvt, ldev);
120 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
121 nvt_efm_disable(nvt);
122 }
123
124 /* select and disable logical device with setting EFM mode*/
125 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
126 {
127 nvt_efm_enable(nvt);
128 nvt_select_logical_dev(nvt, ldev);
129 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
130 nvt_efm_disable(nvt);
131 }
132
133 /* write val to cir config register */
134 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
135 {
136 outb(val, nvt->cir_addr + offset);
137 }
138
139 /* read val from cir config register */
140 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
141 {
142 return inb(nvt->cir_addr + offset);
143 }
144
145 /* write val to cir wake register */
146 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
147 u8 val, u8 offset)
148 {
149 outb(val, nvt->cir_wake_addr + offset);
150 }
151
152 /* read val from cir wake config register */
153 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
154 {
155 return inb(nvt->cir_wake_addr + offset);
156 }
157
158 /* don't override io address if one is set already */
159 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
160 {
161 unsigned long old_addr;
162
163 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
164 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
165
166 if (old_addr)
167 *ioaddr = old_addr;
168 else {
169 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
170 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
171 }
172 }
173
174 static ssize_t wakeup_data_show(struct device *dev,
175 struct device_attribute *attr,
176 char *buf)
177 {
178 struct rc_dev *rc_dev = to_rc_dev(dev);
179 struct nvt_dev *nvt = rc_dev->priv;
180 int fifo_len, duration;
181 unsigned long flags;
182 ssize_t buf_len = 0;
183 int i;
184
185 spin_lock_irqsave(&nvt->nvt_lock, flags);
186
187 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
188 fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
189
190 /* go to first element to be read */
191 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
193
194 for (i = 0; i < fifo_len; i++) {
195 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
196 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
197 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
198 "%d ", duration);
199 }
200 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
201
202 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
203
204 return buf_len;
205 }
206
207 static ssize_t wakeup_data_store(struct device *dev,
208 struct device_attribute *attr,
209 const char *buf, size_t len)
210 {
211 struct rc_dev *rc_dev = to_rc_dev(dev);
212 struct nvt_dev *nvt = rc_dev->priv;
213 unsigned long flags;
214 u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE];
215 char **argv;
216 int i, count;
217 unsigned int val;
218 ssize_t ret;
219
220 argv = argv_split(GFP_KERNEL, buf, &count);
221 if (!argv)
222 return -ENOMEM;
223 if (!count || count > WAKEUP_MAX_SIZE) {
224 ret = -EINVAL;
225 goto out;
226 }
227
228 for (i = 0; i < count; i++) {
229 ret = kstrtouint(argv[i], 10, &val);
230 if (ret)
231 goto out;
232 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
233 if (!val || val > 0x7f) {
234 ret = -EINVAL;
235 goto out;
236 }
237 wake_buf[i] = val;
238 /* sequence must start with a pulse */
239 if (i % 2 == 0)
240 wake_buf[i] |= BUF_PULSE_BIT;
241 }
242
243 /* hardcode the tolerance to 10% */
244 tolerance = DIV_ROUND_UP(count, 10);
245
246 spin_lock_irqsave(&nvt->nvt_lock, flags);
247
248 nvt_clear_cir_wake_fifo(nvt);
249 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
250 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
251
252 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
253
254 /* enable writes to wake fifo */
255 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
256 CIR_WAKE_IRCON);
257
258 for (i = 0; i < count; i++)
259 nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA);
260
261 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
262
263 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
264
265 ret = len;
266 out:
267 argv_free(argv);
268 return ret;
269 }
270 static DEVICE_ATTR_RW(wakeup_data);
271
272 /* dump current cir register contents */
273 static void cir_dump_regs(struct nvt_dev *nvt)
274 {
275 nvt_efm_enable(nvt);
276 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
277
278 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
279 pr_info(" * CR CIR ACTIVE : 0x%x\n",
280 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
281 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
282 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
283 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
284 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
285 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
286
287 nvt_efm_disable(nvt);
288
289 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
290 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
291 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
292 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
293 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
294 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
295 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
296 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
297 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
298 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
299 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
300 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
301 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
302 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
303 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
304 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
305 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
306 }
307
308 /* dump current cir wake register contents */
309 static void cir_wake_dump_regs(struct nvt_dev *nvt)
310 {
311 u8 i, fifo_len;
312
313 nvt_efm_enable(nvt);
314 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
315
316 pr_info("%s: Dump CIR WAKE logical device registers:\n",
317 NVT_DRIVER_NAME);
318 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
319 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
320 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
321 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
322 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
323 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
324 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
325
326 nvt_efm_disable(nvt);
327
328 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
329 pr_info(" * IRCON: 0x%x\n",
330 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
331 pr_info(" * IRSTS: 0x%x\n",
332 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
333 pr_info(" * IREN: 0x%x\n",
334 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
335 pr_info(" * FIFO CMP DEEP: 0x%x\n",
336 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
337 pr_info(" * FIFO CMP TOL: 0x%x\n",
338 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
339 pr_info(" * FIFO COUNT: 0x%x\n",
340 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
341 pr_info(" * SLCH: 0x%x\n",
342 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
343 pr_info(" * SLCL: 0x%x\n",
344 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
345 pr_info(" * FIFOCON: 0x%x\n",
346 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
347 pr_info(" * SRXFSTS: 0x%x\n",
348 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
349 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
350 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
351 pr_info(" * WR FIFO DATA: 0x%x\n",
352 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
353 pr_info(" * RD FIFO ONLY: 0x%x\n",
354 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
355 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
356 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
357 pr_info(" * FIFO IGNORE: 0x%x\n",
358 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
359 pr_info(" * IRFSM: 0x%x\n",
360 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
361
362 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
363 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
364 pr_info("* Contents =");
365 for (i = 0; i < fifo_len; i++)
366 pr_cont(" %02x",
367 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
368 pr_cont("\n");
369 }
370
371 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
372 {
373 int i;
374
375 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
376 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
377 nvt->chip_ver = nvt_chips[i].chip_ver;
378 return nvt_chips[i].name;
379 }
380
381 return NULL;
382 }
383
384
385 /* detect hardware features */
386 static int nvt_hw_detect(struct nvt_dev *nvt)
387 {
388 const char *chip_name;
389 int chip_id;
390
391 nvt_efm_enable(nvt);
392
393 /* Check if we're wired for the alternate EFER setup */
394 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
395 if (nvt->chip_major == 0xff) {
396 nvt->cr_efir = CR_EFIR2;
397 nvt->cr_efdr = CR_EFDR2;
398 nvt_efm_enable(nvt);
399 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
400 }
401 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
402
403 nvt_efm_disable(nvt);
404
405 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
406 if (chip_id == NVT_INVALID) {
407 dev_err(&nvt->pdev->dev,
408 "No device found on either EFM port\n");
409 return -ENODEV;
410 }
411
412 chip_name = nvt_find_chip(nvt, chip_id);
413
414 /* warn, but still let the driver load, if we don't know this chip */
415 if (!chip_name)
416 dev_warn(&nvt->pdev->dev,
417 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
418 nvt->chip_major, nvt->chip_minor);
419 else
420 dev_info(&nvt->pdev->dev,
421 "found %s or compatible: chip id: 0x%02x 0x%02x",
422 chip_name, nvt->chip_major, nvt->chip_minor);
423
424 return 0;
425 }
426
427 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
428 {
429 u8 val, psreg, psmask, psval;
430
431 if (is_w83667hg(nvt)) {
432 psreg = CR_MULTIFUNC_PIN_SEL;
433 psmask = MULTIFUNC_PIN_SEL_MASK;
434 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
435 } else {
436 psreg = CR_OUTPUT_PIN_SEL;
437 psmask = OUTPUT_PIN_SEL_MASK;
438 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
439 }
440
441 /* output pin selection: enable CIR, with WB sensor enabled */
442 val = nvt_cr_read(nvt, psreg);
443 val &= psmask;
444 val |= psval;
445 nvt_cr_write(nvt, val, psreg);
446
447 /* Select CIR logical device */
448 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
449
450 nvt_set_ioaddr(nvt, &nvt->cir_addr);
451
452 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
453
454 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
455 nvt->cir_addr, nvt->cir_irq);
456 }
457
458 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
459 {
460 /* Select ACPI logical device and anable it */
461 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
462 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
463
464 /* Enable CIR Wake via PSOUT# (Pin60) */
465 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
466
467 /* enable pme interrupt of cir wakeup event */
468 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
469
470 /* Select CIR Wake logical device */
471 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
472
473 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
474
475 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
476 nvt->cir_wake_addr);
477 }
478
479 /* clear out the hardware's cir rx fifo */
480 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
481 {
482 u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
483 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
484 }
485
486 /* clear out the hardware's cir wake rx fifo */
487 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
488 {
489 u8 val, config;
490
491 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
492
493 /* clearing wake fifo works in learning mode only */
494 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
495 CIR_WAKE_IRCON);
496
497 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
498 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
499 CIR_WAKE_FIFOCON);
500
501 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
502 }
503
504 /* clear out the hardware's cir tx fifo */
505 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
506 {
507 u8 val;
508
509 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
510 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
511 }
512
513 /* enable RX Trigger Level Reach and Packet End interrupts */
514 static void nvt_set_cir_iren(struct nvt_dev *nvt)
515 {
516 u8 iren;
517
518 iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
519 nvt_cir_reg_write(nvt, iren, CIR_IREN);
520 }
521
522 static void nvt_cir_regs_init(struct nvt_dev *nvt)
523 {
524 /* set sample limit count (PE interrupt raised when reached) */
525 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
526 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
527
528 /* set fifo irq trigger levels */
529 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
530 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
531
532 /*
533 * Enable TX and RX, specify carrier on = low, off = high, and set
534 * sample period (currently 50us)
535 */
536 nvt_cir_reg_write(nvt,
537 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
538 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
539 CIR_IRCON);
540
541 /* clear hardware rx and tx fifos */
542 nvt_clear_cir_fifo(nvt);
543 nvt_clear_tx_fifo(nvt);
544
545 /* clear any and all stray interrupts */
546 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
547
548 /* and finally, enable interrupts */
549 nvt_set_cir_iren(nvt);
550
551 /* enable the CIR logical device */
552 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
553 }
554
555 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
556 {
557 /*
558 * Disable RX, set specific carrier on = low, off = high,
559 * and sample period (currently 50us)
560 */
561 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
562 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
563 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
564 CIR_WAKE_IRCON);
565
566 /* clear any and all stray interrupts */
567 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
568
569 /* enable the CIR WAKE logical device */
570 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
571 }
572
573 static void nvt_enable_wake(struct nvt_dev *nvt)
574 {
575 unsigned long flags;
576
577 nvt_efm_enable(nvt);
578
579 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
580 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
581 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
582
583 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
584 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
585
586 nvt_efm_disable(nvt);
587
588 spin_lock_irqsave(&nvt->nvt_lock, flags);
589
590 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
591 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
592 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
593 CIR_WAKE_IRCON);
594 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
595 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
596
597 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
598 }
599
600 #if 0 /* Currently unused */
601 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
602 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
603 {
604 u32 count, carrier, duration = 0;
605 int i;
606
607 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
608 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
609
610 for (i = 0; i < nvt->pkts; i++) {
611 if (nvt->buf[i] & BUF_PULSE_BIT)
612 duration += nvt->buf[i] & BUF_LEN_MASK;
613 }
614
615 duration *= SAMPLE_PERIOD;
616
617 if (!count || !duration) {
618 dev_notice(&nvt->pdev->dev,
619 "Unable to determine carrier! (c:%u, d:%u)",
620 count, duration);
621 return 0;
622 }
623
624 carrier = MS_TO_NS(count) / duration;
625
626 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
627 nvt_dbg("WTF? Carrier frequency out of range!");
628
629 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
630 carrier, count, duration);
631
632 return carrier;
633 }
634 #endif
635 /*
636 * set carrier frequency
637 *
638 * set carrier on 2 registers: CP & CC
639 * always set CP as 0x81
640 * set CC by SPEC, CC = 3MHz/carrier - 1
641 */
642 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
643 {
644 struct nvt_dev *nvt = dev->priv;
645 u16 val;
646
647 if (carrier == 0)
648 return -EINVAL;
649
650 nvt_cir_reg_write(nvt, 1, CIR_CP);
651 val = 3000000 / (carrier) - 1;
652 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
653
654 nvt_dbg("cp: 0x%x cc: 0x%x\n",
655 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
656
657 return 0;
658 }
659
660 /*
661 * nvt_tx_ir
662 *
663 * 1) clean TX fifo first (handled by AP)
664 * 2) copy data from user space
665 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
666 * 4) send 9 packets to TX FIFO to open TTR
667 * in interrupt_handler:
668 * 5) send all data out
669 * go back to write():
670 * 6) disable TX interrupts, re-enable RX interupts
671 *
672 * The key problem of this function is user space data may larger than
673 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
674 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
675 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
676 * set TXFCONT as 0xff, until buf_count less than 0xff.
677 */
678 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
679 {
680 struct nvt_dev *nvt = dev->priv;
681 unsigned long flags;
682 unsigned int i;
683 u8 iren;
684 int ret;
685
686 spin_lock_irqsave(&nvt->tx.lock, flags);
687
688 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
689 nvt->tx.buf_count = (ret * sizeof(unsigned));
690
691 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
692
693 nvt->tx.cur_buf_num = 0;
694
695 /* save currently enabled interrupts */
696 iren = nvt_cir_reg_read(nvt, CIR_IREN);
697
698 /* now disable all interrupts, save TFU & TTR */
699 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
700
701 nvt->tx.tx_state = ST_TX_REPLY;
702
703 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
704 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
705
706 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
707 for (i = 0; i < 9; i++)
708 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
709
710 spin_unlock_irqrestore(&nvt->tx.lock, flags);
711
712 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
713
714 spin_lock_irqsave(&nvt->tx.lock, flags);
715 nvt->tx.tx_state = ST_TX_NONE;
716 spin_unlock_irqrestore(&nvt->tx.lock, flags);
717
718 /* restore enabled interrupts to prior state */
719 nvt_cir_reg_write(nvt, iren, CIR_IREN);
720
721 return ret;
722 }
723
724 /* dump contents of the last rx buffer we got from the hw rx fifo */
725 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
726 {
727 int i;
728
729 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
730 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
731 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
732 printk(KERN_CONT "\n");
733 }
734
735 /*
736 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
737 * trigger decode when appropriate.
738 *
739 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
740 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
741 * (default 50us) intervals for that pulse/space. A discrete signal is
742 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
743 * to signal more IR coming (repeats) or end of IR, respectively. We store
744 * sample data in the raw event kfifo until we see 0x7<something> (except f)
745 * or 0x80, at which time, we trigger a decode operation.
746 */
747 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
748 {
749 DEFINE_IR_RAW_EVENT(rawir);
750 u8 sample;
751 int i;
752
753 nvt_dbg_verbose("%s firing", __func__);
754
755 if (debug)
756 nvt_dump_rx_buf(nvt);
757
758 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
759
760 for (i = 0; i < nvt->pkts; i++) {
761 sample = nvt->buf[i];
762
763 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
764 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
765 * SAMPLE_PERIOD);
766
767 nvt_dbg("Storing %s with duration %d",
768 rawir.pulse ? "pulse" : "space", rawir.duration);
769
770 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
771
772 /*
773 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
774 * indicates end of IR signal, but new data incoming. In both
775 * cases, it means we're ready to call ir_raw_event_handle
776 */
777 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
778 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
779 ir_raw_event_handle(nvt->rdev);
780 }
781 }
782
783 nvt->pkts = 0;
784
785 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
786 ir_raw_event_handle(nvt->rdev);
787
788 nvt_dbg_verbose("%s done", __func__);
789 }
790
791 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
792 {
793 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
794
795 nvt->pkts = 0;
796 nvt_clear_cir_fifo(nvt);
797 ir_raw_event_reset(nvt->rdev);
798 }
799
800 /* copy data from hardware rx fifo into driver buffer */
801 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
802 {
803 u8 fifocount, val;
804 unsigned int b_idx;
805 int i;
806
807 /* Get count of how many bytes to read from RX FIFO */
808 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
809 /* if we get 0xff, probably means the logical dev is disabled */
810 if (fifocount == 0xff)
811 return;
812
813 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
814
815 b_idx = nvt->pkts;
816
817 /* This should never happen, but lets check anyway... */
818 if (b_idx + fifocount > RX_BUF_LEN) {
819 nvt_process_rx_ir_data(nvt);
820 b_idx = 0;
821 }
822
823 /* Read fifocount bytes from CIR Sample RX FIFO register */
824 for (i = 0; i < fifocount; i++) {
825 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
826 nvt->buf[b_idx + i] = val;
827 }
828
829 nvt->pkts += fifocount;
830 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
831
832 nvt_process_rx_ir_data(nvt);
833 }
834
835 static void nvt_cir_log_irqs(u8 status, u8 iren)
836 {
837 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
838 status, iren,
839 status & CIR_IRSTS_RDR ? " RDR" : "",
840 status & CIR_IRSTS_RTR ? " RTR" : "",
841 status & CIR_IRSTS_PE ? " PE" : "",
842 status & CIR_IRSTS_RFO ? " RFO" : "",
843 status & CIR_IRSTS_TE ? " TE" : "",
844 status & CIR_IRSTS_TTR ? " TTR" : "",
845 status & CIR_IRSTS_TFU ? " TFU" : "",
846 status & CIR_IRSTS_GH ? " GH" : "",
847 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
848 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
849 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
850 }
851
852 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
853 {
854 unsigned long flags;
855 u8 tx_state;
856
857 spin_lock_irqsave(&nvt->tx.lock, flags);
858 tx_state = nvt->tx.tx_state;
859 spin_unlock_irqrestore(&nvt->tx.lock, flags);
860
861 return tx_state == ST_TX_NONE;
862 }
863
864 /* interrupt service routine for incoming and outgoing CIR data */
865 static irqreturn_t nvt_cir_isr(int irq, void *data)
866 {
867 struct nvt_dev *nvt = data;
868 u8 status, iren;
869 unsigned long flags;
870
871 nvt_dbg_verbose("%s firing", __func__);
872
873 spin_lock_irqsave(&nvt->nvt_lock, flags);
874
875 /*
876 * Get IR Status register contents. Write 1 to ack/clear
877 *
878 * bit: reg name - description
879 * 7: CIR_IRSTS_RDR - RX Data Ready
880 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
881 * 5: CIR_IRSTS_PE - Packet End
882 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
883 * 3: CIR_IRSTS_TE - TX FIFO Empty
884 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
885 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
886 * 0: CIR_IRSTS_GH - Min Length Detected
887 */
888 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
889 iren = nvt_cir_reg_read(nvt, CIR_IREN);
890
891 /* IRQ may be shared with CIR WAKE, therefore check for each
892 * status bit whether the related interrupt source is enabled
893 */
894 if (!(status & iren)) {
895 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
896 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
897 return IRQ_NONE;
898 }
899
900 /* ack/clear all irq flags we've got */
901 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
902 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
903
904 nvt_cir_log_irqs(status, iren);
905
906 if (status & CIR_IRSTS_RFO)
907 nvt_handle_rx_fifo_overrun(nvt);
908
909 if (status & CIR_IRSTS_RTR) {
910 /* We only do rx if not tx'ing */
911 if (nvt_cir_tx_inactive(nvt))
912 nvt_get_rx_ir_data(nvt);
913 }
914
915 if (status & CIR_IRSTS_PE) {
916 if (nvt_cir_tx_inactive(nvt))
917 nvt_get_rx_ir_data(nvt);
918 }
919
920 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
921
922 if (status & CIR_IRSTS_TE)
923 nvt_clear_tx_fifo(nvt);
924
925 if (status & CIR_IRSTS_TTR) {
926 unsigned int pos, count;
927 u8 tmp;
928
929 spin_lock_irqsave(&nvt->tx.lock, flags);
930
931 pos = nvt->tx.cur_buf_num;
932 count = nvt->tx.buf_count;
933
934 /* Write data into the hardware tx fifo while pos < count */
935 if (pos < count) {
936 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
937 nvt->tx.cur_buf_num++;
938 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
939 } else {
940 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
941 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
942 }
943
944 spin_unlock_irqrestore(&nvt->tx.lock, flags);
945
946 }
947
948 if (status & CIR_IRSTS_TFU) {
949 spin_lock_irqsave(&nvt->tx.lock, flags);
950 if (nvt->tx.tx_state == ST_TX_REPLY) {
951 nvt->tx.tx_state = ST_TX_REQUEST;
952 wake_up(&nvt->tx.queue);
953 }
954 spin_unlock_irqrestore(&nvt->tx.lock, flags);
955 }
956
957 nvt_dbg_verbose("%s done", __func__);
958 return IRQ_HANDLED;
959 }
960
961 static void nvt_disable_cir(struct nvt_dev *nvt)
962 {
963 unsigned long flags;
964
965 spin_lock_irqsave(&nvt->nvt_lock, flags);
966
967 /* disable CIR interrupts */
968 nvt_cir_reg_write(nvt, 0, CIR_IREN);
969
970 /* clear any and all pending interrupts */
971 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
972
973 /* clear all function enable flags */
974 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
975
976 /* clear hardware rx and tx fifos */
977 nvt_clear_cir_fifo(nvt);
978 nvt_clear_tx_fifo(nvt);
979
980 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
981
982 /* disable the CIR logical device */
983 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
984 }
985
986 static int nvt_open(struct rc_dev *dev)
987 {
988 struct nvt_dev *nvt = dev->priv;
989 unsigned long flags;
990
991 spin_lock_irqsave(&nvt->nvt_lock, flags);
992
993 /* set function enable flags */
994 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
995 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
996 CIR_IRCON);
997
998 /* clear all pending interrupts */
999 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1000
1001 /* enable interrupts */
1002 nvt_set_cir_iren(nvt);
1003
1004 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1005
1006 /* enable the CIR logical device */
1007 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
1008
1009 return 0;
1010 }
1011
1012 static void nvt_close(struct rc_dev *dev)
1013 {
1014 struct nvt_dev *nvt = dev->priv;
1015
1016 nvt_disable_cir(nvt);
1017 }
1018
1019 /* Allocate memory, probe hardware, and initialize everything */
1020 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1021 {
1022 struct nvt_dev *nvt;
1023 struct rc_dev *rdev;
1024 int ret = -ENOMEM;
1025
1026 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
1027 if (!nvt)
1028 return ret;
1029
1030 /* input device for IR remote (and tx) */
1031 rdev = rc_allocate_device();
1032 if (!rdev)
1033 goto exit_free_dev_rdev;
1034
1035 ret = -ENODEV;
1036 /* activate pnp device */
1037 if (pnp_activate_dev(pdev) < 0) {
1038 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1039 goto exit_free_dev_rdev;
1040 }
1041
1042 /* validate pnp resources */
1043 if (!pnp_port_valid(pdev, 0) ||
1044 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1045 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1046 goto exit_free_dev_rdev;
1047 }
1048
1049 if (!pnp_irq_valid(pdev, 0)) {
1050 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1051 goto exit_free_dev_rdev;
1052 }
1053
1054 if (!pnp_port_valid(pdev, 1) ||
1055 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1056 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1057 goto exit_free_dev_rdev;
1058 }
1059
1060 nvt->cir_addr = pnp_port_start(pdev, 0);
1061 nvt->cir_irq = pnp_irq(pdev, 0);
1062
1063 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1064
1065 nvt->cr_efir = CR_EFIR;
1066 nvt->cr_efdr = CR_EFDR;
1067
1068 spin_lock_init(&nvt->nvt_lock);
1069 spin_lock_init(&nvt->tx.lock);
1070
1071 pnp_set_drvdata(pdev, nvt);
1072 nvt->pdev = pdev;
1073
1074 init_waitqueue_head(&nvt->tx.queue);
1075
1076 ret = nvt_hw_detect(nvt);
1077 if (ret)
1078 goto exit_free_dev_rdev;
1079
1080 /* Initialize CIR & CIR Wake Logical Devices */
1081 nvt_efm_enable(nvt);
1082 nvt_cir_ldev_init(nvt);
1083 nvt_cir_wake_ldev_init(nvt);
1084 nvt_efm_disable(nvt);
1085
1086 /*
1087 * Initialize CIR & CIR Wake Config Registers
1088 * and enable logical devices
1089 */
1090 nvt_cir_regs_init(nvt);
1091 nvt_cir_wake_regs_init(nvt);
1092
1093 /* Set up the rc device */
1094 rdev->priv = nvt;
1095 rdev->driver_type = RC_DRIVER_IR_RAW;
1096 rdev->allowed_protocols = RC_BIT_ALL;
1097 rdev->open = nvt_open;
1098 rdev->close = nvt_close;
1099 rdev->tx_ir = nvt_tx_ir;
1100 rdev->s_tx_carrier = nvt_set_tx_carrier;
1101 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1102 rdev->input_phys = "nuvoton/cir0";
1103 rdev->input_id.bustype = BUS_HOST;
1104 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1105 rdev->input_id.product = nvt->chip_major;
1106 rdev->input_id.version = nvt->chip_minor;
1107 rdev->dev.parent = &pdev->dev;
1108 rdev->driver_name = NVT_DRIVER_NAME;
1109 rdev->map_name = RC_MAP_RC6_MCE;
1110 rdev->timeout = MS_TO_NS(100);
1111 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1112 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1113 #if 0
1114 rdev->min_timeout = XYZ;
1115 rdev->max_timeout = XYZ;
1116 /* tx bits */
1117 rdev->tx_resolution = XYZ;
1118 #endif
1119 nvt->rdev = rdev;
1120
1121 ret = rc_register_device(rdev);
1122 if (ret)
1123 goto exit_free_dev_rdev;
1124
1125 ret = -EBUSY;
1126 /* now claim resources */
1127 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1128 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1129 goto exit_unregister_device;
1130
1131 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1132 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1133 goto exit_unregister_device;
1134
1135 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1136 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1137 goto exit_unregister_device;
1138
1139 ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1140 if (ret)
1141 goto exit_unregister_device;
1142
1143 device_init_wakeup(&pdev->dev, true);
1144
1145 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1146 if (debug) {
1147 cir_dump_regs(nvt);
1148 cir_wake_dump_regs(nvt);
1149 }
1150
1151 return 0;
1152
1153 exit_unregister_device:
1154 rc_unregister_device(rdev);
1155 rdev = NULL;
1156 exit_free_dev_rdev:
1157 rc_free_device(rdev);
1158
1159 return ret;
1160 }
1161
1162 static void nvt_remove(struct pnp_dev *pdev)
1163 {
1164 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1165
1166 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1167
1168 nvt_disable_cir(nvt);
1169
1170 /* enable CIR Wake (for IR power-on) */
1171 nvt_enable_wake(nvt);
1172
1173 rc_unregister_device(nvt->rdev);
1174 }
1175
1176 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1177 {
1178 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1179 unsigned long flags;
1180
1181 nvt_dbg("%s called", __func__);
1182
1183 spin_lock_irqsave(&nvt->tx.lock, flags);
1184 nvt->tx.tx_state = ST_TX_NONE;
1185 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1186
1187 spin_lock_irqsave(&nvt->nvt_lock, flags);
1188
1189 /* disable all CIR interrupts */
1190 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1191
1192 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1193
1194 /* disable cir logical dev */
1195 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1196
1197 /* make sure wake is enabled */
1198 nvt_enable_wake(nvt);
1199
1200 return 0;
1201 }
1202
1203 static int nvt_resume(struct pnp_dev *pdev)
1204 {
1205 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1206
1207 nvt_dbg("%s called", __func__);
1208
1209 nvt_cir_regs_init(nvt);
1210 nvt_cir_wake_regs_init(nvt);
1211
1212 return 0;
1213 }
1214
1215 static void nvt_shutdown(struct pnp_dev *pdev)
1216 {
1217 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1218
1219 nvt_enable_wake(nvt);
1220 }
1221
1222 static const struct pnp_device_id nvt_ids[] = {
1223 { "WEC0530", 0 }, /* CIR */
1224 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1225 { "", 0 },
1226 };
1227
1228 static struct pnp_driver nvt_driver = {
1229 .name = NVT_DRIVER_NAME,
1230 .id_table = nvt_ids,
1231 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1232 .probe = nvt_probe,
1233 .remove = nvt_remove,
1234 .suspend = nvt_suspend,
1235 .resume = nvt_resume,
1236 .shutdown = nvt_shutdown,
1237 };
1238
1239 module_param(debug, int, S_IRUGO | S_IWUSR);
1240 MODULE_PARM_DESC(debug, "Enable debugging output");
1241
1242 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1243 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1244
1245 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1246 MODULE_LICENSE("GPL");
1247
1248 module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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