2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
40 #include "nuvoton-cir.h"
42 static const struct nvt_chip nvt_chips
[] = {
43 { "w83667hg", NVT_W83667HG
},
44 { "NCT6775F", NVT_6775F
},
45 { "NCT6776F", NVT_6776F
},
46 { "NCT6779D", NVT_6779D
},
49 static inline bool is_w83667hg(struct nvt_dev
*nvt
)
51 return nvt
->chip_ver
== NVT_W83667HG
;
54 /* write val to config reg */
55 static inline void nvt_cr_write(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
57 outb(reg
, nvt
->cr_efir
);
58 outb(val
, nvt
->cr_efdr
);
61 /* read val from config reg */
62 static inline u8
nvt_cr_read(struct nvt_dev
*nvt
, u8 reg
)
64 outb(reg
, nvt
->cr_efir
);
65 return inb(nvt
->cr_efdr
);
68 /* update config register bit without changing other bits */
69 static inline void nvt_set_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
71 u8 tmp
= nvt_cr_read(nvt
, reg
) | val
;
72 nvt_cr_write(nvt
, tmp
, reg
);
75 /* clear config register bit without changing other bits */
76 static inline void nvt_clear_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
78 u8 tmp
= nvt_cr_read(nvt
, reg
) & ~val
;
79 nvt_cr_write(nvt
, tmp
, reg
);
82 /* enter extended function mode */
83 static inline int nvt_efm_enable(struct nvt_dev
*nvt
)
85 if (!request_muxed_region(nvt
->cr_efir
, 2, NVT_DRIVER_NAME
))
88 /* Enabling Extended Function Mode explicitly requires writing 2x */
89 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
90 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
95 /* exit extended function mode */
96 static inline void nvt_efm_disable(struct nvt_dev
*nvt
)
98 outb(EFER_EFM_DISABLE
, nvt
->cr_efir
);
100 release_region(nvt
->cr_efir
, 2);
104 * When you want to address a specific logical device, write its logical
105 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
106 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
108 static inline void nvt_select_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
110 nvt_cr_write(nvt
, ldev
, CR_LOGICAL_DEV_SEL
);
113 /* select and enable logical device with setting EFM mode*/
114 static inline void nvt_enable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
117 nvt_select_logical_dev(nvt
, ldev
);
118 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
119 nvt_efm_disable(nvt
);
122 /* select and disable logical device with setting EFM mode*/
123 static inline void nvt_disable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
126 nvt_select_logical_dev(nvt
, ldev
);
127 nvt_cr_write(nvt
, LOGICAL_DEV_DISABLE
, CR_LOGICAL_DEV_EN
);
128 nvt_efm_disable(nvt
);
131 /* write val to cir config register */
132 static inline void nvt_cir_reg_write(struct nvt_dev
*nvt
, u8 val
, u8 offset
)
134 outb(val
, nvt
->cir_addr
+ offset
);
137 /* read val from cir config register */
138 static u8
nvt_cir_reg_read(struct nvt_dev
*nvt
, u8 offset
)
142 val
= inb(nvt
->cir_addr
+ offset
);
147 /* write val to cir wake register */
148 static inline void nvt_cir_wake_reg_write(struct nvt_dev
*nvt
,
151 outb(val
, nvt
->cir_wake_addr
+ offset
);
154 /* read val from cir wake config register */
155 static u8
nvt_cir_wake_reg_read(struct nvt_dev
*nvt
, u8 offset
)
159 val
= inb(nvt
->cir_wake_addr
+ offset
);
164 /* don't override io address if one is set already */
165 static void nvt_set_ioaddr(struct nvt_dev
*nvt
, unsigned long *ioaddr
)
167 unsigned long old_addr
;
169 old_addr
= nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8;
170 old_addr
|= nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
);
175 nvt_cr_write(nvt
, *ioaddr
>> 8, CR_CIR_BASE_ADDR_HI
);
176 nvt_cr_write(nvt
, *ioaddr
& 0xff, CR_CIR_BASE_ADDR_LO
);
180 /* dump current cir register contents */
181 static void cir_dump_regs(struct nvt_dev
*nvt
)
184 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
186 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME
);
187 pr_info(" * CR CIR ACTIVE : 0x%x\n",
188 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
189 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
190 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
191 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
192 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
193 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
195 nvt_efm_disable(nvt
);
197 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME
);
198 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRCON
));
199 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRSTS
));
200 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IREN
));
201 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_RXFCONT
));
202 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CP
));
203 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CC
));
204 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCH
));
205 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCL
));
206 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FIFOCON
));
207 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFIFOSTS
));
208 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SRXFIFO
));
209 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_TXFCONT
));
210 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_STXFIFO
));
211 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCH
));
212 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCL
));
213 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFSM
));
216 /* dump current cir wake register contents */
217 static void cir_wake_dump_regs(struct nvt_dev
*nvt
)
222 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
224 pr_info("%s: Dump CIR WAKE logical device registers:\n",
226 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
227 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
228 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
229 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
230 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
231 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
232 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
234 nvt_efm_disable(nvt
);
236 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME
);
237 pr_info(" * IRCON: 0x%x\n",
238 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
));
239 pr_info(" * IRSTS: 0x%x\n",
240 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
));
241 pr_info(" * IREN: 0x%x\n",
242 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
));
243 pr_info(" * FIFO CMP DEEP: 0x%x\n",
244 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_DEEP
));
245 pr_info(" * FIFO CMP TOL: 0x%x\n",
246 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_TOL
));
247 pr_info(" * FIFO COUNT: 0x%x\n",
248 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
));
249 pr_info(" * SLCH: 0x%x\n",
250 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCH
));
251 pr_info(" * SLCL: 0x%x\n",
252 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCL
));
253 pr_info(" * FIFOCON: 0x%x\n",
254 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
));
255 pr_info(" * SRXFSTS: 0x%x\n",
256 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SRXFSTS
));
257 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
258 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SAMPLE_RX_FIFO
));
259 pr_info(" * WR FIFO DATA: 0x%x\n",
260 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_WR_FIFO_DATA
));
261 pr_info(" * RD FIFO ONLY: 0x%x\n",
262 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
263 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
264 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
));
265 pr_info(" * FIFO IGNORE: 0x%x\n",
266 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_IGNORE
));
267 pr_info(" * IRFSM: 0x%x\n",
268 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRFSM
));
270 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
271 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME
, fifo_len
);
272 pr_info("* Contents =");
273 for (i
= 0; i
< fifo_len
; i
++)
275 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
279 static inline const char *nvt_find_chip(struct nvt_dev
*nvt
, int id
)
283 for (i
= 0; i
< ARRAY_SIZE(nvt_chips
); i
++)
284 if ((id
& SIO_ID_MASK
) == nvt_chips
[i
].chip_ver
) {
285 nvt
->chip_ver
= nvt_chips
[i
].chip_ver
;
286 return nvt_chips
[i
].name
;
293 /* detect hardware features */
294 static int nvt_hw_detect(struct nvt_dev
*nvt
)
296 const char *chip_name
;
301 /* Check if we're wired for the alternate EFER setup */
302 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
303 if (nvt
->chip_major
== 0xff) {
304 nvt
->cr_efir
= CR_EFIR2
;
305 nvt
->cr_efdr
= CR_EFDR2
;
307 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
309 nvt
->chip_minor
= nvt_cr_read(nvt
, CR_CHIP_ID_LO
);
311 nvt_efm_disable(nvt
);
313 chip_id
= nvt
->chip_major
<< 8 | nvt
->chip_minor
;
314 if (chip_id
== NVT_INVALID
) {
315 dev_err(&nvt
->pdev
->dev
,
316 "No device found on either EFM port\n");
320 chip_name
= nvt_find_chip(nvt
, chip_id
);
322 /* warn, but still let the driver load, if we don't know this chip */
324 dev_warn(&nvt
->pdev
->dev
,
325 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
326 nvt
->chip_major
, nvt
->chip_minor
);
328 dev_info(&nvt
->pdev
->dev
,
329 "found %s or compatible: chip id: 0x%02x 0x%02x",
330 chip_name
, nvt
->chip_major
, nvt
->chip_minor
);
335 static void nvt_cir_ldev_init(struct nvt_dev
*nvt
)
337 u8 val
, psreg
, psmask
, psval
;
339 if (is_w83667hg(nvt
)) {
340 psreg
= CR_MULTIFUNC_PIN_SEL
;
341 psmask
= MULTIFUNC_PIN_SEL_MASK
;
342 psval
= MULTIFUNC_ENABLE_CIR
| MULTIFUNC_ENABLE_CIRWB
;
344 psreg
= CR_OUTPUT_PIN_SEL
;
345 psmask
= OUTPUT_PIN_SEL_MASK
;
346 psval
= OUTPUT_ENABLE_CIR
| OUTPUT_ENABLE_CIRWB
;
349 /* output pin selection: enable CIR, with WB sensor enabled */
350 val
= nvt_cr_read(nvt
, psreg
);
353 nvt_cr_write(nvt
, val
, psreg
);
355 /* Select CIR logical device */
356 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
358 nvt_set_ioaddr(nvt
, &nvt
->cir_addr
);
360 nvt_cr_write(nvt
, nvt
->cir_irq
, CR_CIR_IRQ_RSRC
);
362 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
363 nvt
->cir_addr
, nvt
->cir_irq
);
366 static void nvt_cir_wake_ldev_init(struct nvt_dev
*nvt
)
368 /* Select ACPI logical device and anable it */
369 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
370 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
372 /* Enable CIR Wake via PSOUT# (Pin60) */
373 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
375 /* enable pme interrupt of cir wakeup event */
376 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
378 /* Select CIR Wake logical device */
379 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
381 nvt_set_ioaddr(nvt
, &nvt
->cir_wake_addr
);
383 nvt_cr_write(nvt
, nvt
->cir_wake_irq
, CR_CIR_IRQ_RSRC
);
385 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
386 nvt
->cir_wake_addr
, nvt
->cir_wake_irq
);
389 /* clear out the hardware's cir rx fifo */
390 static void nvt_clear_cir_fifo(struct nvt_dev
*nvt
)
394 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
395 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
398 /* clear out the hardware's cir wake rx fifo */
399 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
)
403 config
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
);
405 /* clearing wake fifo works in learning mode only */
406 nvt_cir_wake_reg_write(nvt
, config
& ~CIR_WAKE_IRCON_MODE0
,
409 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
);
410 nvt_cir_wake_reg_write(nvt
, val
| CIR_WAKE_FIFOCON_RXFIFOCLR
,
413 nvt_cir_wake_reg_write(nvt
, config
, CIR_WAKE_IRCON
);
416 /* clear out the hardware's cir tx fifo */
417 static void nvt_clear_tx_fifo(struct nvt_dev
*nvt
)
421 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
422 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_TXFIFOCLR
, CIR_FIFOCON
);
425 /* enable RX Trigger Level Reach and Packet End interrupts */
426 static void nvt_set_cir_iren(struct nvt_dev
*nvt
)
430 iren
= CIR_IREN_RTR
| CIR_IREN_PE
;
431 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
434 static void nvt_cir_regs_init(struct nvt_dev
*nvt
)
436 /* set sample limit count (PE interrupt raised when reached) */
437 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_SLCH
);
438 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_SLCL
);
440 /* set fifo irq trigger levels */
441 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV
|
442 CIR_FIFOCON_RX_TRIGGER_LEV
, CIR_FIFOCON
);
445 * Enable TX and RX, specify carrier on = low, off = high, and set
446 * sample period (currently 50us)
448 nvt_cir_reg_write(nvt
,
449 CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
450 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
453 /* clear hardware rx and tx fifos */
454 nvt_clear_cir_fifo(nvt
);
455 nvt_clear_tx_fifo(nvt
);
457 /* clear any and all stray interrupts */
458 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
460 /* and finally, enable interrupts */
461 nvt_set_cir_iren(nvt
);
463 /* enable the CIR logical device */
464 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
467 static void nvt_cir_wake_regs_init(struct nvt_dev
*nvt
)
469 /* set number of bytes needed for wake from s3 (default 65) */
470 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_FIFO_CMP_BYTES
,
471 CIR_WAKE_FIFO_CMP_DEEP
);
473 /* set tolerance/variance allowed per byte during wake compare */
474 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_CMP_TOLERANCE
,
475 CIR_WAKE_FIFO_CMP_TOL
);
477 /* set sample limit count (PE interrupt raised when reached) */
478 nvt_cir_wake_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_WAKE_SLCH
);
479 nvt_cir_wake_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_WAKE_SLCL
);
481 /* set cir wake fifo rx trigger level (currently 67) */
482 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV
,
486 * Enable TX and RX, specific carrier on = low, off = high, and set
487 * sample period (currently 50us)
489 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
490 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
491 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
494 /* clear cir wake rx fifo */
495 nvt_clear_cir_wake_fifo(nvt
);
497 /* clear any and all stray interrupts */
498 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
500 /* enable the CIR WAKE logical device */
501 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
504 static void nvt_enable_wake(struct nvt_dev
*nvt
)
508 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
509 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
510 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
512 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
513 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
515 nvt_efm_disable(nvt
);
517 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
518 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
519 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
521 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
522 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
525 #if 0 /* Currently unused */
526 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
527 static u32
nvt_rx_carrier_detect(struct nvt_dev
*nvt
)
529 u32 count
, carrier
, duration
= 0;
532 count
= nvt_cir_reg_read(nvt
, CIR_FCCL
) |
533 nvt_cir_reg_read(nvt
, CIR_FCCH
) << 8;
535 for (i
= 0; i
< nvt
->pkts
; i
++) {
536 if (nvt
->buf
[i
] & BUF_PULSE_BIT
)
537 duration
+= nvt
->buf
[i
] & BUF_LEN_MASK
;
540 duration
*= SAMPLE_PERIOD
;
542 if (!count
|| !duration
) {
543 dev_notice(&nvt
->pdev
->dev
,
544 "Unable to determine carrier! (c:%u, d:%u)",
549 carrier
= MS_TO_NS(count
) / duration
;
551 if ((carrier
> MAX_CARRIER
) || (carrier
< MIN_CARRIER
))
552 nvt_dbg("WTF? Carrier frequency out of range!");
554 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
555 carrier
, count
, duration
);
561 * set carrier frequency
563 * set carrier on 2 registers: CP & CC
564 * always set CP as 0x81
565 * set CC by SPEC, CC = 3MHz/carrier - 1
567 static int nvt_set_tx_carrier(struct rc_dev
*dev
, u32 carrier
)
569 struct nvt_dev
*nvt
= dev
->priv
;
575 nvt_cir_reg_write(nvt
, 1, CIR_CP
);
576 val
= 3000000 / (carrier
) - 1;
577 nvt_cir_reg_write(nvt
, val
& 0xff, CIR_CC
);
579 nvt_dbg("cp: 0x%x cc: 0x%x\n",
580 nvt_cir_reg_read(nvt
, CIR_CP
), nvt_cir_reg_read(nvt
, CIR_CC
));
588 * 1) clean TX fifo first (handled by AP)
589 * 2) copy data from user space
590 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
591 * 4) send 9 packets to TX FIFO to open TTR
592 * in interrupt_handler:
593 * 5) send all data out
594 * go back to write():
595 * 6) disable TX interrupts, re-enable RX interupts
597 * The key problem of this function is user space data may larger than
598 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
599 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
600 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
601 * set TXFCONT as 0xff, until buf_count less than 0xff.
603 static int nvt_tx_ir(struct rc_dev
*dev
, unsigned *txbuf
, unsigned n
)
605 struct nvt_dev
*nvt
= dev
->priv
;
611 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
613 ret
= min((unsigned)(TX_BUF_LEN
/ sizeof(unsigned)), n
);
614 nvt
->tx
.buf_count
= (ret
* sizeof(unsigned));
616 memcpy(nvt
->tx
.buf
, txbuf
, nvt
->tx
.buf_count
);
618 nvt
->tx
.cur_buf_num
= 0;
620 /* save currently enabled interrupts */
621 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
623 /* now disable all interrupts, save TFU & TTR */
624 nvt_cir_reg_write(nvt
, CIR_IREN_TFU
| CIR_IREN_TTR
, CIR_IREN
);
626 nvt
->tx
.tx_state
= ST_TX_REPLY
;
628 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV_8
|
629 CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
631 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
632 for (i
= 0; i
< 9; i
++)
633 nvt_cir_reg_write(nvt
, 0x01, CIR_STXFIFO
);
635 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
637 wait_event(nvt
->tx
.queue
, nvt
->tx
.tx_state
== ST_TX_REQUEST
);
639 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
640 nvt
->tx
.tx_state
= ST_TX_NONE
;
641 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
643 /* restore enabled interrupts to prior state */
644 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
649 /* dump contents of the last rx buffer we got from the hw rx fifo */
650 static void nvt_dump_rx_buf(struct nvt_dev
*nvt
)
654 printk(KERN_DEBUG
"%s (len %d): ", __func__
, nvt
->pkts
);
655 for (i
= 0; (i
< nvt
->pkts
) && (i
< RX_BUF_LEN
); i
++)
656 printk(KERN_CONT
"0x%02x ", nvt
->buf
[i
]);
657 printk(KERN_CONT
"\n");
661 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
662 * trigger decode when appropriate.
664 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
665 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
666 * (default 50us) intervals for that pulse/space. A discrete signal is
667 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
668 * to signal more IR coming (repeats) or end of IR, respectively. We store
669 * sample data in the raw event kfifo until we see 0x7<something> (except f)
670 * or 0x80, at which time, we trigger a decode operation.
672 static void nvt_process_rx_ir_data(struct nvt_dev
*nvt
)
674 DEFINE_IR_RAW_EVENT(rawir
);
678 nvt_dbg_verbose("%s firing", __func__
);
681 nvt_dump_rx_buf(nvt
);
683 nvt_dbg_verbose("Processing buffer of len %d", nvt
->pkts
);
685 init_ir_raw_event(&rawir
);
687 for (i
= 0; i
< nvt
->pkts
; i
++) {
688 sample
= nvt
->buf
[i
];
690 rawir
.pulse
= ((sample
& BUF_PULSE_BIT
) != 0);
691 rawir
.duration
= US_TO_NS((sample
& BUF_LEN_MASK
)
694 nvt_dbg("Storing %s with duration %d",
695 rawir
.pulse
? "pulse" : "space", rawir
.duration
);
697 ir_raw_event_store_with_filter(nvt
->rdev
, &rawir
);
700 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
701 * indicates end of IR signal, but new data incoming. In both
702 * cases, it means we're ready to call ir_raw_event_handle
704 if ((sample
== BUF_PULSE_BIT
) && (i
+ 1 < nvt
->pkts
)) {
705 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
706 ir_raw_event_handle(nvt
->rdev
);
712 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
713 ir_raw_event_handle(nvt
->rdev
);
715 nvt_dbg_verbose("%s done", __func__
);
718 static void nvt_handle_rx_fifo_overrun(struct nvt_dev
*nvt
)
720 dev_warn(&nvt
->pdev
->dev
, "RX FIFO overrun detected, flushing data!");
723 nvt_clear_cir_fifo(nvt
);
724 ir_raw_event_reset(nvt
->rdev
);
727 /* copy data from hardware rx fifo into driver buffer */
728 static void nvt_get_rx_ir_data(struct nvt_dev
*nvt
)
733 bool overrun
= false;
736 /* Get count of how many bytes to read from RX FIFO */
737 fifocount
= nvt_cir_reg_read(nvt
, CIR_RXFCONT
);
738 /* if we get 0xff, probably means the logical dev is disabled */
739 if (fifocount
== 0xff)
741 /* watch out for a fifo overrun condition */
742 else if (fifocount
> RX_BUF_LEN
) {
744 fifocount
= RX_BUF_LEN
;
747 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount
);
749 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
753 /* This should never happen, but lets check anyway... */
754 if (b_idx
+ fifocount
> RX_BUF_LEN
) {
755 nvt_process_rx_ir_data(nvt
);
759 /* Read fifocount bytes from CIR Sample RX FIFO register */
760 for (i
= 0; i
< fifocount
; i
++) {
761 val
= nvt_cir_reg_read(nvt
, CIR_SRXFIFO
);
762 nvt
->buf
[b_idx
+ i
] = val
;
765 nvt
->pkts
+= fifocount
;
766 nvt_dbg("%s: pkts now %d", __func__
, nvt
->pkts
);
768 nvt_process_rx_ir_data(nvt
);
771 nvt_handle_rx_fifo_overrun(nvt
);
773 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
776 static void nvt_cir_log_irqs(u8 status
, u8 iren
)
778 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
780 status
& CIR_IRSTS_RDR
? " RDR" : "",
781 status
& CIR_IRSTS_RTR
? " RTR" : "",
782 status
& CIR_IRSTS_PE
? " PE" : "",
783 status
& CIR_IRSTS_RFO
? " RFO" : "",
784 status
& CIR_IRSTS_TE
? " TE" : "",
785 status
& CIR_IRSTS_TTR
? " TTR" : "",
786 status
& CIR_IRSTS_TFU
? " TFU" : "",
787 status
& CIR_IRSTS_GH
? " GH" : "",
788 status
& ~(CIR_IRSTS_RDR
| CIR_IRSTS_RTR
| CIR_IRSTS_PE
|
789 CIR_IRSTS_RFO
| CIR_IRSTS_TE
| CIR_IRSTS_TTR
|
790 CIR_IRSTS_TFU
| CIR_IRSTS_GH
) ? " ?" : "");
793 static bool nvt_cir_tx_inactive(struct nvt_dev
*nvt
)
798 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
799 tx_state
= nvt
->tx
.tx_state
;
800 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
802 return tx_state
== ST_TX_NONE
;
805 /* interrupt service routine for incoming and outgoing CIR data */
806 static irqreturn_t
nvt_cir_isr(int irq
, void *data
)
808 struct nvt_dev
*nvt
= data
;
809 u8 status
, iren
, cur_state
;
812 nvt_dbg_verbose("%s firing", __func__
);
815 * Get IR Status register contents. Write 1 to ack/clear
817 * bit: reg name - description
818 * 7: CIR_IRSTS_RDR - RX Data Ready
819 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
820 * 5: CIR_IRSTS_PE - Packet End
821 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
822 * 3: CIR_IRSTS_TE - TX FIFO Empty
823 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
824 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
825 * 0: CIR_IRSTS_GH - Min Length Detected
827 status
= nvt_cir_reg_read(nvt
, CIR_IRSTS
);
829 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__
);
830 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
834 /* ack/clear all irq flags we've got */
835 nvt_cir_reg_write(nvt
, status
, CIR_IRSTS
);
836 nvt_cir_reg_write(nvt
, 0, CIR_IRSTS
);
838 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
839 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
841 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__
);
845 nvt_cir_log_irqs(status
, iren
);
847 if (status
& CIR_IRSTS_RTR
) {
848 /* FIXME: add code for study/learn mode */
849 /* We only do rx if not tx'ing */
850 if (nvt_cir_tx_inactive(nvt
))
851 nvt_get_rx_ir_data(nvt
);
854 if (status
& CIR_IRSTS_PE
) {
855 if (nvt_cir_tx_inactive(nvt
))
856 nvt_get_rx_ir_data(nvt
);
858 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
860 cur_state
= nvt
->study_state
;
862 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
864 if (cur_state
== ST_STUDY_NONE
)
865 nvt_clear_cir_fifo(nvt
);
868 if (status
& CIR_IRSTS_TE
)
869 nvt_clear_tx_fifo(nvt
);
871 if (status
& CIR_IRSTS_TTR
) {
872 unsigned int pos
, count
;
875 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
877 pos
= nvt
->tx
.cur_buf_num
;
878 count
= nvt
->tx
.buf_count
;
880 /* Write data into the hardware tx fifo while pos < count */
882 nvt_cir_reg_write(nvt
, nvt
->tx
.buf
[pos
], CIR_STXFIFO
);
883 nvt
->tx
.cur_buf_num
++;
884 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
886 tmp
= nvt_cir_reg_read(nvt
, CIR_IREN
);
887 nvt_cir_reg_write(nvt
, tmp
& ~CIR_IREN_TTR
, CIR_IREN
);
890 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
894 if (status
& CIR_IRSTS_TFU
) {
895 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
896 if (nvt
->tx
.tx_state
== ST_TX_REPLY
) {
897 nvt
->tx
.tx_state
= ST_TX_REQUEST
;
898 wake_up(&nvt
->tx
.queue
);
900 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
903 nvt_dbg_verbose("%s done", __func__
);
907 /* Interrupt service routine for CIR Wake */
908 static irqreturn_t
nvt_cir_wake_isr(int irq
, void *data
)
910 u8 status
, iren
, val
;
911 struct nvt_dev
*nvt
= data
;
914 nvt_dbg_wake("%s firing", __func__
);
916 status
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
);
920 if (status
& CIR_WAKE_IRSTS_IR_PENDING
)
921 nvt_clear_cir_wake_fifo(nvt
);
923 nvt_cir_wake_reg_write(nvt
, status
, CIR_WAKE_IRSTS
);
924 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IRSTS
);
926 /* Interrupt may be shared with CIR, bail if Wake not enabled */
927 iren
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
);
929 nvt_dbg_wake("%s exiting, wake not enabled", __func__
);
933 if ((status
& CIR_WAKE_IRSTS_PE
) &&
934 (nvt
->wake_state
== ST_WAKE_START
)) {
935 while (nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
)) {
936 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
937 nvt_dbg("setting wake up key: 0x%x", val
);
940 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
941 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
942 nvt
->wake_state
= ST_WAKE_FINISH
;
943 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
946 nvt_dbg_wake("%s done", __func__
);
950 static void nvt_enable_cir(struct nvt_dev
*nvt
)
952 /* set function enable flags */
953 nvt_cir_reg_write(nvt
, CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
954 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
957 /* enable the CIR logical device */
958 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
960 /* clear all pending interrupts */
961 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
963 /* enable interrupts */
964 nvt_set_cir_iren(nvt
);
967 static void nvt_disable_cir(struct nvt_dev
*nvt
)
969 /* disable CIR interrupts */
970 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
972 /* clear any and all pending interrupts */
973 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
975 /* clear all function enable flags */
976 nvt_cir_reg_write(nvt
, 0, CIR_IRCON
);
978 /* clear hardware rx and tx fifos */
979 nvt_clear_cir_fifo(nvt
);
980 nvt_clear_tx_fifo(nvt
);
982 /* disable the CIR logical device */
983 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
986 static int nvt_open(struct rc_dev
*dev
)
988 struct nvt_dev
*nvt
= dev
->priv
;
991 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
993 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
998 static void nvt_close(struct rc_dev
*dev
)
1000 struct nvt_dev
*nvt
= dev
->priv
;
1001 unsigned long flags
;
1003 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1004 nvt_disable_cir(nvt
);
1005 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1008 /* Allocate memory, probe hardware, and initialize everything */
1009 static int nvt_probe(struct pnp_dev
*pdev
, const struct pnp_device_id
*dev_id
)
1011 struct nvt_dev
*nvt
;
1012 struct rc_dev
*rdev
;
1015 nvt
= devm_kzalloc(&pdev
->dev
, sizeof(struct nvt_dev
), GFP_KERNEL
);
1019 /* input device for IR remote (and tx) */
1020 rdev
= rc_allocate_device();
1022 goto exit_free_dev_rdev
;
1025 /* activate pnp device */
1026 if (pnp_activate_dev(pdev
) < 0) {
1027 dev_err(&pdev
->dev
, "Could not activate PNP device!\n");
1028 goto exit_free_dev_rdev
;
1031 /* validate pnp resources */
1032 if (!pnp_port_valid(pdev
, 0) ||
1033 pnp_port_len(pdev
, 0) < CIR_IOREG_LENGTH
) {
1034 dev_err(&pdev
->dev
, "IR PNP Port not valid!\n");
1035 goto exit_free_dev_rdev
;
1038 if (!pnp_irq_valid(pdev
, 0)) {
1039 dev_err(&pdev
->dev
, "PNP IRQ not valid!\n");
1040 goto exit_free_dev_rdev
;
1043 if (!pnp_port_valid(pdev
, 1) ||
1044 pnp_port_len(pdev
, 1) < CIR_IOREG_LENGTH
) {
1045 dev_err(&pdev
->dev
, "Wake PNP Port not valid!\n");
1046 goto exit_free_dev_rdev
;
1049 nvt
->cir_addr
= pnp_port_start(pdev
, 0);
1050 nvt
->cir_irq
= pnp_irq(pdev
, 0);
1052 nvt
->cir_wake_addr
= pnp_port_start(pdev
, 1);
1053 /* irq is always shared between cir and cir wake */
1054 nvt
->cir_wake_irq
= nvt
->cir_irq
;
1056 nvt
->cr_efir
= CR_EFIR
;
1057 nvt
->cr_efdr
= CR_EFDR
;
1059 spin_lock_init(&nvt
->nvt_lock
);
1060 spin_lock_init(&nvt
->tx
.lock
);
1062 pnp_set_drvdata(pdev
, nvt
);
1065 init_waitqueue_head(&nvt
->tx
.queue
);
1067 ret
= nvt_hw_detect(nvt
);
1069 goto exit_free_dev_rdev
;
1071 /* Initialize CIR & CIR Wake Logical Devices */
1072 nvt_efm_enable(nvt
);
1073 nvt_cir_ldev_init(nvt
);
1074 nvt_cir_wake_ldev_init(nvt
);
1075 nvt_efm_disable(nvt
);
1078 * Initialize CIR & CIR Wake Config Registers
1079 * and enable logical devices
1081 nvt_cir_regs_init(nvt
);
1082 nvt_cir_wake_regs_init(nvt
);
1084 /* Set up the rc device */
1086 rdev
->driver_type
= RC_DRIVER_IR_RAW
;
1087 rdev
->allowed_protocols
= RC_BIT_ALL
;
1088 rdev
->open
= nvt_open
;
1089 rdev
->close
= nvt_close
;
1090 rdev
->tx_ir
= nvt_tx_ir
;
1091 rdev
->s_tx_carrier
= nvt_set_tx_carrier
;
1092 rdev
->input_name
= "Nuvoton w836x7hg Infrared Remote Transceiver";
1093 rdev
->input_phys
= "nuvoton/cir0";
1094 rdev
->input_id
.bustype
= BUS_HOST
;
1095 rdev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND2
;
1096 rdev
->input_id
.product
= nvt
->chip_major
;
1097 rdev
->input_id
.version
= nvt
->chip_minor
;
1098 rdev
->dev
.parent
= &pdev
->dev
;
1099 rdev
->driver_name
= NVT_DRIVER_NAME
;
1100 rdev
->map_name
= RC_MAP_RC6_MCE
;
1101 rdev
->timeout
= MS_TO_NS(100);
1102 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1103 rdev
->rx_resolution
= US_TO_NS(CIR_SAMPLE_PERIOD
);
1105 rdev
->min_timeout
= XYZ
;
1106 rdev
->max_timeout
= XYZ
;
1108 rdev
->tx_resolution
= XYZ
;
1112 ret
= rc_register_device(rdev
);
1114 goto exit_free_dev_rdev
;
1117 /* now claim resources */
1118 if (!devm_request_region(&pdev
->dev
, nvt
->cir_addr
,
1119 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
))
1120 goto exit_unregister_device
;
1122 if (devm_request_irq(&pdev
->dev
, nvt
->cir_irq
, nvt_cir_isr
,
1123 IRQF_SHARED
, NVT_DRIVER_NAME
, (void *)nvt
))
1124 goto exit_unregister_device
;
1126 if (!devm_request_region(&pdev
->dev
, nvt
->cir_wake_addr
,
1127 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
"-wake"))
1128 goto exit_unregister_device
;
1130 if (devm_request_irq(&pdev
->dev
, nvt
->cir_wake_irq
,
1131 nvt_cir_wake_isr
, IRQF_SHARED
,
1132 NVT_DRIVER_NAME
"-wake", (void *)nvt
))
1133 goto exit_unregister_device
;
1135 device_init_wakeup(&pdev
->dev
, true);
1137 dev_notice(&pdev
->dev
, "driver has been successfully loaded\n");
1140 cir_wake_dump_regs(nvt
);
1145 exit_unregister_device
:
1146 rc_unregister_device(rdev
);
1149 rc_free_device(rdev
);
1154 static void nvt_remove(struct pnp_dev
*pdev
)
1156 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1157 unsigned long flags
;
1159 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1161 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1162 nvt_disable_cir(nvt
);
1163 /* enable CIR Wake (for IR power-on) */
1164 nvt_enable_wake(nvt
);
1165 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1167 rc_unregister_device(nvt
->rdev
);
1170 static int nvt_suspend(struct pnp_dev
*pdev
, pm_message_t state
)
1172 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1173 unsigned long flags
;
1175 nvt_dbg("%s called", __func__
);
1177 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
1178 nvt
->tx
.tx_state
= ST_TX_NONE
;
1179 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
1181 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1183 /* zero out misc state tracking */
1184 nvt
->study_state
= ST_STUDY_NONE
;
1185 nvt
->wake_state
= ST_WAKE_NONE
;
1187 /* disable all CIR interrupts */
1188 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1190 /* disable cir logical dev */
1191 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
1193 /* make sure wake is enabled */
1194 nvt_enable_wake(nvt
);
1196 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1201 static int nvt_resume(struct pnp_dev
*pdev
)
1203 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1205 nvt_dbg("%s called", __func__
);
1207 nvt_cir_regs_init(nvt
);
1208 nvt_cir_wake_regs_init(nvt
);
1213 static void nvt_shutdown(struct pnp_dev
*pdev
)
1215 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1216 unsigned long flags
;
1218 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1219 nvt_enable_wake(nvt
);
1220 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1223 static const struct pnp_device_id nvt_ids
[] = {
1224 { "WEC0530", 0 }, /* CIR */
1225 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1229 static struct pnp_driver nvt_driver
= {
1230 .name
= NVT_DRIVER_NAME
,
1231 .id_table
= nvt_ids
,
1232 .flags
= PNP_DRIVER_RES_DO_NOT_CHANGE
,
1234 .remove
= nvt_remove
,
1235 .suspend
= nvt_suspend
,
1236 .resume
= nvt_resume
,
1237 .shutdown
= nvt_shutdown
,
1240 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
1241 MODULE_PARM_DESC(debug
, "Enable debugging output");
1243 MODULE_DEVICE_TABLE(pnp
, nvt_ids
);
1244 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1246 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1247 MODULE_LICENSE("GPL");
1249 module_pnp_driver(nvt_driver
);