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[media] media: rc: nuvoton: fix rx fifo overrun handling
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
43
44 static const struct nvt_chip nvt_chips[] = {
45 { "w83667hg", NVT_W83667HG },
46 { "NCT6775F", NVT_6775F },
47 { "NCT6776F", NVT_6776F },
48 { "NCT6779D", NVT_6779D },
49 };
50
51 static inline bool is_w83667hg(struct nvt_dev *nvt)
52 {
53 return nvt->chip_ver == NVT_W83667HG;
54 }
55
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 outb(reg, nvt->cr_efir);
60 outb(val, nvt->cr_efdr);
61 }
62
63 /* read val from config reg */
64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
65 {
66 outb(reg, nvt->cr_efir);
67 return inb(nvt->cr_efdr);
68 }
69
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
72 {
73 u8 tmp = nvt_cr_read(nvt, reg) | val;
74 nvt_cr_write(nvt, tmp, reg);
75 }
76
77 /* clear config register bit without changing other bits */
78 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
79 {
80 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
81 nvt_cr_write(nvt, tmp, reg);
82 }
83
84 /* enter extended function mode */
85 static inline int nvt_efm_enable(struct nvt_dev *nvt)
86 {
87 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
88 return -EBUSY;
89
90 /* Enabling Extended Function Mode explicitly requires writing 2x */
91 outb(EFER_EFM_ENABLE, nvt->cr_efir);
92 outb(EFER_EFM_ENABLE, nvt->cr_efir);
93
94 return 0;
95 }
96
97 /* exit extended function mode */
98 static inline void nvt_efm_disable(struct nvt_dev *nvt)
99 {
100 outb(EFER_EFM_DISABLE, nvt->cr_efir);
101
102 release_region(nvt->cr_efir, 2);
103 }
104
105 /*
106 * When you want to address a specific logical device, write its logical
107 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
108 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
109 */
110 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
111 {
112 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
113 }
114
115 /* select and enable logical device with setting EFM mode*/
116 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
117 {
118 nvt_efm_enable(nvt);
119 nvt_select_logical_dev(nvt, ldev);
120 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
121 nvt_efm_disable(nvt);
122 }
123
124 /* select and disable logical device with setting EFM mode*/
125 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
126 {
127 nvt_efm_enable(nvt);
128 nvt_select_logical_dev(nvt, ldev);
129 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
130 nvt_efm_disable(nvt);
131 }
132
133 /* write val to cir config register */
134 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
135 {
136 outb(val, nvt->cir_addr + offset);
137 }
138
139 /* read val from cir config register */
140 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
141 {
142 u8 val;
143
144 val = inb(nvt->cir_addr + offset);
145
146 return val;
147 }
148
149 /* write val to cir wake register */
150 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
151 u8 val, u8 offset)
152 {
153 outb(val, nvt->cir_wake_addr + offset);
154 }
155
156 /* read val from cir wake config register */
157 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
158 {
159 u8 val;
160
161 val = inb(nvt->cir_wake_addr + offset);
162
163 return val;
164 }
165
166 /* don't override io address if one is set already */
167 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
168 {
169 unsigned long old_addr;
170
171 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
172 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
173
174 if (old_addr)
175 *ioaddr = old_addr;
176 else {
177 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
178 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
179 }
180 }
181
182 static ssize_t wakeup_data_show(struct device *dev,
183 struct device_attribute *attr,
184 char *buf)
185 {
186 struct rc_dev *rc_dev = to_rc_dev(dev);
187 struct nvt_dev *nvt = rc_dev->priv;
188 int fifo_len, duration;
189 unsigned long flags;
190 ssize_t buf_len = 0;
191 int i;
192
193 spin_lock_irqsave(&nvt->nvt_lock, flags);
194
195 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
196 fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
197
198 /* go to first element to be read */
199 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
201
202 for (i = 0; i < fifo_len; i++) {
203 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
204 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
205 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
206 "%d ", duration);
207 }
208 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
209
210 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
211
212 return buf_len;
213 }
214
215 static ssize_t wakeup_data_store(struct device *dev,
216 struct device_attribute *attr,
217 const char *buf, size_t len)
218 {
219 struct rc_dev *rc_dev = to_rc_dev(dev);
220 struct nvt_dev *nvt = rc_dev->priv;
221 unsigned long flags;
222 u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE];
223 char **argv;
224 int i, count;
225 unsigned int val;
226 ssize_t ret;
227
228 argv = argv_split(GFP_KERNEL, buf, &count);
229 if (!argv)
230 return -ENOMEM;
231 if (!count || count > WAKEUP_MAX_SIZE) {
232 ret = -EINVAL;
233 goto out;
234 }
235
236 for (i = 0; i < count; i++) {
237 ret = kstrtouint(argv[i], 10, &val);
238 if (ret)
239 goto out;
240 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
241 if (!val || val > 0x7f) {
242 ret = -EINVAL;
243 goto out;
244 }
245 wake_buf[i] = val;
246 /* sequence must start with a pulse */
247 if (i % 2 == 0)
248 wake_buf[i] |= BUF_PULSE_BIT;
249 }
250
251 /* hardcode the tolerance to 10% */
252 tolerance = DIV_ROUND_UP(count, 10);
253
254 spin_lock_irqsave(&nvt->nvt_lock, flags);
255
256 nvt_clear_cir_wake_fifo(nvt);
257 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
258 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
259
260 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
261
262 /* enable writes to wake fifo */
263 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
264 CIR_WAKE_IRCON);
265
266 for (i = 0; i < count; i++)
267 nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA);
268
269 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
270
271 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
272
273 ret = len;
274 out:
275 argv_free(argv);
276 return ret;
277 }
278 static DEVICE_ATTR_RW(wakeup_data);
279
280 /* dump current cir register contents */
281 static void cir_dump_regs(struct nvt_dev *nvt)
282 {
283 nvt_efm_enable(nvt);
284 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
285
286 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
287 pr_info(" * CR CIR ACTIVE : 0x%x\n",
288 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
289 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
290 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
291 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
292 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
293 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
294
295 nvt_efm_disable(nvt);
296
297 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
298 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
299 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
300 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
301 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
302 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
303 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
304 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
305 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
306 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
307 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
308 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
309 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
310 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
311 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
312 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
313 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
314 }
315
316 /* dump current cir wake register contents */
317 static void cir_wake_dump_regs(struct nvt_dev *nvt)
318 {
319 u8 i, fifo_len;
320
321 nvt_efm_enable(nvt);
322 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
323
324 pr_info("%s: Dump CIR WAKE logical device registers:\n",
325 NVT_DRIVER_NAME);
326 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
327 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
328 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
329 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
330 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
331 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
332 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
333
334 nvt_efm_disable(nvt);
335
336 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
337 pr_info(" * IRCON: 0x%x\n",
338 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
339 pr_info(" * IRSTS: 0x%x\n",
340 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
341 pr_info(" * IREN: 0x%x\n",
342 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
343 pr_info(" * FIFO CMP DEEP: 0x%x\n",
344 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
345 pr_info(" * FIFO CMP TOL: 0x%x\n",
346 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
347 pr_info(" * FIFO COUNT: 0x%x\n",
348 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
349 pr_info(" * SLCH: 0x%x\n",
350 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
351 pr_info(" * SLCL: 0x%x\n",
352 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
353 pr_info(" * FIFOCON: 0x%x\n",
354 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
355 pr_info(" * SRXFSTS: 0x%x\n",
356 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
357 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
358 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
359 pr_info(" * WR FIFO DATA: 0x%x\n",
360 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
361 pr_info(" * RD FIFO ONLY: 0x%x\n",
362 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
363 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
364 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
365 pr_info(" * FIFO IGNORE: 0x%x\n",
366 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
367 pr_info(" * IRFSM: 0x%x\n",
368 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
369
370 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
371 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
372 pr_info("* Contents =");
373 for (i = 0; i < fifo_len; i++)
374 pr_cont(" %02x",
375 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
376 pr_cont("\n");
377 }
378
379 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
380 {
381 int i;
382
383 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
384 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
385 nvt->chip_ver = nvt_chips[i].chip_ver;
386 return nvt_chips[i].name;
387 }
388
389 return NULL;
390 }
391
392
393 /* detect hardware features */
394 static int nvt_hw_detect(struct nvt_dev *nvt)
395 {
396 const char *chip_name;
397 int chip_id;
398
399 nvt_efm_enable(nvt);
400
401 /* Check if we're wired for the alternate EFER setup */
402 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
403 if (nvt->chip_major == 0xff) {
404 nvt->cr_efir = CR_EFIR2;
405 nvt->cr_efdr = CR_EFDR2;
406 nvt_efm_enable(nvt);
407 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
408 }
409 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
410
411 nvt_efm_disable(nvt);
412
413 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
414 if (chip_id == NVT_INVALID) {
415 dev_err(&nvt->pdev->dev,
416 "No device found on either EFM port\n");
417 return -ENODEV;
418 }
419
420 chip_name = nvt_find_chip(nvt, chip_id);
421
422 /* warn, but still let the driver load, if we don't know this chip */
423 if (!chip_name)
424 dev_warn(&nvt->pdev->dev,
425 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
426 nvt->chip_major, nvt->chip_minor);
427 else
428 dev_info(&nvt->pdev->dev,
429 "found %s or compatible: chip id: 0x%02x 0x%02x",
430 chip_name, nvt->chip_major, nvt->chip_minor);
431
432 return 0;
433 }
434
435 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
436 {
437 u8 val, psreg, psmask, psval;
438
439 if (is_w83667hg(nvt)) {
440 psreg = CR_MULTIFUNC_PIN_SEL;
441 psmask = MULTIFUNC_PIN_SEL_MASK;
442 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
443 } else {
444 psreg = CR_OUTPUT_PIN_SEL;
445 psmask = OUTPUT_PIN_SEL_MASK;
446 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
447 }
448
449 /* output pin selection: enable CIR, with WB sensor enabled */
450 val = nvt_cr_read(nvt, psreg);
451 val &= psmask;
452 val |= psval;
453 nvt_cr_write(nvt, val, psreg);
454
455 /* Select CIR logical device */
456 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
457
458 nvt_set_ioaddr(nvt, &nvt->cir_addr);
459
460 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
461
462 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
463 nvt->cir_addr, nvt->cir_irq);
464 }
465
466 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
467 {
468 /* Select ACPI logical device and anable it */
469 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
470 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
471
472 /* Enable CIR Wake via PSOUT# (Pin60) */
473 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
474
475 /* enable pme interrupt of cir wakeup event */
476 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
477
478 /* Select CIR Wake logical device */
479 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
480
481 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
482
483 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
484
485 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
486 nvt->cir_wake_addr, nvt->cir_wake_irq);
487 }
488
489 /* clear out the hardware's cir rx fifo */
490 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
491 {
492 u8 val;
493
494 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
495 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
496 }
497
498 /* clear out the hardware's cir wake rx fifo */
499 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
500 {
501 u8 val, config;
502
503 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
504
505 /* clearing wake fifo works in learning mode only */
506 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
507 CIR_WAKE_IRCON);
508
509 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
510 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
511 CIR_WAKE_FIFOCON);
512
513 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
514 }
515
516 /* clear out the hardware's cir tx fifo */
517 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
518 {
519 u8 val;
520
521 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
522 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
523 }
524
525 /* enable RX Trigger Level Reach and Packet End interrupts */
526 static void nvt_set_cir_iren(struct nvt_dev *nvt)
527 {
528 u8 iren;
529
530 iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
531 nvt_cir_reg_write(nvt, iren, CIR_IREN);
532 }
533
534 static void nvt_cir_regs_init(struct nvt_dev *nvt)
535 {
536 /* set sample limit count (PE interrupt raised when reached) */
537 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
538 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
539
540 /* set fifo irq trigger levels */
541 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
542 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
543
544 /*
545 * Enable TX and RX, specify carrier on = low, off = high, and set
546 * sample period (currently 50us)
547 */
548 nvt_cir_reg_write(nvt,
549 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
550 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
551 CIR_IRCON);
552
553 /* clear hardware rx and tx fifos */
554 nvt_clear_cir_fifo(nvt);
555 nvt_clear_tx_fifo(nvt);
556
557 /* clear any and all stray interrupts */
558 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
559
560 /* and finally, enable interrupts */
561 nvt_set_cir_iren(nvt);
562
563 /* enable the CIR logical device */
564 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
565 }
566
567 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
568 {
569 /* set number of bytes needed for wake from s3 (default 65) */
570 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
571 CIR_WAKE_FIFO_CMP_DEEP);
572
573 /* set tolerance/variance allowed per byte during wake compare */
574 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
575 CIR_WAKE_FIFO_CMP_TOL);
576
577 /* set sample limit count (PE interrupt raised when reached) */
578 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
579 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
580
581 /* set cir wake fifo rx trigger level (currently 67) */
582 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
583 CIR_WAKE_FIFOCON);
584
585 /*
586 * Enable TX and RX, specific carrier on = low, off = high, and set
587 * sample period (currently 50us)
588 */
589 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
590 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
591 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
592 CIR_WAKE_IRCON);
593
594 /* clear cir wake rx fifo */
595 nvt_clear_cir_wake_fifo(nvt);
596
597 /* clear any and all stray interrupts */
598 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
599
600 /* enable the CIR WAKE logical device */
601 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
602 }
603
604 static void nvt_enable_wake(struct nvt_dev *nvt)
605 {
606 unsigned long flags;
607
608 nvt_efm_enable(nvt);
609
610 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
611 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
612 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
613
614 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
615 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
616
617 nvt_efm_disable(nvt);
618
619 spin_lock_irqsave(&nvt->nvt_lock, flags);
620
621 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
622 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
623 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
624 CIR_WAKE_IRCON);
625 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
626 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
627
628 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
629 }
630
631 #if 0 /* Currently unused */
632 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
633 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
634 {
635 u32 count, carrier, duration = 0;
636 int i;
637
638 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
639 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
640
641 for (i = 0; i < nvt->pkts; i++) {
642 if (nvt->buf[i] & BUF_PULSE_BIT)
643 duration += nvt->buf[i] & BUF_LEN_MASK;
644 }
645
646 duration *= SAMPLE_PERIOD;
647
648 if (!count || !duration) {
649 dev_notice(&nvt->pdev->dev,
650 "Unable to determine carrier! (c:%u, d:%u)",
651 count, duration);
652 return 0;
653 }
654
655 carrier = MS_TO_NS(count) / duration;
656
657 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
658 nvt_dbg("WTF? Carrier frequency out of range!");
659
660 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
661 carrier, count, duration);
662
663 return carrier;
664 }
665 #endif
666 /*
667 * set carrier frequency
668 *
669 * set carrier on 2 registers: CP & CC
670 * always set CP as 0x81
671 * set CC by SPEC, CC = 3MHz/carrier - 1
672 */
673 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
674 {
675 struct nvt_dev *nvt = dev->priv;
676 u16 val;
677
678 if (carrier == 0)
679 return -EINVAL;
680
681 nvt_cir_reg_write(nvt, 1, CIR_CP);
682 val = 3000000 / (carrier) - 1;
683 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
684
685 nvt_dbg("cp: 0x%x cc: 0x%x\n",
686 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
687
688 return 0;
689 }
690
691 /*
692 * nvt_tx_ir
693 *
694 * 1) clean TX fifo first (handled by AP)
695 * 2) copy data from user space
696 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
697 * 4) send 9 packets to TX FIFO to open TTR
698 * in interrupt_handler:
699 * 5) send all data out
700 * go back to write():
701 * 6) disable TX interrupts, re-enable RX interupts
702 *
703 * The key problem of this function is user space data may larger than
704 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
705 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
706 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
707 * set TXFCONT as 0xff, until buf_count less than 0xff.
708 */
709 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
710 {
711 struct nvt_dev *nvt = dev->priv;
712 unsigned long flags;
713 unsigned int i;
714 u8 iren;
715 int ret;
716
717 spin_lock_irqsave(&nvt->tx.lock, flags);
718
719 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
720 nvt->tx.buf_count = (ret * sizeof(unsigned));
721
722 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
723
724 nvt->tx.cur_buf_num = 0;
725
726 /* save currently enabled interrupts */
727 iren = nvt_cir_reg_read(nvt, CIR_IREN);
728
729 /* now disable all interrupts, save TFU & TTR */
730 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
731
732 nvt->tx.tx_state = ST_TX_REPLY;
733
734 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
735 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
736
737 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
738 for (i = 0; i < 9; i++)
739 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
740
741 spin_unlock_irqrestore(&nvt->tx.lock, flags);
742
743 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
744
745 spin_lock_irqsave(&nvt->tx.lock, flags);
746 nvt->tx.tx_state = ST_TX_NONE;
747 spin_unlock_irqrestore(&nvt->tx.lock, flags);
748
749 /* restore enabled interrupts to prior state */
750 nvt_cir_reg_write(nvt, iren, CIR_IREN);
751
752 return ret;
753 }
754
755 /* dump contents of the last rx buffer we got from the hw rx fifo */
756 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
757 {
758 int i;
759
760 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
761 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
762 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
763 printk(KERN_CONT "\n");
764 }
765
766 /*
767 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
768 * trigger decode when appropriate.
769 *
770 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
771 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
772 * (default 50us) intervals for that pulse/space. A discrete signal is
773 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
774 * to signal more IR coming (repeats) or end of IR, respectively. We store
775 * sample data in the raw event kfifo until we see 0x7<something> (except f)
776 * or 0x80, at which time, we trigger a decode operation.
777 */
778 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
779 {
780 DEFINE_IR_RAW_EVENT(rawir);
781 u8 sample;
782 int i;
783
784 nvt_dbg_verbose("%s firing", __func__);
785
786 if (debug)
787 nvt_dump_rx_buf(nvt);
788
789 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
790
791 init_ir_raw_event(&rawir);
792
793 for (i = 0; i < nvt->pkts; i++) {
794 sample = nvt->buf[i];
795
796 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
797 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
798 * SAMPLE_PERIOD);
799
800 nvt_dbg("Storing %s with duration %d",
801 rawir.pulse ? "pulse" : "space", rawir.duration);
802
803 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
804
805 /*
806 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
807 * indicates end of IR signal, but new data incoming. In both
808 * cases, it means we're ready to call ir_raw_event_handle
809 */
810 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
811 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
812 ir_raw_event_handle(nvt->rdev);
813 }
814 }
815
816 nvt->pkts = 0;
817
818 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
819 ir_raw_event_handle(nvt->rdev);
820
821 nvt_dbg_verbose("%s done", __func__);
822 }
823
824 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
825 {
826 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
827
828 nvt->pkts = 0;
829 nvt_clear_cir_fifo(nvt);
830 ir_raw_event_reset(nvt->rdev);
831 }
832
833 /* copy data from hardware rx fifo into driver buffer */
834 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
835 {
836 u8 fifocount, val;
837 unsigned int b_idx;
838 int i;
839
840 /* Get count of how many bytes to read from RX FIFO */
841 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
842 /* if we get 0xff, probably means the logical dev is disabled */
843 if (fifocount == 0xff)
844 return;
845
846 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
847
848 b_idx = nvt->pkts;
849
850 /* This should never happen, but lets check anyway... */
851 if (b_idx + fifocount > RX_BUF_LEN) {
852 nvt_process_rx_ir_data(nvt);
853 b_idx = 0;
854 }
855
856 /* Read fifocount bytes from CIR Sample RX FIFO register */
857 for (i = 0; i < fifocount; i++) {
858 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
859 nvt->buf[b_idx + i] = val;
860 }
861
862 nvt->pkts += fifocount;
863 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
864
865 nvt_process_rx_ir_data(nvt);
866 }
867
868 static void nvt_cir_log_irqs(u8 status, u8 iren)
869 {
870 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
871 status, iren,
872 status & CIR_IRSTS_RDR ? " RDR" : "",
873 status & CIR_IRSTS_RTR ? " RTR" : "",
874 status & CIR_IRSTS_PE ? " PE" : "",
875 status & CIR_IRSTS_RFO ? " RFO" : "",
876 status & CIR_IRSTS_TE ? " TE" : "",
877 status & CIR_IRSTS_TTR ? " TTR" : "",
878 status & CIR_IRSTS_TFU ? " TFU" : "",
879 status & CIR_IRSTS_GH ? " GH" : "",
880 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
881 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
882 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
883 }
884
885 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
886 {
887 unsigned long flags;
888 u8 tx_state;
889
890 spin_lock_irqsave(&nvt->tx.lock, flags);
891 tx_state = nvt->tx.tx_state;
892 spin_unlock_irqrestore(&nvt->tx.lock, flags);
893
894 return tx_state == ST_TX_NONE;
895 }
896
897 /* interrupt service routine for incoming and outgoing CIR data */
898 static irqreturn_t nvt_cir_isr(int irq, void *data)
899 {
900 struct nvt_dev *nvt = data;
901 u8 status, iren, cur_state;
902 unsigned long flags;
903
904 nvt_dbg_verbose("%s firing", __func__);
905
906 spin_lock_irqsave(&nvt->nvt_lock, flags);
907
908 /*
909 * Get IR Status register contents. Write 1 to ack/clear
910 *
911 * bit: reg name - description
912 * 7: CIR_IRSTS_RDR - RX Data Ready
913 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
914 * 5: CIR_IRSTS_PE - Packet End
915 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
916 * 3: CIR_IRSTS_TE - TX FIFO Empty
917 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
918 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
919 * 0: CIR_IRSTS_GH - Min Length Detected
920 */
921 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
922 iren = nvt_cir_reg_read(nvt, CIR_IREN);
923
924 /* IRQ may be shared with CIR WAKE, therefore check for each
925 * status bit whether the related interrupt source is enabled
926 */
927 if (!(status & iren)) {
928 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
929 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
930 return IRQ_NONE;
931 }
932
933 /* ack/clear all irq flags we've got */
934 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
935 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
936
937 nvt_cir_log_irqs(status, iren);
938
939 if (status & CIR_IRSTS_RFO)
940 nvt_handle_rx_fifo_overrun(nvt);
941
942 if (status & CIR_IRSTS_RTR) {
943 /* FIXME: add code for study/learn mode */
944 /* We only do rx if not tx'ing */
945 if (nvt_cir_tx_inactive(nvt))
946 nvt_get_rx_ir_data(nvt);
947 }
948
949 if (status & CIR_IRSTS_PE) {
950 if (nvt_cir_tx_inactive(nvt))
951 nvt_get_rx_ir_data(nvt);
952
953 cur_state = nvt->study_state;
954
955 if (cur_state == ST_STUDY_NONE)
956 nvt_clear_cir_fifo(nvt);
957 }
958
959 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
960
961 if (status & CIR_IRSTS_TE)
962 nvt_clear_tx_fifo(nvt);
963
964 if (status & CIR_IRSTS_TTR) {
965 unsigned int pos, count;
966 u8 tmp;
967
968 spin_lock_irqsave(&nvt->tx.lock, flags);
969
970 pos = nvt->tx.cur_buf_num;
971 count = nvt->tx.buf_count;
972
973 /* Write data into the hardware tx fifo while pos < count */
974 if (pos < count) {
975 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
976 nvt->tx.cur_buf_num++;
977 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
978 } else {
979 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
980 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
981 }
982
983 spin_unlock_irqrestore(&nvt->tx.lock, flags);
984
985 }
986
987 if (status & CIR_IRSTS_TFU) {
988 spin_lock_irqsave(&nvt->tx.lock, flags);
989 if (nvt->tx.tx_state == ST_TX_REPLY) {
990 nvt->tx.tx_state = ST_TX_REQUEST;
991 wake_up(&nvt->tx.queue);
992 }
993 spin_unlock_irqrestore(&nvt->tx.lock, flags);
994 }
995
996 nvt_dbg_verbose("%s done", __func__);
997 return IRQ_HANDLED;
998 }
999
1000 /* Interrupt service routine for CIR Wake */
1001 static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
1002 {
1003 u8 status, iren, val;
1004 struct nvt_dev *nvt = data;
1005 unsigned long flags;
1006
1007 nvt_dbg_wake("%s firing", __func__);
1008
1009 spin_lock_irqsave(&nvt->nvt_lock, flags);
1010
1011 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
1012 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
1013
1014 /* IRQ may be shared with CIR, therefore check for each
1015 * status bit whether the related interrupt source is enabled
1016 */
1017 if (!(status & iren)) {
1018 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1019 return IRQ_NONE;
1020 }
1021
1022 if (status & CIR_WAKE_IRSTS_IR_PENDING)
1023 nvt_clear_cir_wake_fifo(nvt);
1024
1025 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
1026 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
1027
1028 if ((status & CIR_WAKE_IRSTS_PE) &&
1029 (nvt->wake_state == ST_WAKE_START)) {
1030 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
1031 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
1032 nvt_dbg("setting wake up key: 0x%x", val);
1033 }
1034
1035 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
1036 nvt->wake_state = ST_WAKE_FINISH;
1037 }
1038
1039 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1040
1041 nvt_dbg_wake("%s done", __func__);
1042 return IRQ_HANDLED;
1043 }
1044
1045 static void nvt_disable_cir(struct nvt_dev *nvt)
1046 {
1047 unsigned long flags;
1048
1049 spin_lock_irqsave(&nvt->nvt_lock, flags);
1050
1051 /* disable CIR interrupts */
1052 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1053
1054 /* clear any and all pending interrupts */
1055 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1056
1057 /* clear all function enable flags */
1058 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
1059
1060 /* clear hardware rx and tx fifos */
1061 nvt_clear_cir_fifo(nvt);
1062 nvt_clear_tx_fifo(nvt);
1063
1064 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1065
1066 /* disable the CIR logical device */
1067 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1068 }
1069
1070 static int nvt_open(struct rc_dev *dev)
1071 {
1072 struct nvt_dev *nvt = dev->priv;
1073 unsigned long flags;
1074
1075 spin_lock_irqsave(&nvt->nvt_lock, flags);
1076
1077 /* set function enable flags */
1078 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
1079 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
1080 CIR_IRCON);
1081
1082 /* clear all pending interrupts */
1083 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1084
1085 /* enable interrupts */
1086 nvt_set_cir_iren(nvt);
1087
1088 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1089
1090 /* enable the CIR logical device */
1091 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
1092
1093 return 0;
1094 }
1095
1096 static void nvt_close(struct rc_dev *dev)
1097 {
1098 struct nvt_dev *nvt = dev->priv;
1099
1100 nvt_disable_cir(nvt);
1101 }
1102
1103 /* Allocate memory, probe hardware, and initialize everything */
1104 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1105 {
1106 struct nvt_dev *nvt;
1107 struct rc_dev *rdev;
1108 int ret = -ENOMEM;
1109
1110 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
1111 if (!nvt)
1112 return ret;
1113
1114 /* input device for IR remote (and tx) */
1115 rdev = rc_allocate_device();
1116 if (!rdev)
1117 goto exit_free_dev_rdev;
1118
1119 ret = -ENODEV;
1120 /* activate pnp device */
1121 if (pnp_activate_dev(pdev) < 0) {
1122 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1123 goto exit_free_dev_rdev;
1124 }
1125
1126 /* validate pnp resources */
1127 if (!pnp_port_valid(pdev, 0) ||
1128 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1129 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1130 goto exit_free_dev_rdev;
1131 }
1132
1133 if (!pnp_irq_valid(pdev, 0)) {
1134 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1135 goto exit_free_dev_rdev;
1136 }
1137
1138 if (!pnp_port_valid(pdev, 1) ||
1139 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1140 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1141 goto exit_free_dev_rdev;
1142 }
1143
1144 nvt->cir_addr = pnp_port_start(pdev, 0);
1145 nvt->cir_irq = pnp_irq(pdev, 0);
1146
1147 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1148 /* irq is always shared between cir and cir wake */
1149 nvt->cir_wake_irq = nvt->cir_irq;
1150
1151 nvt->cr_efir = CR_EFIR;
1152 nvt->cr_efdr = CR_EFDR;
1153
1154 spin_lock_init(&nvt->nvt_lock);
1155 spin_lock_init(&nvt->tx.lock);
1156
1157 pnp_set_drvdata(pdev, nvt);
1158 nvt->pdev = pdev;
1159
1160 init_waitqueue_head(&nvt->tx.queue);
1161
1162 ret = nvt_hw_detect(nvt);
1163 if (ret)
1164 goto exit_free_dev_rdev;
1165
1166 /* Initialize CIR & CIR Wake Logical Devices */
1167 nvt_efm_enable(nvt);
1168 nvt_cir_ldev_init(nvt);
1169 nvt_cir_wake_ldev_init(nvt);
1170 nvt_efm_disable(nvt);
1171
1172 /*
1173 * Initialize CIR & CIR Wake Config Registers
1174 * and enable logical devices
1175 */
1176 nvt_cir_regs_init(nvt);
1177 nvt_cir_wake_regs_init(nvt);
1178
1179 /* Set up the rc device */
1180 rdev->priv = nvt;
1181 rdev->driver_type = RC_DRIVER_IR_RAW;
1182 rdev->allowed_protocols = RC_BIT_ALL;
1183 rdev->open = nvt_open;
1184 rdev->close = nvt_close;
1185 rdev->tx_ir = nvt_tx_ir;
1186 rdev->s_tx_carrier = nvt_set_tx_carrier;
1187 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1188 rdev->input_phys = "nuvoton/cir0";
1189 rdev->input_id.bustype = BUS_HOST;
1190 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1191 rdev->input_id.product = nvt->chip_major;
1192 rdev->input_id.version = nvt->chip_minor;
1193 rdev->dev.parent = &pdev->dev;
1194 rdev->driver_name = NVT_DRIVER_NAME;
1195 rdev->map_name = RC_MAP_RC6_MCE;
1196 rdev->timeout = MS_TO_NS(100);
1197 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1198 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1199 #if 0
1200 rdev->min_timeout = XYZ;
1201 rdev->max_timeout = XYZ;
1202 /* tx bits */
1203 rdev->tx_resolution = XYZ;
1204 #endif
1205 nvt->rdev = rdev;
1206
1207 ret = rc_register_device(rdev);
1208 if (ret)
1209 goto exit_free_dev_rdev;
1210
1211 ret = -EBUSY;
1212 /* now claim resources */
1213 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1214 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1215 goto exit_unregister_device;
1216
1217 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1218 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1219 goto exit_unregister_device;
1220
1221 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1222 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1223 goto exit_unregister_device;
1224
1225 if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq,
1226 nvt_cir_wake_isr, IRQF_SHARED,
1227 NVT_DRIVER_NAME "-wake", (void *)nvt))
1228 goto exit_unregister_device;
1229
1230 ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1231 if (ret)
1232 goto exit_unregister_device;
1233
1234 device_init_wakeup(&pdev->dev, true);
1235
1236 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1237 if (debug) {
1238 cir_dump_regs(nvt);
1239 cir_wake_dump_regs(nvt);
1240 }
1241
1242 return 0;
1243
1244 exit_unregister_device:
1245 rc_unregister_device(rdev);
1246 rdev = NULL;
1247 exit_free_dev_rdev:
1248 rc_free_device(rdev);
1249
1250 return ret;
1251 }
1252
1253 static void nvt_remove(struct pnp_dev *pdev)
1254 {
1255 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1256
1257 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1258
1259 nvt_disable_cir(nvt);
1260
1261 /* enable CIR Wake (for IR power-on) */
1262 nvt_enable_wake(nvt);
1263
1264 rc_unregister_device(nvt->rdev);
1265 }
1266
1267 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1268 {
1269 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1270 unsigned long flags;
1271
1272 nvt_dbg("%s called", __func__);
1273
1274 spin_lock_irqsave(&nvt->tx.lock, flags);
1275 nvt->tx.tx_state = ST_TX_NONE;
1276 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1277
1278 spin_lock_irqsave(&nvt->nvt_lock, flags);
1279
1280 /* zero out misc state tracking */
1281 nvt->study_state = ST_STUDY_NONE;
1282 nvt->wake_state = ST_WAKE_NONE;
1283
1284 /* disable all CIR interrupts */
1285 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1286
1287 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1288
1289 /* disable cir logical dev */
1290 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1291
1292 /* make sure wake is enabled */
1293 nvt_enable_wake(nvt);
1294
1295 return 0;
1296 }
1297
1298 static int nvt_resume(struct pnp_dev *pdev)
1299 {
1300 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1301
1302 nvt_dbg("%s called", __func__);
1303
1304 nvt_cir_regs_init(nvt);
1305 nvt_cir_wake_regs_init(nvt);
1306
1307 return 0;
1308 }
1309
1310 static void nvt_shutdown(struct pnp_dev *pdev)
1311 {
1312 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1313
1314 nvt_enable_wake(nvt);
1315 }
1316
1317 static const struct pnp_device_id nvt_ids[] = {
1318 { "WEC0530", 0 }, /* CIR */
1319 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1320 { "", 0 },
1321 };
1322
1323 static struct pnp_driver nvt_driver = {
1324 .name = NVT_DRIVER_NAME,
1325 .id_table = nvt_ids,
1326 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1327 .probe = nvt_probe,
1328 .remove = nvt_remove,
1329 .suspend = nvt_suspend,
1330 .resume = nvt_resume,
1331 .shutdown = nvt_shutdown,
1332 };
1333
1334 module_param(debug, int, S_IRUGO | S_IWUSR);
1335 MODULE_PARM_DESC(debug, "Enable debugging output");
1336
1337 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1338 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1339
1340 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1341 MODULE_LICENSE("GPL");
1342
1343 module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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