2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
40 #include "nuvoton-cir.h"
42 /* write val to config reg */
43 static inline void nvt_cr_write(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
45 outb(reg
, nvt
->cr_efir
);
46 outb(val
, nvt
->cr_efdr
);
49 /* read val from config reg */
50 static inline u8
nvt_cr_read(struct nvt_dev
*nvt
, u8 reg
)
52 outb(reg
, nvt
->cr_efir
);
53 return inb(nvt
->cr_efdr
);
56 /* update config register bit without changing other bits */
57 static inline void nvt_set_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
59 u8 tmp
= nvt_cr_read(nvt
, reg
) | val
;
60 nvt_cr_write(nvt
, tmp
, reg
);
63 /* clear config register bit without changing other bits */
64 static inline void nvt_clear_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
66 u8 tmp
= nvt_cr_read(nvt
, reg
) & ~val
;
67 nvt_cr_write(nvt
, tmp
, reg
);
70 /* enter extended function mode */
71 static inline void nvt_efm_enable(struct nvt_dev
*nvt
)
73 /* Enabling Extended Function Mode explicitly requires writing 2x */
74 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
75 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
78 /* exit extended function mode */
79 static inline void nvt_efm_disable(struct nvt_dev
*nvt
)
81 outb(EFER_EFM_DISABLE
, nvt
->cr_efir
);
85 * When you want to address a specific logical device, write its logical
86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
89 static inline void nvt_select_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
91 outb(CR_LOGICAL_DEV_SEL
, nvt
->cr_efir
);
92 outb(ldev
, nvt
->cr_efdr
);
95 /* write val to cir config register */
96 static inline void nvt_cir_reg_write(struct nvt_dev
*nvt
, u8 val
, u8 offset
)
98 outb(val
, nvt
->cir_addr
+ offset
);
101 /* read val from cir config register */
102 static u8
nvt_cir_reg_read(struct nvt_dev
*nvt
, u8 offset
)
106 val
= inb(nvt
->cir_addr
+ offset
);
111 /* write val to cir wake register */
112 static inline void nvt_cir_wake_reg_write(struct nvt_dev
*nvt
,
115 outb(val
, nvt
->cir_wake_addr
+ offset
);
118 /* read val from cir wake config register */
119 static u8
nvt_cir_wake_reg_read(struct nvt_dev
*nvt
, u8 offset
)
123 val
= inb(nvt
->cir_wake_addr
+ offset
);
128 /* dump current cir register contents */
129 static void cir_dump_regs(struct nvt_dev
*nvt
)
132 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME
);
135 pr_info(" * CR CIR ACTIVE : 0x%x\n",
136 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
137 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
138 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
139 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
140 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
141 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
143 nvt_efm_disable(nvt
);
145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME
);
146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRCON
));
147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRSTS
));
148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IREN
));
149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_RXFCONT
));
150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CP
));
151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CC
));
152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCH
));
153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCL
));
154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FIFOCON
));
155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFIFOSTS
));
156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SRXFIFO
));
157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_TXFCONT
));
158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_STXFIFO
));
159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCH
));
160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCL
));
161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFSM
));
164 /* dump current cir wake register contents */
165 static void cir_wake_dump_regs(struct nvt_dev
*nvt
)
170 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
172 pr_info("%s: Dump CIR WAKE logical device registers:\n",
174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
175 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
177 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
178 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
180 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
182 nvt_efm_disable(nvt
);
184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME
);
185 pr_info(" * IRCON: 0x%x\n",
186 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
));
187 pr_info(" * IRSTS: 0x%x\n",
188 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
));
189 pr_info(" * IREN: 0x%x\n",
190 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
));
191 pr_info(" * FIFO CMP DEEP: 0x%x\n",
192 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_DEEP
));
193 pr_info(" * FIFO CMP TOL: 0x%x\n",
194 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_TOL
));
195 pr_info(" * FIFO COUNT: 0x%x\n",
196 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
));
197 pr_info(" * SLCH: 0x%x\n",
198 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCH
));
199 pr_info(" * SLCL: 0x%x\n",
200 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCL
));
201 pr_info(" * FIFOCON: 0x%x\n",
202 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
));
203 pr_info(" * SRXFSTS: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SRXFSTS
));
205 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SAMPLE_RX_FIFO
));
207 pr_info(" * WR FIFO DATA: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_WR_FIFO_DATA
));
209 pr_info(" * RD FIFO ONLY: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
));
213 pr_info(" * FIFO IGNORE: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_IGNORE
));
215 pr_info(" * IRFSM: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRFSM
));
218 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME
, fifo_len
);
220 pr_info("* Contents =");
221 for (i
= 0; i
< fifo_len
; i
++)
223 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
227 /* detect hardware features */
228 static int nvt_hw_detect(struct nvt_dev
*nvt
)
230 u8 chip_major
, chip_minor
;
232 bool chip_unknown
= false;
236 /* Check if we're wired for the alternate EFER setup */
237 chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
238 if (chip_major
== 0xff) {
239 nvt
->cr_efir
= CR_EFIR2
;
240 nvt
->cr_efdr
= CR_EFDR2
;
242 chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
245 chip_minor
= nvt_cr_read(nvt
, CR_CHIP_ID_LO
);
247 /* these are the known working chip revisions... */
248 switch (chip_major
) {
249 case CHIP_ID_HIGH_667
:
250 strcpy(chip_id
, "w83667hg\0");
251 if (chip_minor
!= CHIP_ID_LOW_667
)
254 case CHIP_ID_HIGH_677B
:
255 strcpy(chip_id
, "w83677hg\0");
256 if (chip_minor
!= CHIP_ID_LOW_677B2
&&
257 chip_minor
!= CHIP_ID_LOW_677B3
)
260 case CHIP_ID_HIGH_677C
:
261 strcpy(chip_id
, "w83677hg-c\0");
262 if (chip_minor
!= CHIP_ID_LOW_677C
)
266 strcpy(chip_id
, "w836x7hg\0");
271 /* warn, but still let the driver load, if we don't know this chip */
273 nvt_pr(KERN_WARNING
, "%s: unknown chip, id: 0x%02x 0x%02x, "
274 "it may not work...", chip_id
, chip_major
, chip_minor
);
276 nvt_dbg("%s: chip id: 0x%02x 0x%02x",
277 chip_id
, chip_major
, chip_minor
);
279 nvt_efm_disable(nvt
);
281 nvt
->chip_major
= chip_major
;
282 nvt
->chip_minor
= chip_minor
;
287 static void nvt_cir_ldev_init(struct nvt_dev
*nvt
)
289 u8 val
, psreg
, psmask
, psval
;
291 if (nvt
->chip_major
== CHIP_ID_HIGH_667
) {
292 psreg
= CR_MULTIFUNC_PIN_SEL
;
293 psmask
= MULTIFUNC_PIN_SEL_MASK
;
294 psval
= MULTIFUNC_ENABLE_CIR
| MULTIFUNC_ENABLE_CIRWB
;
296 psreg
= CR_OUTPUT_PIN_SEL
;
297 psmask
= OUTPUT_PIN_SEL_MASK
;
298 psval
= OUTPUT_ENABLE_CIR
| OUTPUT_ENABLE_CIRWB
;
301 /* output pin selection: enable CIR, with WB sensor enabled */
302 val
= nvt_cr_read(nvt
, psreg
);
305 nvt_cr_write(nvt
, val
, psreg
);
307 /* Select CIR logical device and enable */
308 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
309 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
311 nvt_cr_write(nvt
, nvt
->cir_addr
>> 8, CR_CIR_BASE_ADDR_HI
);
312 nvt_cr_write(nvt
, nvt
->cir_addr
& 0xff, CR_CIR_BASE_ADDR_LO
);
314 nvt_cr_write(nvt
, nvt
->cir_irq
, CR_CIR_IRQ_RSRC
);
316 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
317 nvt
->cir_addr
, nvt
->cir_irq
);
320 static void nvt_cir_wake_ldev_init(struct nvt_dev
*nvt
)
322 /* Select ACPI logical device, enable it and CIR Wake */
323 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
324 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
326 /* Enable CIR Wake via PSOUT# (Pin60) */
327 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
329 /* enable pme interrupt of cir wakeup event */
330 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
332 /* Select CIR Wake logical device and enable */
333 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
334 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
336 nvt_cr_write(nvt
, nvt
->cir_wake_addr
>> 8, CR_CIR_BASE_ADDR_HI
);
337 nvt_cr_write(nvt
, nvt
->cir_wake_addr
& 0xff, CR_CIR_BASE_ADDR_LO
);
339 nvt_cr_write(nvt
, nvt
->cir_wake_irq
, CR_CIR_IRQ_RSRC
);
341 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
342 nvt
->cir_wake_addr
, nvt
->cir_wake_irq
);
345 /* clear out the hardware's cir rx fifo */
346 static void nvt_clear_cir_fifo(struct nvt_dev
*nvt
)
350 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
351 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
354 /* clear out the hardware's cir wake rx fifo */
355 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
)
359 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
);
360 nvt_cir_wake_reg_write(nvt
, val
| CIR_WAKE_FIFOCON_RXFIFOCLR
,
364 /* clear out the hardware's cir tx fifo */
365 static void nvt_clear_tx_fifo(struct nvt_dev
*nvt
)
369 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
370 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_TXFIFOCLR
, CIR_FIFOCON
);
373 /* enable RX Trigger Level Reach and Packet End interrupts */
374 static void nvt_set_cir_iren(struct nvt_dev
*nvt
)
378 iren
= CIR_IREN_RTR
| CIR_IREN_PE
;
379 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
382 static void nvt_cir_regs_init(struct nvt_dev
*nvt
)
384 /* set sample limit count (PE interrupt raised when reached) */
385 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_SLCH
);
386 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_SLCL
);
388 /* set fifo irq trigger levels */
389 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV
|
390 CIR_FIFOCON_RX_TRIGGER_LEV
, CIR_FIFOCON
);
393 * Enable TX and RX, specify carrier on = low, off = high, and set
394 * sample period (currently 50us)
396 nvt_cir_reg_write(nvt
,
397 CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
398 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
401 /* clear hardware rx and tx fifos */
402 nvt_clear_cir_fifo(nvt
);
403 nvt_clear_tx_fifo(nvt
);
405 /* clear any and all stray interrupts */
406 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
408 /* and finally, enable interrupts */
409 nvt_set_cir_iren(nvt
);
412 static void nvt_cir_wake_regs_init(struct nvt_dev
*nvt
)
414 /* set number of bytes needed for wake from s3 (default 65) */
415 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_FIFO_CMP_BYTES
,
416 CIR_WAKE_FIFO_CMP_DEEP
);
418 /* set tolerance/variance allowed per byte during wake compare */
419 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_CMP_TOLERANCE
,
420 CIR_WAKE_FIFO_CMP_TOL
);
422 /* set sample limit count (PE interrupt raised when reached) */
423 nvt_cir_wake_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_WAKE_SLCH
);
424 nvt_cir_wake_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_WAKE_SLCL
);
426 /* set cir wake fifo rx trigger level (currently 67) */
427 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV
,
431 * Enable TX and RX, specific carrier on = low, off = high, and set
432 * sample period (currently 50us)
434 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
435 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
436 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
439 /* clear cir wake rx fifo */
440 nvt_clear_cir_wake_fifo(nvt
);
442 /* clear any and all stray interrupts */
443 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
446 static void nvt_enable_wake(struct nvt_dev
*nvt
)
450 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
451 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
452 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
454 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
455 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
457 nvt_efm_disable(nvt
);
459 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
460 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
461 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
463 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
464 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
467 #if 0 /* Currently unused */
468 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
469 static u32
nvt_rx_carrier_detect(struct nvt_dev
*nvt
)
471 u32 count
, carrier
, duration
= 0;
474 count
= nvt_cir_reg_read(nvt
, CIR_FCCL
) |
475 nvt_cir_reg_read(nvt
, CIR_FCCH
) << 8;
477 for (i
= 0; i
< nvt
->pkts
; i
++) {
478 if (nvt
->buf
[i
] & BUF_PULSE_BIT
)
479 duration
+= nvt
->buf
[i
] & BUF_LEN_MASK
;
482 duration
*= SAMPLE_PERIOD
;
484 if (!count
|| !duration
) {
485 nvt_pr(KERN_NOTICE
, "Unable to determine carrier! (c:%u, d:%u)",
490 carrier
= MS_TO_NS(count
) / duration
;
492 if ((carrier
> MAX_CARRIER
) || (carrier
< MIN_CARRIER
))
493 nvt_dbg("WTF? Carrier frequency out of range!");
495 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
496 carrier
, count
, duration
);
502 * set carrier frequency
504 * set carrier on 2 registers: CP & CC
505 * always set CP as 0x81
506 * set CC by SPEC, CC = 3MHz/carrier - 1
508 static int nvt_set_tx_carrier(struct rc_dev
*dev
, u32 carrier
)
510 struct nvt_dev
*nvt
= dev
->priv
;
516 nvt_cir_reg_write(nvt
, 1, CIR_CP
);
517 val
= 3000000 / (carrier
) - 1;
518 nvt_cir_reg_write(nvt
, val
& 0xff, CIR_CC
);
520 nvt_dbg("cp: 0x%x cc: 0x%x\n",
521 nvt_cir_reg_read(nvt
, CIR_CP
), nvt_cir_reg_read(nvt
, CIR_CC
));
529 * 1) clean TX fifo first (handled by AP)
530 * 2) copy data from user space
531 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
532 * 4) send 9 packets to TX FIFO to open TTR
533 * in interrupt_handler:
534 * 5) send all data out
535 * go back to write():
536 * 6) disable TX interrupts, re-enable RX interupts
538 * The key problem of this function is user space data may larger than
539 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
540 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
541 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
542 * set TXFCONT as 0xff, until buf_count less than 0xff.
544 static int nvt_tx_ir(struct rc_dev
*dev
, unsigned *txbuf
, unsigned n
)
546 struct nvt_dev
*nvt
= dev
->priv
;
552 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
554 ret
= min((unsigned)(TX_BUF_LEN
/ sizeof(unsigned)), n
);
555 nvt
->tx
.buf_count
= (ret
* sizeof(unsigned));
557 memcpy(nvt
->tx
.buf
, txbuf
, nvt
->tx
.buf_count
);
559 nvt
->tx
.cur_buf_num
= 0;
561 /* save currently enabled interrupts */
562 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
564 /* now disable all interrupts, save TFU & TTR */
565 nvt_cir_reg_write(nvt
, CIR_IREN_TFU
| CIR_IREN_TTR
, CIR_IREN
);
567 nvt
->tx
.tx_state
= ST_TX_REPLY
;
569 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV_8
|
570 CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
572 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
573 for (i
= 0; i
< 9; i
++)
574 nvt_cir_reg_write(nvt
, 0x01, CIR_STXFIFO
);
576 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
578 wait_event(nvt
->tx
.queue
, nvt
->tx
.tx_state
== ST_TX_REQUEST
);
580 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
581 nvt
->tx
.tx_state
= ST_TX_NONE
;
582 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
584 /* restore enabled interrupts to prior state */
585 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
590 /* dump contents of the last rx buffer we got from the hw rx fifo */
591 static void nvt_dump_rx_buf(struct nvt_dev
*nvt
)
595 printk(KERN_DEBUG
"%s (len %d): ", __func__
, nvt
->pkts
);
596 for (i
= 0; (i
< nvt
->pkts
) && (i
< RX_BUF_LEN
); i
++)
597 printk(KERN_CONT
"0x%02x ", nvt
->buf
[i
]);
598 printk(KERN_CONT
"\n");
602 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
603 * trigger decode when appropriate.
605 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
606 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
607 * (default 50us) intervals for that pulse/space. A discrete signal is
608 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
609 * to signal more IR coming (repeats) or end of IR, respectively. We store
610 * sample data in the raw event kfifo until we see 0x7<something> (except f)
611 * or 0x80, at which time, we trigger a decode operation.
613 static void nvt_process_rx_ir_data(struct nvt_dev
*nvt
)
615 DEFINE_IR_RAW_EVENT(rawir
);
619 nvt_dbg_verbose("%s firing", __func__
);
622 nvt_dump_rx_buf(nvt
);
624 nvt_dbg_verbose("Processing buffer of len %d", nvt
->pkts
);
626 init_ir_raw_event(&rawir
);
628 for (i
= 0; i
< nvt
->pkts
; i
++) {
629 sample
= nvt
->buf
[i
];
631 rawir
.pulse
= ((sample
& BUF_PULSE_BIT
) != 0);
632 rawir
.duration
= US_TO_NS((sample
& BUF_LEN_MASK
)
635 nvt_dbg("Storing %s with duration %d",
636 rawir
.pulse
? "pulse" : "space", rawir
.duration
);
638 ir_raw_event_store_with_filter(nvt
->rdev
, &rawir
);
641 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
642 * indicates end of IR signal, but new data incoming. In both
643 * cases, it means we're ready to call ir_raw_event_handle
645 if ((sample
== BUF_PULSE_BIT
) && (i
+ 1 < nvt
->pkts
)) {
646 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
647 ir_raw_event_handle(nvt
->rdev
);
653 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
654 ir_raw_event_handle(nvt
->rdev
);
656 nvt_dbg_verbose("%s done", __func__
);
659 static void nvt_handle_rx_fifo_overrun(struct nvt_dev
*nvt
)
661 nvt_pr(KERN_WARNING
, "RX FIFO overrun detected, flushing data!");
664 nvt_clear_cir_fifo(nvt
);
665 ir_raw_event_reset(nvt
->rdev
);
668 /* copy data from hardware rx fifo into driver buffer */
669 static void nvt_get_rx_ir_data(struct nvt_dev
*nvt
)
674 bool overrun
= false;
677 /* Get count of how many bytes to read from RX FIFO */
678 fifocount
= nvt_cir_reg_read(nvt
, CIR_RXFCONT
);
679 /* if we get 0xff, probably means the logical dev is disabled */
680 if (fifocount
== 0xff)
682 /* watch out for a fifo overrun condition */
683 else if (fifocount
> RX_BUF_LEN
) {
685 fifocount
= RX_BUF_LEN
;
688 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount
);
690 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
694 /* This should never happen, but lets check anyway... */
695 if (b_idx
+ fifocount
> RX_BUF_LEN
) {
696 nvt_process_rx_ir_data(nvt
);
700 /* Read fifocount bytes from CIR Sample RX FIFO register */
701 for (i
= 0; i
< fifocount
; i
++) {
702 val
= nvt_cir_reg_read(nvt
, CIR_SRXFIFO
);
703 nvt
->buf
[b_idx
+ i
] = val
;
706 nvt
->pkts
+= fifocount
;
707 nvt_dbg("%s: pkts now %d", __func__
, nvt
->pkts
);
709 nvt_process_rx_ir_data(nvt
);
712 nvt_handle_rx_fifo_overrun(nvt
);
714 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
717 static void nvt_cir_log_irqs(u8 status
, u8 iren
)
719 nvt_pr(KERN_INFO
, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
721 status
& CIR_IRSTS_RDR
? " RDR" : "",
722 status
& CIR_IRSTS_RTR
? " RTR" : "",
723 status
& CIR_IRSTS_PE
? " PE" : "",
724 status
& CIR_IRSTS_RFO
? " RFO" : "",
725 status
& CIR_IRSTS_TE
? " TE" : "",
726 status
& CIR_IRSTS_TTR
? " TTR" : "",
727 status
& CIR_IRSTS_TFU
? " TFU" : "",
728 status
& CIR_IRSTS_GH
? " GH" : "",
729 status
& ~(CIR_IRSTS_RDR
| CIR_IRSTS_RTR
| CIR_IRSTS_PE
|
730 CIR_IRSTS_RFO
| CIR_IRSTS_TE
| CIR_IRSTS_TTR
|
731 CIR_IRSTS_TFU
| CIR_IRSTS_GH
) ? " ?" : "");
734 static bool nvt_cir_tx_inactive(struct nvt_dev
*nvt
)
740 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
741 tx_state
= nvt
->tx
.tx_state
;
742 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
744 tx_inactive
= (tx_state
== ST_TX_NONE
);
749 /* interrupt service routine for incoming and outgoing CIR data */
750 static irqreturn_t
nvt_cir_isr(int irq
, void *data
)
752 struct nvt_dev
*nvt
= data
;
753 u8 status
, iren
, cur_state
;
756 nvt_dbg_verbose("%s firing", __func__
);
759 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
760 nvt_efm_disable(nvt
);
763 * Get IR Status register contents. Write 1 to ack/clear
765 * bit: reg name - description
766 * 7: CIR_IRSTS_RDR - RX Data Ready
767 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
768 * 5: CIR_IRSTS_PE - Packet End
769 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
770 * 3: CIR_IRSTS_TE - TX FIFO Empty
771 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
772 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
773 * 0: CIR_IRSTS_GH - Min Length Detected
775 status
= nvt_cir_reg_read(nvt
, CIR_IRSTS
);
777 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__
);
778 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
782 /* ack/clear all irq flags we've got */
783 nvt_cir_reg_write(nvt
, status
, CIR_IRSTS
);
784 nvt_cir_reg_write(nvt
, 0, CIR_IRSTS
);
786 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
787 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
789 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__
);
794 nvt_cir_log_irqs(status
, iren
);
796 if (status
& CIR_IRSTS_RTR
) {
797 /* FIXME: add code for study/learn mode */
798 /* We only do rx if not tx'ing */
799 if (nvt_cir_tx_inactive(nvt
))
800 nvt_get_rx_ir_data(nvt
);
803 if (status
& CIR_IRSTS_PE
) {
804 if (nvt_cir_tx_inactive(nvt
))
805 nvt_get_rx_ir_data(nvt
);
807 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
809 cur_state
= nvt
->study_state
;
811 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
813 if (cur_state
== ST_STUDY_NONE
)
814 nvt_clear_cir_fifo(nvt
);
817 if (status
& CIR_IRSTS_TE
)
818 nvt_clear_tx_fifo(nvt
);
820 if (status
& CIR_IRSTS_TTR
) {
821 unsigned int pos
, count
;
824 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
826 pos
= nvt
->tx
.cur_buf_num
;
827 count
= nvt
->tx
.buf_count
;
829 /* Write data into the hardware tx fifo while pos < count */
831 nvt_cir_reg_write(nvt
, nvt
->tx
.buf
[pos
], CIR_STXFIFO
);
832 nvt
->tx
.cur_buf_num
++;
833 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
835 tmp
= nvt_cir_reg_read(nvt
, CIR_IREN
);
836 nvt_cir_reg_write(nvt
, tmp
& ~CIR_IREN_TTR
, CIR_IREN
);
839 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
843 if (status
& CIR_IRSTS_TFU
) {
844 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
845 if (nvt
->tx
.tx_state
== ST_TX_REPLY
) {
846 nvt
->tx
.tx_state
= ST_TX_REQUEST
;
847 wake_up(&nvt
->tx
.queue
);
849 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
852 nvt_dbg_verbose("%s done", __func__
);
856 /* Interrupt service routine for CIR Wake */
857 static irqreturn_t
nvt_cir_wake_isr(int irq
, void *data
)
859 u8 status
, iren
, val
;
860 struct nvt_dev
*nvt
= data
;
863 nvt_dbg_wake("%s firing", __func__
);
865 status
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
);
869 if (status
& CIR_WAKE_IRSTS_IR_PENDING
)
870 nvt_clear_cir_wake_fifo(nvt
);
872 nvt_cir_wake_reg_write(nvt
, status
, CIR_WAKE_IRSTS
);
873 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IRSTS
);
875 /* Interrupt may be shared with CIR, bail if Wake not enabled */
876 iren
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
);
878 nvt_dbg_wake("%s exiting, wake not enabled", __func__
);
882 if ((status
& CIR_WAKE_IRSTS_PE
) &&
883 (nvt
->wake_state
== ST_WAKE_START
)) {
884 while (nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
)) {
885 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
886 nvt_dbg("setting wake up key: 0x%x", val
);
889 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
890 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
891 nvt
->wake_state
= ST_WAKE_FINISH
;
892 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
895 nvt_dbg_wake("%s done", __func__
);
899 static void nvt_enable_cir(struct nvt_dev
*nvt
)
901 /* set function enable flags */
902 nvt_cir_reg_write(nvt
, CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
903 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
908 /* enable the CIR logical device */
909 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
910 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
912 nvt_efm_disable(nvt
);
914 /* clear all pending interrupts */
915 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
917 /* enable interrupts */
918 nvt_set_cir_iren(nvt
);
921 static void nvt_disable_cir(struct nvt_dev
*nvt
)
923 /* disable CIR interrupts */
924 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
926 /* clear any and all pending interrupts */
927 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
929 /* clear all function enable flags */
930 nvt_cir_reg_write(nvt
, 0, CIR_IRCON
);
932 /* clear hardware rx and tx fifos */
933 nvt_clear_cir_fifo(nvt
);
934 nvt_clear_tx_fifo(nvt
);
938 /* disable the CIR logical device */
939 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
940 nvt_cr_write(nvt
, LOGICAL_DEV_DISABLE
, CR_LOGICAL_DEV_EN
);
942 nvt_efm_disable(nvt
);
945 static int nvt_open(struct rc_dev
*dev
)
947 struct nvt_dev
*nvt
= dev
->priv
;
950 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
952 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
957 static void nvt_close(struct rc_dev
*dev
)
959 struct nvt_dev
*nvt
= dev
->priv
;
962 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
963 nvt_disable_cir(nvt
);
964 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
967 /* Allocate memory, probe hardware, and initialize everything */
968 static int nvt_probe(struct pnp_dev
*pdev
, const struct pnp_device_id
*dev_id
)
974 nvt
= kzalloc(sizeof(struct nvt_dev
), GFP_KERNEL
);
978 /* input device for IR remote (and tx) */
979 rdev
= rc_allocate_device();
981 goto exit_free_dev_rdev
;
984 /* activate pnp device */
985 if (pnp_activate_dev(pdev
) < 0) {
986 dev_err(&pdev
->dev
, "Could not activate PNP device!\n");
987 goto exit_free_dev_rdev
;
990 /* validate pnp resources */
991 if (!pnp_port_valid(pdev
, 0) ||
992 pnp_port_len(pdev
, 0) < CIR_IOREG_LENGTH
) {
993 dev_err(&pdev
->dev
, "IR PNP Port not valid!\n");
994 goto exit_free_dev_rdev
;
997 if (!pnp_irq_valid(pdev
, 0)) {
998 dev_err(&pdev
->dev
, "PNP IRQ not valid!\n");
999 goto exit_free_dev_rdev
;
1002 if (!pnp_port_valid(pdev
, 1) ||
1003 pnp_port_len(pdev
, 1) < CIR_IOREG_LENGTH
) {
1004 dev_err(&pdev
->dev
, "Wake PNP Port not valid!\n");
1005 goto exit_free_dev_rdev
;
1008 nvt
->cir_addr
= pnp_port_start(pdev
, 0);
1009 nvt
->cir_irq
= pnp_irq(pdev
, 0);
1011 nvt
->cir_wake_addr
= pnp_port_start(pdev
, 1);
1012 /* irq is always shared between cir and cir wake */
1013 nvt
->cir_wake_irq
= nvt
->cir_irq
;
1015 nvt
->cr_efir
= CR_EFIR
;
1016 nvt
->cr_efdr
= CR_EFDR
;
1018 spin_lock_init(&nvt
->nvt_lock
);
1019 spin_lock_init(&nvt
->tx
.lock
);
1021 pnp_set_drvdata(pdev
, nvt
);
1024 init_waitqueue_head(&nvt
->tx
.queue
);
1026 ret
= nvt_hw_detect(nvt
);
1028 goto exit_free_dev_rdev
;
1030 /* Initialize CIR & CIR Wake Logical Devices */
1031 nvt_efm_enable(nvt
);
1032 nvt_cir_ldev_init(nvt
);
1033 nvt_cir_wake_ldev_init(nvt
);
1034 nvt_efm_disable(nvt
);
1036 /* Initialize CIR & CIR Wake Config Registers */
1037 nvt_cir_regs_init(nvt
);
1038 nvt_cir_wake_regs_init(nvt
);
1040 /* Set up the rc device */
1042 rdev
->driver_type
= RC_DRIVER_IR_RAW
;
1043 rdev
->allowed_protocols
= RC_BIT_ALL
;
1044 rdev
->open
= nvt_open
;
1045 rdev
->close
= nvt_close
;
1046 rdev
->tx_ir
= nvt_tx_ir
;
1047 rdev
->s_tx_carrier
= nvt_set_tx_carrier
;
1048 rdev
->input_name
= "Nuvoton w836x7hg Infrared Remote Transceiver";
1049 rdev
->input_phys
= "nuvoton/cir0";
1050 rdev
->input_id
.bustype
= BUS_HOST
;
1051 rdev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND2
;
1052 rdev
->input_id
.product
= nvt
->chip_major
;
1053 rdev
->input_id
.version
= nvt
->chip_minor
;
1054 rdev
->dev
.parent
= &pdev
->dev
;
1055 rdev
->driver_name
= NVT_DRIVER_NAME
;
1056 rdev
->map_name
= RC_MAP_RC6_MCE
;
1057 rdev
->timeout
= MS_TO_NS(100);
1058 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1059 rdev
->rx_resolution
= US_TO_NS(CIR_SAMPLE_PERIOD
);
1061 rdev
->min_timeout
= XYZ
;
1062 rdev
->max_timeout
= XYZ
;
1064 rdev
->tx_resolution
= XYZ
;
1068 ret
= rc_register_device(rdev
);
1070 goto exit_free_dev_rdev
;
1073 /* now claim resources */
1074 if (!request_region(nvt
->cir_addr
,
1075 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
))
1076 goto exit_unregister_device
;
1078 if (request_irq(nvt
->cir_irq
, nvt_cir_isr
, IRQF_SHARED
,
1079 NVT_DRIVER_NAME
, (void *)nvt
))
1080 goto exit_release_cir_addr
;
1082 if (!request_region(nvt
->cir_wake_addr
,
1083 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
))
1086 if (request_irq(nvt
->cir_wake_irq
, nvt_cir_wake_isr
, IRQF_SHARED
,
1087 NVT_DRIVER_NAME
, (void *)nvt
))
1088 goto exit_release_cir_wake_addr
;
1090 device_init_wakeup(&pdev
->dev
, true);
1092 nvt_pr(KERN_NOTICE
, "driver has been successfully loaded\n");
1095 cir_wake_dump_regs(nvt
);
1100 exit_release_cir_wake_addr
:
1101 release_region(nvt
->cir_wake_addr
, CIR_IOREG_LENGTH
);
1103 free_irq(nvt
->cir_irq
, nvt
);
1104 exit_release_cir_addr
:
1105 release_region(nvt
->cir_addr
, CIR_IOREG_LENGTH
);
1106 exit_unregister_device
:
1107 rc_unregister_device(rdev
);
1110 rc_free_device(rdev
);
1116 static void nvt_remove(struct pnp_dev
*pdev
)
1118 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1119 unsigned long flags
;
1121 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1123 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1124 nvt_disable_cir(nvt
);
1125 /* enable CIR Wake (for IR power-on) */
1126 nvt_enable_wake(nvt
);
1127 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1129 /* free resources */
1130 free_irq(nvt
->cir_irq
, nvt
);
1131 free_irq(nvt
->cir_wake_irq
, nvt
);
1132 release_region(nvt
->cir_addr
, CIR_IOREG_LENGTH
);
1133 release_region(nvt
->cir_wake_addr
, CIR_IOREG_LENGTH
);
1135 rc_unregister_device(nvt
->rdev
);
1140 static int nvt_suspend(struct pnp_dev
*pdev
, pm_message_t state
)
1142 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1143 unsigned long flags
;
1145 nvt_dbg("%s called", __func__
);
1147 /* zero out misc state tracking */
1148 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1149 nvt
->study_state
= ST_STUDY_NONE
;
1150 nvt
->wake_state
= ST_WAKE_NONE
;
1151 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1153 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
1154 nvt
->tx
.tx_state
= ST_TX_NONE
;
1155 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
1157 /* disable all CIR interrupts */
1158 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1160 nvt_efm_enable(nvt
);
1162 /* disable cir logical dev */
1163 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
1164 nvt_cr_write(nvt
, LOGICAL_DEV_DISABLE
, CR_LOGICAL_DEV_EN
);
1166 nvt_efm_disable(nvt
);
1168 /* make sure wake is enabled */
1169 nvt_enable_wake(nvt
);
1174 static int nvt_resume(struct pnp_dev
*pdev
)
1176 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1178 nvt_dbg("%s called", __func__
);
1180 /* open interrupt */
1181 nvt_set_cir_iren(nvt
);
1183 /* Enable CIR logical device */
1184 nvt_efm_enable(nvt
);
1185 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
1186 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
1188 nvt_efm_disable(nvt
);
1190 nvt_cir_regs_init(nvt
);
1191 nvt_cir_wake_regs_init(nvt
);
1196 static void nvt_shutdown(struct pnp_dev
*pdev
)
1198 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1199 nvt_enable_wake(nvt
);
1202 static const struct pnp_device_id nvt_ids
[] = {
1203 { "WEC0530", 0 }, /* CIR */
1204 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1208 static struct pnp_driver nvt_driver
= {
1209 .name
= NVT_DRIVER_NAME
,
1210 .id_table
= nvt_ids
,
1211 .flags
= PNP_DRIVER_RES_DO_NOT_CHANGE
,
1213 .remove
= nvt_remove
,
1214 .suspend
= nvt_suspend
,
1215 .resume
= nvt_resume
,
1216 .shutdown
= nvt_shutdown
,
1219 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
1220 MODULE_PARM_DESC(debug
, "Enable debugging output");
1222 MODULE_DEVICE_TABLE(pnp
, nvt_ids
);
1223 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1225 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1226 MODULE_LICENSE("GPL");
1228 module_pnp_driver(nvt_driver
);