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[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static const struct nvt_chip nvt_chips[] = {
43 { "w83667hg", NVT_W83667HG },
44 { "NCT6775F", NVT_6775F },
45 { "NCT6776F", NVT_6776F },
46 { "NCT6779D", NVT_6779D },
47 };
48
49 static inline bool is_w83667hg(struct nvt_dev *nvt)
50 {
51 return nvt->chip_ver == NVT_W83667HG;
52 }
53
54 /* write val to config reg */
55 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
56 {
57 outb(reg, nvt->cr_efir);
58 outb(val, nvt->cr_efdr);
59 }
60
61 /* read val from config reg */
62 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
63 {
64 outb(reg, nvt->cr_efir);
65 return inb(nvt->cr_efdr);
66 }
67
68 /* update config register bit without changing other bits */
69 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
70 {
71 u8 tmp = nvt_cr_read(nvt, reg) | val;
72 nvt_cr_write(nvt, tmp, reg);
73 }
74
75 /* clear config register bit without changing other bits */
76 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
77 {
78 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
79 nvt_cr_write(nvt, tmp, reg);
80 }
81
82 /* enter extended function mode */
83 static inline int nvt_efm_enable(struct nvt_dev *nvt)
84 {
85 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
86 return -EBUSY;
87
88 /* Enabling Extended Function Mode explicitly requires writing 2x */
89 outb(EFER_EFM_ENABLE, nvt->cr_efir);
90 outb(EFER_EFM_ENABLE, nvt->cr_efir);
91
92 return 0;
93 }
94
95 /* exit extended function mode */
96 static inline void nvt_efm_disable(struct nvt_dev *nvt)
97 {
98 outb(EFER_EFM_DISABLE, nvt->cr_efir);
99
100 release_region(nvt->cr_efir, 2);
101 }
102
103 /*
104 * When you want to address a specific logical device, write its logical
105 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
106 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
107 */
108 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
109 {
110 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
111 }
112
113 /* select and disable logical device with setting EFM mode*/
114 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
115 {
116 nvt_efm_enable(nvt);
117 nvt_select_logical_dev(nvt, ldev);
118 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
119 nvt_efm_disable(nvt);
120 }
121
122 /* write val to cir config register */
123 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
124 {
125 outb(val, nvt->cir_addr + offset);
126 }
127
128 /* read val from cir config register */
129 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
130 {
131 u8 val;
132
133 val = inb(nvt->cir_addr + offset);
134
135 return val;
136 }
137
138 /* write val to cir wake register */
139 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
140 u8 val, u8 offset)
141 {
142 outb(val, nvt->cir_wake_addr + offset);
143 }
144
145 /* read val from cir wake config register */
146 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
147 {
148 u8 val;
149
150 val = inb(nvt->cir_wake_addr + offset);
151
152 return val;
153 }
154
155 /* dump current cir register contents */
156 static void cir_dump_regs(struct nvt_dev *nvt)
157 {
158 nvt_efm_enable(nvt);
159 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
160
161 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
162 pr_info(" * CR CIR ACTIVE : 0x%x\n",
163 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
164 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
165 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
166 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
167 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
168 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
169
170 nvt_efm_disable(nvt);
171
172 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
173 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
174 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
175 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
176 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
177 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
178 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
179 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
180 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
181 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
182 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
183 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
184 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
185 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
186 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
187 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
188 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
189 }
190
191 /* dump current cir wake register contents */
192 static void cir_wake_dump_regs(struct nvt_dev *nvt)
193 {
194 u8 i, fifo_len;
195
196 nvt_efm_enable(nvt);
197 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
198
199 pr_info("%s: Dump CIR WAKE logical device registers:\n",
200 NVT_DRIVER_NAME);
201 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
202 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
203 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
204 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
205 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
206 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
207 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
208
209 nvt_efm_disable(nvt);
210
211 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
212 pr_info(" * IRCON: 0x%x\n",
213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
214 pr_info(" * IRSTS: 0x%x\n",
215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
216 pr_info(" * IREN: 0x%x\n",
217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
218 pr_info(" * FIFO CMP DEEP: 0x%x\n",
219 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
220 pr_info(" * FIFO CMP TOL: 0x%x\n",
221 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
222 pr_info(" * FIFO COUNT: 0x%x\n",
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
224 pr_info(" * SLCH: 0x%x\n",
225 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
226 pr_info(" * SLCL: 0x%x\n",
227 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
228 pr_info(" * FIFOCON: 0x%x\n",
229 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
230 pr_info(" * SRXFSTS: 0x%x\n",
231 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
232 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
233 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
234 pr_info(" * WR FIFO DATA: 0x%x\n",
235 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
236 pr_info(" * RD FIFO ONLY: 0x%x\n",
237 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
238 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
239 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
240 pr_info(" * FIFO IGNORE: 0x%x\n",
241 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
242 pr_info(" * IRFSM: 0x%x\n",
243 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
244
245 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
246 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
247 pr_info("* Contents =");
248 for (i = 0; i < fifo_len; i++)
249 pr_cont(" %02x",
250 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
251 pr_cont("\n");
252 }
253
254 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
255 {
256 int i;
257
258 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
259 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
260 nvt->chip_ver = nvt_chips[i].chip_ver;
261 return nvt_chips[i].name;
262 }
263
264 return NULL;
265 }
266
267
268 /* detect hardware features */
269 static void nvt_hw_detect(struct nvt_dev *nvt)
270 {
271 const char *chip_name;
272 int chip_id;
273
274 nvt_efm_enable(nvt);
275
276 /* Check if we're wired for the alternate EFER setup */
277 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
278 if (nvt->chip_major == 0xff) {
279 nvt->cr_efir = CR_EFIR2;
280 nvt->cr_efdr = CR_EFDR2;
281 nvt_efm_enable(nvt);
282 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
283 }
284
285 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
286
287 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
288 chip_name = nvt_find_chip(nvt, chip_id);
289
290 /* warn, but still let the driver load, if we don't know this chip */
291 if (!chip_name)
292 dev_warn(&nvt->pdev->dev,
293 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
294 nvt->chip_major, nvt->chip_minor);
295 else
296 dev_info(&nvt->pdev->dev,
297 "found %s or compatible: chip id: 0x%02x 0x%02x",
298 chip_name, nvt->chip_major, nvt->chip_minor);
299
300 nvt_efm_disable(nvt);
301 }
302
303 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
304 {
305 u8 val, psreg, psmask, psval;
306
307 if (is_w83667hg(nvt)) {
308 psreg = CR_MULTIFUNC_PIN_SEL;
309 psmask = MULTIFUNC_PIN_SEL_MASK;
310 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
311 } else {
312 psreg = CR_OUTPUT_PIN_SEL;
313 psmask = OUTPUT_PIN_SEL_MASK;
314 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
315 }
316
317 /* output pin selection: enable CIR, with WB sensor enabled */
318 val = nvt_cr_read(nvt, psreg);
319 val &= psmask;
320 val |= psval;
321 nvt_cr_write(nvt, val, psreg);
322
323 /* Select CIR logical device and enable */
324 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
325 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
326
327 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
328 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
329
330 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
331
332 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
333 nvt->cir_addr, nvt->cir_irq);
334 }
335
336 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
337 {
338 /* Select ACPI logical device, enable it and CIR Wake */
339 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
340 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
341
342 /* Enable CIR Wake via PSOUT# (Pin60) */
343 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
344
345 /* enable pme interrupt of cir wakeup event */
346 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
347
348 /* Select CIR Wake logical device and enable */
349 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
350 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
351
352 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
353 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
354
355 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
356
357 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
358 nvt->cir_wake_addr, nvt->cir_wake_irq);
359 }
360
361 /* clear out the hardware's cir rx fifo */
362 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
363 {
364 u8 val;
365
366 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
367 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
368 }
369
370 /* clear out the hardware's cir wake rx fifo */
371 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
372 {
373 u8 val;
374
375 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
376 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
377 CIR_WAKE_FIFOCON);
378 }
379
380 /* clear out the hardware's cir tx fifo */
381 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
382 {
383 u8 val;
384
385 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
386 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
387 }
388
389 /* enable RX Trigger Level Reach and Packet End interrupts */
390 static void nvt_set_cir_iren(struct nvt_dev *nvt)
391 {
392 u8 iren;
393
394 iren = CIR_IREN_RTR | CIR_IREN_PE;
395 nvt_cir_reg_write(nvt, iren, CIR_IREN);
396 }
397
398 static void nvt_cir_regs_init(struct nvt_dev *nvt)
399 {
400 /* set sample limit count (PE interrupt raised when reached) */
401 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
402 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
403
404 /* set fifo irq trigger levels */
405 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
406 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
407
408 /*
409 * Enable TX and RX, specify carrier on = low, off = high, and set
410 * sample period (currently 50us)
411 */
412 nvt_cir_reg_write(nvt,
413 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
414 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
415 CIR_IRCON);
416
417 /* clear hardware rx and tx fifos */
418 nvt_clear_cir_fifo(nvt);
419 nvt_clear_tx_fifo(nvt);
420
421 /* clear any and all stray interrupts */
422 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
423
424 /* and finally, enable interrupts */
425 nvt_set_cir_iren(nvt);
426 }
427
428 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
429 {
430 /* set number of bytes needed for wake from s3 (default 65) */
431 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
432 CIR_WAKE_FIFO_CMP_DEEP);
433
434 /* set tolerance/variance allowed per byte during wake compare */
435 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
436 CIR_WAKE_FIFO_CMP_TOL);
437
438 /* set sample limit count (PE interrupt raised when reached) */
439 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
440 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
441
442 /* set cir wake fifo rx trigger level (currently 67) */
443 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
444 CIR_WAKE_FIFOCON);
445
446 /*
447 * Enable TX and RX, specific carrier on = low, off = high, and set
448 * sample period (currently 50us)
449 */
450 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
451 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
452 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
453 CIR_WAKE_IRCON);
454
455 /* clear cir wake rx fifo */
456 nvt_clear_cir_wake_fifo(nvt);
457
458 /* clear any and all stray interrupts */
459 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
460 }
461
462 static void nvt_enable_wake(struct nvt_dev *nvt)
463 {
464 nvt_efm_enable(nvt);
465
466 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
467 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
468 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
469
470 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
471 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
472
473 nvt_efm_disable(nvt);
474
475 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
476 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
477 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
478 CIR_WAKE_IRCON);
479 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
480 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
481 }
482
483 #if 0 /* Currently unused */
484 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
485 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
486 {
487 u32 count, carrier, duration = 0;
488 int i;
489
490 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
491 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
492
493 for (i = 0; i < nvt->pkts; i++) {
494 if (nvt->buf[i] & BUF_PULSE_BIT)
495 duration += nvt->buf[i] & BUF_LEN_MASK;
496 }
497
498 duration *= SAMPLE_PERIOD;
499
500 if (!count || !duration) {
501 dev_notice(&nvt->pdev->dev,
502 "Unable to determine carrier! (c:%u, d:%u)",
503 count, duration);
504 return 0;
505 }
506
507 carrier = MS_TO_NS(count) / duration;
508
509 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
510 nvt_dbg("WTF? Carrier frequency out of range!");
511
512 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
513 carrier, count, duration);
514
515 return carrier;
516 }
517 #endif
518 /*
519 * set carrier frequency
520 *
521 * set carrier on 2 registers: CP & CC
522 * always set CP as 0x81
523 * set CC by SPEC, CC = 3MHz/carrier - 1
524 */
525 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
526 {
527 struct nvt_dev *nvt = dev->priv;
528 u16 val;
529
530 if (carrier == 0)
531 return -EINVAL;
532
533 nvt_cir_reg_write(nvt, 1, CIR_CP);
534 val = 3000000 / (carrier) - 1;
535 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
536
537 nvt_dbg("cp: 0x%x cc: 0x%x\n",
538 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
539
540 return 0;
541 }
542
543 /*
544 * nvt_tx_ir
545 *
546 * 1) clean TX fifo first (handled by AP)
547 * 2) copy data from user space
548 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
549 * 4) send 9 packets to TX FIFO to open TTR
550 * in interrupt_handler:
551 * 5) send all data out
552 * go back to write():
553 * 6) disable TX interrupts, re-enable RX interupts
554 *
555 * The key problem of this function is user space data may larger than
556 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
557 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
558 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
559 * set TXFCONT as 0xff, until buf_count less than 0xff.
560 */
561 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
562 {
563 struct nvt_dev *nvt = dev->priv;
564 unsigned long flags;
565 unsigned int i;
566 u8 iren;
567 int ret;
568
569 spin_lock_irqsave(&nvt->tx.lock, flags);
570
571 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
572 nvt->tx.buf_count = (ret * sizeof(unsigned));
573
574 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
575
576 nvt->tx.cur_buf_num = 0;
577
578 /* save currently enabled interrupts */
579 iren = nvt_cir_reg_read(nvt, CIR_IREN);
580
581 /* now disable all interrupts, save TFU & TTR */
582 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
583
584 nvt->tx.tx_state = ST_TX_REPLY;
585
586 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
587 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
588
589 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
590 for (i = 0; i < 9; i++)
591 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
592
593 spin_unlock_irqrestore(&nvt->tx.lock, flags);
594
595 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
596
597 spin_lock_irqsave(&nvt->tx.lock, flags);
598 nvt->tx.tx_state = ST_TX_NONE;
599 spin_unlock_irqrestore(&nvt->tx.lock, flags);
600
601 /* restore enabled interrupts to prior state */
602 nvt_cir_reg_write(nvt, iren, CIR_IREN);
603
604 return ret;
605 }
606
607 /* dump contents of the last rx buffer we got from the hw rx fifo */
608 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
609 {
610 int i;
611
612 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
613 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
614 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
615 printk(KERN_CONT "\n");
616 }
617
618 /*
619 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
620 * trigger decode when appropriate.
621 *
622 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
623 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
624 * (default 50us) intervals for that pulse/space. A discrete signal is
625 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
626 * to signal more IR coming (repeats) or end of IR, respectively. We store
627 * sample data in the raw event kfifo until we see 0x7<something> (except f)
628 * or 0x80, at which time, we trigger a decode operation.
629 */
630 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
631 {
632 DEFINE_IR_RAW_EVENT(rawir);
633 u8 sample;
634 int i;
635
636 nvt_dbg_verbose("%s firing", __func__);
637
638 if (debug)
639 nvt_dump_rx_buf(nvt);
640
641 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
642
643 init_ir_raw_event(&rawir);
644
645 for (i = 0; i < nvt->pkts; i++) {
646 sample = nvt->buf[i];
647
648 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
649 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
650 * SAMPLE_PERIOD);
651
652 nvt_dbg("Storing %s with duration %d",
653 rawir.pulse ? "pulse" : "space", rawir.duration);
654
655 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
656
657 /*
658 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
659 * indicates end of IR signal, but new data incoming. In both
660 * cases, it means we're ready to call ir_raw_event_handle
661 */
662 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
663 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
664 ir_raw_event_handle(nvt->rdev);
665 }
666 }
667
668 nvt->pkts = 0;
669
670 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
671 ir_raw_event_handle(nvt->rdev);
672
673 nvt_dbg_verbose("%s done", __func__);
674 }
675
676 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
677 {
678 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
679
680 nvt->pkts = 0;
681 nvt_clear_cir_fifo(nvt);
682 ir_raw_event_reset(nvt->rdev);
683 }
684
685 /* copy data from hardware rx fifo into driver buffer */
686 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
687 {
688 unsigned long flags;
689 u8 fifocount, val;
690 unsigned int b_idx;
691 bool overrun = false;
692 int i;
693
694 /* Get count of how many bytes to read from RX FIFO */
695 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
696 /* if we get 0xff, probably means the logical dev is disabled */
697 if (fifocount == 0xff)
698 return;
699 /* watch out for a fifo overrun condition */
700 else if (fifocount > RX_BUF_LEN) {
701 overrun = true;
702 fifocount = RX_BUF_LEN;
703 }
704
705 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
706
707 spin_lock_irqsave(&nvt->nvt_lock, flags);
708
709 b_idx = nvt->pkts;
710
711 /* This should never happen, but lets check anyway... */
712 if (b_idx + fifocount > RX_BUF_LEN) {
713 nvt_process_rx_ir_data(nvt);
714 b_idx = 0;
715 }
716
717 /* Read fifocount bytes from CIR Sample RX FIFO register */
718 for (i = 0; i < fifocount; i++) {
719 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
720 nvt->buf[b_idx + i] = val;
721 }
722
723 nvt->pkts += fifocount;
724 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
725
726 nvt_process_rx_ir_data(nvt);
727
728 if (overrun)
729 nvt_handle_rx_fifo_overrun(nvt);
730
731 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
732 }
733
734 static void nvt_cir_log_irqs(u8 status, u8 iren)
735 {
736 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
737 status, iren,
738 status & CIR_IRSTS_RDR ? " RDR" : "",
739 status & CIR_IRSTS_RTR ? " RTR" : "",
740 status & CIR_IRSTS_PE ? " PE" : "",
741 status & CIR_IRSTS_RFO ? " RFO" : "",
742 status & CIR_IRSTS_TE ? " TE" : "",
743 status & CIR_IRSTS_TTR ? " TTR" : "",
744 status & CIR_IRSTS_TFU ? " TFU" : "",
745 status & CIR_IRSTS_GH ? " GH" : "",
746 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
747 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
748 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
749 }
750
751 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
752 {
753 unsigned long flags;
754 u8 tx_state;
755
756 spin_lock_irqsave(&nvt->tx.lock, flags);
757 tx_state = nvt->tx.tx_state;
758 spin_unlock_irqrestore(&nvt->tx.lock, flags);
759
760 return tx_state == ST_TX_NONE;
761 }
762
763 /* interrupt service routine for incoming and outgoing CIR data */
764 static irqreturn_t nvt_cir_isr(int irq, void *data)
765 {
766 struct nvt_dev *nvt = data;
767 u8 status, iren, cur_state;
768 unsigned long flags;
769
770 nvt_dbg_verbose("%s firing", __func__);
771
772 nvt_efm_enable(nvt);
773 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
774 nvt_efm_disable(nvt);
775
776 /*
777 * Get IR Status register contents. Write 1 to ack/clear
778 *
779 * bit: reg name - description
780 * 7: CIR_IRSTS_RDR - RX Data Ready
781 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
782 * 5: CIR_IRSTS_PE - Packet End
783 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
784 * 3: CIR_IRSTS_TE - TX FIFO Empty
785 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
786 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
787 * 0: CIR_IRSTS_GH - Min Length Detected
788 */
789 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
790 if (!status) {
791 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
792 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
793 return IRQ_NONE;
794 }
795
796 /* ack/clear all irq flags we've got */
797 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
798 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
799
800 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
801 iren = nvt_cir_reg_read(nvt, CIR_IREN);
802 if (!iren) {
803 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
804 return IRQ_NONE;
805 }
806
807 nvt_cir_log_irqs(status, iren);
808
809 if (status & CIR_IRSTS_RTR) {
810 /* FIXME: add code for study/learn mode */
811 /* We only do rx if not tx'ing */
812 if (nvt_cir_tx_inactive(nvt))
813 nvt_get_rx_ir_data(nvt);
814 }
815
816 if (status & CIR_IRSTS_PE) {
817 if (nvt_cir_tx_inactive(nvt))
818 nvt_get_rx_ir_data(nvt);
819
820 spin_lock_irqsave(&nvt->nvt_lock, flags);
821
822 cur_state = nvt->study_state;
823
824 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
825
826 if (cur_state == ST_STUDY_NONE)
827 nvt_clear_cir_fifo(nvt);
828 }
829
830 if (status & CIR_IRSTS_TE)
831 nvt_clear_tx_fifo(nvt);
832
833 if (status & CIR_IRSTS_TTR) {
834 unsigned int pos, count;
835 u8 tmp;
836
837 spin_lock_irqsave(&nvt->tx.lock, flags);
838
839 pos = nvt->tx.cur_buf_num;
840 count = nvt->tx.buf_count;
841
842 /* Write data into the hardware tx fifo while pos < count */
843 if (pos < count) {
844 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
845 nvt->tx.cur_buf_num++;
846 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
847 } else {
848 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
849 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
850 }
851
852 spin_unlock_irqrestore(&nvt->tx.lock, flags);
853
854 }
855
856 if (status & CIR_IRSTS_TFU) {
857 spin_lock_irqsave(&nvt->tx.lock, flags);
858 if (nvt->tx.tx_state == ST_TX_REPLY) {
859 nvt->tx.tx_state = ST_TX_REQUEST;
860 wake_up(&nvt->tx.queue);
861 }
862 spin_unlock_irqrestore(&nvt->tx.lock, flags);
863 }
864
865 nvt_dbg_verbose("%s done", __func__);
866 return IRQ_HANDLED;
867 }
868
869 /* Interrupt service routine for CIR Wake */
870 static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
871 {
872 u8 status, iren, val;
873 struct nvt_dev *nvt = data;
874 unsigned long flags;
875
876 nvt_dbg_wake("%s firing", __func__);
877
878 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
879 if (!status)
880 return IRQ_NONE;
881
882 if (status & CIR_WAKE_IRSTS_IR_PENDING)
883 nvt_clear_cir_wake_fifo(nvt);
884
885 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
886 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
887
888 /* Interrupt may be shared with CIR, bail if Wake not enabled */
889 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
890 if (!iren) {
891 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
892 return IRQ_HANDLED;
893 }
894
895 if ((status & CIR_WAKE_IRSTS_PE) &&
896 (nvt->wake_state == ST_WAKE_START)) {
897 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
898 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
899 nvt_dbg("setting wake up key: 0x%x", val);
900 }
901
902 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
903 spin_lock_irqsave(&nvt->nvt_lock, flags);
904 nvt->wake_state = ST_WAKE_FINISH;
905 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
906 }
907
908 nvt_dbg_wake("%s done", __func__);
909 return IRQ_HANDLED;
910 }
911
912 static void nvt_enable_cir(struct nvt_dev *nvt)
913 {
914 /* set function enable flags */
915 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
916 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
917 CIR_IRCON);
918
919 nvt_efm_enable(nvt);
920
921 /* enable the CIR logical device */
922 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
923 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
924
925 nvt_efm_disable(nvt);
926
927 /* clear all pending interrupts */
928 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
929
930 /* enable interrupts */
931 nvt_set_cir_iren(nvt);
932 }
933
934 static void nvt_disable_cir(struct nvt_dev *nvt)
935 {
936 /* disable CIR interrupts */
937 nvt_cir_reg_write(nvt, 0, CIR_IREN);
938
939 /* clear any and all pending interrupts */
940 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
941
942 /* clear all function enable flags */
943 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
944
945 /* clear hardware rx and tx fifos */
946 nvt_clear_cir_fifo(nvt);
947 nvt_clear_tx_fifo(nvt);
948
949 /* disable the CIR logical device */
950 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
951 }
952
953 static int nvt_open(struct rc_dev *dev)
954 {
955 struct nvt_dev *nvt = dev->priv;
956 unsigned long flags;
957
958 spin_lock_irqsave(&nvt->nvt_lock, flags);
959 nvt_enable_cir(nvt);
960 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
961
962 return 0;
963 }
964
965 static void nvt_close(struct rc_dev *dev)
966 {
967 struct nvt_dev *nvt = dev->priv;
968 unsigned long flags;
969
970 spin_lock_irqsave(&nvt->nvt_lock, flags);
971 nvt_disable_cir(nvt);
972 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
973 }
974
975 /* Allocate memory, probe hardware, and initialize everything */
976 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
977 {
978 struct nvt_dev *nvt;
979 struct rc_dev *rdev;
980 int ret = -ENOMEM;
981
982 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
983 if (!nvt)
984 return ret;
985
986 /* input device for IR remote (and tx) */
987 rdev = rc_allocate_device();
988 if (!rdev)
989 goto exit_free_dev_rdev;
990
991 ret = -ENODEV;
992 /* activate pnp device */
993 if (pnp_activate_dev(pdev) < 0) {
994 dev_err(&pdev->dev, "Could not activate PNP device!\n");
995 goto exit_free_dev_rdev;
996 }
997
998 /* validate pnp resources */
999 if (!pnp_port_valid(pdev, 0) ||
1000 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1001 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1002 goto exit_free_dev_rdev;
1003 }
1004
1005 if (!pnp_irq_valid(pdev, 0)) {
1006 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1007 goto exit_free_dev_rdev;
1008 }
1009
1010 if (!pnp_port_valid(pdev, 1) ||
1011 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1012 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1013 goto exit_free_dev_rdev;
1014 }
1015
1016 nvt->cir_addr = pnp_port_start(pdev, 0);
1017 nvt->cir_irq = pnp_irq(pdev, 0);
1018
1019 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1020 /* irq is always shared between cir and cir wake */
1021 nvt->cir_wake_irq = nvt->cir_irq;
1022
1023 nvt->cr_efir = CR_EFIR;
1024 nvt->cr_efdr = CR_EFDR;
1025
1026 spin_lock_init(&nvt->nvt_lock);
1027 spin_lock_init(&nvt->tx.lock);
1028
1029 pnp_set_drvdata(pdev, nvt);
1030 nvt->pdev = pdev;
1031
1032 init_waitqueue_head(&nvt->tx.queue);
1033
1034 nvt_hw_detect(nvt);
1035
1036 /* Initialize CIR & CIR Wake Logical Devices */
1037 nvt_efm_enable(nvt);
1038 nvt_cir_ldev_init(nvt);
1039 nvt_cir_wake_ldev_init(nvt);
1040 nvt_efm_disable(nvt);
1041
1042 /* Initialize CIR & CIR Wake Config Registers */
1043 nvt_cir_regs_init(nvt);
1044 nvt_cir_wake_regs_init(nvt);
1045
1046 /* Set up the rc device */
1047 rdev->priv = nvt;
1048 rdev->driver_type = RC_DRIVER_IR_RAW;
1049 rdev->allowed_protocols = RC_BIT_ALL;
1050 rdev->open = nvt_open;
1051 rdev->close = nvt_close;
1052 rdev->tx_ir = nvt_tx_ir;
1053 rdev->s_tx_carrier = nvt_set_tx_carrier;
1054 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1055 rdev->input_phys = "nuvoton/cir0";
1056 rdev->input_id.bustype = BUS_HOST;
1057 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1058 rdev->input_id.product = nvt->chip_major;
1059 rdev->input_id.version = nvt->chip_minor;
1060 rdev->dev.parent = &pdev->dev;
1061 rdev->driver_name = NVT_DRIVER_NAME;
1062 rdev->map_name = RC_MAP_RC6_MCE;
1063 rdev->timeout = MS_TO_NS(100);
1064 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1065 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1066 #if 0
1067 rdev->min_timeout = XYZ;
1068 rdev->max_timeout = XYZ;
1069 /* tx bits */
1070 rdev->tx_resolution = XYZ;
1071 #endif
1072 nvt->rdev = rdev;
1073
1074 ret = rc_register_device(rdev);
1075 if (ret)
1076 goto exit_free_dev_rdev;
1077
1078 ret = -EBUSY;
1079 /* now claim resources */
1080 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1081 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1082 goto exit_unregister_device;
1083
1084 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1085 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1086 goto exit_unregister_device;
1087
1088 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1089 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1090 goto exit_unregister_device;
1091
1092 if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq,
1093 nvt_cir_wake_isr, IRQF_SHARED,
1094 NVT_DRIVER_NAME "-wake", (void *)nvt))
1095 goto exit_unregister_device;
1096
1097 device_init_wakeup(&pdev->dev, true);
1098
1099 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1100 if (debug) {
1101 cir_dump_regs(nvt);
1102 cir_wake_dump_regs(nvt);
1103 }
1104
1105 return 0;
1106
1107 exit_unregister_device:
1108 rc_unregister_device(rdev);
1109 rdev = NULL;
1110 exit_free_dev_rdev:
1111 rc_free_device(rdev);
1112
1113 return ret;
1114 }
1115
1116 static void nvt_remove(struct pnp_dev *pdev)
1117 {
1118 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1119 unsigned long flags;
1120
1121 spin_lock_irqsave(&nvt->nvt_lock, flags);
1122 /* disable CIR */
1123 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1124 nvt_disable_cir(nvt);
1125 /* enable CIR Wake (for IR power-on) */
1126 nvt_enable_wake(nvt);
1127 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1128
1129 rc_unregister_device(nvt->rdev);
1130 }
1131
1132 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1133 {
1134 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1135 unsigned long flags;
1136
1137 nvt_dbg("%s called", __func__);
1138
1139 /* zero out misc state tracking */
1140 spin_lock_irqsave(&nvt->nvt_lock, flags);
1141 nvt->study_state = ST_STUDY_NONE;
1142 nvt->wake_state = ST_WAKE_NONE;
1143 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1144
1145 spin_lock_irqsave(&nvt->tx.lock, flags);
1146 nvt->tx.tx_state = ST_TX_NONE;
1147 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1148
1149 /* disable all CIR interrupts */
1150 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1151
1152 /* disable cir logical dev */
1153 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1154
1155 /* make sure wake is enabled */
1156 nvt_enable_wake(nvt);
1157
1158 return 0;
1159 }
1160
1161 static int nvt_resume(struct pnp_dev *pdev)
1162 {
1163 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1164
1165 nvt_dbg("%s called", __func__);
1166
1167 /* open interrupt */
1168 nvt_set_cir_iren(nvt);
1169
1170 /* Enable CIR logical device */
1171 nvt_efm_enable(nvt);
1172 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1173 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1174
1175 nvt_efm_disable(nvt);
1176
1177 nvt_cir_regs_init(nvt);
1178 nvt_cir_wake_regs_init(nvt);
1179
1180 return 0;
1181 }
1182
1183 static void nvt_shutdown(struct pnp_dev *pdev)
1184 {
1185 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1186 nvt_enable_wake(nvt);
1187 }
1188
1189 static const struct pnp_device_id nvt_ids[] = {
1190 { "WEC0530", 0 }, /* CIR */
1191 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1192 { "", 0 },
1193 };
1194
1195 static struct pnp_driver nvt_driver = {
1196 .name = NVT_DRIVER_NAME,
1197 .id_table = nvt_ids,
1198 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1199 .probe = nvt_probe,
1200 .remove = nvt_remove,
1201 .suspend = nvt_suspend,
1202 .resume = nvt_resume,
1203 .shutdown = nvt_shutdown,
1204 };
1205
1206 module_param(debug, int, S_IRUGO | S_IWUSR);
1207 MODULE_PARM_DESC(debug, "Enable debugging output");
1208
1209 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1210 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1211
1212 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1213 MODULE_LICENSE("GPL");
1214
1215 module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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