2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
40 #include "nuvoton-cir.h"
42 static const struct nvt_chip nvt_chips
[] = {
43 { "w83667hg", NVT_W83667HG
},
44 { "NCT6775F", NVT_6775F
},
45 { "NCT6776F", NVT_6776F
},
46 { "NCT6779D", NVT_6779D
},
49 static inline bool is_w83667hg(struct nvt_dev
*nvt
)
51 return nvt
->chip_ver
== NVT_W83667HG
;
54 /* write val to config reg */
55 static inline void nvt_cr_write(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
57 outb(reg
, nvt
->cr_efir
);
58 outb(val
, nvt
->cr_efdr
);
61 /* read val from config reg */
62 static inline u8
nvt_cr_read(struct nvt_dev
*nvt
, u8 reg
)
64 outb(reg
, nvt
->cr_efir
);
65 return inb(nvt
->cr_efdr
);
68 /* update config register bit without changing other bits */
69 static inline void nvt_set_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
71 u8 tmp
= nvt_cr_read(nvt
, reg
) | val
;
72 nvt_cr_write(nvt
, tmp
, reg
);
75 /* clear config register bit without changing other bits */
76 static inline void nvt_clear_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
78 u8 tmp
= nvt_cr_read(nvt
, reg
) & ~val
;
79 nvt_cr_write(nvt
, tmp
, reg
);
82 /* enter extended function mode */
83 static inline int nvt_efm_enable(struct nvt_dev
*nvt
)
85 if (!request_muxed_region(nvt
->cr_efir
, 2, NVT_DRIVER_NAME
))
88 /* Enabling Extended Function Mode explicitly requires writing 2x */
89 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
90 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
95 /* exit extended function mode */
96 static inline void nvt_efm_disable(struct nvt_dev
*nvt
)
98 outb(EFER_EFM_DISABLE
, nvt
->cr_efir
);
100 release_region(nvt
->cr_efir
, 2);
104 * When you want to address a specific logical device, write its logical
105 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
106 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
108 static inline void nvt_select_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
110 nvt_cr_write(nvt
, ldev
, CR_LOGICAL_DEV_SEL
);
113 /* select and enable logical device with setting EFM mode*/
114 static inline void nvt_enable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
117 nvt_select_logical_dev(nvt
, ldev
);
118 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
119 nvt_efm_disable(nvt
);
122 /* select and disable logical device with setting EFM mode*/
123 static inline void nvt_disable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
126 nvt_select_logical_dev(nvt
, ldev
);
127 nvt_cr_write(nvt
, LOGICAL_DEV_DISABLE
, CR_LOGICAL_DEV_EN
);
128 nvt_efm_disable(nvt
);
131 /* write val to cir config register */
132 static inline void nvt_cir_reg_write(struct nvt_dev
*nvt
, u8 val
, u8 offset
)
134 outb(val
, nvt
->cir_addr
+ offset
);
137 /* read val from cir config register */
138 static u8
nvt_cir_reg_read(struct nvt_dev
*nvt
, u8 offset
)
142 val
= inb(nvt
->cir_addr
+ offset
);
147 /* write val to cir wake register */
148 static inline void nvt_cir_wake_reg_write(struct nvt_dev
*nvt
,
151 outb(val
, nvt
->cir_wake_addr
+ offset
);
154 /* read val from cir wake config register */
155 static u8
nvt_cir_wake_reg_read(struct nvt_dev
*nvt
, u8 offset
)
159 val
= inb(nvt
->cir_wake_addr
+ offset
);
164 /* dump current cir register contents */
165 static void cir_dump_regs(struct nvt_dev
*nvt
)
168 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
170 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME
);
171 pr_info(" * CR CIR ACTIVE : 0x%x\n",
172 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
173 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
174 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
175 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
176 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
177 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
179 nvt_efm_disable(nvt
);
181 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME
);
182 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRCON
));
183 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRSTS
));
184 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IREN
));
185 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_RXFCONT
));
186 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CP
));
187 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CC
));
188 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCH
));
189 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCL
));
190 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FIFOCON
));
191 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFIFOSTS
));
192 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SRXFIFO
));
193 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_TXFCONT
));
194 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_STXFIFO
));
195 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCH
));
196 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCL
));
197 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFSM
));
200 /* dump current cir wake register contents */
201 static void cir_wake_dump_regs(struct nvt_dev
*nvt
)
206 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
208 pr_info("%s: Dump CIR WAKE logical device registers:\n",
210 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
211 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
212 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
213 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
214 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
215 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
216 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
218 nvt_efm_disable(nvt
);
220 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME
);
221 pr_info(" * IRCON: 0x%x\n",
222 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
));
223 pr_info(" * IRSTS: 0x%x\n",
224 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
));
225 pr_info(" * IREN: 0x%x\n",
226 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
));
227 pr_info(" * FIFO CMP DEEP: 0x%x\n",
228 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_DEEP
));
229 pr_info(" * FIFO CMP TOL: 0x%x\n",
230 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_TOL
));
231 pr_info(" * FIFO COUNT: 0x%x\n",
232 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
));
233 pr_info(" * SLCH: 0x%x\n",
234 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCH
));
235 pr_info(" * SLCL: 0x%x\n",
236 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCL
));
237 pr_info(" * FIFOCON: 0x%x\n",
238 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
));
239 pr_info(" * SRXFSTS: 0x%x\n",
240 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SRXFSTS
));
241 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
242 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SAMPLE_RX_FIFO
));
243 pr_info(" * WR FIFO DATA: 0x%x\n",
244 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_WR_FIFO_DATA
));
245 pr_info(" * RD FIFO ONLY: 0x%x\n",
246 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
247 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
248 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
));
249 pr_info(" * FIFO IGNORE: 0x%x\n",
250 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_IGNORE
));
251 pr_info(" * IRFSM: 0x%x\n",
252 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRFSM
));
254 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
255 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME
, fifo_len
);
256 pr_info("* Contents =");
257 for (i
= 0; i
< fifo_len
; i
++)
259 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
263 static inline const char *nvt_find_chip(struct nvt_dev
*nvt
, int id
)
267 for (i
= 0; i
< ARRAY_SIZE(nvt_chips
); i
++)
268 if ((id
& SIO_ID_MASK
) == nvt_chips
[i
].chip_ver
) {
269 nvt
->chip_ver
= nvt_chips
[i
].chip_ver
;
270 return nvt_chips
[i
].name
;
277 /* detect hardware features */
278 static void nvt_hw_detect(struct nvt_dev
*nvt
)
280 const char *chip_name
;
285 /* Check if we're wired for the alternate EFER setup */
286 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
287 if (nvt
->chip_major
== 0xff) {
288 nvt
->cr_efir
= CR_EFIR2
;
289 nvt
->cr_efdr
= CR_EFDR2
;
291 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
294 nvt
->chip_minor
= nvt_cr_read(nvt
, CR_CHIP_ID_LO
);
296 chip_id
= nvt
->chip_major
<< 8 | nvt
->chip_minor
;
297 chip_name
= nvt_find_chip(nvt
, chip_id
);
299 /* warn, but still let the driver load, if we don't know this chip */
301 dev_warn(&nvt
->pdev
->dev
,
302 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
303 nvt
->chip_major
, nvt
->chip_minor
);
305 dev_info(&nvt
->pdev
->dev
,
306 "found %s or compatible: chip id: 0x%02x 0x%02x",
307 chip_name
, nvt
->chip_major
, nvt
->chip_minor
);
309 nvt_efm_disable(nvt
);
312 static void nvt_cir_ldev_init(struct nvt_dev
*nvt
)
314 u8 val
, psreg
, psmask
, psval
;
316 if (is_w83667hg(nvt
)) {
317 psreg
= CR_MULTIFUNC_PIN_SEL
;
318 psmask
= MULTIFUNC_PIN_SEL_MASK
;
319 psval
= MULTIFUNC_ENABLE_CIR
| MULTIFUNC_ENABLE_CIRWB
;
321 psreg
= CR_OUTPUT_PIN_SEL
;
322 psmask
= OUTPUT_PIN_SEL_MASK
;
323 psval
= OUTPUT_ENABLE_CIR
| OUTPUT_ENABLE_CIRWB
;
326 /* output pin selection: enable CIR, with WB sensor enabled */
327 val
= nvt_cr_read(nvt
, psreg
);
330 nvt_cr_write(nvt
, val
, psreg
);
332 /* Select CIR logical device */
333 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
335 nvt_cr_write(nvt
, nvt
->cir_addr
>> 8, CR_CIR_BASE_ADDR_HI
);
336 nvt_cr_write(nvt
, nvt
->cir_addr
& 0xff, CR_CIR_BASE_ADDR_LO
);
338 nvt_cr_write(nvt
, nvt
->cir_irq
, CR_CIR_IRQ_RSRC
);
340 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
341 nvt
->cir_addr
, nvt
->cir_irq
);
344 static void nvt_cir_wake_ldev_init(struct nvt_dev
*nvt
)
346 /* Select ACPI logical device and anable it */
347 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
348 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
350 /* Enable CIR Wake via PSOUT# (Pin60) */
351 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
353 /* enable pme interrupt of cir wakeup event */
354 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
356 /* Select CIR Wake logical device */
357 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
359 nvt_cr_write(nvt
, nvt
->cir_wake_addr
>> 8, CR_CIR_BASE_ADDR_HI
);
360 nvt_cr_write(nvt
, nvt
->cir_wake_addr
& 0xff, CR_CIR_BASE_ADDR_LO
);
362 nvt_cr_write(nvt
, nvt
->cir_wake_irq
, CR_CIR_IRQ_RSRC
);
364 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
365 nvt
->cir_wake_addr
, nvt
->cir_wake_irq
);
368 /* clear out the hardware's cir rx fifo */
369 static void nvt_clear_cir_fifo(struct nvt_dev
*nvt
)
373 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
374 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
377 /* clear out the hardware's cir wake rx fifo */
378 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
)
382 config
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
);
384 /* clearing wake fifo works in learning mode only */
385 nvt_cir_wake_reg_write(nvt
, config
& ~CIR_WAKE_IRCON_MODE0
,
388 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
);
389 nvt_cir_wake_reg_write(nvt
, val
| CIR_WAKE_FIFOCON_RXFIFOCLR
,
392 nvt_cir_wake_reg_write(nvt
, config
, CIR_WAKE_IRCON
);
395 /* clear out the hardware's cir tx fifo */
396 static void nvt_clear_tx_fifo(struct nvt_dev
*nvt
)
400 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
401 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_TXFIFOCLR
, CIR_FIFOCON
);
404 /* enable RX Trigger Level Reach and Packet End interrupts */
405 static void nvt_set_cir_iren(struct nvt_dev
*nvt
)
409 iren
= CIR_IREN_RTR
| CIR_IREN_PE
;
410 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
413 static void nvt_cir_regs_init(struct nvt_dev
*nvt
)
415 /* set sample limit count (PE interrupt raised when reached) */
416 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_SLCH
);
417 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_SLCL
);
419 /* set fifo irq trigger levels */
420 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV
|
421 CIR_FIFOCON_RX_TRIGGER_LEV
, CIR_FIFOCON
);
424 * Enable TX and RX, specify carrier on = low, off = high, and set
425 * sample period (currently 50us)
427 nvt_cir_reg_write(nvt
,
428 CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
429 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
432 /* clear hardware rx and tx fifos */
433 nvt_clear_cir_fifo(nvt
);
434 nvt_clear_tx_fifo(nvt
);
436 /* clear any and all stray interrupts */
437 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
439 /* and finally, enable interrupts */
440 nvt_set_cir_iren(nvt
);
442 /* enable the CIR logical device */
443 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
446 static void nvt_cir_wake_regs_init(struct nvt_dev
*nvt
)
448 /* set number of bytes needed for wake from s3 (default 65) */
449 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_FIFO_CMP_BYTES
,
450 CIR_WAKE_FIFO_CMP_DEEP
);
452 /* set tolerance/variance allowed per byte during wake compare */
453 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_CMP_TOLERANCE
,
454 CIR_WAKE_FIFO_CMP_TOL
);
456 /* set sample limit count (PE interrupt raised when reached) */
457 nvt_cir_wake_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_WAKE_SLCH
);
458 nvt_cir_wake_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_WAKE_SLCL
);
460 /* set cir wake fifo rx trigger level (currently 67) */
461 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV
,
465 * Enable TX and RX, specific carrier on = low, off = high, and set
466 * sample period (currently 50us)
468 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
469 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
470 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
473 /* clear cir wake rx fifo */
474 nvt_clear_cir_wake_fifo(nvt
);
476 /* clear any and all stray interrupts */
477 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
479 /* enable the CIR WAKE logical device */
480 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
483 static void nvt_enable_wake(struct nvt_dev
*nvt
)
487 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
488 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
489 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
491 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
492 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
494 nvt_efm_disable(nvt
);
496 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
497 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
498 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
500 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
501 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
504 #if 0 /* Currently unused */
505 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
506 static u32
nvt_rx_carrier_detect(struct nvt_dev
*nvt
)
508 u32 count
, carrier
, duration
= 0;
511 count
= nvt_cir_reg_read(nvt
, CIR_FCCL
) |
512 nvt_cir_reg_read(nvt
, CIR_FCCH
) << 8;
514 for (i
= 0; i
< nvt
->pkts
; i
++) {
515 if (nvt
->buf
[i
] & BUF_PULSE_BIT
)
516 duration
+= nvt
->buf
[i
] & BUF_LEN_MASK
;
519 duration
*= SAMPLE_PERIOD
;
521 if (!count
|| !duration
) {
522 dev_notice(&nvt
->pdev
->dev
,
523 "Unable to determine carrier! (c:%u, d:%u)",
528 carrier
= MS_TO_NS(count
) / duration
;
530 if ((carrier
> MAX_CARRIER
) || (carrier
< MIN_CARRIER
))
531 nvt_dbg("WTF? Carrier frequency out of range!");
533 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
534 carrier
, count
, duration
);
540 * set carrier frequency
542 * set carrier on 2 registers: CP & CC
543 * always set CP as 0x81
544 * set CC by SPEC, CC = 3MHz/carrier - 1
546 static int nvt_set_tx_carrier(struct rc_dev
*dev
, u32 carrier
)
548 struct nvt_dev
*nvt
= dev
->priv
;
554 nvt_cir_reg_write(nvt
, 1, CIR_CP
);
555 val
= 3000000 / (carrier
) - 1;
556 nvt_cir_reg_write(nvt
, val
& 0xff, CIR_CC
);
558 nvt_dbg("cp: 0x%x cc: 0x%x\n",
559 nvt_cir_reg_read(nvt
, CIR_CP
), nvt_cir_reg_read(nvt
, CIR_CC
));
567 * 1) clean TX fifo first (handled by AP)
568 * 2) copy data from user space
569 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
570 * 4) send 9 packets to TX FIFO to open TTR
571 * in interrupt_handler:
572 * 5) send all data out
573 * go back to write():
574 * 6) disable TX interrupts, re-enable RX interupts
576 * The key problem of this function is user space data may larger than
577 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
578 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
579 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
580 * set TXFCONT as 0xff, until buf_count less than 0xff.
582 static int nvt_tx_ir(struct rc_dev
*dev
, unsigned *txbuf
, unsigned n
)
584 struct nvt_dev
*nvt
= dev
->priv
;
590 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
592 ret
= min((unsigned)(TX_BUF_LEN
/ sizeof(unsigned)), n
);
593 nvt
->tx
.buf_count
= (ret
* sizeof(unsigned));
595 memcpy(nvt
->tx
.buf
, txbuf
, nvt
->tx
.buf_count
);
597 nvt
->tx
.cur_buf_num
= 0;
599 /* save currently enabled interrupts */
600 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
602 /* now disable all interrupts, save TFU & TTR */
603 nvt_cir_reg_write(nvt
, CIR_IREN_TFU
| CIR_IREN_TTR
, CIR_IREN
);
605 nvt
->tx
.tx_state
= ST_TX_REPLY
;
607 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV_8
|
608 CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
610 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
611 for (i
= 0; i
< 9; i
++)
612 nvt_cir_reg_write(nvt
, 0x01, CIR_STXFIFO
);
614 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
616 wait_event(nvt
->tx
.queue
, nvt
->tx
.tx_state
== ST_TX_REQUEST
);
618 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
619 nvt
->tx
.tx_state
= ST_TX_NONE
;
620 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
622 /* restore enabled interrupts to prior state */
623 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
628 /* dump contents of the last rx buffer we got from the hw rx fifo */
629 static void nvt_dump_rx_buf(struct nvt_dev
*nvt
)
633 printk(KERN_DEBUG
"%s (len %d): ", __func__
, nvt
->pkts
);
634 for (i
= 0; (i
< nvt
->pkts
) && (i
< RX_BUF_LEN
); i
++)
635 printk(KERN_CONT
"0x%02x ", nvt
->buf
[i
]);
636 printk(KERN_CONT
"\n");
640 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
641 * trigger decode when appropriate.
643 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
644 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
645 * (default 50us) intervals for that pulse/space. A discrete signal is
646 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
647 * to signal more IR coming (repeats) or end of IR, respectively. We store
648 * sample data in the raw event kfifo until we see 0x7<something> (except f)
649 * or 0x80, at which time, we trigger a decode operation.
651 static void nvt_process_rx_ir_data(struct nvt_dev
*nvt
)
653 DEFINE_IR_RAW_EVENT(rawir
);
657 nvt_dbg_verbose("%s firing", __func__
);
660 nvt_dump_rx_buf(nvt
);
662 nvt_dbg_verbose("Processing buffer of len %d", nvt
->pkts
);
664 init_ir_raw_event(&rawir
);
666 for (i
= 0; i
< nvt
->pkts
; i
++) {
667 sample
= nvt
->buf
[i
];
669 rawir
.pulse
= ((sample
& BUF_PULSE_BIT
) != 0);
670 rawir
.duration
= US_TO_NS((sample
& BUF_LEN_MASK
)
673 nvt_dbg("Storing %s with duration %d",
674 rawir
.pulse
? "pulse" : "space", rawir
.duration
);
676 ir_raw_event_store_with_filter(nvt
->rdev
, &rawir
);
679 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
680 * indicates end of IR signal, but new data incoming. In both
681 * cases, it means we're ready to call ir_raw_event_handle
683 if ((sample
== BUF_PULSE_BIT
) && (i
+ 1 < nvt
->pkts
)) {
684 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
685 ir_raw_event_handle(nvt
->rdev
);
691 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
692 ir_raw_event_handle(nvt
->rdev
);
694 nvt_dbg_verbose("%s done", __func__
);
697 static void nvt_handle_rx_fifo_overrun(struct nvt_dev
*nvt
)
699 dev_warn(&nvt
->pdev
->dev
, "RX FIFO overrun detected, flushing data!");
702 nvt_clear_cir_fifo(nvt
);
703 ir_raw_event_reset(nvt
->rdev
);
706 /* copy data from hardware rx fifo into driver buffer */
707 static void nvt_get_rx_ir_data(struct nvt_dev
*nvt
)
712 bool overrun
= false;
715 /* Get count of how many bytes to read from RX FIFO */
716 fifocount
= nvt_cir_reg_read(nvt
, CIR_RXFCONT
);
717 /* if we get 0xff, probably means the logical dev is disabled */
718 if (fifocount
== 0xff)
720 /* watch out for a fifo overrun condition */
721 else if (fifocount
> RX_BUF_LEN
) {
723 fifocount
= RX_BUF_LEN
;
726 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount
);
728 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
732 /* This should never happen, but lets check anyway... */
733 if (b_idx
+ fifocount
> RX_BUF_LEN
) {
734 nvt_process_rx_ir_data(nvt
);
738 /* Read fifocount bytes from CIR Sample RX FIFO register */
739 for (i
= 0; i
< fifocount
; i
++) {
740 val
= nvt_cir_reg_read(nvt
, CIR_SRXFIFO
);
741 nvt
->buf
[b_idx
+ i
] = val
;
744 nvt
->pkts
+= fifocount
;
745 nvt_dbg("%s: pkts now %d", __func__
, nvt
->pkts
);
747 nvt_process_rx_ir_data(nvt
);
750 nvt_handle_rx_fifo_overrun(nvt
);
752 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
755 static void nvt_cir_log_irqs(u8 status
, u8 iren
)
757 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
759 status
& CIR_IRSTS_RDR
? " RDR" : "",
760 status
& CIR_IRSTS_RTR
? " RTR" : "",
761 status
& CIR_IRSTS_PE
? " PE" : "",
762 status
& CIR_IRSTS_RFO
? " RFO" : "",
763 status
& CIR_IRSTS_TE
? " TE" : "",
764 status
& CIR_IRSTS_TTR
? " TTR" : "",
765 status
& CIR_IRSTS_TFU
? " TFU" : "",
766 status
& CIR_IRSTS_GH
? " GH" : "",
767 status
& ~(CIR_IRSTS_RDR
| CIR_IRSTS_RTR
| CIR_IRSTS_PE
|
768 CIR_IRSTS_RFO
| CIR_IRSTS_TE
| CIR_IRSTS_TTR
|
769 CIR_IRSTS_TFU
| CIR_IRSTS_GH
) ? " ?" : "");
772 static bool nvt_cir_tx_inactive(struct nvt_dev
*nvt
)
777 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
778 tx_state
= nvt
->tx
.tx_state
;
779 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
781 return tx_state
== ST_TX_NONE
;
784 /* interrupt service routine for incoming and outgoing CIR data */
785 static irqreturn_t
nvt_cir_isr(int irq
, void *data
)
787 struct nvt_dev
*nvt
= data
;
788 u8 status
, iren
, cur_state
;
791 nvt_dbg_verbose("%s firing", __func__
);
794 * Get IR Status register contents. Write 1 to ack/clear
796 * bit: reg name - description
797 * 7: CIR_IRSTS_RDR - RX Data Ready
798 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
799 * 5: CIR_IRSTS_PE - Packet End
800 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
801 * 3: CIR_IRSTS_TE - TX FIFO Empty
802 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
803 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
804 * 0: CIR_IRSTS_GH - Min Length Detected
806 status
= nvt_cir_reg_read(nvt
, CIR_IRSTS
);
808 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__
);
809 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
813 /* ack/clear all irq flags we've got */
814 nvt_cir_reg_write(nvt
, status
, CIR_IRSTS
);
815 nvt_cir_reg_write(nvt
, 0, CIR_IRSTS
);
817 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
818 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
820 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__
);
824 nvt_cir_log_irqs(status
, iren
);
826 if (status
& CIR_IRSTS_RTR
) {
827 /* FIXME: add code for study/learn mode */
828 /* We only do rx if not tx'ing */
829 if (nvt_cir_tx_inactive(nvt
))
830 nvt_get_rx_ir_data(nvt
);
833 if (status
& CIR_IRSTS_PE
) {
834 if (nvt_cir_tx_inactive(nvt
))
835 nvt_get_rx_ir_data(nvt
);
837 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
839 cur_state
= nvt
->study_state
;
841 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
843 if (cur_state
== ST_STUDY_NONE
)
844 nvt_clear_cir_fifo(nvt
);
847 if (status
& CIR_IRSTS_TE
)
848 nvt_clear_tx_fifo(nvt
);
850 if (status
& CIR_IRSTS_TTR
) {
851 unsigned int pos
, count
;
854 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
856 pos
= nvt
->tx
.cur_buf_num
;
857 count
= nvt
->tx
.buf_count
;
859 /* Write data into the hardware tx fifo while pos < count */
861 nvt_cir_reg_write(nvt
, nvt
->tx
.buf
[pos
], CIR_STXFIFO
);
862 nvt
->tx
.cur_buf_num
++;
863 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
865 tmp
= nvt_cir_reg_read(nvt
, CIR_IREN
);
866 nvt_cir_reg_write(nvt
, tmp
& ~CIR_IREN_TTR
, CIR_IREN
);
869 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
873 if (status
& CIR_IRSTS_TFU
) {
874 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
875 if (nvt
->tx
.tx_state
== ST_TX_REPLY
) {
876 nvt
->tx
.tx_state
= ST_TX_REQUEST
;
877 wake_up(&nvt
->tx
.queue
);
879 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
882 nvt_dbg_verbose("%s done", __func__
);
886 /* Interrupt service routine for CIR Wake */
887 static irqreturn_t
nvt_cir_wake_isr(int irq
, void *data
)
889 u8 status
, iren
, val
;
890 struct nvt_dev
*nvt
= data
;
893 nvt_dbg_wake("%s firing", __func__
);
895 status
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
);
899 if (status
& CIR_WAKE_IRSTS_IR_PENDING
)
900 nvt_clear_cir_wake_fifo(nvt
);
902 nvt_cir_wake_reg_write(nvt
, status
, CIR_WAKE_IRSTS
);
903 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IRSTS
);
905 /* Interrupt may be shared with CIR, bail if Wake not enabled */
906 iren
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
);
908 nvt_dbg_wake("%s exiting, wake not enabled", __func__
);
912 if ((status
& CIR_WAKE_IRSTS_PE
) &&
913 (nvt
->wake_state
== ST_WAKE_START
)) {
914 while (nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
)) {
915 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
916 nvt_dbg("setting wake up key: 0x%x", val
);
919 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
920 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
921 nvt
->wake_state
= ST_WAKE_FINISH
;
922 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
925 nvt_dbg_wake("%s done", __func__
);
929 static void nvt_enable_cir(struct nvt_dev
*nvt
)
931 /* set function enable flags */
932 nvt_cir_reg_write(nvt
, CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
933 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
936 /* enable the CIR logical device */
937 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
939 /* clear all pending interrupts */
940 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
942 /* enable interrupts */
943 nvt_set_cir_iren(nvt
);
946 static void nvt_disable_cir(struct nvt_dev
*nvt
)
948 /* disable CIR interrupts */
949 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
951 /* clear any and all pending interrupts */
952 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
954 /* clear all function enable flags */
955 nvt_cir_reg_write(nvt
, 0, CIR_IRCON
);
957 /* clear hardware rx and tx fifos */
958 nvt_clear_cir_fifo(nvt
);
959 nvt_clear_tx_fifo(nvt
);
961 /* disable the CIR logical device */
962 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
965 static int nvt_open(struct rc_dev
*dev
)
967 struct nvt_dev
*nvt
= dev
->priv
;
970 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
972 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
977 static void nvt_close(struct rc_dev
*dev
)
979 struct nvt_dev
*nvt
= dev
->priv
;
982 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
983 nvt_disable_cir(nvt
);
984 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
987 /* Allocate memory, probe hardware, and initialize everything */
988 static int nvt_probe(struct pnp_dev
*pdev
, const struct pnp_device_id
*dev_id
)
994 nvt
= devm_kzalloc(&pdev
->dev
, sizeof(struct nvt_dev
), GFP_KERNEL
);
998 /* input device for IR remote (and tx) */
999 rdev
= rc_allocate_device();
1001 goto exit_free_dev_rdev
;
1004 /* activate pnp device */
1005 if (pnp_activate_dev(pdev
) < 0) {
1006 dev_err(&pdev
->dev
, "Could not activate PNP device!\n");
1007 goto exit_free_dev_rdev
;
1010 /* validate pnp resources */
1011 if (!pnp_port_valid(pdev
, 0) ||
1012 pnp_port_len(pdev
, 0) < CIR_IOREG_LENGTH
) {
1013 dev_err(&pdev
->dev
, "IR PNP Port not valid!\n");
1014 goto exit_free_dev_rdev
;
1017 if (!pnp_irq_valid(pdev
, 0)) {
1018 dev_err(&pdev
->dev
, "PNP IRQ not valid!\n");
1019 goto exit_free_dev_rdev
;
1022 if (!pnp_port_valid(pdev
, 1) ||
1023 pnp_port_len(pdev
, 1) < CIR_IOREG_LENGTH
) {
1024 dev_err(&pdev
->dev
, "Wake PNP Port not valid!\n");
1025 goto exit_free_dev_rdev
;
1028 nvt
->cir_addr
= pnp_port_start(pdev
, 0);
1029 nvt
->cir_irq
= pnp_irq(pdev
, 0);
1031 nvt
->cir_wake_addr
= pnp_port_start(pdev
, 1);
1032 /* irq is always shared between cir and cir wake */
1033 nvt
->cir_wake_irq
= nvt
->cir_irq
;
1035 nvt
->cr_efir
= CR_EFIR
;
1036 nvt
->cr_efdr
= CR_EFDR
;
1038 spin_lock_init(&nvt
->nvt_lock
);
1039 spin_lock_init(&nvt
->tx
.lock
);
1041 pnp_set_drvdata(pdev
, nvt
);
1044 init_waitqueue_head(&nvt
->tx
.queue
);
1048 /* Initialize CIR & CIR Wake Logical Devices */
1049 nvt_efm_enable(nvt
);
1050 nvt_cir_ldev_init(nvt
);
1051 nvt_cir_wake_ldev_init(nvt
);
1052 nvt_efm_disable(nvt
);
1055 * Initialize CIR & CIR Wake Config Registers
1056 * and enable logical devices
1058 nvt_cir_regs_init(nvt
);
1059 nvt_cir_wake_regs_init(nvt
);
1061 /* Set up the rc device */
1063 rdev
->driver_type
= RC_DRIVER_IR_RAW
;
1064 rdev
->allowed_protocols
= RC_BIT_ALL
;
1065 rdev
->open
= nvt_open
;
1066 rdev
->close
= nvt_close
;
1067 rdev
->tx_ir
= nvt_tx_ir
;
1068 rdev
->s_tx_carrier
= nvt_set_tx_carrier
;
1069 rdev
->input_name
= "Nuvoton w836x7hg Infrared Remote Transceiver";
1070 rdev
->input_phys
= "nuvoton/cir0";
1071 rdev
->input_id
.bustype
= BUS_HOST
;
1072 rdev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND2
;
1073 rdev
->input_id
.product
= nvt
->chip_major
;
1074 rdev
->input_id
.version
= nvt
->chip_minor
;
1075 rdev
->dev
.parent
= &pdev
->dev
;
1076 rdev
->driver_name
= NVT_DRIVER_NAME
;
1077 rdev
->map_name
= RC_MAP_RC6_MCE
;
1078 rdev
->timeout
= MS_TO_NS(100);
1079 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1080 rdev
->rx_resolution
= US_TO_NS(CIR_SAMPLE_PERIOD
);
1082 rdev
->min_timeout
= XYZ
;
1083 rdev
->max_timeout
= XYZ
;
1085 rdev
->tx_resolution
= XYZ
;
1089 ret
= rc_register_device(rdev
);
1091 goto exit_free_dev_rdev
;
1094 /* now claim resources */
1095 if (!devm_request_region(&pdev
->dev
, nvt
->cir_addr
,
1096 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
))
1097 goto exit_unregister_device
;
1099 if (devm_request_irq(&pdev
->dev
, nvt
->cir_irq
, nvt_cir_isr
,
1100 IRQF_SHARED
, NVT_DRIVER_NAME
, (void *)nvt
))
1101 goto exit_unregister_device
;
1103 if (!devm_request_region(&pdev
->dev
, nvt
->cir_wake_addr
,
1104 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
"-wake"))
1105 goto exit_unregister_device
;
1107 if (devm_request_irq(&pdev
->dev
, nvt
->cir_wake_irq
,
1108 nvt_cir_wake_isr
, IRQF_SHARED
,
1109 NVT_DRIVER_NAME
"-wake", (void *)nvt
))
1110 goto exit_unregister_device
;
1112 device_init_wakeup(&pdev
->dev
, true);
1114 dev_notice(&pdev
->dev
, "driver has been successfully loaded\n");
1117 cir_wake_dump_regs(nvt
);
1122 exit_unregister_device
:
1123 rc_unregister_device(rdev
);
1126 rc_free_device(rdev
);
1131 static void nvt_remove(struct pnp_dev
*pdev
)
1133 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1134 unsigned long flags
;
1136 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1138 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1139 nvt_disable_cir(nvt
);
1140 /* enable CIR Wake (for IR power-on) */
1141 nvt_enable_wake(nvt
);
1142 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1144 rc_unregister_device(nvt
->rdev
);
1147 static int nvt_suspend(struct pnp_dev
*pdev
, pm_message_t state
)
1149 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1150 unsigned long flags
;
1152 nvt_dbg("%s called", __func__
);
1154 /* zero out misc state tracking */
1155 spin_lock_irqsave(&nvt
->nvt_lock
, flags
);
1156 nvt
->study_state
= ST_STUDY_NONE
;
1157 nvt
->wake_state
= ST_WAKE_NONE
;
1158 spin_unlock_irqrestore(&nvt
->nvt_lock
, flags
);
1160 spin_lock_irqsave(&nvt
->tx
.lock
, flags
);
1161 nvt
->tx
.tx_state
= ST_TX_NONE
;
1162 spin_unlock_irqrestore(&nvt
->tx
.lock
, flags
);
1164 /* disable all CIR interrupts */
1165 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
1167 /* disable cir logical dev */
1168 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
1170 /* make sure wake is enabled */
1171 nvt_enable_wake(nvt
);
1176 static int nvt_resume(struct pnp_dev
*pdev
)
1178 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1180 nvt_dbg("%s called", __func__
);
1182 nvt_cir_regs_init(nvt
);
1183 nvt_cir_wake_regs_init(nvt
);
1188 static void nvt_shutdown(struct pnp_dev
*pdev
)
1190 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1191 nvt_enable_wake(nvt
);
1194 static const struct pnp_device_id nvt_ids
[] = {
1195 { "WEC0530", 0 }, /* CIR */
1196 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1200 static struct pnp_driver nvt_driver
= {
1201 .name
= NVT_DRIVER_NAME
,
1202 .id_table
= nvt_ids
,
1203 .flags
= PNP_DRIVER_RES_DO_NOT_CHANGE
,
1205 .remove
= nvt_remove
,
1206 .suspend
= nvt_suspend
,
1207 .resume
= nvt_resume
,
1208 .shutdown
= nvt_shutdown
,
1211 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
1212 MODULE_PARM_DESC(debug
, "Enable debugging output");
1214 MODULE_DEVICE_TABLE(pnp
, nvt_ids
);
1215 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1217 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1218 MODULE_LICENSE("GPL");
1220 module_pnp_driver(nvt_driver
);