drivers/media/video/marvell-ccic/mcam-core.h

   1 /*
   2  * Marvell camera core structures.
   3  *
   4  * Copyright 2011 Jonathan Corbet corbet@lwn.net
   5  */
   6
   7 /*
   8  * Tracking of streaming I/O buffers.
   9  * FIXME doesn't belong in this file
  10  */
  11 struct mcam_sio_buffer {
  12         struct list_head list;
  13         struct v4l2_buffer v4lbuf;
  14         char *buffer;   /* Where it lives in kernel space */
  15         int mapcount;
  16         struct mcam_camera *cam;
  17 };
  18
  19 enum mcam_state {
  20         S_NOTREADY,     /* Not yet initialized */
  21         S_IDLE,         /* Just hanging around */
  22         S_FLAKED,       /* Some sort of problem */
  23         S_SINGLEREAD,   /* In read() */
  24         S_SPECREAD,     /* Speculative read (for future read()) */
  25         S_STREAMING     /* Streaming data */
  26 };
  27 #define MAX_DMA_BUFS 3
  28
  29 /*
  30  * A description of one of our devices.
  31  * Locking: controlled by s_mutex.  Certain fields, however, require
  32  *          the dev_lock spinlock; they are marked as such by comments.
  33  *          dev_lock is also required for access to device registers.
  34  */
  35 struct mcam_camera {
  36         /*
  37          * These fields should be set by the platform code prior to
  38          * calling mcam_register().
  39          */
  40         struct i2c_adapter i2c_adapter;
  41         unsigned char __iomem *regs;
  42         spinlock_t dev_lock;
  43         struct device *dev; /* For messages, dma alloc */
  44         unsigned int chip_id;
  45
  46         /*
  47          * Callbacks from the core to the platform code.
  48          */
  49         void (*plat_power_up) (struct mcam_camera *cam);
  50         void (*plat_power_down) (struct mcam_camera *cam);
  51
  52         /*
  53          * Everything below here is private to the mcam core and
  54          * should not be touched by the platform code.
  55          */
  56         struct v4l2_device v4l2_dev;
  57         enum mcam_state state;
  58         unsigned long flags;            /* Buffer status, mainly (dev_lock) */
  59         int users;                      /* How many open FDs */
  60         struct file *owner;             /* Who has data access (v4l2) */
  61
  62         /*
  63          * Subsystem structures.
  64          */
  65         struct video_device vdev;
  66         struct v4l2_subdev *sensor;
  67         unsigned short sensor_addr;
  68
  69         struct list_head dev_list;      /* link to other devices */
  70
  71         /* DMA buffers */
  72         unsigned int nbufs;             /* How many are alloc'd */
  73         int next_buf;                   /* Next to consume (dev_lock) */
  74         unsigned int dma_buf_size;      /* allocated size */
  75         void *dma_bufs[MAX_DMA_BUFS];   /* Internal buffer addresses */
  76         dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
  77         unsigned int specframes;        /* Unconsumed spec frames (dev_lock) */
  78         unsigned int sequence;          /* Frame sequence number */
  79         unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual buffers */
  80
  81         /* Streaming buffers */
  82         unsigned int n_sbufs;           /* How many we have */
  83         struct mcam_sio_buffer *sb_bufs; /* The array of housekeeping structs */
  84         struct list_head sb_avail;      /* Available for data (we own) (dev_lock) */
  85         struct list_head sb_full;       /* With data (user space owns) (dev_lock) */
  86         struct tasklet_struct s_tasklet;
  87
  88         /* Current operating parameters */
  89         u32 sensor_type;                /* Currently ov7670 only */
  90         struct v4l2_pix_format pix_format;
  91         enum v4l2_mbus_pixelcode mbus_code;
  92
  93         /* Locks */
  94         struct mutex s_mutex; /* Access to this structure */
  95
  96         /* Misc */
  97         wait_queue_head_t iowait;       /* Waiting on frame data */
  98 };
  99
 100
 101 /*
 102  * Register I/O functions.  These are here because the platform code
 103  * may legitimately need to mess with the register space.
 104  */
 105 /*
 106  * Device register I/O
 107  */
 108 static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
 109                 unsigned int val)
 110 {
 111         iowrite32(val, cam->regs + reg);
 112 }
 113
 114 static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
 115                 unsigned int reg)
 116 {
 117         return ioread32(cam->regs + reg);
 118 }
 119
 120
 121 static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
 122                 unsigned int val, unsigned int mask)
 123 {
 124         unsigned int v = mcam_reg_read(cam, reg);
 125
 126         v = (v & ~mask) | (val & mask);
 127         mcam_reg_write(cam, reg, v);
 128 }
 129
 130 static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
 131                 unsigned int reg, unsigned int val)
 132 {
 133         mcam_reg_write_mask(cam, reg, 0, val);
 134 }
 135
 136 static inline void mcam_reg_set_bit(struct mcam_camera *cam,
 137                 unsigned int reg, unsigned int val)
 138 {
 139         mcam_reg_write_mask(cam, reg, val, val);
 140 }
 141
 142 /*
 143  * Functions for use by platform code.
 144  */
 145 int mccic_register(struct mcam_camera *cam);
 146 int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
 147 void mccic_shutdown(struct mcam_camera *cam);
 148 #ifdef CONFIG_PM
 149 void mccic_suspend(struct mcam_camera *cam);
 150 int mccic_resume(struct mcam_camera *cam);
 151 #endif
 152
 153 /*
 154  * Register definitions for the m88alp01 camera interface.  Offsets in bytes
 155  * as given in the spec.
 156  */
 157 #define REG_Y0BAR       0x00
 158 #define REG_Y1BAR       0x04
 159 #define REG_Y2BAR       0x08
 160 /* ... */
 161
 162 #define REG_IMGPITCH    0x24    /* Image pitch register */
 163 #define   IMGP_YP_SHFT    2             /* Y pitch params */
 164 #define   IMGP_YP_MASK    0x00003ffc    /* Y pitch field */
 165 #define   IMGP_UVP_SHFT   18            /* UV pitch (planar) */
 166 #define   IMGP_UVP_MASK   0x3ffc0000
 167 #define REG_IRQSTATRAW  0x28    /* RAW IRQ Status */
 168 #define   IRQ_EOF0        0x00000001    /* End of frame 0 */
 169 #define   IRQ_EOF1        0x00000002    /* End of frame 1 */
 170 #define   IRQ_EOF2        0x00000004    /* End of frame 2 */
 171 #define   IRQ_SOF0        0x00000008    /* Start of frame 0 */
 172 #define   IRQ_SOF1        0x00000010    /* Start of frame 1 */
 173 #define   IRQ_SOF2        0x00000020    /* Start of frame 2 */
 174 #define   IRQ_OVERFLOW    0x00000040    /* FIFO overflow */
 175 #define   IRQ_TWSIW       0x00010000    /* TWSI (smbus) write */
 176 #define   IRQ_TWSIR       0x00020000    /* TWSI read */
 177 #define   IRQ_TWSIE       0x00040000    /* TWSI error */
 178 #define   TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
 179 #define   FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
 180 #define   ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
 181 #define REG_IRQMASK     0x2c    /* IRQ mask - same bits as IRQSTAT */
 182 #define REG_IRQSTAT     0x30    /* IRQ status / clear */
 183
 184 #define REG_IMGSIZE     0x34    /* Image size */
 185 #define  IMGSZ_V_MASK     0x1fff0000
 186 #define  IMGSZ_V_SHIFT    16
 187 #define  IMGSZ_H_MASK     0x00003fff
 188 #define REG_IMGOFFSET   0x38    /* IMage offset */
 189
 190 #define REG_CTRL0       0x3c    /* Control 0 */
 191 #define   C0_ENABLE       0x00000001    /* Makes the whole thing go */
 192
 193 /* Mask for all the format bits */
 194 #define   C0_DF_MASK      0x00fffffc    /* Bits 2-23 */
 195
 196 /* RGB ordering */
 197 #define   C0_RGB4_RGBX    0x00000000
 198 #define   C0_RGB4_XRGB    0x00000004
 199 #define   C0_RGB4_BGRX    0x00000008
 200 #define   C0_RGB4_XBGR    0x0000000c
 201 #define   C0_RGB5_RGGB    0x00000000
 202 #define   C0_RGB5_GRBG    0x00000004
 203 #define   C0_RGB5_GBRG    0x00000008
 204 #define   C0_RGB5_BGGR    0x0000000c
 205
 206 /* Spec has two fields for DIN and DOUT, but they must match, so
 207    combine them here. */
 208 #define   C0_DF_YUV       0x00000000    /* Data is YUV      */
 209 #define   C0_DF_RGB       0x000000a0    /* ... RGB                  */
 210 #define   C0_DF_BAYER     0x00000140    /* ... Bayer                */
 211 /* 8-8-8 must be missing from the below - ask */
 212 #define   C0_RGBF_565     0x00000000
 213 #define   C0_RGBF_444     0x00000800
 214 #define   C0_RGB_BGR      0x00001000    /* Blue comes first */
 215 #define   C0_YUV_PLANAR   0x00000000    /* YUV 422 planar format */
 216 #define   C0_YUV_PACKED   0x00008000    /* YUV 422 packed       */
 217 #define   C0_YUV_420PL    0x0000a000    /* YUV 420 planar       */
 218 /* Think that 420 packed must be 111 - ask */
 219 #define   C0_YUVE_YUYV    0x00000000    /* Y1CbY0Cr             */
 220 #define   C0_YUVE_YVYU    0x00010000    /* Y1CrY0Cb             */
 221 #define   C0_YUVE_VYUY    0x00020000    /* CrY1CbY0             */
 222 #define   C0_YUVE_UYVY    0x00030000    /* CbY1CrY0             */
 223 #define   C0_YUVE_XYUV    0x00000000    /* 420: .YUV            */
 224 #define   C0_YUVE_XYVU    0x00010000    /* 420: .YVU            */
 225 #define   C0_YUVE_XUVY    0x00020000    /* 420: .UVY            */
 226 #define   C0_YUVE_XVUY    0x00030000    /* 420: .VUY            */
 227 /* Bayer bits 18,19 if needed */
 228 #define   C0_HPOL_LOW     0x01000000    /* HSYNC polarity active low */
 229 #define   C0_VPOL_LOW     0x02000000    /* VSYNC polarity active low */
 230 #define   C0_VCLK_LOW     0x04000000    /* VCLK on falling edge */
 231 #define   C0_DOWNSCALE    0x08000000    /* Enable downscaler */
 232 #define   C0_SIFM_MASK    0xc0000000    /* SIF mode bits */
 233 #define   C0_SIF_HVSYNC   0x00000000    /* Use H/VSYNC */
 234 #define   CO_SOF_NOSYNC   0x40000000    /* Use inband active signaling */
 235
 236
 237 #define REG_CTRL1       0x40    /* Control 1 */
 238 #define   C1_444ALPHA     0x00f00000    /* Alpha field in RGB444 */
 239 #define   C1_ALPHA_SHFT   20
 240 #define   C1_DMAB32       0x00000000    /* 32-byte DMA burst */
 241 #define   C1_DMAB16       0x02000000    /* 16-byte DMA burst */
 242 #define   C1_DMAB64       0x04000000    /* 64-byte DMA burst */
 243 #define   C1_DMAB_MASK    0x06000000
 244 #define   C1_TWOBUFS      0x08000000    /* Use only two DMA buffers */
 245 #define   C1_PWRDWN       0x10000000    /* Power down */
 246
 247 #define REG_CLKCTRL     0x88    /* Clock control */
 248 #define   CLK_DIV_MASK    0x0000ffff    /* Upper bits RW "reserved" */
 249
 250 #define REG_GPR         0xb4    /* General purpose register.  This
 251                                    controls inputs to the power and reset
 252                                    pins on the OV7670 used with OLPC;
 253                                    other deployments could differ.  */
 254 #define   GPR_C1EN        0x00000020    /* Pad 1 (power down) enable */
 255 #define   GPR_C0EN        0x00000010    /* Pad 0 (reset) enable */
 256 #define   GPR_C1          0x00000002    /* Control 1 value */
 257 /*
 258  * Control 0 is wired to reset on OLPC machines.  For ov7x sensors,
 259  * it is active low, for 0v6x, instead, it's active high.  What
 260  * fun.
 261  */
 262 #define   GPR_C0          0x00000001    /* Control 0 value */
 263
 264 #define REG_TWSIC0      0xb8    /* TWSI (smbus) control 0 */
 265 #define   TWSIC0_EN       0x00000001    /* TWSI enable */
 266 #define   TWSIC0_MODE     0x00000002    /* 1 = 16-bit, 0 = 8-bit */
 267 #define   TWSIC0_SID      0x000003fc    /* Slave ID */
 268 #define   TWSIC0_SID_SHIFT 2
 269 #define   TWSIC0_CLKDIV   0x0007fc00    /* Clock divider */
 270 #define   TWSIC0_MASKACK  0x00400000    /* Mask ack from sensor */
 271 #define   TWSIC0_OVMAGIC  0x00800000    /* Make it work on OV sensors */
 272
 273 #define REG_TWSIC1      0xbc    /* TWSI control 1 */
 274 #define   TWSIC1_DATA     0x0000ffff    /* Data to/from camchip */
 275 #define   TWSIC1_ADDR     0x00ff0000    /* Address (register) */
 276 #define   TWSIC1_ADDR_SHIFT 16
 277 #define   TWSIC1_READ     0x01000000    /* Set for read op */
 278 #define   TWSIC1_WSTAT    0x02000000    /* Write status */
 279 #define   TWSIC1_RVALID   0x04000000    /* Read data valid */
 280 #define   TWSIC1_ERROR    0x08000000    /* Something screwed up */
 281
 282
 283 #define REG_UBAR        0xc4    /* Upper base address register */
 284
 285 /*
 286  * Here's the weird global control registers which are said to live
 287  * way up here.
 288  */
 289 #define REG_GL_CSR     0x3004  /* Control/status register */
 290 #define   GCSR_SRS       0x00000001     /* SW Reset set */
 291 #define   GCSR_SRC       0x00000002     /* SW Reset clear */
 292 #define   GCSR_MRS       0x00000004     /* Master reset set */
 293 #define   GCSR_MRC       0x00000008     /* HW Reset clear */
 294 #define   GCSR_CCIC_EN   0x00004000    /* CCIC Clock enable */
 295 #define REG_GL_IMASK   0x300c  /* Interrupt mask register */
 296 #define   GIMSK_CCIC_EN          0x00000004    /* CCIC Interrupt enable */
 297
 298 #define REG_GL_FCR      0x3038  /* GPIO functional control register */
 299 #define   GFCR_GPIO_ON    0x08          /* Camera GPIO enabled */
 300 #define REG_GL_GPIOR    0x315c  /* GPIO register */
 301 #define   GGPIO_OUT             0x80000 /* GPIO output */
 302 #define   GGPIO_VAL             0x00008 /* Output pin value */
 303
 304 #define REG_LEN                (REG_GL_IMASK + 4)
 305
 306
 307 /*
 308  * Useful stuff that probably belongs somewhere global.
 309  */
 310 #define VGA_WIDTH       640
 311 #define VGA_HEIGHT      480