drivers/mfd/twl4030-irq.c

   1 /*
   2  * twl4030-irq.c - TWL4030/TPS659x0 irq support
   3  *
   4  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   5  *
   6  * Modifications to defer interrupt handling to a kernel thread:
   7  * Copyright (C) 2006 MontaVista Software, Inc.
   8  *
   9  * Based on tlv320aic23.c:
  10  * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  11  *
  12  * Code cleanup and modifications to IRQ handler.
  13  * by syed khasim <x0khasim@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  28  */
  29
  30 #include <linux/export.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/irq.h>
  33 #include <linux/slab.h>
  34 #include <linux/of.h>
  35 #include <linux/irqdomain.h>
  36 #include <linux/i2c/twl.h>
  37
  38 #include "twl-core.h"
  39
  40 /*
  41  * TWL4030 IRQ handling has two stages in hardware, and thus in software.
  42  * The Primary Interrupt Handler (PIH) stage exposes status bits saying
  43  * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
  44  * SIH modules are more traditional IRQ components, which support per-IRQ
  45  * enable/disable and trigger controls; they do most of the work.
  46  *
  47  * These chips are designed to support IRQ handling from two different
  48  * I2C masters.  Each has a dedicated IRQ line, and dedicated IRQ status
  49  * and mask registers in the PIH and SIH modules.
  50  *
  51  * We set up IRQs starting at a platform-specified base, always starting
  52  * with PIH and the SIH for PWR_INT and then usually adding GPIO:
  53  *      base + 0  .. base + 7   PIH
  54  *      base + 8  .. base + 15  SIH for PWR_INT
  55  *      base + 16 .. base + 33  SIH for GPIO
  56  */
  57 #define TWL4030_CORE_NR_IRQS    8
  58 #define TWL4030_PWR_NR_IRQS     8
  59
  60 /* PIH register offsets */
  61 #define REG_PIH_ISR_P1                  0x01
  62 #define REG_PIH_ISR_P2                  0x02
  63 #define REG_PIH_SIR                     0x03    /* for testing */
  64
  65 /* Linux could (eventually) use either IRQ line */
  66 static int irq_line;
  67
  68 struct sih {
  69         char    name[8];
  70         u8      module;                 /* module id */
  71         u8      control_offset;         /* for SIH_CTRL */
  72         bool    set_cor;
  73
  74         u8      bits;                   /* valid in isr/imr */
  75         u8      bytes_ixr;              /* bytelen of ISR/IMR/SIR */
  76
  77         u8      edr_offset;
  78         u8      bytes_edr;              /* bytelen of EDR */
  79
  80         u8      irq_lines;              /* number of supported irq lines */
  81
  82         /* SIR ignored -- set interrupt, for testing only */
  83         struct sih_irq_data {
  84                 u8      isr_offset;
  85                 u8      imr_offset;
  86         } mask[2];
  87         /* + 2 bytes padding */
  88 };
  89
  90 static const struct sih *sih_modules;
  91 static int nr_sih_modules;
  92
  93 #define SIH_INITIALIZER(modname, nbits) \
  94         .module         = TWL4030_MODULE_ ## modname, \
  95         .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
  96         .bits           = nbits, \
  97         .bytes_ixr      = DIV_ROUND_UP(nbits, 8), \
  98         .edr_offset     = TWL4030_ ## modname ## _EDR, \
  99         .bytes_edr      = DIV_ROUND_UP((2*(nbits)), 8), \
 100         .irq_lines      = 2, \
 101         .mask = { { \
 102                 .isr_offset     = TWL4030_ ## modname ## _ISR1, \
 103                 .imr_offset     = TWL4030_ ## modname ## _IMR1, \
 104         }, \
 105         { \
 106                 .isr_offset     = TWL4030_ ## modname ## _ISR2, \
 107                 .imr_offset     = TWL4030_ ## modname ## _IMR2, \
 108         }, },
 109
 110 /* register naming policies are inconsistent ... */
 111 #define TWL4030_INT_PWR_EDR             TWL4030_INT_PWR_EDR1
 112 #define TWL4030_MODULE_KEYPAD_KEYP      TWL4030_MODULE_KEYPAD
 113 #define TWL4030_MODULE_INT_PWR          TWL4030_MODULE_INT
 114
 115
 116 /*
 117  * Order in this table matches order in PIH_ISR.  That is,
 118  * BIT(n) in PIH_ISR is sih_modules[n].
 119  */
 120 /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
 121 static const struct sih sih_modules_twl4030[6] = {
 122         [0] = {
 123                 .name           = "gpio",
 124                 .module         = TWL4030_MODULE_GPIO,
 125                 .control_offset = REG_GPIO_SIH_CTRL,
 126                 .set_cor        = true,
 127                 .bits           = TWL4030_GPIO_MAX,
 128                 .bytes_ixr      = 3,
 129                 /* Note: *all* of these IRQs default to no-trigger */
 130                 .edr_offset     = REG_GPIO_EDR1,
 131                 .bytes_edr      = 5,
 132                 .irq_lines      = 2,
 133                 .mask = { {
 134                         .isr_offset     = REG_GPIO_ISR1A,
 135                         .imr_offset     = REG_GPIO_IMR1A,
 136                 }, {
 137                         .isr_offset     = REG_GPIO_ISR1B,
 138                         .imr_offset     = REG_GPIO_IMR1B,
 139                 }, },
 140         },
 141         [1] = {
 142                 .name           = "keypad",
 143                 .set_cor        = true,
 144                 SIH_INITIALIZER(KEYPAD_KEYP, 4)
 145         },
 146         [2] = {
 147                 .name           = "bci",
 148                 .module         = TWL4030_MODULE_INTERRUPTS,
 149                 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
 150                 .set_cor        = true,
 151                 .bits           = 12,
 152                 .bytes_ixr      = 2,
 153                 .edr_offset     = TWL4030_INTERRUPTS_BCIEDR1,
 154                 /* Note: most of these IRQs default to no-trigger */
 155                 .bytes_edr      = 3,
 156                 .irq_lines      = 2,
 157                 .mask = { {
 158                         .isr_offset     = TWL4030_INTERRUPTS_BCIISR1A,
 159                         .imr_offset     = TWL4030_INTERRUPTS_BCIIMR1A,
 160                 }, {
 161                         .isr_offset     = TWL4030_INTERRUPTS_BCIISR1B,
 162                         .imr_offset     = TWL4030_INTERRUPTS_BCIIMR1B,
 163                 }, },
 164         },
 165         [3] = {
 166                 .name           = "madc",
 167                 SIH_INITIALIZER(MADC, 4)
 168         },
 169         [4] = {
 170                 /* USB doesn't use the same SIH organization */
 171                 .name           = "usb",
 172         },
 173         [5] = {
 174                 .name           = "power",
 175                 .set_cor        = true,
 176                 SIH_INITIALIZER(INT_PWR, 8)
 177         },
 178                 /* there are no SIH modules #6 or #7 ... */
 179 };
 180
 181 static const struct sih sih_modules_twl5031[8] = {
 182         [0] = {
 183                 .name           = "gpio",
 184                 .module         = TWL4030_MODULE_GPIO,
 185                 .control_offset = REG_GPIO_SIH_CTRL,
 186                 .set_cor        = true,
 187                 .bits           = TWL4030_GPIO_MAX,
 188                 .bytes_ixr      = 3,
 189                 /* Note: *all* of these IRQs default to no-trigger */
 190                 .edr_offset     = REG_GPIO_EDR1,
 191                 .bytes_edr      = 5,
 192                 .irq_lines      = 2,
 193                 .mask = { {
 194                         .isr_offset     = REG_GPIO_ISR1A,
 195                         .imr_offset     = REG_GPIO_IMR1A,
 196                 }, {
 197                         .isr_offset     = REG_GPIO_ISR1B,
 198                         .imr_offset     = REG_GPIO_IMR1B,
 199                 }, },
 200         },
 201         [1] = {
 202                 .name           = "keypad",
 203                 .set_cor        = true,
 204                 SIH_INITIALIZER(KEYPAD_KEYP, 4)
 205         },
 206         [2] = {
 207                 .name           = "bci",
 208                 .module         = TWL5031_MODULE_INTERRUPTS,
 209                 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
 210                 .bits           = 7,
 211                 .bytes_ixr      = 1,
 212                 .edr_offset     = TWL5031_INTERRUPTS_BCIEDR1,
 213                 /* Note: most of these IRQs default to no-trigger */
 214                 .bytes_edr      = 2,
 215                 .irq_lines      = 2,
 216                 .mask = { {
 217                         .isr_offset     = TWL5031_INTERRUPTS_BCIISR1,
 218                         .imr_offset     = TWL5031_INTERRUPTS_BCIIMR1,
 219                 }, {
 220                         .isr_offset     = TWL5031_INTERRUPTS_BCIISR2,
 221                         .imr_offset     = TWL5031_INTERRUPTS_BCIIMR2,
 222                 }, },
 223         },
 224         [3] = {
 225                 .name           = "madc",
 226                 SIH_INITIALIZER(MADC, 4)
 227         },
 228         [4] = {
 229                 /* USB doesn't use the same SIH organization */
 230                 .name           = "usb",
 231         },
 232         [5] = {
 233                 .name           = "power",
 234                 .set_cor        = true,
 235                 SIH_INITIALIZER(INT_PWR, 8)
 236         },
 237         [6] = {
 238                 /*
 239                  * ECI/DBI doesn't use the same SIH organization.
 240                  * For example, it supports only one interrupt output line.
 241                  * That is, the interrupts are seen on both INT1 and INT2 lines.
 242                  */
 243                 .name           = "eci_dbi",
 244                 .module         = TWL5031_MODULE_ACCESSORY,
 245                 .bits           = 9,
 246                 .bytes_ixr      = 2,
 247                 .irq_lines      = 1,
 248                 .mask = { {
 249                         .isr_offset     = TWL5031_ACIIDR_LSB,
 250                         .imr_offset     = TWL5031_ACIIMR_LSB,
 251                 }, },
 252
 253         },
 254         [7] = {
 255                 /* Audio accessory */
 256                 .name           = "audio",
 257                 .module         = TWL5031_MODULE_ACCESSORY,
 258                 .control_offset = TWL5031_ACCSIHCTRL,
 259                 .bits           = 2,
 260                 .bytes_ixr      = 1,
 261                 .edr_offset     = TWL5031_ACCEDR1,
 262                 /* Note: most of these IRQs default to no-trigger */
 263                 .bytes_edr      = 1,
 264                 .irq_lines      = 2,
 265                 .mask = { {
 266                         .isr_offset     = TWL5031_ACCISR1,
 267                         .imr_offset     = TWL5031_ACCIMR1,
 268                 }, {
 269                         .isr_offset     = TWL5031_ACCISR2,
 270                         .imr_offset     = TWL5031_ACCIMR2,
 271                 }, },
 272         },
 273 };
 274
 275 #undef TWL4030_MODULE_KEYPAD_KEYP
 276 #undef TWL4030_MODULE_INT_PWR
 277 #undef TWL4030_INT_PWR_EDR
 278
 279 /*----------------------------------------------------------------------*/
 280
 281 static unsigned twl4030_irq_base;
 282
 283 /*
 284  * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
 285  * This is a chained interrupt, so there is no desc->action method for it.
 286  * Now we need to query the interrupt controller in the twl4030 to determine
 287  * which module is generating the interrupt request.  However, we can't do i2c
 288  * transactions in interrupt context, so we must defer that work to a kernel
 289  * thread.  All we do here is acknowledge and mask the interrupt and wakeup
 290  * the kernel thread.
 291  */
 292 static irqreturn_t handle_twl4030_pih(int irq, void *devid)
 293 {
 294         irqreturn_t     ret;
 295         u8              pih_isr;
 296
 297         ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr,
 298                               REG_PIH_ISR_P1);
 299         if (ret) {
 300                 pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret);
 301                 return IRQ_NONE;
 302         }
 303
 304         while (pih_isr) {
 305                 unsigned long   pending = __ffs(pih_isr);
 306                 unsigned int    irq;
 307
 308                 pih_isr &= ~BIT(pending);
 309                 irq = pending + twl4030_irq_base;
 310                 handle_nested_irq(irq);
 311         }
 312
 313         return IRQ_HANDLED;
 314 }
 315
 316 /*----------------------------------------------------------------------*/
 317
 318 /*
 319  * twl4030_init_sih_modules() ... start from a known state where no
 320  * IRQs will be coming in, and where we can quickly enable them then
 321  * handle them as they arrive.  Mask all IRQs: maybe init SIH_CTRL.
 322  *
 323  * NOTE:  we don't touch EDR registers here; they stay with hardware
 324  * defaults or whatever the last value was.  Note that when both EDR
 325  * bits for an IRQ are clear, that's as if its IMR bit is set...
 326  */
 327 static int twl4030_init_sih_modules(unsigned line)
 328 {
 329         const struct sih *sih;
 330         u8 buf[4];
 331         int i;
 332         int status;
 333
 334         /* line 0 == int1_n signal; line 1 == int2_n signal */
 335         if (line > 1)
 336                 return -EINVAL;
 337
 338         irq_line = line;
 339
 340         /* disable all interrupts on our line */
 341         memset(buf, 0xff, sizeof(buf));
 342         sih = sih_modules;
 343         for (i = 0; i < nr_sih_modules; i++, sih++) {
 344                 /* skip USB -- it's funky */
 345                 if (!sih->bytes_ixr)
 346                         continue;
 347
 348                 /* Not all the SIH modules support multiple interrupt lines */
 349                 if (sih->irq_lines <= line)
 350                         continue;
 351
 352                 status = twl_i2c_write(sih->module, buf,
 353                                 sih->mask[line].imr_offset, sih->bytes_ixr);
 354                 if (status < 0)
 355                         pr_err("twl4030: err %d initializing %s %s\n",
 356                                         status, sih->name, "IMR");
 357
 358                 /*
 359                  * Maybe disable "exclusive" mode; buffer second pending irq;
 360                  * set Clear-On-Read (COR) bit.
 361                  *
 362                  * NOTE that sometimes COR polarity is documented as being
 363                  * inverted:  for MADC, COR=1 means "clear on write".
 364                  * And for PWR_INT it's not documented...
 365                  */
 366                 if (sih->set_cor) {
 367                         status = twl_i2c_write_u8(sih->module,
 368                                         TWL4030_SIH_CTRL_COR_MASK,
 369                                         sih->control_offset);
 370                         if (status < 0)
 371                                 pr_err("twl4030: err %d initializing %s %s\n",
 372                                                 status, sih->name, "SIH_CTRL");
 373                 }
 374         }
 375
 376         sih = sih_modules;
 377         for (i = 0; i < nr_sih_modules; i++, sih++) {
 378                 u8 rxbuf[4];
 379                 int j;
 380
 381                 /* skip USB */
 382                 if (!sih->bytes_ixr)
 383                         continue;
 384
 385                 /* Not all the SIH modules support multiple interrupt lines */
 386                 if (sih->irq_lines <= line)
 387                         continue;
 388
 389                 /*
 390                  * Clear pending interrupt status.  Either the read was
 391                  * enough, or we need to write those bits.  Repeat, in
 392                  * case an IRQ is pending (PENDDIS=0) ... that's not
 393                  * uncommon with PWR_INT.PWRON.
 394                  */
 395                 for (j = 0; j < 2; j++) {
 396                         status = twl_i2c_read(sih->module, rxbuf,
 397                                 sih->mask[line].isr_offset, sih->bytes_ixr);
 398                         if (status < 0)
 399                                 pr_warn("twl4030: err %d initializing %s %s\n",
 400                                         status, sih->name, "ISR");
 401
 402                         if (!sih->set_cor) {
 403                                 status = twl_i2c_write(sih->module, buf,
 404                                         sih->mask[line].isr_offset,
 405                                         sih->bytes_ixr);
 406                                 if (status < 0)
 407                                         pr_warn("twl4030: write failed: %d\n",
 408                                                 status);
 409                         }
 410                         /*
 411                          * else COR=1 means read sufficed.
 412                          * (for most SIH modules...)
 413                          */
 414                 }
 415         }
 416
 417         return 0;
 418 }
 419
 420 static inline void activate_irq(int irq)
 421 {
 422         irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
 423 }
 424
 425 /*----------------------------------------------------------------------*/
 426
 427 struct sih_agent {
 428         int                     irq_base;
 429         const struct sih        *sih;
 430
 431         u32                     imr;
 432         bool                    imr_change_pending;
 433
 434         u32                     edge_change;
 435
 436         struct mutex            irq_lock;
 437         char                    *irq_name;
 438 };
 439
 440 /*----------------------------------------------------------------------*/
 441
 442 /*
 443  * All irq_chip methods get issued from code holding irq_desc[irq].lock,
 444  * which can't perform the underlying I2C operations (because they sleep).
 445  * So we must hand them off to a thread (workqueue) and cope with asynch
 446  * completion, potentially including some re-ordering, of these requests.
 447  */
 448
 449 static void twl4030_sih_mask(struct irq_data *data)
 450 {
 451         struct sih_agent *agent = irq_data_get_irq_chip_data(data);
 452
 453         agent->imr |= BIT(data->irq - agent->irq_base);
 454         agent->imr_change_pending = true;
 455 }
 456
 457 static void twl4030_sih_unmask(struct irq_data *data)
 458 {
 459         struct sih_agent *agent = irq_data_get_irq_chip_data(data);
 460
 461         agent->imr &= ~BIT(data->irq - agent->irq_base);
 462         agent->imr_change_pending = true;
 463 }
 464
 465 static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
 466 {
 467         struct sih_agent *agent = irq_data_get_irq_chip_data(data);
 468
 469         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 470                 return -EINVAL;
 471
 472         if (irqd_get_trigger_type(data) != trigger)
 473                 agent->edge_change |= BIT(data->irq - agent->irq_base);
 474
 475         return 0;
 476 }
 477
 478 static void twl4030_sih_bus_lock(struct irq_data *data)
 479 {
 480         struct sih_agent        *agent = irq_data_get_irq_chip_data(data);
 481
 482         mutex_lock(&agent->irq_lock);
 483 }
 484
 485 static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
 486 {
 487         struct sih_agent        *agent = irq_data_get_irq_chip_data(data);
 488         const struct sih        *sih = agent->sih;
 489         int                     status;
 490
 491         if (agent->imr_change_pending) {
 492                 union {
 493                         u32     word;
 494                         u8      bytes[4];
 495                 } imr;
 496
 497                 /* byte[0] gets overwritten as we write ... */
 498                 imr.word = cpu_to_le32(agent->imr);
 499                 agent->imr_change_pending = false;
 500
 501                 /* write the whole mask ... simpler than subsetting it */
 502                 status = twl_i2c_write(sih->module, imr.bytes,
 503                                 sih->mask[irq_line].imr_offset,
 504                                 sih->bytes_ixr);
 505                 if (status)
 506                         pr_err("twl4030: %s, %s --> %d\n", __func__,
 507                                         "write", status);
 508         }
 509
 510         if (agent->edge_change) {
 511                 u32             edge_change;
 512                 u8              bytes[6];
 513
 514                 edge_change = agent->edge_change;
 515                 agent->edge_change = 0;
 516
 517                 /*
 518                  * Read, reserving first byte for write scratch.  Yes, this
 519                  * could be cached for some speedup ... but be careful about
 520                  * any processor on the other IRQ line, EDR registers are
 521                  * shared.
 522                  */
 523                 status = twl_i2c_read(sih->module, bytes,
 524                                 sih->edr_offset, sih->bytes_edr);
 525                 if (status) {
 526                         pr_err("twl4030: %s, %s --> %d\n", __func__,
 527                                         "read", status);
 528                         return;
 529                 }
 530
 531                 /* Modify only the bits we know must change */
 532                 while (edge_change) {
 533                         int             i = fls(edge_change) - 1;
 534                         int             byte = i >> 2;
 535                         int             off = (i & 0x3) * 2;
 536                         unsigned int    type;
 537
 538                         bytes[byte] &= ~(0x03 << off);
 539
 540                         type = irq_get_trigger_type(i + agent->irq_base);
 541                         if (type & IRQ_TYPE_EDGE_RISING)
 542                                 bytes[byte] |= BIT(off + 1);
 543                         if (type & IRQ_TYPE_EDGE_FALLING)
 544                                 bytes[byte] |= BIT(off + 0);
 545
 546                         edge_change &= ~BIT(i);
 547                 }
 548
 549                 /* Write */
 550                 status = twl_i2c_write(sih->module, bytes,
 551                                 sih->edr_offset, sih->bytes_edr);
 552                 if (status)
 553                         pr_err("twl4030: %s, %s --> %d\n", __func__,
 554                                         "write", status);
 555         }
 556
 557         mutex_unlock(&agent->irq_lock);
 558 }
 559
 560 static struct irq_chip twl4030_sih_irq_chip = {
 561         .name           = "twl4030",
 562         .irq_mask       = twl4030_sih_mask,
 563         .irq_unmask     = twl4030_sih_unmask,
 564         .irq_set_type   = twl4030_sih_set_type,
 565         .irq_bus_lock   = twl4030_sih_bus_lock,
 566         .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
 567         .flags          = IRQCHIP_SKIP_SET_WAKE,
 568 };
 569
 570 /*----------------------------------------------------------------------*/
 571
 572 static inline int sih_read_isr(const struct sih *sih)
 573 {
 574         int status;
 575         union {
 576                 u8 bytes[4];
 577                 u32 word;
 578         } isr;
 579
 580         /* FIXME need retry-on-error ... */
 581
 582         isr.word = 0;
 583         status = twl_i2c_read(sih->module, isr.bytes,
 584                         sih->mask[irq_line].isr_offset, sih->bytes_ixr);
 585
 586         return (status < 0) ? status : le32_to_cpu(isr.word);
 587 }
 588
 589 /*
 590  * Generic handler for SIH interrupts ... we "know" this is called
 591  * in task context, with IRQs enabled.
 592  */
 593 static irqreturn_t handle_twl4030_sih(int irq, void *data)
 594 {
 595         struct sih_agent *agent = irq_get_handler_data(irq);
 596         const struct sih *sih = agent->sih;
 597         int isr;
 598
 599         /* reading ISR acks the IRQs, using clear-on-read mode */
 600         isr = sih_read_isr(sih);
 601
 602         if (isr < 0) {
 603                 pr_err("twl4030: %s SIH, read ISR error %d\n",
 604                         sih->name, isr);
 605                 /* REVISIT:  recover; eventually mask it all, etc */
 606                 return IRQ_HANDLED;
 607         }
 608
 609         while (isr) {
 610                 irq = fls(isr);
 611                 irq--;
 612                 isr &= ~BIT(irq);
 613
 614                 if (irq < sih->bits)
 615                         handle_nested_irq(agent->irq_base + irq);
 616                 else
 617                         pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
 618                                 sih->name, irq);
 619         }
 620         return IRQ_HANDLED;
 621 }
 622
 623 /* returns the first IRQ used by this SIH bank, or negative errno */
 624 int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 625 {
 626         int                     sih_mod;
 627         const struct sih        *sih = NULL;
 628         struct sih_agent        *agent;
 629         int                     i, irq;
 630         int                     status = -EINVAL;
 631
 632         /* only support modules with standard clear-on-read for now */
 633         for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
 634                         sih_mod++, sih++) {
 635                 if (sih->module == module && sih->set_cor) {
 636                         status = 0;
 637                         break;
 638                 }
 639         }
 640
 641         if (status < 0)
 642                 return status;
 643
 644         agent = kzalloc(sizeof(*agent), GFP_KERNEL);
 645         if (!agent)
 646                 return -ENOMEM;
 647
 648         agent->irq_base = irq_base;
 649         agent->sih = sih;
 650         agent->imr = ~0;
 651         mutex_init(&agent->irq_lock);
 652
 653         for (i = 0; i < sih->bits; i++) {
 654                 irq = irq_base + i;
 655
 656                 irq_set_chip_data(irq, agent);
 657                 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
 658                                          handle_edge_irq);
 659                 irq_set_nested_thread(irq, 1);
 660                 activate_irq(irq);
 661         }
 662
 663         /* replace generic PIH handler (handle_simple_irq) */
 664         irq = sih_mod + twl4030_irq_base;
 665         irq_set_handler_data(irq, agent);
 666         agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
 667         status = request_threaded_irq(irq, NULL, handle_twl4030_sih,
 668                                       IRQF_EARLY_RESUME | IRQF_ONESHOT,
 669                                       agent->irq_name ?: sih->name, NULL);
 670
 671         dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
 672                         irq, irq_base, irq_base + i - 1);
 673
 674         return status < 0 ? status : irq_base;
 675 }
 676
 677 /* FIXME need a call to reverse twl4030_sih_setup() ... */
 678
 679 /*----------------------------------------------------------------------*/
 680
 681 /* FIXME pass in which interrupt line we'll use ... */
 682 #define twl_irq_line    0
 683
 684 int twl4030_init_irq(struct device *dev, int irq_num)
 685 {
 686         static struct irq_chip  twl4030_irq_chip;
 687         int                     status, i;
 688         int                     irq_base, irq_end, nr_irqs;
 689         struct                  device_node *node = dev->of_node;
 690
 691         /*
 692          * TWL core and pwr interrupts must be contiguous because
 693          * the hwirqs numbers are defined contiguously from 1 to 15.
 694          * Create only one domain for both.
 695          */
 696         nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
 697
 698         irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
 699         if (IS_ERR_VALUE(irq_base)) {
 700                 dev_err(dev, "Fail to allocate IRQ descs\n");
 701                 return irq_base;
 702         }
 703
 704         irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
 705                               &irq_domain_simple_ops, NULL);
 706
 707         irq_end = irq_base + TWL4030_CORE_NR_IRQS;
 708
 709         /*
 710          * Mask and clear all TWL4030 interrupts since initially we do
 711          * not have any TWL4030 module interrupt handlers present
 712          */
 713         status = twl4030_init_sih_modules(twl_irq_line);
 714         if (status < 0)
 715                 return status;
 716
 717         twl4030_irq_base = irq_base;
 718
 719         /*
 720          * Install an irq handler for each of the SIH modules;
 721          * clone dummy irq_chip since PIH can't *do* anything
 722          */
 723         twl4030_irq_chip = dummy_irq_chip;
 724         twl4030_irq_chip.name = "twl4030";
 725
 726         twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
 727
 728         for (i = irq_base; i < irq_end; i++) {
 729                 irq_set_chip_and_handler(i, &twl4030_irq_chip,
 730                                          handle_simple_irq);
 731                 irq_set_nested_thread(i, 1);
 732                 activate_irq(i);
 733         }
 734
 735         dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
 736                         irq_num, irq_base, irq_end);
 737
 738         /* ... and the PWR_INT module ... */
 739         status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
 740         if (status < 0) {
 741                 dev_err(dev, "sih_setup PWR INT --> %d\n", status);
 742                 goto fail;
 743         }
 744
 745         /* install an irq handler to demultiplex the TWL4030 interrupt */
 746         status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
 747                                       IRQF_ONESHOT,
 748                                       "TWL4030-PIH", NULL);
 749         if (status < 0) {
 750                 dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
 751                 goto fail_rqirq;
 752         }
 753         enable_irq_wake(irq_num);
 754
 755         return irq_base;
 756 fail_rqirq:
 757         /* clean up twl4030_sih_setup */
 758 fail:
 759         for (i = irq_base; i < irq_end; i++) {
 760                 irq_set_nested_thread(i, 0);
 761                 irq_set_chip_and_handler(i, NULL, NULL);
 762         }
 763
 764         return status;
 765 }
 766
 767 int twl4030_exit_irq(void)
 768 {
 769         /* FIXME undo twl_init_irq() */
 770         if (twl4030_irq_base) {
 771                 pr_err("twl4030: can't yet clean up IRQs?\n");
 772                 return -ENOSYS;
 773         }
 774         return 0;
 775 }
 776
 777 int twl4030_init_chip_irq(const char *chip)
 778 {
 779         if (!strcmp(chip, "twl5031")) {
 780                 sih_modules = sih_modules_twl5031;
 781                 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
 782         } else {
 783                 sih_modules = sih_modules_twl4030;
 784                 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
 785         }
 786
 787         return 0;
 788 }