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[deliverable/linux.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data);
58 static int sdhci_do_get_cd(struct sdhci_host *host);
59
60 #ifdef CONFIG_PM
61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
65 #else
66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 {
68 return 0;
69 }
70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 {
72 return 0;
73 }
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75 {
76 }
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78 {
79 }
80 #endif
81
82 static void sdhci_dumpregs(struct sdhci_host *host)
83 {
84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host->mmc));
86
87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host, SDHCI_CAPABILITIES),
116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host, SDHCI_COMMAND),
119 sdhci_readl(host, SDHCI_MAX_CURRENT));
120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
122
123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129 else
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133 }
134
135 pr_debug(DRIVER_NAME ": ===========================================\n");
136 }
137
138 /*****************************************************************************\
139 * *
140 * Low level functions *
141 * *
142 \*****************************************************************************/
143
144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145 {
146 u32 present;
147
148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
150 return;
151
152 if (enable) {
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
155
156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
158 } else {
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160 }
161
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
164 }
165
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 {
168 sdhci_set_card_detection(host, true);
169 }
170
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 {
173 sdhci_set_card_detection(host, false);
174 }
175
176 void sdhci_reset(struct sdhci_host *host, u8 mask)
177 {
178 unsigned long timeout;
179
180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
181
182 if (mask & SDHCI_RESET_ALL) {
183 host->clock = 0;
184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
187 }
188
189 /* Wait max 100 ms */
190 timeout = 100;
191
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
194 if (timeout == 0) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
198 return;
199 }
200 timeout--;
201 mdelay(1);
202 }
203 }
204 EXPORT_SYMBOL_GPL(sdhci_reset);
205
206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207 {
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
209 if (!sdhci_do_get_cd(host))
210 return;
211 }
212
213 host->ops->reset(host, mask);
214
215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
219 }
220
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
223 }
224 }
225
226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
228 static void sdhci_init(struct sdhci_host *host, int soft)
229 {
230 if (soft)
231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
232 else
233 sdhci_do_reset(host, SDHCI_RESET_ALL);
234
235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 SDHCI_INT_RESPONSE;
240
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
243
244 if (soft) {
245 /* force clock reconfiguration */
246 host->clock = 0;
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
248 }
249 }
250
251 static void sdhci_reinit(struct sdhci_host *host)
252 {
253 sdhci_init(host, 0);
254 sdhci_enable_card_detection(host);
255 }
256
257 static void sdhci_activate_led(struct sdhci_host *host)
258 {
259 u8 ctrl;
260
261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
262 ctrl |= SDHCI_CTRL_LED;
263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
264 }
265
266 static void sdhci_deactivate_led(struct sdhci_host *host)
267 {
268 u8 ctrl;
269
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl &= ~SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 }
274
275 #ifdef SDHCI_USE_LEDS_CLASS
276 static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
278 {
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280 unsigned long flags;
281
282 spin_lock_irqsave(&host->lock, flags);
283
284 if (host->runtime_suspended)
285 goto out;
286
287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
289 else
290 sdhci_activate_led(host);
291 out:
292 spin_unlock_irqrestore(&host->lock, flags);
293 }
294 #endif
295
296 /*****************************************************************************\
297 * *
298 * Core functions *
299 * *
300 \*****************************************************************************/
301
302 static void sdhci_read_block_pio(struct sdhci_host *host)
303 {
304 unsigned long flags;
305 size_t blksize, len, chunk;
306 u32 uninitialized_var(scratch);
307 u8 *buf;
308
309 DBG("PIO reading\n");
310
311 blksize = host->data->blksz;
312 chunk = 0;
313
314 local_irq_save(flags);
315
316 while (blksize) {
317 BUG_ON(!sg_miter_next(&host->sg_miter));
318
319 len = min(host->sg_miter.length, blksize);
320
321 blksize -= len;
322 host->sg_miter.consumed = len;
323
324 buf = host->sg_miter.addr;
325
326 while (len) {
327 if (chunk == 0) {
328 scratch = sdhci_readl(host, SDHCI_BUFFER);
329 chunk = 4;
330 }
331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
338 }
339 }
340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
344 }
345
346 static void sdhci_write_block_pio(struct sdhci_host *host)
347 {
348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
352
353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
356 chunk = 0;
357 scratch = 0;
358
359 local_irq_save(flags);
360
361 while (blksize) {
362 BUG_ON(!sg_miter_next(&host->sg_miter));
363
364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
370
371 while (len) {
372 scratch |= (u32)*buf << (chunk * 8);
373
374 buf++;
375 chunk++;
376 len--;
377
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
379 sdhci_writel(host, scratch, SDHCI_BUFFER);
380 chunk = 0;
381 scratch = 0;
382 }
383 }
384 }
385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
389 }
390
391 static void sdhci_transfer_pio(struct sdhci_host *host)
392 {
393 u32 mask;
394
395 BUG_ON(!host->data);
396
397 if (host->blocks == 0)
398 return;
399
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
402 else
403 mask = SDHCI_SPACE_AVAILABLE;
404
405 /*
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
409 */
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
412 mask = ~0;
413
414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416 udelay(100);
417
418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
420 else
421 sdhci_write_block_pio(host);
422
423 host->blocks--;
424 if (host->blocks == 0)
425 break;
426 }
427
428 DBG("PIO transfer complete.\n");
429 }
430
431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432 {
433 local_irq_save(*flags);
434 return kmap_atomic(sg_page(sg)) + sg->offset;
435 }
436
437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438 {
439 kunmap_atomic(buffer);
440 local_irq_restore(*flags);
441 }
442
443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
445 {
446 struct sdhci_adma2_64_desc *dma_desc = desc;
447
448 /* 32-bit and 64-bit descriptors have these members in same position */
449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
455 }
456
457 static void sdhci_adma_mark_end(void *desc)
458 {
459 struct sdhci_adma2_64_desc *dma_desc = desc;
460
461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
463 }
464
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
467 {
468 struct scatterlist *sg;
469 unsigned long flags;
470 dma_addr_t addr, align_addr;
471 void *desc, *align;
472 char *buffer;
473 int len, offset, i;
474
475 /*
476 * The spec does not specify endianness of descriptor table.
477 * We currently guess that it is LE.
478 */
479
480 host->sg_count = sdhci_pre_dma_transfer(host, data);
481 if (host->sg_count < 0)
482 return -EINVAL;
483
484 desc = host->adma_table;
485 align = host->align_buffer;
486
487 align_addr = host->align_addr;
488
489 for_each_sg(data->sg, sg, host->sg_count, i) {
490 addr = sg_dma_address(sg);
491 len = sg_dma_len(sg);
492
493 /*
494 * The SDHCI specification states that ADMA addresses must
495 * be 32-bit aligned. If they aren't, then we use a bounce
496 * buffer for the (up to three) bytes that screw up the
497 * alignment.
498 */
499 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
500 SDHCI_ADMA2_MASK;
501 if (offset) {
502 if (data->flags & MMC_DATA_WRITE) {
503 buffer = sdhci_kmap_atomic(sg, &flags);
504 memcpy(align, buffer, offset);
505 sdhci_kunmap_atomic(buffer, &flags);
506 }
507
508 /* tran, valid */
509 sdhci_adma_write_desc(host, desc, align_addr, offset,
510 ADMA2_TRAN_VALID);
511
512 BUG_ON(offset > 65536);
513
514 align += SDHCI_ADMA2_ALIGN;
515 align_addr += SDHCI_ADMA2_ALIGN;
516
517 desc += host->desc_sz;
518
519 addr += offset;
520 len -= offset;
521 }
522
523 BUG_ON(len > 65536);
524
525 if (len) {
526 /* tran, valid */
527 sdhci_adma_write_desc(host, desc, addr, len,
528 ADMA2_TRAN_VALID);
529 desc += host->desc_sz;
530 }
531
532 /*
533 * If this triggers then we have a calculation bug
534 * somewhere. :/
535 */
536 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
537 }
538
539 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
540 /* Mark the last descriptor as the terminating descriptor */
541 if (desc != host->adma_table) {
542 desc -= host->desc_sz;
543 sdhci_adma_mark_end(desc);
544 }
545 } else {
546 /* Add a terminating entry - nop, end, valid */
547 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
548 }
549 return 0;
550 }
551
552 static void sdhci_adma_table_post(struct sdhci_host *host,
553 struct mmc_data *data)
554 {
555 struct scatterlist *sg;
556 int i, size;
557 void *align;
558 char *buffer;
559 unsigned long flags;
560
561 if (data->flags & MMC_DATA_READ) {
562 bool has_unaligned = false;
563
564 /* Do a quick scan of the SG list for any unaligned mappings */
565 for_each_sg(data->sg, sg, host->sg_count, i)
566 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
567 has_unaligned = true;
568 break;
569 }
570
571 if (has_unaligned) {
572 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
573 data->sg_len, DMA_FROM_DEVICE);
574
575 align = host->align_buffer;
576
577 for_each_sg(data->sg, sg, host->sg_count, i) {
578 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
579 size = SDHCI_ADMA2_ALIGN -
580 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
581
582 buffer = sdhci_kmap_atomic(sg, &flags);
583 memcpy(buffer, align, size);
584 sdhci_kunmap_atomic(buffer, &flags);
585
586 align += SDHCI_ADMA2_ALIGN;
587 }
588 }
589 }
590 }
591 }
592
593 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
594 {
595 u8 count;
596 struct mmc_data *data = cmd->data;
597 unsigned target_timeout, current_timeout;
598
599 /*
600 * If the host controller provides us with an incorrect timeout
601 * value, just skip the check and use 0xE. The hardware may take
602 * longer to time out, but that's much better than having a too-short
603 * timeout value.
604 */
605 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
606 return 0xE;
607
608 /* Unspecified timeout, assume max */
609 if (!data && !cmd->busy_timeout)
610 return 0xE;
611
612 /* timeout in us */
613 if (!data)
614 target_timeout = cmd->busy_timeout * 1000;
615 else {
616 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
617 if (host->clock && data->timeout_clks) {
618 unsigned long long val;
619
620 /*
621 * data->timeout_clks is in units of clock cycles.
622 * host->clock is in Hz. target_timeout is in us.
623 * Hence, us = 1000000 * cycles / Hz. Round up.
624 */
625 val = 1000000 * data->timeout_clks;
626 if (do_div(val, host->clock))
627 target_timeout++;
628 target_timeout += val;
629 }
630 }
631
632 /*
633 * Figure out needed cycles.
634 * We do this in steps in order to fit inside a 32 bit int.
635 * The first step is the minimum timeout, which will have a
636 * minimum resolution of 6 bits:
637 * (1) 2^13*1000 > 2^22,
638 * (2) host->timeout_clk < 2^16
639 * =>
640 * (1) / (2) > 2^6
641 */
642 count = 0;
643 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
644 while (current_timeout < target_timeout) {
645 count++;
646 current_timeout <<= 1;
647 if (count >= 0xF)
648 break;
649 }
650
651 if (count >= 0xF) {
652 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
653 mmc_hostname(host->mmc), count, cmd->opcode);
654 count = 0xE;
655 }
656
657 return count;
658 }
659
660 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
661 {
662 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
663 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
664
665 if (host->flags & SDHCI_REQ_USE_DMA)
666 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
667 else
668 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
669
670 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
671 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
672 }
673
674 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
675 {
676 u8 count;
677
678 if (host->ops->set_timeout) {
679 host->ops->set_timeout(host, cmd);
680 } else {
681 count = sdhci_calc_timeout(host, cmd);
682 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
683 }
684 }
685
686 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
687 {
688 u8 ctrl;
689 struct mmc_data *data = cmd->data;
690 int ret;
691
692 WARN_ON(host->data);
693
694 if (data || (cmd->flags & MMC_RSP_BUSY))
695 sdhci_set_timeout(host, cmd);
696
697 if (!data)
698 return;
699
700 /* Sanity checks */
701 BUG_ON(data->blksz * data->blocks > 524288);
702 BUG_ON(data->blksz > host->mmc->max_blk_size);
703 BUG_ON(data->blocks > 65535);
704
705 host->data = data;
706 host->data_early = 0;
707 host->data->bytes_xfered = 0;
708
709 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
710 host->flags |= SDHCI_REQ_USE_DMA;
711
712 /*
713 * FIXME: This doesn't account for merging when mapping the
714 * scatterlist.
715 */
716 if (host->flags & SDHCI_REQ_USE_DMA) {
717 int broken, i;
718 struct scatterlist *sg;
719
720 broken = 0;
721 if (host->flags & SDHCI_USE_ADMA) {
722 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
723 broken = 1;
724 } else {
725 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
726 broken = 1;
727 }
728
729 if (unlikely(broken)) {
730 for_each_sg(data->sg, sg, data->sg_len, i) {
731 if (sg->length & 0x3) {
732 DBG("Reverting to PIO because of transfer size (%d)\n",
733 sg->length);
734 host->flags &= ~SDHCI_REQ_USE_DMA;
735 break;
736 }
737 }
738 }
739 }
740
741 /*
742 * The assumption here being that alignment is the same after
743 * translation to device address space.
744 */
745 if (host->flags & SDHCI_REQ_USE_DMA) {
746 int broken, i;
747 struct scatterlist *sg;
748
749 broken = 0;
750 if (host->flags & SDHCI_USE_ADMA) {
751 /*
752 * As we use 3 byte chunks to work around
753 * alignment problems, we need to check this
754 * quirk.
755 */
756 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
757 broken = 1;
758 } else {
759 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
760 broken = 1;
761 }
762
763 if (unlikely(broken)) {
764 for_each_sg(data->sg, sg, data->sg_len, i) {
765 if (sg->offset & 0x3) {
766 DBG("Reverting to PIO because of bad alignment\n");
767 host->flags &= ~SDHCI_REQ_USE_DMA;
768 break;
769 }
770 }
771 }
772 }
773
774 if (host->flags & SDHCI_REQ_USE_DMA) {
775 if (host->flags & SDHCI_USE_ADMA) {
776 ret = sdhci_adma_table_pre(host, data);
777 if (ret) {
778 /*
779 * This only happens when someone fed
780 * us an invalid request.
781 */
782 WARN_ON(1);
783 host->flags &= ~SDHCI_REQ_USE_DMA;
784 } else {
785 sdhci_writel(host, host->adma_addr,
786 SDHCI_ADMA_ADDRESS);
787 if (host->flags & SDHCI_USE_64_BIT_DMA)
788 sdhci_writel(host,
789 (u64)host->adma_addr >> 32,
790 SDHCI_ADMA_ADDRESS_HI);
791 }
792 } else {
793 int sg_cnt;
794
795 sg_cnt = sdhci_pre_dma_transfer(host, data);
796 if (sg_cnt <= 0) {
797 /*
798 * This only happens when someone fed
799 * us an invalid request.
800 */
801 WARN_ON(1);
802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 } else {
804 WARN_ON(sg_cnt != 1);
805 sdhci_writel(host, sg_dma_address(data->sg),
806 SDHCI_DMA_ADDRESS);
807 }
808 }
809 }
810
811 /*
812 * Always adjust the DMA selection as some controllers
813 * (e.g. JMicron) can't do PIO properly when the selection
814 * is ADMA.
815 */
816 if (host->version >= SDHCI_SPEC_200) {
817 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
818 ctrl &= ~SDHCI_CTRL_DMA_MASK;
819 if ((host->flags & SDHCI_REQ_USE_DMA) &&
820 (host->flags & SDHCI_USE_ADMA)) {
821 if (host->flags & SDHCI_USE_64_BIT_DMA)
822 ctrl |= SDHCI_CTRL_ADMA64;
823 else
824 ctrl |= SDHCI_CTRL_ADMA32;
825 } else {
826 ctrl |= SDHCI_CTRL_SDMA;
827 }
828 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
829 }
830
831 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
832 int flags;
833
834 flags = SG_MITER_ATOMIC;
835 if (host->data->flags & MMC_DATA_READ)
836 flags |= SG_MITER_TO_SG;
837 else
838 flags |= SG_MITER_FROM_SG;
839 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
840 host->blocks = data->blocks;
841 }
842
843 sdhci_set_transfer_irqs(host);
844
845 /* Set the DMA boundary value and block size */
846 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
847 data->blksz), SDHCI_BLOCK_SIZE);
848 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
849 }
850
851 static void sdhci_set_transfer_mode(struct sdhci_host *host,
852 struct mmc_command *cmd)
853 {
854 u16 mode = 0;
855 struct mmc_data *data = cmd->data;
856
857 if (data == NULL) {
858 if (host->quirks2 &
859 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
860 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
861 } else {
862 /* clear Auto CMD settings for no data CMDs */
863 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
864 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
865 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
866 }
867 return;
868 }
869
870 WARN_ON(!host->data);
871
872 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
873 mode = SDHCI_TRNS_BLK_CNT_EN;
874
875 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
876 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
877 /*
878 * If we are sending CMD23, CMD12 never gets sent
879 * on successful completion (so no Auto-CMD12).
880 */
881 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
882 (cmd->opcode != SD_IO_RW_EXTENDED))
883 mode |= SDHCI_TRNS_AUTO_CMD12;
884 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
885 mode |= SDHCI_TRNS_AUTO_CMD23;
886 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
887 }
888 }
889
890 if (data->flags & MMC_DATA_READ)
891 mode |= SDHCI_TRNS_READ;
892 if (host->flags & SDHCI_REQ_USE_DMA)
893 mode |= SDHCI_TRNS_DMA;
894
895 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
896 }
897
898 static void sdhci_finish_data(struct sdhci_host *host)
899 {
900 struct mmc_data *data;
901
902 BUG_ON(!host->data);
903
904 data = host->data;
905 host->data = NULL;
906
907 if (host->flags & SDHCI_REQ_USE_DMA) {
908 if (host->flags & SDHCI_USE_ADMA)
909 sdhci_adma_table_post(host, data);
910
911 if (data->host_cookie == COOKIE_MAPPED) {
912 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
913 (data->flags & MMC_DATA_READ) ?
914 DMA_FROM_DEVICE : DMA_TO_DEVICE);
915 data->host_cookie = COOKIE_UNMAPPED;
916 }
917 }
918
919 /*
920 * The specification states that the block count register must
921 * be updated, but it does not specify at what point in the
922 * data flow. That makes the register entirely useless to read
923 * back so we have to assume that nothing made it to the card
924 * in the event of an error.
925 */
926 if (data->error)
927 data->bytes_xfered = 0;
928 else
929 data->bytes_xfered = data->blksz * data->blocks;
930
931 /*
932 * Need to send CMD12 if -
933 * a) open-ended multiblock transfer (no CMD23)
934 * b) error in multiblock transfer
935 */
936 if (data->stop &&
937 (data->error ||
938 !host->mrq->sbc)) {
939
940 /*
941 * The controller needs a reset of internal state machines
942 * upon error conditions.
943 */
944 if (data->error) {
945 sdhci_do_reset(host, SDHCI_RESET_CMD);
946 sdhci_do_reset(host, SDHCI_RESET_DATA);
947 }
948
949 sdhci_send_command(host, data->stop);
950 } else
951 tasklet_schedule(&host->finish_tasklet);
952 }
953
954 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
955 {
956 int flags;
957 u32 mask;
958 unsigned long timeout;
959
960 WARN_ON(host->cmd);
961
962 /* Initially, a command has no error */
963 cmd->error = 0;
964
965 /* Wait max 10 ms */
966 timeout = 10;
967
968 mask = SDHCI_CMD_INHIBIT;
969 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
970 mask |= SDHCI_DATA_INHIBIT;
971
972 /* We shouldn't wait for data inihibit for stop commands, even
973 though they might use busy signaling */
974 if (host->mrq->data && (cmd == host->mrq->data->stop))
975 mask &= ~SDHCI_DATA_INHIBIT;
976
977 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
978 if (timeout == 0) {
979 pr_err("%s: Controller never released inhibit bit(s).\n",
980 mmc_hostname(host->mmc));
981 sdhci_dumpregs(host);
982 cmd->error = -EIO;
983 tasklet_schedule(&host->finish_tasklet);
984 return;
985 }
986 timeout--;
987 mdelay(1);
988 }
989
990 timeout = jiffies;
991 if (!cmd->data && cmd->busy_timeout > 9000)
992 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
993 else
994 timeout += 10 * HZ;
995 mod_timer(&host->timer, timeout);
996
997 host->cmd = cmd;
998 host->busy_handle = 0;
999
1000 sdhci_prepare_data(host, cmd);
1001
1002 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1003
1004 sdhci_set_transfer_mode(host, cmd);
1005
1006 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1007 pr_err("%s: Unsupported response type!\n",
1008 mmc_hostname(host->mmc));
1009 cmd->error = -EINVAL;
1010 tasklet_schedule(&host->finish_tasklet);
1011 return;
1012 }
1013
1014 if (!(cmd->flags & MMC_RSP_PRESENT))
1015 flags = SDHCI_CMD_RESP_NONE;
1016 else if (cmd->flags & MMC_RSP_136)
1017 flags = SDHCI_CMD_RESP_LONG;
1018 else if (cmd->flags & MMC_RSP_BUSY)
1019 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1020 else
1021 flags = SDHCI_CMD_RESP_SHORT;
1022
1023 if (cmd->flags & MMC_RSP_CRC)
1024 flags |= SDHCI_CMD_CRC;
1025 if (cmd->flags & MMC_RSP_OPCODE)
1026 flags |= SDHCI_CMD_INDEX;
1027
1028 /* CMD19 is special in that the Data Present Select should be set */
1029 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1030 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1031 flags |= SDHCI_CMD_DATA;
1032
1033 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1034 }
1035 EXPORT_SYMBOL_GPL(sdhci_send_command);
1036
1037 static void sdhci_finish_command(struct sdhci_host *host)
1038 {
1039 int i;
1040
1041 BUG_ON(host->cmd == NULL);
1042
1043 if (host->cmd->flags & MMC_RSP_PRESENT) {
1044 if (host->cmd->flags & MMC_RSP_136) {
1045 /* CRC is stripped so we need to do some shifting. */
1046 for (i = 0;i < 4;i++) {
1047 host->cmd->resp[i] = sdhci_readl(host,
1048 SDHCI_RESPONSE + (3-i)*4) << 8;
1049 if (i != 3)
1050 host->cmd->resp[i] |=
1051 sdhci_readb(host,
1052 SDHCI_RESPONSE + (3-i)*4-1);
1053 }
1054 } else {
1055 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1056 }
1057 }
1058
1059 /* Finished CMD23, now send actual command. */
1060 if (host->cmd == host->mrq->sbc) {
1061 host->cmd = NULL;
1062 sdhci_send_command(host, host->mrq->cmd);
1063 } else {
1064
1065 /* Processed actual command. */
1066 if (host->data && host->data_early)
1067 sdhci_finish_data(host);
1068
1069 if (!host->cmd->data)
1070 tasklet_schedule(&host->finish_tasklet);
1071
1072 host->cmd = NULL;
1073 }
1074 }
1075
1076 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1077 {
1078 u16 preset = 0;
1079
1080 switch (host->timing) {
1081 case MMC_TIMING_UHS_SDR12:
1082 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1083 break;
1084 case MMC_TIMING_UHS_SDR25:
1085 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1086 break;
1087 case MMC_TIMING_UHS_SDR50:
1088 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1089 break;
1090 case MMC_TIMING_UHS_SDR104:
1091 case MMC_TIMING_MMC_HS200:
1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1093 break;
1094 case MMC_TIMING_UHS_DDR50:
1095 case MMC_TIMING_MMC_DDR52:
1096 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1097 break;
1098 case MMC_TIMING_MMC_HS400:
1099 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1100 break;
1101 default:
1102 pr_warn("%s: Invalid UHS-I mode selected\n",
1103 mmc_hostname(host->mmc));
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1105 break;
1106 }
1107 return preset;
1108 }
1109
1110 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1111 {
1112 int div = 0; /* Initialized for compiler warning */
1113 int real_div = div, clk_mul = 1;
1114 u16 clk = 0;
1115 unsigned long timeout;
1116 bool switch_base_clk = false;
1117
1118 host->mmc->actual_clock = 0;
1119
1120 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1121 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1122 mdelay(1);
1123
1124 if (clock == 0)
1125 return;
1126
1127 if (host->version >= SDHCI_SPEC_300) {
1128 if (host->preset_enabled) {
1129 u16 pre_val;
1130
1131 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1132 pre_val = sdhci_get_preset_value(host);
1133 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1134 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1135 if (host->clk_mul &&
1136 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1137 clk = SDHCI_PROG_CLOCK_MODE;
1138 real_div = div + 1;
1139 clk_mul = host->clk_mul;
1140 } else {
1141 real_div = max_t(int, 1, div << 1);
1142 }
1143 goto clock_set;
1144 }
1145
1146 /*
1147 * Check if the Host Controller supports Programmable Clock
1148 * Mode.
1149 */
1150 if (host->clk_mul) {
1151 for (div = 1; div <= 1024; div++) {
1152 if ((host->max_clk * host->clk_mul / div)
1153 <= clock)
1154 break;
1155 }
1156 if ((host->max_clk * host->clk_mul / div) <= clock) {
1157 /*
1158 * Set Programmable Clock Mode in the Clock
1159 * Control register.
1160 */
1161 clk = SDHCI_PROG_CLOCK_MODE;
1162 real_div = div;
1163 clk_mul = host->clk_mul;
1164 div--;
1165 } else {
1166 /*
1167 * Divisor can be too small to reach clock
1168 * speed requirement. Then use the base clock.
1169 */
1170 switch_base_clk = true;
1171 }
1172 }
1173
1174 if (!host->clk_mul || switch_base_clk) {
1175 /* Version 3.00 divisors must be a multiple of 2. */
1176 if (host->max_clk <= clock)
1177 div = 1;
1178 else {
1179 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1180 div += 2) {
1181 if ((host->max_clk / div) <= clock)
1182 break;
1183 }
1184 }
1185 real_div = div;
1186 div >>= 1;
1187 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1188 && !div && host->max_clk <= 25000000)
1189 div = 1;
1190 }
1191 } else {
1192 /* Version 2.00 divisors must be a power of 2. */
1193 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1194 if ((host->max_clk / div) <= clock)
1195 break;
1196 }
1197 real_div = div;
1198 div >>= 1;
1199 }
1200
1201 clock_set:
1202 if (real_div)
1203 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1204 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1205 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1206 << SDHCI_DIVIDER_HI_SHIFT;
1207 clk |= SDHCI_CLOCK_INT_EN;
1208 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1209
1210 /* Wait max 20 ms */
1211 timeout = 20;
1212 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1213 & SDHCI_CLOCK_INT_STABLE)) {
1214 if (timeout == 0) {
1215 pr_err("%s: Internal clock never stabilised.\n",
1216 mmc_hostname(host->mmc));
1217 sdhci_dumpregs(host);
1218 return;
1219 }
1220 timeout--;
1221 mdelay(1);
1222 }
1223
1224 clk |= SDHCI_CLOCK_CARD_EN;
1225 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1226 }
1227 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1228
1229 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1230 unsigned short vdd)
1231 {
1232 struct mmc_host *mmc = host->mmc;
1233 u8 pwr = 0;
1234
1235 if (mode != MMC_POWER_OFF) {
1236 switch (1 << vdd) {
1237 case MMC_VDD_165_195:
1238 pwr = SDHCI_POWER_180;
1239 break;
1240 case MMC_VDD_29_30:
1241 case MMC_VDD_30_31:
1242 pwr = SDHCI_POWER_300;
1243 break;
1244 case MMC_VDD_32_33:
1245 case MMC_VDD_33_34:
1246 pwr = SDHCI_POWER_330;
1247 break;
1248 default:
1249 WARN(1, "%s: Invalid vdd %#x\n",
1250 mmc_hostname(host->mmc), vdd);
1251 break;
1252 }
1253 }
1254
1255 if (host->pwr == pwr)
1256 return;
1257
1258 host->pwr = pwr;
1259
1260 if (pwr == 0) {
1261 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1262 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1263 sdhci_runtime_pm_bus_off(host);
1264 vdd = 0;
1265 } else {
1266 /*
1267 * Spec says that we should clear the power reg before setting
1268 * a new value. Some controllers don't seem to like this though.
1269 */
1270 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1271 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1272
1273 /*
1274 * At least the Marvell CaFe chip gets confused if we set the
1275 * voltage and set turn on power at the same time, so set the
1276 * voltage first.
1277 */
1278 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1279 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1280
1281 pwr |= SDHCI_POWER_ON;
1282
1283 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1284
1285 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1286 sdhci_runtime_pm_bus_on(host);
1287
1288 /*
1289 * Some controllers need an extra 10ms delay of 10ms before
1290 * they can apply clock after applying power
1291 */
1292 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1293 mdelay(10);
1294 }
1295
1296 if (!IS_ERR(mmc->supply.vmmc)) {
1297 spin_unlock_irq(&host->lock);
1298 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1299 spin_lock_irq(&host->lock);
1300 }
1301 }
1302
1303 /*****************************************************************************\
1304 * *
1305 * MMC callbacks *
1306 * *
1307 \*****************************************************************************/
1308
1309 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1310 {
1311 struct sdhci_host *host;
1312 int present;
1313 unsigned long flags;
1314
1315 host = mmc_priv(mmc);
1316
1317 sdhci_runtime_pm_get(host);
1318
1319 /* Firstly check card presence */
1320 present = mmc->ops->get_cd(mmc);
1321
1322 spin_lock_irqsave(&host->lock, flags);
1323
1324 WARN_ON(host->mrq != NULL);
1325
1326 #ifndef SDHCI_USE_LEDS_CLASS
1327 sdhci_activate_led(host);
1328 #endif
1329
1330 /*
1331 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1332 * requests if Auto-CMD12 is enabled.
1333 */
1334 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1335 if (mrq->stop) {
1336 mrq->data->stop = NULL;
1337 mrq->stop = NULL;
1338 }
1339 }
1340
1341 host->mrq = mrq;
1342
1343 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1344 host->mrq->cmd->error = -ENOMEDIUM;
1345 tasklet_schedule(&host->finish_tasklet);
1346 } else {
1347 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1348 sdhci_send_command(host, mrq->sbc);
1349 else
1350 sdhci_send_command(host, mrq->cmd);
1351 }
1352
1353 mmiowb();
1354 spin_unlock_irqrestore(&host->lock, flags);
1355 }
1356
1357 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1358 {
1359 u8 ctrl;
1360
1361 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1362 if (width == MMC_BUS_WIDTH_8) {
1363 ctrl &= ~SDHCI_CTRL_4BITBUS;
1364 if (host->version >= SDHCI_SPEC_300)
1365 ctrl |= SDHCI_CTRL_8BITBUS;
1366 } else {
1367 if (host->version >= SDHCI_SPEC_300)
1368 ctrl &= ~SDHCI_CTRL_8BITBUS;
1369 if (width == MMC_BUS_WIDTH_4)
1370 ctrl |= SDHCI_CTRL_4BITBUS;
1371 else
1372 ctrl &= ~SDHCI_CTRL_4BITBUS;
1373 }
1374 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1375 }
1376 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1377
1378 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1379 {
1380 u16 ctrl_2;
1381
1382 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1383 /* Select Bus Speed Mode for host */
1384 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1385 if ((timing == MMC_TIMING_MMC_HS200) ||
1386 (timing == MMC_TIMING_UHS_SDR104))
1387 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1388 else if (timing == MMC_TIMING_UHS_SDR12)
1389 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1390 else if (timing == MMC_TIMING_UHS_SDR25)
1391 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1392 else if (timing == MMC_TIMING_UHS_SDR50)
1393 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1394 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1395 (timing == MMC_TIMING_MMC_DDR52))
1396 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1397 else if (timing == MMC_TIMING_MMC_HS400)
1398 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1399 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1400 }
1401 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1402
1403 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1404 {
1405 unsigned long flags;
1406 u8 ctrl;
1407 struct mmc_host *mmc = host->mmc;
1408
1409 spin_lock_irqsave(&host->lock, flags);
1410
1411 if (host->flags & SDHCI_DEVICE_DEAD) {
1412 spin_unlock_irqrestore(&host->lock, flags);
1413 if (!IS_ERR(mmc->supply.vmmc) &&
1414 ios->power_mode == MMC_POWER_OFF)
1415 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1416 return;
1417 }
1418
1419 /*
1420 * Reset the chip on each power off.
1421 * Should clear out any weird states.
1422 */
1423 if (ios->power_mode == MMC_POWER_OFF) {
1424 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1425 sdhci_reinit(host);
1426 }
1427
1428 if (host->version >= SDHCI_SPEC_300 &&
1429 (ios->power_mode == MMC_POWER_UP) &&
1430 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1431 sdhci_enable_preset_value(host, false);
1432
1433 if (!ios->clock || ios->clock != host->clock) {
1434 host->ops->set_clock(host, ios->clock);
1435 host->clock = ios->clock;
1436
1437 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1438 host->clock) {
1439 host->timeout_clk = host->mmc->actual_clock ?
1440 host->mmc->actual_clock / 1000 :
1441 host->clock / 1000;
1442 host->mmc->max_busy_timeout =
1443 host->ops->get_max_timeout_count ?
1444 host->ops->get_max_timeout_count(host) :
1445 1 << 27;
1446 host->mmc->max_busy_timeout /= host->timeout_clk;
1447 }
1448 }
1449
1450 sdhci_set_power(host, ios->power_mode, ios->vdd);
1451
1452 if (host->ops->platform_send_init_74_clocks)
1453 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1454
1455 host->ops->set_bus_width(host, ios->bus_width);
1456
1457 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1458
1459 if ((ios->timing == MMC_TIMING_SD_HS ||
1460 ios->timing == MMC_TIMING_MMC_HS)
1461 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1462 ctrl |= SDHCI_CTRL_HISPD;
1463 else
1464 ctrl &= ~SDHCI_CTRL_HISPD;
1465
1466 if (host->version >= SDHCI_SPEC_300) {
1467 u16 clk, ctrl_2;
1468
1469 /* In case of UHS-I modes, set High Speed Enable */
1470 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1471 (ios->timing == MMC_TIMING_MMC_HS200) ||
1472 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1473 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1474 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1475 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1476 (ios->timing == MMC_TIMING_UHS_SDR25))
1477 ctrl |= SDHCI_CTRL_HISPD;
1478
1479 if (!host->preset_enabled) {
1480 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1481 /*
1482 * We only need to set Driver Strength if the
1483 * preset value enable is not set.
1484 */
1485 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1486 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1487 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1488 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1489 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1490 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1491 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1492 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1493 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1494 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1495 else {
1496 pr_warn("%s: invalid driver type, default to driver type B\n",
1497 mmc_hostname(mmc));
1498 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1499 }
1500
1501 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1502 } else {
1503 /*
1504 * According to SDHC Spec v3.00, if the Preset Value
1505 * Enable in the Host Control 2 register is set, we
1506 * need to reset SD Clock Enable before changing High
1507 * Speed Enable to avoid generating clock gliches.
1508 */
1509
1510 /* Reset SD Clock Enable */
1511 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1512 clk &= ~SDHCI_CLOCK_CARD_EN;
1513 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1514
1515 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1516
1517 /* Re-enable SD Clock */
1518 host->ops->set_clock(host, host->clock);
1519 }
1520
1521 /* Reset SD Clock Enable */
1522 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1523 clk &= ~SDHCI_CLOCK_CARD_EN;
1524 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1525
1526 host->ops->set_uhs_signaling(host, ios->timing);
1527 host->timing = ios->timing;
1528
1529 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1530 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1531 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1532 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1533 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1534 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1535 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1536 u16 preset;
1537
1538 sdhci_enable_preset_value(host, true);
1539 preset = sdhci_get_preset_value(host);
1540 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1541 >> SDHCI_PRESET_DRV_SHIFT;
1542 }
1543
1544 /* Re-enable SD Clock */
1545 host->ops->set_clock(host, host->clock);
1546 } else
1547 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1548
1549 /*
1550 * Some (ENE) controllers go apeshit on some ios operation,
1551 * signalling timeout and CRC errors even on CMD0. Resetting
1552 * it on each ios seems to solve the problem.
1553 */
1554 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1555 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1556
1557 mmiowb();
1558 spin_unlock_irqrestore(&host->lock, flags);
1559 }
1560
1561 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1562 {
1563 struct sdhci_host *host = mmc_priv(mmc);
1564
1565 sdhci_runtime_pm_get(host);
1566 sdhci_do_set_ios(host, ios);
1567 sdhci_runtime_pm_put(host);
1568 }
1569
1570 static int sdhci_do_get_cd(struct sdhci_host *host)
1571 {
1572 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1573
1574 if (host->flags & SDHCI_DEVICE_DEAD)
1575 return 0;
1576
1577 /* If nonremovable, assume that the card is always present. */
1578 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1579 return 1;
1580
1581 /*
1582 * Try slot gpio detect, if defined it take precedence
1583 * over build in controller functionality
1584 */
1585 if (!IS_ERR_VALUE(gpio_cd))
1586 return !!gpio_cd;
1587
1588 /* If polling, assume that the card is always present. */
1589 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1590 return 1;
1591
1592 /* Host native card detect */
1593 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1594 }
1595
1596 static int sdhci_get_cd(struct mmc_host *mmc)
1597 {
1598 struct sdhci_host *host = mmc_priv(mmc);
1599 int ret;
1600
1601 sdhci_runtime_pm_get(host);
1602 ret = sdhci_do_get_cd(host);
1603 sdhci_runtime_pm_put(host);
1604 return ret;
1605 }
1606
1607 static int sdhci_check_ro(struct sdhci_host *host)
1608 {
1609 unsigned long flags;
1610 int is_readonly;
1611
1612 spin_lock_irqsave(&host->lock, flags);
1613
1614 if (host->flags & SDHCI_DEVICE_DEAD)
1615 is_readonly = 0;
1616 else if (host->ops->get_ro)
1617 is_readonly = host->ops->get_ro(host);
1618 else
1619 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1620 & SDHCI_WRITE_PROTECT);
1621
1622 spin_unlock_irqrestore(&host->lock, flags);
1623
1624 /* This quirk needs to be replaced by a callback-function later */
1625 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1626 !is_readonly : is_readonly;
1627 }
1628
1629 #define SAMPLE_COUNT 5
1630
1631 static int sdhci_do_get_ro(struct sdhci_host *host)
1632 {
1633 int i, ro_count;
1634
1635 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1636 return sdhci_check_ro(host);
1637
1638 ro_count = 0;
1639 for (i = 0; i < SAMPLE_COUNT; i++) {
1640 if (sdhci_check_ro(host)) {
1641 if (++ro_count > SAMPLE_COUNT / 2)
1642 return 1;
1643 }
1644 msleep(30);
1645 }
1646 return 0;
1647 }
1648
1649 static void sdhci_hw_reset(struct mmc_host *mmc)
1650 {
1651 struct sdhci_host *host = mmc_priv(mmc);
1652
1653 if (host->ops && host->ops->hw_reset)
1654 host->ops->hw_reset(host);
1655 }
1656
1657 static int sdhci_get_ro(struct mmc_host *mmc)
1658 {
1659 struct sdhci_host *host = mmc_priv(mmc);
1660 int ret;
1661
1662 sdhci_runtime_pm_get(host);
1663 ret = sdhci_do_get_ro(host);
1664 sdhci_runtime_pm_put(host);
1665 return ret;
1666 }
1667
1668 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1669 {
1670 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1671 if (enable)
1672 host->ier |= SDHCI_INT_CARD_INT;
1673 else
1674 host->ier &= ~SDHCI_INT_CARD_INT;
1675
1676 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1677 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1678 mmiowb();
1679 }
1680 }
1681
1682 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1683 {
1684 struct sdhci_host *host = mmc_priv(mmc);
1685 unsigned long flags;
1686
1687 sdhci_runtime_pm_get(host);
1688
1689 spin_lock_irqsave(&host->lock, flags);
1690 if (enable)
1691 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1692 else
1693 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1694
1695 sdhci_enable_sdio_irq_nolock(host, enable);
1696 spin_unlock_irqrestore(&host->lock, flags);
1697
1698 sdhci_runtime_pm_put(host);
1699 }
1700
1701 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1702 struct mmc_ios *ios)
1703 {
1704 struct mmc_host *mmc = host->mmc;
1705 u16 ctrl;
1706 int ret;
1707
1708 /*
1709 * Signal Voltage Switching is only applicable for Host Controllers
1710 * v3.00 and above.
1711 */
1712 if (host->version < SDHCI_SPEC_300)
1713 return 0;
1714
1715 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1716
1717 switch (ios->signal_voltage) {
1718 case MMC_SIGNAL_VOLTAGE_330:
1719 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1720 ctrl &= ~SDHCI_CTRL_VDD_180;
1721 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1722
1723 if (!IS_ERR(mmc->supply.vqmmc)) {
1724 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1725 3600000);
1726 if (ret) {
1727 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1728 mmc_hostname(mmc));
1729 return -EIO;
1730 }
1731 }
1732 /* Wait for 5ms */
1733 usleep_range(5000, 5500);
1734
1735 /* 3.3V regulator output should be stable within 5 ms */
1736 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1737 if (!(ctrl & SDHCI_CTRL_VDD_180))
1738 return 0;
1739
1740 pr_warn("%s: 3.3V regulator output did not became stable\n",
1741 mmc_hostname(mmc));
1742
1743 return -EAGAIN;
1744 case MMC_SIGNAL_VOLTAGE_180:
1745 if (!IS_ERR(mmc->supply.vqmmc)) {
1746 ret = regulator_set_voltage(mmc->supply.vqmmc,
1747 1700000, 1950000);
1748 if (ret) {
1749 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1750 mmc_hostname(mmc));
1751 return -EIO;
1752 }
1753 }
1754
1755 /*
1756 * Enable 1.8V Signal Enable in the Host Control2
1757 * register
1758 */
1759 ctrl |= SDHCI_CTRL_VDD_180;
1760 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1761
1762 /* Some controller need to do more when switching */
1763 if (host->ops->voltage_switch)
1764 host->ops->voltage_switch(host);
1765
1766 /* 1.8V regulator output should be stable within 5 ms */
1767 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1768 if (ctrl & SDHCI_CTRL_VDD_180)
1769 return 0;
1770
1771 pr_warn("%s: 1.8V regulator output did not became stable\n",
1772 mmc_hostname(mmc));
1773
1774 return -EAGAIN;
1775 case MMC_SIGNAL_VOLTAGE_120:
1776 if (!IS_ERR(mmc->supply.vqmmc)) {
1777 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1778 1300000);
1779 if (ret) {
1780 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1781 mmc_hostname(mmc));
1782 return -EIO;
1783 }
1784 }
1785 return 0;
1786 default:
1787 /* No signal voltage switch required */
1788 return 0;
1789 }
1790 }
1791
1792 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1793 struct mmc_ios *ios)
1794 {
1795 struct sdhci_host *host = mmc_priv(mmc);
1796 int err;
1797
1798 if (host->version < SDHCI_SPEC_300)
1799 return 0;
1800 sdhci_runtime_pm_get(host);
1801 err = sdhci_do_start_signal_voltage_switch(host, ios);
1802 sdhci_runtime_pm_put(host);
1803 return err;
1804 }
1805
1806 static int sdhci_card_busy(struct mmc_host *mmc)
1807 {
1808 struct sdhci_host *host = mmc_priv(mmc);
1809 u32 present_state;
1810
1811 sdhci_runtime_pm_get(host);
1812 /* Check whether DAT[3:0] is 0000 */
1813 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1814 sdhci_runtime_pm_put(host);
1815
1816 return !(present_state & SDHCI_DATA_LVL_MASK);
1817 }
1818
1819 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1820 {
1821 struct sdhci_host *host = mmc_priv(mmc);
1822 unsigned long flags;
1823
1824 spin_lock_irqsave(&host->lock, flags);
1825 host->flags |= SDHCI_HS400_TUNING;
1826 spin_unlock_irqrestore(&host->lock, flags);
1827
1828 return 0;
1829 }
1830
1831 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1832 {
1833 struct sdhci_host *host = mmc_priv(mmc);
1834 u16 ctrl;
1835 int tuning_loop_counter = MAX_TUNING_LOOP;
1836 int err = 0;
1837 unsigned long flags;
1838 unsigned int tuning_count = 0;
1839 bool hs400_tuning;
1840
1841 sdhci_runtime_pm_get(host);
1842 spin_lock_irqsave(&host->lock, flags);
1843
1844 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1845 host->flags &= ~SDHCI_HS400_TUNING;
1846
1847 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1848 tuning_count = host->tuning_count;
1849
1850 /*
1851 * The Host Controller needs tuning in case of SDR104 and DDR50
1852 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1853 * the Capabilities register.
1854 * If the Host Controller supports the HS200 mode then the
1855 * tuning function has to be executed.
1856 */
1857 switch (host->timing) {
1858 /* HS400 tuning is done in HS200 mode */
1859 case MMC_TIMING_MMC_HS400:
1860 err = -EINVAL;
1861 goto out_unlock;
1862
1863 case MMC_TIMING_MMC_HS200:
1864 /*
1865 * Periodic re-tuning for HS400 is not expected to be needed, so
1866 * disable it here.
1867 */
1868 if (hs400_tuning)
1869 tuning_count = 0;
1870 break;
1871
1872 case MMC_TIMING_UHS_SDR104:
1873 case MMC_TIMING_UHS_DDR50:
1874 break;
1875
1876 case MMC_TIMING_UHS_SDR50:
1877 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1878 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1879 break;
1880 /* FALLTHROUGH */
1881
1882 default:
1883 goto out_unlock;
1884 }
1885
1886 if (host->ops->platform_execute_tuning) {
1887 spin_unlock_irqrestore(&host->lock, flags);
1888 err = host->ops->platform_execute_tuning(host, opcode);
1889 sdhci_runtime_pm_put(host);
1890 return err;
1891 }
1892
1893 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1894 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1895 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1896 ctrl |= SDHCI_CTRL_TUNED_CLK;
1897 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1898
1899 /*
1900 * As per the Host Controller spec v3.00, tuning command
1901 * generates Buffer Read Ready interrupt, so enable that.
1902 *
1903 * Note: The spec clearly says that when tuning sequence
1904 * is being performed, the controller does not generate
1905 * interrupts other than Buffer Read Ready interrupt. But
1906 * to make sure we don't hit a controller bug, we _only_
1907 * enable Buffer Read Ready interrupt here.
1908 */
1909 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1910 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1911
1912 /*
1913 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1914 * of loops reaches 40 times or a timeout of 150ms occurs.
1915 */
1916 do {
1917 struct mmc_command cmd = {0};
1918 struct mmc_request mrq = {NULL};
1919
1920 cmd.opcode = opcode;
1921 cmd.arg = 0;
1922 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1923 cmd.retries = 0;
1924 cmd.data = NULL;
1925 cmd.error = 0;
1926
1927 if (tuning_loop_counter-- == 0)
1928 break;
1929
1930 mrq.cmd = &cmd;
1931 host->mrq = &mrq;
1932
1933 /*
1934 * In response to CMD19, the card sends 64 bytes of tuning
1935 * block to the Host Controller. So we set the block size
1936 * to 64 here.
1937 */
1938 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1939 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1940 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1941 SDHCI_BLOCK_SIZE);
1942 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1943 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1944 SDHCI_BLOCK_SIZE);
1945 } else {
1946 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1947 SDHCI_BLOCK_SIZE);
1948 }
1949
1950 /*
1951 * The tuning block is sent by the card to the host controller.
1952 * So we set the TRNS_READ bit in the Transfer Mode register.
1953 * This also takes care of setting DMA Enable and Multi Block
1954 * Select in the same register to 0.
1955 */
1956 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1957
1958 sdhci_send_command(host, &cmd);
1959
1960 host->cmd = NULL;
1961 host->mrq = NULL;
1962
1963 spin_unlock_irqrestore(&host->lock, flags);
1964 /* Wait for Buffer Read Ready interrupt */
1965 wait_event_interruptible_timeout(host->buf_ready_int,
1966 (host->tuning_done == 1),
1967 msecs_to_jiffies(50));
1968 spin_lock_irqsave(&host->lock, flags);
1969
1970 if (!host->tuning_done) {
1971 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
1972 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1973 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1974 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1975 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1976
1977 err = -EIO;
1978 goto out;
1979 }
1980
1981 host->tuning_done = 0;
1982
1983 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1984
1985 /* eMMC spec does not require a delay between tuning cycles */
1986 if (opcode == MMC_SEND_TUNING_BLOCK)
1987 mdelay(1);
1988 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1989
1990 /*
1991 * The Host Driver has exhausted the maximum number of loops allowed,
1992 * so use fixed sampling frequency.
1993 */
1994 if (tuning_loop_counter < 0) {
1995 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1996 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1997 }
1998 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1999 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2000 err = -EIO;
2001 }
2002
2003 out:
2004 if (tuning_count) {
2005 /*
2006 * In case tuning fails, host controllers which support
2007 * re-tuning can try tuning again at a later time, when the
2008 * re-tuning timer expires. So for these controllers, we
2009 * return 0. Since there might be other controllers who do not
2010 * have this capability, we return error for them.
2011 */
2012 err = 0;
2013 }
2014
2015 host->mmc->retune_period = err ? 0 : tuning_count;
2016
2017 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2018 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2019 out_unlock:
2020 spin_unlock_irqrestore(&host->lock, flags);
2021 sdhci_runtime_pm_put(host);
2022
2023 return err;
2024 }
2025
2026 static int sdhci_select_drive_strength(struct mmc_card *card,
2027 unsigned int max_dtr, int host_drv,
2028 int card_drv, int *drv_type)
2029 {
2030 struct sdhci_host *host = mmc_priv(card->host);
2031
2032 if (!host->ops->select_drive_strength)
2033 return 0;
2034
2035 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2036 card_drv, drv_type);
2037 }
2038
2039 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2040 {
2041 /* Host Controller v3.00 defines preset value registers */
2042 if (host->version < SDHCI_SPEC_300)
2043 return;
2044
2045 /*
2046 * We only enable or disable Preset Value if they are not already
2047 * enabled or disabled respectively. Otherwise, we bail out.
2048 */
2049 if (host->preset_enabled != enable) {
2050 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2051
2052 if (enable)
2053 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2054 else
2055 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2056
2057 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2058
2059 if (enable)
2060 host->flags |= SDHCI_PV_ENABLED;
2061 else
2062 host->flags &= ~SDHCI_PV_ENABLED;
2063
2064 host->preset_enabled = enable;
2065 }
2066 }
2067
2068 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2069 int err)
2070 {
2071 struct sdhci_host *host = mmc_priv(mmc);
2072 struct mmc_data *data = mrq->data;
2073
2074 if (data->host_cookie == COOKIE_GIVEN ||
2075 data->host_cookie == COOKIE_MAPPED)
2076 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2077 data->flags & MMC_DATA_WRITE ?
2078 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2079
2080 data->host_cookie = COOKIE_UNMAPPED;
2081 }
2082
2083 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2084 struct mmc_data *data)
2085 {
2086 int sg_count;
2087
2088 if (data->host_cookie == COOKIE_MAPPED) {
2089 data->host_cookie = COOKIE_GIVEN;
2090 return data->sg_count;
2091 }
2092
2093 WARN_ON(data->host_cookie == COOKIE_GIVEN);
2094
2095 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2096 data->flags & MMC_DATA_WRITE ?
2097 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2098
2099 if (sg_count == 0)
2100 return -ENOSPC;
2101
2102 data->sg_count = sg_count;
2103 data->host_cookie = COOKIE_MAPPED;
2104
2105 return sg_count;
2106 }
2107
2108 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2109 bool is_first_req)
2110 {
2111 struct sdhci_host *host = mmc_priv(mmc);
2112
2113 mrq->data->host_cookie = COOKIE_UNMAPPED;
2114
2115 if (host->flags & SDHCI_REQ_USE_DMA)
2116 sdhci_pre_dma_transfer(host, mrq->data);
2117 }
2118
2119 static void sdhci_card_event(struct mmc_host *mmc)
2120 {
2121 struct sdhci_host *host = mmc_priv(mmc);
2122 unsigned long flags;
2123 int present;
2124
2125 /* First check if client has provided their own card event */
2126 if (host->ops->card_event)
2127 host->ops->card_event(host);
2128
2129 present = sdhci_do_get_cd(host);
2130
2131 spin_lock_irqsave(&host->lock, flags);
2132
2133 /* Check host->mrq first in case we are runtime suspended */
2134 if (host->mrq && !present) {
2135 pr_err("%s: Card removed during transfer!\n",
2136 mmc_hostname(host->mmc));
2137 pr_err("%s: Resetting controller.\n",
2138 mmc_hostname(host->mmc));
2139
2140 sdhci_do_reset(host, SDHCI_RESET_CMD);
2141 sdhci_do_reset(host, SDHCI_RESET_DATA);
2142
2143 host->mrq->cmd->error = -ENOMEDIUM;
2144 tasklet_schedule(&host->finish_tasklet);
2145 }
2146
2147 spin_unlock_irqrestore(&host->lock, flags);
2148 }
2149
2150 static const struct mmc_host_ops sdhci_ops = {
2151 .request = sdhci_request,
2152 .post_req = sdhci_post_req,
2153 .pre_req = sdhci_pre_req,
2154 .set_ios = sdhci_set_ios,
2155 .get_cd = sdhci_get_cd,
2156 .get_ro = sdhci_get_ro,
2157 .hw_reset = sdhci_hw_reset,
2158 .enable_sdio_irq = sdhci_enable_sdio_irq,
2159 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2160 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2161 .execute_tuning = sdhci_execute_tuning,
2162 .select_drive_strength = sdhci_select_drive_strength,
2163 .card_event = sdhci_card_event,
2164 .card_busy = sdhci_card_busy,
2165 };
2166
2167 /*****************************************************************************\
2168 * *
2169 * Tasklets *
2170 * *
2171 \*****************************************************************************/
2172
2173 static void sdhci_tasklet_finish(unsigned long param)
2174 {
2175 struct sdhci_host *host;
2176 unsigned long flags;
2177 struct mmc_request *mrq;
2178
2179 host = (struct sdhci_host*)param;
2180
2181 spin_lock_irqsave(&host->lock, flags);
2182
2183 /*
2184 * If this tasklet gets rescheduled while running, it will
2185 * be run again afterwards but without any active request.
2186 */
2187 if (!host->mrq) {
2188 spin_unlock_irqrestore(&host->lock, flags);
2189 return;
2190 }
2191
2192 del_timer(&host->timer);
2193
2194 mrq = host->mrq;
2195
2196 /*
2197 * Always unmap the data buffers if they were mapped by
2198 * sdhci_prepare_data() whenever we finish with a request.
2199 * This avoids leaking DMA mappings on error.
2200 */
2201 if (host->flags & SDHCI_REQ_USE_DMA) {
2202 struct mmc_data *data = mrq->data;
2203
2204 if (data && data->host_cookie == COOKIE_MAPPED) {
2205 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2206 (data->flags & MMC_DATA_READ) ?
2207 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2208 data->host_cookie = COOKIE_UNMAPPED;
2209 }
2210 }
2211
2212 /*
2213 * The controller needs a reset of internal state machines
2214 * upon error conditions.
2215 */
2216 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2217 ((mrq->cmd && mrq->cmd->error) ||
2218 (mrq->sbc && mrq->sbc->error) ||
2219 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2220 (mrq->data->stop && mrq->data->stop->error))) ||
2221 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2222
2223 /* Some controllers need this kick or reset won't work here */
2224 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2225 /* This is to force an update */
2226 host->ops->set_clock(host, host->clock);
2227
2228 /* Spec says we should do both at the same time, but Ricoh
2229 controllers do not like that. */
2230 sdhci_do_reset(host, SDHCI_RESET_CMD);
2231 sdhci_do_reset(host, SDHCI_RESET_DATA);
2232 }
2233
2234 host->mrq = NULL;
2235 host->cmd = NULL;
2236 host->data = NULL;
2237
2238 #ifndef SDHCI_USE_LEDS_CLASS
2239 sdhci_deactivate_led(host);
2240 #endif
2241
2242 mmiowb();
2243 spin_unlock_irqrestore(&host->lock, flags);
2244
2245 mmc_request_done(host->mmc, mrq);
2246 sdhci_runtime_pm_put(host);
2247 }
2248
2249 static void sdhci_timeout_timer(unsigned long data)
2250 {
2251 struct sdhci_host *host;
2252 unsigned long flags;
2253
2254 host = (struct sdhci_host*)data;
2255
2256 spin_lock_irqsave(&host->lock, flags);
2257
2258 if (host->mrq) {
2259 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2260 mmc_hostname(host->mmc));
2261 sdhci_dumpregs(host);
2262
2263 if (host->data) {
2264 host->data->error = -ETIMEDOUT;
2265 sdhci_finish_data(host);
2266 } else {
2267 if (host->cmd)
2268 host->cmd->error = -ETIMEDOUT;
2269 else
2270 host->mrq->cmd->error = -ETIMEDOUT;
2271
2272 tasklet_schedule(&host->finish_tasklet);
2273 }
2274 }
2275
2276 mmiowb();
2277 spin_unlock_irqrestore(&host->lock, flags);
2278 }
2279
2280 /*****************************************************************************\
2281 * *
2282 * Interrupt handling *
2283 * *
2284 \*****************************************************************************/
2285
2286 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2287 {
2288 BUG_ON(intmask == 0);
2289
2290 if (!host->cmd) {
2291 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2292 mmc_hostname(host->mmc), (unsigned)intmask);
2293 sdhci_dumpregs(host);
2294 return;
2295 }
2296
2297 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2298 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2299 if (intmask & SDHCI_INT_TIMEOUT)
2300 host->cmd->error = -ETIMEDOUT;
2301 else
2302 host->cmd->error = -EILSEQ;
2303
2304 /*
2305 * If this command initiates a data phase and a response
2306 * CRC error is signalled, the card can start transferring
2307 * data - the card may have received the command without
2308 * error. We must not terminate the mmc_request early.
2309 *
2310 * If the card did not receive the command or returned an
2311 * error which prevented it sending data, the data phase
2312 * will time out.
2313 */
2314 if (host->cmd->data &&
2315 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2316 SDHCI_INT_CRC) {
2317 host->cmd = NULL;
2318 return;
2319 }
2320
2321 tasklet_schedule(&host->finish_tasklet);
2322 return;
2323 }
2324
2325 /*
2326 * The host can send and interrupt when the busy state has
2327 * ended, allowing us to wait without wasting CPU cycles.
2328 * Unfortunately this is overloaded on the "data complete"
2329 * interrupt, so we need to take some care when handling
2330 * it.
2331 *
2332 * Note: The 1.0 specification is a bit ambiguous about this
2333 * feature so there might be some problems with older
2334 * controllers.
2335 */
2336 if (host->cmd->flags & MMC_RSP_BUSY) {
2337 if (host->cmd->data)
2338 DBG("Cannot wait for busy signal when also doing a data transfer");
2339 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2340 && !host->busy_handle) {
2341 /* Mark that command complete before busy is ended */
2342 host->busy_handle = 1;
2343 return;
2344 }
2345
2346 /* The controller does not support the end-of-busy IRQ,
2347 * fall through and take the SDHCI_INT_RESPONSE */
2348 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2349 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2350 *mask &= ~SDHCI_INT_DATA_END;
2351 }
2352
2353 if (intmask & SDHCI_INT_RESPONSE)
2354 sdhci_finish_command(host);
2355 }
2356
2357 #ifdef CONFIG_MMC_DEBUG
2358 static void sdhci_adma_show_error(struct sdhci_host *host)
2359 {
2360 const char *name = mmc_hostname(host->mmc);
2361 void *desc = host->adma_table;
2362
2363 sdhci_dumpregs(host);
2364
2365 while (true) {
2366 struct sdhci_adma2_64_desc *dma_desc = desc;
2367
2368 if (host->flags & SDHCI_USE_64_BIT_DMA)
2369 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2370 name, desc, le32_to_cpu(dma_desc->addr_hi),
2371 le32_to_cpu(dma_desc->addr_lo),
2372 le16_to_cpu(dma_desc->len),
2373 le16_to_cpu(dma_desc->cmd));
2374 else
2375 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2376 name, desc, le32_to_cpu(dma_desc->addr_lo),
2377 le16_to_cpu(dma_desc->len),
2378 le16_to_cpu(dma_desc->cmd));
2379
2380 desc += host->desc_sz;
2381
2382 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2383 break;
2384 }
2385 }
2386 #else
2387 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2388 #endif
2389
2390 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2391 {
2392 u32 command;
2393 BUG_ON(intmask == 0);
2394
2395 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2396 if (intmask & SDHCI_INT_DATA_AVAIL) {
2397 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2398 if (command == MMC_SEND_TUNING_BLOCK ||
2399 command == MMC_SEND_TUNING_BLOCK_HS200) {
2400 host->tuning_done = 1;
2401 wake_up(&host->buf_ready_int);
2402 return;
2403 }
2404 }
2405
2406 if (!host->data) {
2407 /*
2408 * The "data complete" interrupt is also used to
2409 * indicate that a busy state has ended. See comment
2410 * above in sdhci_cmd_irq().
2411 */
2412 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2413 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2414 host->cmd->error = -ETIMEDOUT;
2415 tasklet_schedule(&host->finish_tasklet);
2416 return;
2417 }
2418 if (intmask & SDHCI_INT_DATA_END) {
2419 /*
2420 * Some cards handle busy-end interrupt
2421 * before the command completed, so make
2422 * sure we do things in the proper order.
2423 */
2424 if (host->busy_handle)
2425 sdhci_finish_command(host);
2426 else
2427 host->busy_handle = 1;
2428 return;
2429 }
2430 }
2431
2432 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2433 mmc_hostname(host->mmc), (unsigned)intmask);
2434 sdhci_dumpregs(host);
2435
2436 return;
2437 }
2438
2439 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2440 host->data->error = -ETIMEDOUT;
2441 else if (intmask & SDHCI_INT_DATA_END_BIT)
2442 host->data->error = -EILSEQ;
2443 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2444 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2445 != MMC_BUS_TEST_R)
2446 host->data->error = -EILSEQ;
2447 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2448 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2449 sdhci_adma_show_error(host);
2450 host->data->error = -EIO;
2451 if (host->ops->adma_workaround)
2452 host->ops->adma_workaround(host, intmask);
2453 }
2454
2455 if (host->data->error)
2456 sdhci_finish_data(host);
2457 else {
2458 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2459 sdhci_transfer_pio(host);
2460
2461 /*
2462 * We currently don't do anything fancy with DMA
2463 * boundaries, but as we can't disable the feature
2464 * we need to at least restart the transfer.
2465 *
2466 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2467 * should return a valid address to continue from, but as
2468 * some controllers are faulty, don't trust them.
2469 */
2470 if (intmask & SDHCI_INT_DMA_END) {
2471 u32 dmastart, dmanow;
2472 dmastart = sg_dma_address(host->data->sg);
2473 dmanow = dmastart + host->data->bytes_xfered;
2474 /*
2475 * Force update to the next DMA block boundary.
2476 */
2477 dmanow = (dmanow &
2478 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2479 SDHCI_DEFAULT_BOUNDARY_SIZE;
2480 host->data->bytes_xfered = dmanow - dmastart;
2481 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2482 " next 0x%08x\n",
2483 mmc_hostname(host->mmc), dmastart,
2484 host->data->bytes_xfered, dmanow);
2485 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2486 }
2487
2488 if (intmask & SDHCI_INT_DATA_END) {
2489 if (host->cmd) {
2490 /*
2491 * Data managed to finish before the
2492 * command completed. Make sure we do
2493 * things in the proper order.
2494 */
2495 host->data_early = 1;
2496 } else {
2497 sdhci_finish_data(host);
2498 }
2499 }
2500 }
2501 }
2502
2503 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2504 {
2505 irqreturn_t result = IRQ_NONE;
2506 struct sdhci_host *host = dev_id;
2507 u32 intmask, mask, unexpected = 0;
2508 int max_loops = 16;
2509
2510 spin_lock(&host->lock);
2511
2512 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2513 spin_unlock(&host->lock);
2514 return IRQ_NONE;
2515 }
2516
2517 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2518 if (!intmask || intmask == 0xffffffff) {
2519 result = IRQ_NONE;
2520 goto out;
2521 }
2522
2523 do {
2524 /* Clear selected interrupts. */
2525 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2526 SDHCI_INT_BUS_POWER);
2527 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2528
2529 DBG("*** %s got interrupt: 0x%08x\n",
2530 mmc_hostname(host->mmc), intmask);
2531
2532 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2533 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2534 SDHCI_CARD_PRESENT;
2535
2536 /*
2537 * There is a observation on i.mx esdhc. INSERT
2538 * bit will be immediately set again when it gets
2539 * cleared, if a card is inserted. We have to mask
2540 * the irq to prevent interrupt storm which will
2541 * freeze the system. And the REMOVE gets the
2542 * same situation.
2543 *
2544 * More testing are needed here to ensure it works
2545 * for other platforms though.
2546 */
2547 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2548 SDHCI_INT_CARD_REMOVE);
2549 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2550 SDHCI_INT_CARD_INSERT;
2551 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2552 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2553
2554 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2555 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2556
2557 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2558 SDHCI_INT_CARD_REMOVE);
2559 result = IRQ_WAKE_THREAD;
2560 }
2561
2562 if (intmask & SDHCI_INT_CMD_MASK)
2563 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2564 &intmask);
2565
2566 if (intmask & SDHCI_INT_DATA_MASK)
2567 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2568
2569 if (intmask & SDHCI_INT_BUS_POWER)
2570 pr_err("%s: Card is consuming too much power!\n",
2571 mmc_hostname(host->mmc));
2572
2573 if (intmask & SDHCI_INT_CARD_INT) {
2574 sdhci_enable_sdio_irq_nolock(host, false);
2575 host->thread_isr |= SDHCI_INT_CARD_INT;
2576 result = IRQ_WAKE_THREAD;
2577 }
2578
2579 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2580 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2581 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2582 SDHCI_INT_CARD_INT);
2583
2584 if (intmask) {
2585 unexpected |= intmask;
2586 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2587 }
2588
2589 if (result == IRQ_NONE)
2590 result = IRQ_HANDLED;
2591
2592 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2593 } while (intmask && --max_loops);
2594 out:
2595 spin_unlock(&host->lock);
2596
2597 if (unexpected) {
2598 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2599 mmc_hostname(host->mmc), unexpected);
2600 sdhci_dumpregs(host);
2601 }
2602
2603 return result;
2604 }
2605
2606 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2607 {
2608 struct sdhci_host *host = dev_id;
2609 unsigned long flags;
2610 u32 isr;
2611
2612 spin_lock_irqsave(&host->lock, flags);
2613 isr = host->thread_isr;
2614 host->thread_isr = 0;
2615 spin_unlock_irqrestore(&host->lock, flags);
2616
2617 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2618 sdhci_card_event(host->mmc);
2619 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2620 }
2621
2622 if (isr & SDHCI_INT_CARD_INT) {
2623 sdio_run_irqs(host->mmc);
2624
2625 spin_lock_irqsave(&host->lock, flags);
2626 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2627 sdhci_enable_sdio_irq_nolock(host, true);
2628 spin_unlock_irqrestore(&host->lock, flags);
2629 }
2630
2631 return isr ? IRQ_HANDLED : IRQ_NONE;
2632 }
2633
2634 /*****************************************************************************\
2635 * *
2636 * Suspend/resume *
2637 * *
2638 \*****************************************************************************/
2639
2640 #ifdef CONFIG_PM
2641 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2642 {
2643 u8 val;
2644 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2645 | SDHCI_WAKE_ON_INT;
2646
2647 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2648 val |= mask ;
2649 /* Avoid fake wake up */
2650 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2651 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2652 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2653 }
2654 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2655
2656 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2657 {
2658 u8 val;
2659 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2660 | SDHCI_WAKE_ON_INT;
2661
2662 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2663 val &= ~mask;
2664 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2665 }
2666
2667 int sdhci_suspend_host(struct sdhci_host *host)
2668 {
2669 sdhci_disable_card_detection(host);
2670
2671 mmc_retune_timer_stop(host->mmc);
2672 mmc_retune_needed(host->mmc);
2673
2674 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2675 host->ier = 0;
2676 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2677 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2678 free_irq(host->irq, host);
2679 } else {
2680 sdhci_enable_irq_wakeups(host);
2681 enable_irq_wake(host->irq);
2682 }
2683 return 0;
2684 }
2685
2686 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2687
2688 int sdhci_resume_host(struct sdhci_host *host)
2689 {
2690 int ret = 0;
2691
2692 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2693 if (host->ops->enable_dma)
2694 host->ops->enable_dma(host);
2695 }
2696
2697 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2698 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2699 /* Card keeps power but host controller does not */
2700 sdhci_init(host, 0);
2701 host->pwr = 0;
2702 host->clock = 0;
2703 sdhci_do_set_ios(host, &host->mmc->ios);
2704 } else {
2705 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2706 mmiowb();
2707 }
2708
2709 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2710 ret = request_threaded_irq(host->irq, sdhci_irq,
2711 sdhci_thread_irq, IRQF_SHARED,
2712 mmc_hostname(host->mmc), host);
2713 if (ret)
2714 return ret;
2715 } else {
2716 sdhci_disable_irq_wakeups(host);
2717 disable_irq_wake(host->irq);
2718 }
2719
2720 sdhci_enable_card_detection(host);
2721
2722 return ret;
2723 }
2724
2725 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2726
2727 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2728 {
2729 return pm_runtime_get_sync(host->mmc->parent);
2730 }
2731
2732 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2733 {
2734 pm_runtime_mark_last_busy(host->mmc->parent);
2735 return pm_runtime_put_autosuspend(host->mmc->parent);
2736 }
2737
2738 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2739 {
2740 if (host->bus_on)
2741 return;
2742 host->bus_on = true;
2743 pm_runtime_get_noresume(host->mmc->parent);
2744 }
2745
2746 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2747 {
2748 if (!host->bus_on)
2749 return;
2750 host->bus_on = false;
2751 pm_runtime_put_noidle(host->mmc->parent);
2752 }
2753
2754 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2755 {
2756 unsigned long flags;
2757
2758 mmc_retune_timer_stop(host->mmc);
2759 mmc_retune_needed(host->mmc);
2760
2761 spin_lock_irqsave(&host->lock, flags);
2762 host->ier &= SDHCI_INT_CARD_INT;
2763 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2764 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2765 spin_unlock_irqrestore(&host->lock, flags);
2766
2767 synchronize_hardirq(host->irq);
2768
2769 spin_lock_irqsave(&host->lock, flags);
2770 host->runtime_suspended = true;
2771 spin_unlock_irqrestore(&host->lock, flags);
2772
2773 return 0;
2774 }
2775 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2776
2777 int sdhci_runtime_resume_host(struct sdhci_host *host)
2778 {
2779 unsigned long flags;
2780 int host_flags = host->flags;
2781
2782 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2783 if (host->ops->enable_dma)
2784 host->ops->enable_dma(host);
2785 }
2786
2787 sdhci_init(host, 0);
2788
2789 /* Force clock and power re-program */
2790 host->pwr = 0;
2791 host->clock = 0;
2792 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2793 sdhci_do_set_ios(host, &host->mmc->ios);
2794
2795 if ((host_flags & SDHCI_PV_ENABLED) &&
2796 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2797 spin_lock_irqsave(&host->lock, flags);
2798 sdhci_enable_preset_value(host, true);
2799 spin_unlock_irqrestore(&host->lock, flags);
2800 }
2801
2802 spin_lock_irqsave(&host->lock, flags);
2803
2804 host->runtime_suspended = false;
2805
2806 /* Enable SDIO IRQ */
2807 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2808 sdhci_enable_sdio_irq_nolock(host, true);
2809
2810 /* Enable Card Detection */
2811 sdhci_enable_card_detection(host);
2812
2813 spin_unlock_irqrestore(&host->lock, flags);
2814
2815 return 0;
2816 }
2817 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2818
2819 #endif /* CONFIG_PM */
2820
2821 /*****************************************************************************\
2822 * *
2823 * Device allocation/registration *
2824 * *
2825 \*****************************************************************************/
2826
2827 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2828 size_t priv_size)
2829 {
2830 struct mmc_host *mmc;
2831 struct sdhci_host *host;
2832
2833 WARN_ON(dev == NULL);
2834
2835 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2836 if (!mmc)
2837 return ERR_PTR(-ENOMEM);
2838
2839 host = mmc_priv(mmc);
2840 host->mmc = mmc;
2841 host->mmc_host_ops = sdhci_ops;
2842 mmc->ops = &host->mmc_host_ops;
2843
2844 return host;
2845 }
2846
2847 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2848
2849 int sdhci_add_host(struct sdhci_host *host)
2850 {
2851 struct mmc_host *mmc;
2852 u32 caps[2] = {0, 0};
2853 u32 max_current_caps;
2854 unsigned int ocr_avail;
2855 unsigned int override_timeout_clk;
2856 u32 max_clk;
2857 int ret;
2858
2859 WARN_ON(host == NULL);
2860 if (host == NULL)
2861 return -EINVAL;
2862
2863 mmc = host->mmc;
2864
2865 if (debug_quirks)
2866 host->quirks = debug_quirks;
2867 if (debug_quirks2)
2868 host->quirks2 = debug_quirks2;
2869
2870 override_timeout_clk = host->timeout_clk;
2871
2872 sdhci_do_reset(host, SDHCI_RESET_ALL);
2873
2874 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2875 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2876 >> SDHCI_SPEC_VER_SHIFT;
2877 if (host->version > SDHCI_SPEC_300) {
2878 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2879 mmc_hostname(mmc), host->version);
2880 }
2881
2882 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2883 sdhci_readl(host, SDHCI_CAPABILITIES);
2884
2885 if (host->version >= SDHCI_SPEC_300)
2886 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2887 host->caps1 :
2888 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2889
2890 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2891 host->flags |= SDHCI_USE_SDMA;
2892 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2893 DBG("Controller doesn't have SDMA capability\n");
2894 else
2895 host->flags |= SDHCI_USE_SDMA;
2896
2897 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2898 (host->flags & SDHCI_USE_SDMA)) {
2899 DBG("Disabling DMA as it is marked broken\n");
2900 host->flags &= ~SDHCI_USE_SDMA;
2901 }
2902
2903 if ((host->version >= SDHCI_SPEC_200) &&
2904 (caps[0] & SDHCI_CAN_DO_ADMA2))
2905 host->flags |= SDHCI_USE_ADMA;
2906
2907 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2908 (host->flags & SDHCI_USE_ADMA)) {
2909 DBG("Disabling ADMA as it is marked broken\n");
2910 host->flags &= ~SDHCI_USE_ADMA;
2911 }
2912
2913 /*
2914 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2915 * and *must* do 64-bit DMA. A driver has the opportunity to change
2916 * that during the first call to ->enable_dma(). Similarly
2917 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2918 * implement.
2919 */
2920 if (caps[0] & SDHCI_CAN_64BIT)
2921 host->flags |= SDHCI_USE_64_BIT_DMA;
2922
2923 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2924 if (host->ops->enable_dma) {
2925 if (host->ops->enable_dma(host)) {
2926 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2927 mmc_hostname(mmc));
2928 host->flags &=
2929 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2930 }
2931 }
2932 }
2933
2934 /* SDMA does not support 64-bit DMA */
2935 if (host->flags & SDHCI_USE_64_BIT_DMA)
2936 host->flags &= ~SDHCI_USE_SDMA;
2937
2938 if (host->flags & SDHCI_USE_ADMA) {
2939 dma_addr_t dma;
2940 void *buf;
2941
2942 /*
2943 * The DMA descriptor table size is calculated as the maximum
2944 * number of segments times 2, to allow for an alignment
2945 * descriptor for each segment, plus 1 for a nop end descriptor,
2946 * all multipled by the descriptor size.
2947 */
2948 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2949 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2950 SDHCI_ADMA2_64_DESC_SZ;
2951 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2952 } else {
2953 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2954 SDHCI_ADMA2_32_DESC_SZ;
2955 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2956 }
2957
2958 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
2959 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2960 host->adma_table_sz, &dma, GFP_KERNEL);
2961 if (!buf) {
2962 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2963 mmc_hostname(mmc));
2964 host->flags &= ~SDHCI_USE_ADMA;
2965 } else if ((dma + host->align_buffer_sz) &
2966 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
2967 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2968 mmc_hostname(mmc));
2969 host->flags &= ~SDHCI_USE_ADMA;
2970 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2971 host->adma_table_sz, buf, dma);
2972 } else {
2973 host->align_buffer = buf;
2974 host->align_addr = dma;
2975
2976 host->adma_table = buf + host->align_buffer_sz;
2977 host->adma_addr = dma + host->align_buffer_sz;
2978 }
2979 }
2980
2981 /*
2982 * If we use DMA, then it's up to the caller to set the DMA
2983 * mask, but PIO does not need the hw shim so we set a new
2984 * mask here in that case.
2985 */
2986 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2987 host->dma_mask = DMA_BIT_MASK(64);
2988 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2989 }
2990
2991 if (host->version >= SDHCI_SPEC_300)
2992 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2993 >> SDHCI_CLOCK_BASE_SHIFT;
2994 else
2995 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2996 >> SDHCI_CLOCK_BASE_SHIFT;
2997
2998 host->max_clk *= 1000000;
2999 if (host->max_clk == 0 || host->quirks &
3000 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3001 if (!host->ops->get_max_clock) {
3002 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3003 mmc_hostname(mmc));
3004 return -ENODEV;
3005 }
3006 host->max_clk = host->ops->get_max_clock(host);
3007 }
3008
3009 /*
3010 * In case of Host Controller v3.00, find out whether clock
3011 * multiplier is supported.
3012 */
3013 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3014 SDHCI_CLOCK_MUL_SHIFT;
3015
3016 /*
3017 * In case the value in Clock Multiplier is 0, then programmable
3018 * clock mode is not supported, otherwise the actual clock
3019 * multiplier is one more than the value of Clock Multiplier
3020 * in the Capabilities Register.
3021 */
3022 if (host->clk_mul)
3023 host->clk_mul += 1;
3024
3025 /*
3026 * Set host parameters.
3027 */
3028 max_clk = host->max_clk;
3029
3030 if (host->ops->get_min_clock)
3031 mmc->f_min = host->ops->get_min_clock(host);
3032 else if (host->version >= SDHCI_SPEC_300) {
3033 if (host->clk_mul) {
3034 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3035 max_clk = host->max_clk * host->clk_mul;
3036 } else
3037 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3038 } else
3039 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3040
3041 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3042 mmc->f_max = max_clk;
3043
3044 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3045 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3046 SDHCI_TIMEOUT_CLK_SHIFT;
3047 if (host->timeout_clk == 0) {
3048 if (host->ops->get_timeout_clock) {
3049 host->timeout_clk =
3050 host->ops->get_timeout_clock(host);
3051 } else {
3052 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3053 mmc_hostname(mmc));
3054 return -ENODEV;
3055 }
3056 }
3057
3058 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3059 host->timeout_clk *= 1000;
3060
3061 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3062 host->ops->get_max_timeout_count(host) : 1 << 27;
3063 mmc->max_busy_timeout /= host->timeout_clk;
3064 }
3065
3066 if (override_timeout_clk)
3067 host->timeout_clk = override_timeout_clk;
3068
3069 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3070 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3071
3072 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3073 host->flags |= SDHCI_AUTO_CMD12;
3074
3075 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3076 if ((host->version >= SDHCI_SPEC_300) &&
3077 ((host->flags & SDHCI_USE_ADMA) ||
3078 !(host->flags & SDHCI_USE_SDMA)) &&
3079 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3080 host->flags |= SDHCI_AUTO_CMD23;
3081 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3082 } else {
3083 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3084 }
3085
3086 /*
3087 * A controller may support 8-bit width, but the board itself
3088 * might not have the pins brought out. Boards that support
3089 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3090 * their platform code before calling sdhci_add_host(), and we
3091 * won't assume 8-bit width for hosts without that CAP.
3092 */
3093 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3094 mmc->caps |= MMC_CAP_4_BIT_DATA;
3095
3096 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3097 mmc->caps &= ~MMC_CAP_CMD23;
3098
3099 if (caps[0] & SDHCI_CAN_DO_HISPD)
3100 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3101
3102 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3103 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3104 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3105 mmc->caps |= MMC_CAP_NEEDS_POLL;
3106
3107 /* If there are external regulators, get them */
3108 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3109 return -EPROBE_DEFER;
3110
3111 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3112 if (!IS_ERR(mmc->supply.vqmmc)) {
3113 ret = regulator_enable(mmc->supply.vqmmc);
3114 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3115 1950000))
3116 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3117 SDHCI_SUPPORT_SDR50 |
3118 SDHCI_SUPPORT_DDR50);
3119 if (ret) {
3120 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3121 mmc_hostname(mmc), ret);
3122 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3123 }
3124 }
3125
3126 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3127 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3128 SDHCI_SUPPORT_DDR50);
3129
3130 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3131 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3132 SDHCI_SUPPORT_DDR50))
3133 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3134
3135 /* SDR104 supports also implies SDR50 support */
3136 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3137 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3138 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3139 * field can be promoted to support HS200.
3140 */
3141 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3142 mmc->caps2 |= MMC_CAP2_HS200;
3143 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3144 mmc->caps |= MMC_CAP_UHS_SDR50;
3145
3146 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3147 (caps[1] & SDHCI_SUPPORT_HS400))
3148 mmc->caps2 |= MMC_CAP2_HS400;
3149
3150 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3151 (IS_ERR(mmc->supply.vqmmc) ||
3152 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3153 1300000)))
3154 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3155
3156 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3157 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3158 mmc->caps |= MMC_CAP_UHS_DDR50;
3159
3160 /* Does the host need tuning for SDR50? */
3161 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3162 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3163
3164 /* Does the host need tuning for SDR104 / HS200? */
3165 if (mmc->caps2 & MMC_CAP2_HS200)
3166 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3167
3168 /* Driver Type(s) (A, C, D) supported by the host */
3169 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3170 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3171 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3172 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3173 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3174 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3175
3176 /* Initial value for re-tuning timer count */
3177 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3178 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3179
3180 /*
3181 * In case Re-tuning Timer is not disabled, the actual value of
3182 * re-tuning timer will be 2 ^ (n - 1).
3183 */
3184 if (host->tuning_count)
3185 host->tuning_count = 1 << (host->tuning_count - 1);
3186
3187 /* Re-tuning mode supported by the Host Controller */
3188 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3189 SDHCI_RETUNING_MODE_SHIFT;
3190
3191 ocr_avail = 0;
3192
3193 /*
3194 * According to SD Host Controller spec v3.00, if the Host System
3195 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3196 * the value is meaningful only if Voltage Support in the Capabilities
3197 * register is set. The actual current value is 4 times the register
3198 * value.
3199 */
3200 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3201 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3202 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3203 if (curr > 0) {
3204
3205 /* convert to SDHCI_MAX_CURRENT format */
3206 curr = curr/1000; /* convert to mA */
3207 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3208
3209 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3210 max_current_caps =
3211 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3212 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3213 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3214 }
3215 }
3216
3217 if (caps[0] & SDHCI_CAN_VDD_330) {
3218 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3219
3220 mmc->max_current_330 = ((max_current_caps &
3221 SDHCI_MAX_CURRENT_330_MASK) >>
3222 SDHCI_MAX_CURRENT_330_SHIFT) *
3223 SDHCI_MAX_CURRENT_MULTIPLIER;
3224 }
3225 if (caps[0] & SDHCI_CAN_VDD_300) {
3226 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3227
3228 mmc->max_current_300 = ((max_current_caps &
3229 SDHCI_MAX_CURRENT_300_MASK) >>
3230 SDHCI_MAX_CURRENT_300_SHIFT) *
3231 SDHCI_MAX_CURRENT_MULTIPLIER;
3232 }
3233 if (caps[0] & SDHCI_CAN_VDD_180) {
3234 ocr_avail |= MMC_VDD_165_195;
3235
3236 mmc->max_current_180 = ((max_current_caps &
3237 SDHCI_MAX_CURRENT_180_MASK) >>
3238 SDHCI_MAX_CURRENT_180_SHIFT) *
3239 SDHCI_MAX_CURRENT_MULTIPLIER;
3240 }
3241
3242 /* If OCR set by host, use it instead. */
3243 if (host->ocr_mask)
3244 ocr_avail = host->ocr_mask;
3245
3246 /* If OCR set by external regulators, give it highest prio. */
3247 if (mmc->ocr_avail)
3248 ocr_avail = mmc->ocr_avail;
3249
3250 mmc->ocr_avail = ocr_avail;
3251 mmc->ocr_avail_sdio = ocr_avail;
3252 if (host->ocr_avail_sdio)
3253 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3254 mmc->ocr_avail_sd = ocr_avail;
3255 if (host->ocr_avail_sd)
3256 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3257 else /* normal SD controllers don't support 1.8V */
3258 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3259 mmc->ocr_avail_mmc = ocr_avail;
3260 if (host->ocr_avail_mmc)
3261 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3262
3263 if (mmc->ocr_avail == 0) {
3264 pr_err("%s: Hardware doesn't report any support voltages.\n",
3265 mmc_hostname(mmc));
3266 return -ENODEV;
3267 }
3268
3269 spin_lock_init(&host->lock);
3270
3271 /*
3272 * Maximum number of segments. Depends on if the hardware
3273 * can do scatter/gather or not.
3274 */
3275 if (host->flags & SDHCI_USE_ADMA)
3276 mmc->max_segs = SDHCI_MAX_SEGS;
3277 else if (host->flags & SDHCI_USE_SDMA)
3278 mmc->max_segs = 1;
3279 else /* PIO */
3280 mmc->max_segs = SDHCI_MAX_SEGS;
3281
3282 /*
3283 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3284 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3285 * is less anyway.
3286 */
3287 mmc->max_req_size = 524288;
3288
3289 /*
3290 * Maximum segment size. Could be one segment with the maximum number
3291 * of bytes. When doing hardware scatter/gather, each entry cannot
3292 * be larger than 64 KiB though.
3293 */
3294 if (host->flags & SDHCI_USE_ADMA) {
3295 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3296 mmc->max_seg_size = 65535;
3297 else
3298 mmc->max_seg_size = 65536;
3299 } else {
3300 mmc->max_seg_size = mmc->max_req_size;
3301 }
3302
3303 /*
3304 * Maximum block size. This varies from controller to controller and
3305 * is specified in the capabilities register.
3306 */
3307 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3308 mmc->max_blk_size = 2;
3309 } else {
3310 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3311 SDHCI_MAX_BLOCK_SHIFT;
3312 if (mmc->max_blk_size >= 3) {
3313 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3314 mmc_hostname(mmc));
3315 mmc->max_blk_size = 0;
3316 }
3317 }
3318
3319 mmc->max_blk_size = 512 << mmc->max_blk_size;
3320
3321 /*
3322 * Maximum block count.
3323 */
3324 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3325
3326 /*
3327 * Init tasklets.
3328 */
3329 tasklet_init(&host->finish_tasklet,
3330 sdhci_tasklet_finish, (unsigned long)host);
3331
3332 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3333
3334 init_waitqueue_head(&host->buf_ready_int);
3335
3336 sdhci_init(host, 0);
3337
3338 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3339 IRQF_SHARED, mmc_hostname(mmc), host);
3340 if (ret) {
3341 pr_err("%s: Failed to request IRQ %d: %d\n",
3342 mmc_hostname(mmc), host->irq, ret);
3343 goto untasklet;
3344 }
3345
3346 #ifdef CONFIG_MMC_DEBUG
3347 sdhci_dumpregs(host);
3348 #endif
3349
3350 #ifdef SDHCI_USE_LEDS_CLASS
3351 snprintf(host->led_name, sizeof(host->led_name),
3352 "%s::", mmc_hostname(mmc));
3353 host->led.name = host->led_name;
3354 host->led.brightness = LED_OFF;
3355 host->led.default_trigger = mmc_hostname(mmc);
3356 host->led.brightness_set = sdhci_led_control;
3357
3358 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3359 if (ret) {
3360 pr_err("%s: Failed to register LED device: %d\n",
3361 mmc_hostname(mmc), ret);
3362 goto reset;
3363 }
3364 #endif
3365
3366 mmiowb();
3367
3368 mmc_add_host(mmc);
3369
3370 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3371 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3372 (host->flags & SDHCI_USE_ADMA) ?
3373 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3374 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3375
3376 sdhci_enable_card_detection(host);
3377
3378 return 0;
3379
3380 #ifdef SDHCI_USE_LEDS_CLASS
3381 reset:
3382 sdhci_do_reset(host, SDHCI_RESET_ALL);
3383 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3384 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3385 free_irq(host->irq, host);
3386 #endif
3387 untasklet:
3388 tasklet_kill(&host->finish_tasklet);
3389
3390 return ret;
3391 }
3392
3393 EXPORT_SYMBOL_GPL(sdhci_add_host);
3394
3395 void sdhci_remove_host(struct sdhci_host *host, int dead)
3396 {
3397 struct mmc_host *mmc = host->mmc;
3398 unsigned long flags;
3399
3400 if (dead) {
3401 spin_lock_irqsave(&host->lock, flags);
3402
3403 host->flags |= SDHCI_DEVICE_DEAD;
3404
3405 if (host->mrq) {
3406 pr_err("%s: Controller removed during "
3407 " transfer!\n", mmc_hostname(mmc));
3408
3409 host->mrq->cmd->error = -ENOMEDIUM;
3410 tasklet_schedule(&host->finish_tasklet);
3411 }
3412
3413 spin_unlock_irqrestore(&host->lock, flags);
3414 }
3415
3416 sdhci_disable_card_detection(host);
3417
3418 mmc_remove_host(mmc);
3419
3420 #ifdef SDHCI_USE_LEDS_CLASS
3421 led_classdev_unregister(&host->led);
3422 #endif
3423
3424 if (!dead)
3425 sdhci_do_reset(host, SDHCI_RESET_ALL);
3426
3427 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3428 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3429 free_irq(host->irq, host);
3430
3431 del_timer_sync(&host->timer);
3432
3433 tasklet_kill(&host->finish_tasklet);
3434
3435 if (!IS_ERR(mmc->supply.vqmmc))
3436 regulator_disable(mmc->supply.vqmmc);
3437
3438 if (host->align_buffer)
3439 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3440 host->adma_table_sz, host->align_buffer,
3441 host->align_addr);
3442
3443 host->adma_table = NULL;
3444 host->align_buffer = NULL;
3445 }
3446
3447 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3448
3449 void sdhci_free_host(struct sdhci_host *host)
3450 {
3451 mmc_free_host(host->mmc);
3452 }
3453
3454 EXPORT_SYMBOL_GPL(sdhci_free_host);
3455
3456 /*****************************************************************************\
3457 * *
3458 * Driver init/exit *
3459 * *
3460 \*****************************************************************************/
3461
3462 static int __init sdhci_drv_init(void)
3463 {
3464 pr_info(DRIVER_NAME
3465 ": Secure Digital Host Controller Interface driver\n");
3466 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3467
3468 return 0;
3469 }
3470
3471 static void __exit sdhci_drv_exit(void)
3472 {
3473 }
3474
3475 module_init(sdhci_drv_init);
3476 module_exit(sdhci_drv_exit);
3477
3478 module_param(debug_quirks, uint, 0444);
3479 module_param(debug_quirks2, uint, 0444);
3480
3481 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3482 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3483 MODULE_LICENSE("GPL");
3484
3485 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3486 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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