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Merge tag 'pwm/for-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry...
[deliverable/linux.git] / drivers / net / dsa / bcm_sf2.c
1 /*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <net/dsa.h>
25 #include <linux/ethtool.h>
26 #include <linux/if_bridge.h>
27 #include <linux/brcmphy.h>
28
29 #include "bcm_sf2.h"
30 #include "bcm_sf2_regs.h"
31
32 /* String, offset, and register size in bytes if different from 4 bytes */
33 static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
34 { "TxOctets", 0x000, 8 },
35 { "TxDropPkts", 0x020 },
36 { "TxQPKTQ0", 0x030 },
37 { "TxBroadcastPkts", 0x040 },
38 { "TxMulticastPkts", 0x050 },
39 { "TxUnicastPKts", 0x060 },
40 { "TxCollisions", 0x070 },
41 { "TxSingleCollision", 0x080 },
42 { "TxMultipleCollision", 0x090 },
43 { "TxDeferredCollision", 0x0a0 },
44 { "TxLateCollision", 0x0b0 },
45 { "TxExcessiveCollision", 0x0c0 },
46 { "TxFrameInDisc", 0x0d0 },
47 { "TxPausePkts", 0x0e0 },
48 { "TxQPKTQ1", 0x0f0 },
49 { "TxQPKTQ2", 0x100 },
50 { "TxQPKTQ3", 0x110 },
51 { "TxQPKTQ4", 0x120 },
52 { "TxQPKTQ5", 0x130 },
53 { "RxOctets", 0x140, 8 },
54 { "RxUndersizePkts", 0x160 },
55 { "RxPausePkts", 0x170 },
56 { "RxPkts64Octets", 0x180 },
57 { "RxPkts65to127Octets", 0x190 },
58 { "RxPkts128to255Octets", 0x1a0 },
59 { "RxPkts256to511Octets", 0x1b0 },
60 { "RxPkts512to1023Octets", 0x1c0 },
61 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
62 { "RxOversizePkts", 0x1e0 },
63 { "RxJabbers", 0x1f0 },
64 { "RxAlignmentErrors", 0x200 },
65 { "RxFCSErrors", 0x210 },
66 { "RxGoodOctets", 0x220, 8 },
67 { "RxDropPkts", 0x240 },
68 { "RxUnicastPkts", 0x250 },
69 { "RxMulticastPkts", 0x260 },
70 { "RxBroadcastPkts", 0x270 },
71 { "RxSAChanges", 0x280 },
72 { "RxFragments", 0x290 },
73 { "RxJumboPkt", 0x2a0 },
74 { "RxSymblErr", 0x2b0 },
75 { "InRangeErrCount", 0x2c0 },
76 { "OutRangeErrCount", 0x2d0 },
77 { "EEELpiEvent", 0x2e0 },
78 { "EEELpiDuration", 0x2f0 },
79 { "RxDiscard", 0x300, 8 },
80 { "TxQPKTQ6", 0x320 },
81 { "TxQPKTQ7", 0x330 },
82 { "TxPkts64Octets", 0x340 },
83 { "TxPkts65to127Octets", 0x350 },
84 { "TxPkts128to255Octets", 0x360 },
85 { "TxPkts256to511Ocets", 0x370 },
86 { "TxPkts512to1023Ocets", 0x380 },
87 { "TxPkts1024toMaxPktOcets", 0x390 },
88 };
89
90 #define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
91
92 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
93 int port, uint8_t *data)
94 {
95 unsigned int i;
96
97 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
98 memcpy(data + i * ETH_GSTRING_LEN,
99 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
100 }
101
102 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
103 int port, uint64_t *data)
104 {
105 struct bcm_sf2_priv *priv = ds_to_priv(ds);
106 const struct bcm_sf2_hw_stats *s;
107 unsigned int i;
108 u64 val = 0;
109 u32 offset;
110
111 mutex_lock(&priv->stats_mutex);
112
113 /* Now fetch the per-port counters */
114 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
115 s = &bcm_sf2_mib[i];
116
117 /* Do a latched 64-bit read if needed */
118 offset = s->reg + CORE_P_MIB_OFFSET(port);
119 if (s->sizeof_stat == 8)
120 val = core_readq(priv, offset);
121 else
122 val = core_readl(priv, offset);
123
124 data[i] = (u64)val;
125 }
126
127 mutex_unlock(&priv->stats_mutex);
128 }
129
130 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
131 {
132 return BCM_SF2_STATS_SIZE;
133 }
134
135 static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
136 {
137 return "Broadcom Starfighter 2";
138 }
139
140 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
141 {
142 struct bcm_sf2_priv *priv = ds_to_priv(ds);
143 unsigned int i;
144 u32 reg;
145
146 /* Enable the IMP Port to be in the same VLAN as the other ports
147 * on a per-port basis such that we only have Port i and IMP in
148 * the same VLAN.
149 */
150 for (i = 0; i < priv->hw_params.num_ports; i++) {
151 if (!((1 << i) & ds->phys_port_mask))
152 continue;
153
154 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
155 reg |= (1 << cpu_port);
156 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
157 }
158 }
159
160 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
161 {
162 struct bcm_sf2_priv *priv = ds_to_priv(ds);
163 u32 reg, val;
164
165 /* Enable the port memories */
166 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
167 reg &= ~P_TXQ_PSM_VDD(port);
168 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
169
170 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
171 reg = core_readl(priv, CORE_IMP_CTL);
172 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
173 reg &= ~(RX_DIS | TX_DIS);
174 core_writel(priv, reg, CORE_IMP_CTL);
175
176 /* Enable forwarding */
177 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
178
179 /* Enable IMP port in dumb mode */
180 reg = core_readl(priv, CORE_SWITCH_CTRL);
181 reg |= MII_DUMB_FWDG_EN;
182 core_writel(priv, reg, CORE_SWITCH_CTRL);
183
184 /* Resolve which bit controls the Broadcom tag */
185 switch (port) {
186 case 8:
187 val = BRCM_HDR_EN_P8;
188 break;
189 case 7:
190 val = BRCM_HDR_EN_P7;
191 break;
192 case 5:
193 val = BRCM_HDR_EN_P5;
194 break;
195 default:
196 val = 0;
197 break;
198 }
199
200 /* Enable Broadcom tags for IMP port */
201 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
202 reg |= val;
203 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
204
205 /* Enable reception Broadcom tag for CPU TX (switch RX) to
206 * allow us to tag outgoing frames
207 */
208 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
209 reg &= ~(1 << port);
210 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
211
212 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
213 * allow delivering frames to the per-port net_devices
214 */
215 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
216 reg &= ~(1 << port);
217 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
218
219 /* Force link status for IMP port */
220 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
221 reg |= (MII_SW_OR | LINK_STS);
222 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
223 }
224
225 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
226 {
227 struct bcm_sf2_priv *priv = ds_to_priv(ds);
228 u32 reg;
229
230 reg = core_readl(priv, CORE_EEE_EN_CTRL);
231 if (enable)
232 reg |= 1 << port;
233 else
234 reg &= ~(1 << port);
235 core_writel(priv, reg, CORE_EEE_EN_CTRL);
236 }
237
238 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
239 {
240 struct bcm_sf2_priv *priv = ds_to_priv(ds);
241 u32 reg;
242
243 reg = reg_readl(priv, REG_SPHY_CNTRL);
244 if (enable) {
245 reg |= PHY_RESET;
246 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
247 reg_writel(priv, reg, REG_SPHY_CNTRL);
248 udelay(21);
249 reg = reg_readl(priv, REG_SPHY_CNTRL);
250 reg &= ~PHY_RESET;
251 } else {
252 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
253 reg_writel(priv, reg, REG_SPHY_CNTRL);
254 mdelay(1);
255 reg |= CK25_DIS;
256 }
257 reg_writel(priv, reg, REG_SPHY_CNTRL);
258
259 /* Use PHY-driven LED signaling */
260 if (!enable) {
261 reg = reg_readl(priv, REG_LED_CNTRL(0));
262 reg |= SPDLNK_SRC_SEL;
263 reg_writel(priv, reg, REG_LED_CNTRL(0));
264 }
265 }
266
267 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
268 struct phy_device *phy)
269 {
270 struct bcm_sf2_priv *priv = ds_to_priv(ds);
271 s8 cpu_port = ds->dst[ds->index].cpu_port;
272 u32 reg;
273
274 /* Clear the memory power down */
275 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
276 reg &= ~P_TXQ_PSM_VDD(port);
277 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
278
279 /* Clear the Rx and Tx disable bits and set to no spanning tree */
280 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
281
282 /* Re-enable the GPHY and re-apply workarounds */
283 if (port == 0 && priv->hw_params.num_gphy == 1) {
284 bcm_sf2_gphy_enable_set(ds, true);
285 if (phy) {
286 /* if phy_stop() has been called before, phy
287 * will be in halted state, and phy_start()
288 * will call resume.
289 *
290 * the resume path does not configure back
291 * autoneg settings, and since we hard reset
292 * the phy manually here, we need to reset the
293 * state machine also.
294 */
295 phy->state = PHY_READY;
296 phy_init_hw(phy);
297 }
298 }
299
300 /* Enable port 7 interrupts to get notified */
301 if (port == 7)
302 intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
303
304 /* Set this port, and only this one to be in the default VLAN,
305 * if member of a bridge, restore its membership prior to
306 * bringing down this port.
307 */
308 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
309 reg &= ~PORT_VLAN_CTRL_MASK;
310 reg |= (1 << port);
311 reg |= priv->port_sts[port].vlan_ctl_mask;
312 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
313
314 bcm_sf2_imp_vlan_setup(ds, cpu_port);
315
316 /* If EEE was enabled, restore it */
317 if (priv->port_sts[port].eee.eee_enabled)
318 bcm_sf2_eee_enable_set(ds, port, true);
319
320 return 0;
321 }
322
323 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
324 struct phy_device *phy)
325 {
326 struct bcm_sf2_priv *priv = ds_to_priv(ds);
327 u32 off, reg;
328
329 if (priv->wol_ports_mask & (1 << port))
330 return;
331
332 if (port == 7) {
333 intrl2_1_mask_set(priv, P_IRQ_MASK(P7_IRQ_OFF));
334 intrl2_1_writel(priv, P_IRQ_MASK(P7_IRQ_OFF), INTRL2_CPU_CLEAR);
335 }
336
337 if (port == 0 && priv->hw_params.num_gphy == 1)
338 bcm_sf2_gphy_enable_set(ds, false);
339
340 if (dsa_is_cpu_port(ds, port))
341 off = CORE_IMP_CTL;
342 else
343 off = CORE_G_PCTL_PORT(port);
344
345 reg = core_readl(priv, off);
346 reg |= RX_DIS | TX_DIS;
347 core_writel(priv, reg, off);
348
349 /* Power down the port memory */
350 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
351 reg |= P_TXQ_PSM_VDD(port);
352 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
353 }
354
355 /* Returns 0 if EEE was not enabled, or 1 otherwise
356 */
357 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
358 struct phy_device *phy)
359 {
360 struct bcm_sf2_priv *priv = ds_to_priv(ds);
361 struct ethtool_eee *p = &priv->port_sts[port].eee;
362 int ret;
363
364 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
365
366 ret = phy_init_eee(phy, 0);
367 if (ret)
368 return 0;
369
370 bcm_sf2_eee_enable_set(ds, port, true);
371
372 return 1;
373 }
374
375 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
376 struct ethtool_eee *e)
377 {
378 struct bcm_sf2_priv *priv = ds_to_priv(ds);
379 struct ethtool_eee *p = &priv->port_sts[port].eee;
380 u32 reg;
381
382 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
383 e->eee_enabled = p->eee_enabled;
384 e->eee_active = !!(reg & (1 << port));
385
386 return 0;
387 }
388
389 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
390 struct phy_device *phydev,
391 struct ethtool_eee *e)
392 {
393 struct bcm_sf2_priv *priv = ds_to_priv(ds);
394 struct ethtool_eee *p = &priv->port_sts[port].eee;
395
396 p->eee_enabled = e->eee_enabled;
397
398 if (!p->eee_enabled) {
399 bcm_sf2_eee_enable_set(ds, port, false);
400 } else {
401 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
402 if (!p->eee_enabled)
403 return -EOPNOTSUPP;
404 }
405
406 return 0;
407 }
408
409 /* Fast-ageing of ARL entries for a given port, equivalent to an ARL
410 * flush for that port.
411 */
412 static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
413 {
414 struct bcm_sf2_priv *priv = ds_to_priv(ds);
415 unsigned int timeout = 1000;
416 u32 reg;
417
418 core_writel(priv, port, CORE_FAST_AGE_PORT);
419
420 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
421 reg |= EN_AGE_PORT | FAST_AGE_STR_DONE;
422 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
423
424 do {
425 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
426 if (!(reg & FAST_AGE_STR_DONE))
427 break;
428
429 cpu_relax();
430 } while (timeout--);
431
432 if (!timeout)
433 return -ETIMEDOUT;
434
435 return 0;
436 }
437
438 static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
439 u32 br_port_mask)
440 {
441 struct bcm_sf2_priv *priv = ds_to_priv(ds);
442 unsigned int i;
443 u32 reg, p_ctl;
444
445 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
446
447 for (i = 0; i < priv->hw_params.num_ports; i++) {
448 if (!((1 << i) & br_port_mask))
449 continue;
450
451 /* Add this local port to the remote port VLAN control
452 * membership and update the remote port bitmask
453 */
454 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
455 reg |= 1 << port;
456 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
457 priv->port_sts[i].vlan_ctl_mask = reg;
458
459 p_ctl |= 1 << i;
460 }
461
462 /* Configure the local port VLAN control membership to include
463 * remote ports and update the local port bitmask
464 */
465 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
466 priv->port_sts[port].vlan_ctl_mask = p_ctl;
467
468 return 0;
469 }
470
471 static int bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port,
472 u32 br_port_mask)
473 {
474 struct bcm_sf2_priv *priv = ds_to_priv(ds);
475 unsigned int i;
476 u32 reg, p_ctl;
477
478 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
479
480 for (i = 0; i < priv->hw_params.num_ports; i++) {
481 /* Don't touch the remaining ports */
482 if (!((1 << i) & br_port_mask))
483 continue;
484
485 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
486 reg &= ~(1 << port);
487 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
488 priv->port_sts[port].vlan_ctl_mask = reg;
489
490 /* Prevent self removal to preserve isolation */
491 if (port != i)
492 p_ctl &= ~(1 << i);
493 }
494
495 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
496 priv->port_sts[port].vlan_ctl_mask = p_ctl;
497
498 return 0;
499 }
500
501 static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
502 u8 state)
503 {
504 struct bcm_sf2_priv *priv = ds_to_priv(ds);
505 u8 hw_state, cur_hw_state;
506 int ret = 0;
507 u32 reg;
508
509 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
510 cur_hw_state = reg >> G_MISTP_STATE_SHIFT;
511
512 switch (state) {
513 case BR_STATE_DISABLED:
514 hw_state = G_MISTP_DIS_STATE;
515 break;
516 case BR_STATE_LISTENING:
517 hw_state = G_MISTP_LISTEN_STATE;
518 break;
519 case BR_STATE_LEARNING:
520 hw_state = G_MISTP_LEARN_STATE;
521 break;
522 case BR_STATE_FORWARDING:
523 hw_state = G_MISTP_FWD_STATE;
524 break;
525 case BR_STATE_BLOCKING:
526 hw_state = G_MISTP_BLOCK_STATE;
527 break;
528 default:
529 pr_err("%s: invalid STP state: %d\n", __func__, state);
530 return -EINVAL;
531 }
532
533 /* Fast-age ARL entries if we are moving a port from Learning or
534 * Forwarding state to Disabled, Blocking or Listening state
535 */
536 if (cur_hw_state != hw_state) {
537 if (cur_hw_state & 4 && !(hw_state & 4)) {
538 ret = bcm_sf2_sw_fast_age_port(ds, port);
539 if (ret) {
540 pr_err("%s: fast-ageing failed\n", __func__);
541 return ret;
542 }
543 }
544 }
545
546 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
547 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
548 reg |= hw_state;
549 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
550
551 return 0;
552 }
553
554 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
555 {
556 struct bcm_sf2_priv *priv = dev_id;
557
558 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
559 ~priv->irq0_mask;
560 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
561
562 return IRQ_HANDLED;
563 }
564
565 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
566 {
567 struct bcm_sf2_priv *priv = dev_id;
568
569 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
570 ~priv->irq1_mask;
571 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
572
573 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
574 priv->port_sts[7].link = 1;
575 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
576 priv->port_sts[7].link = 0;
577
578 return IRQ_HANDLED;
579 }
580
581 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
582 {
583 unsigned int timeout = 1000;
584 u32 reg;
585
586 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
587 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
588 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
589
590 do {
591 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
592 if (!(reg & SOFTWARE_RESET))
593 break;
594
595 usleep_range(1000, 2000);
596 } while (timeout-- > 0);
597
598 if (timeout == 0)
599 return -ETIMEDOUT;
600
601 return 0;
602 }
603
604 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
605 {
606 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
607 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
608 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
609 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
610 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
611 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
612 }
613
614 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
615 {
616 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
617 struct bcm_sf2_priv *priv = ds_to_priv(ds);
618 struct device_node *dn;
619 void __iomem **base;
620 unsigned int port;
621 unsigned int i;
622 u32 reg, rev;
623 int ret;
624
625 spin_lock_init(&priv->indir_lock);
626 mutex_init(&priv->stats_mutex);
627
628 /* All the interesting properties are at the parent device_node
629 * level
630 */
631 dn = ds->pd->of_node->parent;
632
633 priv->irq0 = irq_of_parse_and_map(dn, 0);
634 priv->irq1 = irq_of_parse_and_map(dn, 1);
635
636 base = &priv->core;
637 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
638 *base = of_iomap(dn, i);
639 if (*base == NULL) {
640 pr_err("unable to find register: %s\n", reg_names[i]);
641 ret = -ENOMEM;
642 goto out_unmap;
643 }
644 base++;
645 }
646
647 ret = bcm_sf2_sw_rst(priv);
648 if (ret) {
649 pr_err("unable to software reset switch: %d\n", ret);
650 goto out_unmap;
651 }
652
653 /* Disable all interrupts and request them */
654 bcm_sf2_intr_disable(priv);
655
656 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
657 "switch_0", priv);
658 if (ret < 0) {
659 pr_err("failed to request switch_0 IRQ\n");
660 goto out_unmap;
661 }
662
663 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
664 "switch_1", priv);
665 if (ret < 0) {
666 pr_err("failed to request switch_1 IRQ\n");
667 goto out_free_irq0;
668 }
669
670 /* Reset the MIB counters */
671 reg = core_readl(priv, CORE_GMNCFGCFG);
672 reg |= RST_MIB_CNT;
673 core_writel(priv, reg, CORE_GMNCFGCFG);
674 reg &= ~RST_MIB_CNT;
675 core_writel(priv, reg, CORE_GMNCFGCFG);
676
677 /* Get the maximum number of ports for this switch */
678 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
679 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
680 priv->hw_params.num_ports = DSA_MAX_PORTS;
681
682 /* Assume a single GPHY setup if we can't read that property */
683 if (of_property_read_u32(dn, "brcm,num-gphy",
684 &priv->hw_params.num_gphy))
685 priv->hw_params.num_gphy = 1;
686
687 /* Enable all valid ports and disable those unused */
688 for (port = 0; port < priv->hw_params.num_ports; port++) {
689 /* IMP port receives special treatment */
690 if ((1 << port) & ds->phys_port_mask)
691 bcm_sf2_port_setup(ds, port, NULL);
692 else if (dsa_is_cpu_port(ds, port))
693 bcm_sf2_imp_setup(ds, port);
694 else
695 bcm_sf2_port_disable(ds, port, NULL);
696 }
697
698 /* Include the pseudo-PHY address and the broadcast PHY address to
699 * divert reads towards our workaround. This is only required for
700 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
701 * that we can use the regular SWITCH_MDIO master controller instead.
702 *
703 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
704 * to have a 1:1 mapping between Port address and PHY address in order
705 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
706 * not what we want here, so we initialize phys_mii_mask 0 to always
707 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
708 */
709 if (of_machine_is_compatible("brcm,bcm7445d0"))
710 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
711 else
712 ds->phys_mii_mask = 0;
713
714 rev = reg_readl(priv, REG_SWITCH_REVISION);
715 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
716 SWITCH_TOP_REV_MASK;
717 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
718
719 rev = reg_readl(priv, REG_PHY_REVISION);
720 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
721
722 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
723 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
724 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
725 priv->core, priv->irq0, priv->irq1);
726
727 return 0;
728
729 out_free_irq0:
730 free_irq(priv->irq0, priv);
731 out_unmap:
732 base = &priv->core;
733 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
734 if (*base)
735 iounmap(*base);
736 base++;
737 }
738 return ret;
739 }
740
741 static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
742 {
743 return 0;
744 }
745
746 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
747 {
748 struct bcm_sf2_priv *priv = ds_to_priv(ds);
749
750 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
751 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
752 * the REG_PHY_REVISION register layout is.
753 */
754
755 return priv->hw_params.gphy_rev;
756 }
757
758 static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
759 int regnum, u16 val)
760 {
761 struct bcm_sf2_priv *priv = ds_to_priv(ds);
762 int ret = 0;
763 u32 reg;
764
765 reg = reg_readl(priv, REG_SWITCH_CNTRL);
766 reg |= MDIO_MASTER_SEL;
767 reg_writel(priv, reg, REG_SWITCH_CNTRL);
768
769 /* Page << 8 | offset */
770 reg = 0x70;
771 reg <<= 2;
772 core_writel(priv, addr, reg);
773
774 /* Page << 8 | offset */
775 reg = 0x80 << 8 | regnum << 1;
776 reg <<= 2;
777
778 if (op)
779 ret = core_readl(priv, reg);
780 else
781 core_writel(priv, val, reg);
782
783 reg = reg_readl(priv, REG_SWITCH_CNTRL);
784 reg &= ~MDIO_MASTER_SEL;
785 reg_writel(priv, reg, REG_SWITCH_CNTRL);
786
787 return ret & 0xffff;
788 }
789
790 static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
791 {
792 /* Intercept reads from the MDIO broadcast address or Broadcom
793 * pseudo-PHY address
794 */
795 switch (addr) {
796 case 0:
797 case BRCM_PSEUDO_PHY_ADDR:
798 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
799 default:
800 return 0xffff;
801 }
802 }
803
804 static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
805 u16 val)
806 {
807 /* Intercept writes to the MDIO broadcast address or Broadcom
808 * pseudo-PHY address
809 */
810 switch (addr) {
811 case 0:
812 case BRCM_PSEUDO_PHY_ADDR:
813 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
814 break;
815 }
816
817 return 0;
818 }
819
820 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
821 struct phy_device *phydev)
822 {
823 struct bcm_sf2_priv *priv = ds_to_priv(ds);
824 u32 id_mode_dis = 0, port_mode;
825 const char *str = NULL;
826 u32 reg;
827
828 switch (phydev->interface) {
829 case PHY_INTERFACE_MODE_RGMII:
830 str = "RGMII (no delay)";
831 id_mode_dis = 1;
832 case PHY_INTERFACE_MODE_RGMII_TXID:
833 if (!str)
834 str = "RGMII (TX delay)";
835 port_mode = EXT_GPHY;
836 break;
837 case PHY_INTERFACE_MODE_MII:
838 str = "MII";
839 port_mode = EXT_EPHY;
840 break;
841 case PHY_INTERFACE_MODE_REVMII:
842 str = "Reverse MII";
843 port_mode = EXT_REVMII;
844 break;
845 default:
846 /* All other PHYs: internal and MoCA */
847 goto force_link;
848 }
849
850 /* If the link is down, just disable the interface to conserve power */
851 if (!phydev->link) {
852 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
853 reg &= ~RGMII_MODE_EN;
854 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
855 goto force_link;
856 }
857
858 /* Clear id_mode_dis bit, and the existing port mode, but
859 * make sure we enable the RGMII block for data to pass
860 */
861 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
862 reg &= ~ID_MODE_DIS;
863 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
864 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
865
866 reg |= port_mode | RGMII_MODE_EN;
867 if (id_mode_dis)
868 reg |= ID_MODE_DIS;
869
870 if (phydev->pause) {
871 if (phydev->asym_pause)
872 reg |= TX_PAUSE_EN;
873 reg |= RX_PAUSE_EN;
874 }
875
876 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
877
878 pr_info("Port %d configured for %s\n", port, str);
879
880 force_link:
881 /* Force link settings detected from the PHY */
882 reg = SW_OVERRIDE;
883 switch (phydev->speed) {
884 case SPEED_1000:
885 reg |= SPDSTS_1000 << SPEED_SHIFT;
886 break;
887 case SPEED_100:
888 reg |= SPDSTS_100 << SPEED_SHIFT;
889 break;
890 }
891
892 if (phydev->link)
893 reg |= LINK_STS;
894 if (phydev->duplex == DUPLEX_FULL)
895 reg |= DUPLX_MODE;
896
897 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
898 }
899
900 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
901 struct fixed_phy_status *status)
902 {
903 struct bcm_sf2_priv *priv = ds_to_priv(ds);
904 u32 duplex, pause;
905 u32 reg;
906
907 duplex = core_readl(priv, CORE_DUPSTS);
908 pause = core_readl(priv, CORE_PAUSESTS);
909
910 status->link = 0;
911
912 /* Port 7 is special as we do not get link status from CORE_LNKSTS,
913 * which means that we need to force the link at the port override
914 * level to get the data to flow. We do use what the interrupt handler
915 * did determine before.
916 *
917 * For the other ports, we just force the link status, since this is
918 * a fixed PHY device.
919 */
920 if (port == 7) {
921 status->link = priv->port_sts[port].link;
922 /* For MoCA interfaces, also force a link down notification
923 * since some version of the user-space daemon (mocad) use
924 * cmd->autoneg to force the link, which messes up the PHY
925 * state machine and make it go in PHY_FORCING state instead.
926 */
927 if (!status->link)
928 netif_carrier_off(ds->ports[port]);
929 status->duplex = 1;
930 } else {
931 status->link = 1;
932 status->duplex = !!(duplex & (1 << port));
933 }
934
935 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
936 reg |= SW_OVERRIDE;
937 if (status->link)
938 reg |= LINK_STS;
939 else
940 reg &= ~LINK_STS;
941 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
942
943 if ((pause & (1 << port)) &&
944 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
945 status->asym_pause = 1;
946 status->pause = 1;
947 }
948
949 if (pause & (1 << port))
950 status->pause = 1;
951 }
952
953 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
954 {
955 struct bcm_sf2_priv *priv = ds_to_priv(ds);
956 unsigned int port;
957
958 bcm_sf2_intr_disable(priv);
959
960 /* Disable all ports physically present including the IMP
961 * port, the other ones have already been disabled during
962 * bcm_sf2_sw_setup
963 */
964 for (port = 0; port < DSA_MAX_PORTS; port++) {
965 if ((1 << port) & ds->phys_port_mask ||
966 dsa_is_cpu_port(ds, port))
967 bcm_sf2_port_disable(ds, port, NULL);
968 }
969
970 return 0;
971 }
972
973 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
974 {
975 struct bcm_sf2_priv *priv = ds_to_priv(ds);
976 unsigned int port;
977 int ret;
978
979 ret = bcm_sf2_sw_rst(priv);
980 if (ret) {
981 pr_err("%s: failed to software reset switch\n", __func__);
982 return ret;
983 }
984
985 if (priv->hw_params.num_gphy == 1)
986 bcm_sf2_gphy_enable_set(ds, true);
987
988 for (port = 0; port < DSA_MAX_PORTS; port++) {
989 if ((1 << port) & ds->phys_port_mask)
990 bcm_sf2_port_setup(ds, port, NULL);
991 else if (dsa_is_cpu_port(ds, port))
992 bcm_sf2_imp_setup(ds, port);
993 }
994
995 return 0;
996 }
997
998 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
999 struct ethtool_wolinfo *wol)
1000 {
1001 struct net_device *p = ds->dst[ds->index].master_netdev;
1002 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1003 struct ethtool_wolinfo pwol;
1004
1005 /* Get the parent device WoL settings */
1006 p->ethtool_ops->get_wol(p, &pwol);
1007
1008 /* Advertise the parent device supported settings */
1009 wol->supported = pwol.supported;
1010 memset(&wol->sopass, 0, sizeof(wol->sopass));
1011
1012 if (pwol.wolopts & WAKE_MAGICSECURE)
1013 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1014
1015 if (priv->wol_ports_mask & (1 << port))
1016 wol->wolopts = pwol.wolopts;
1017 else
1018 wol->wolopts = 0;
1019 }
1020
1021 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1022 struct ethtool_wolinfo *wol)
1023 {
1024 struct net_device *p = ds->dst[ds->index].master_netdev;
1025 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1026 s8 cpu_port = ds->dst[ds->index].cpu_port;
1027 struct ethtool_wolinfo pwol;
1028
1029 p->ethtool_ops->get_wol(p, &pwol);
1030 if (wol->wolopts & ~pwol.supported)
1031 return -EINVAL;
1032
1033 if (wol->wolopts)
1034 priv->wol_ports_mask |= (1 << port);
1035 else
1036 priv->wol_ports_mask &= ~(1 << port);
1037
1038 /* If we have at least one port enabled, make sure the CPU port
1039 * is also enabled. If the CPU port is the last one enabled, we disable
1040 * it since this configuration does not make sense.
1041 */
1042 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1043 priv->wol_ports_mask |= (1 << cpu_port);
1044 else
1045 priv->wol_ports_mask &= ~(1 << cpu_port);
1046
1047 return p->ethtool_ops->set_wol(p, wol);
1048 }
1049
1050 static struct dsa_switch_driver bcm_sf2_switch_driver = {
1051 .tag_protocol = DSA_TAG_PROTO_BRCM,
1052 .priv_size = sizeof(struct bcm_sf2_priv),
1053 .probe = bcm_sf2_sw_probe,
1054 .setup = bcm_sf2_sw_setup,
1055 .set_addr = bcm_sf2_sw_set_addr,
1056 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1057 .phy_read = bcm_sf2_sw_phy_read,
1058 .phy_write = bcm_sf2_sw_phy_write,
1059 .get_strings = bcm_sf2_sw_get_strings,
1060 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1061 .get_sset_count = bcm_sf2_sw_get_sset_count,
1062 .adjust_link = bcm_sf2_sw_adjust_link,
1063 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1064 .suspend = bcm_sf2_sw_suspend,
1065 .resume = bcm_sf2_sw_resume,
1066 .get_wol = bcm_sf2_sw_get_wol,
1067 .set_wol = bcm_sf2_sw_set_wol,
1068 .port_enable = bcm_sf2_port_setup,
1069 .port_disable = bcm_sf2_port_disable,
1070 .get_eee = bcm_sf2_sw_get_eee,
1071 .set_eee = bcm_sf2_sw_set_eee,
1072 .port_join_bridge = bcm_sf2_sw_br_join,
1073 .port_leave_bridge = bcm_sf2_sw_br_leave,
1074 .port_stp_update = bcm_sf2_sw_br_set_stp_state,
1075 };
1076
1077 static int __init bcm_sf2_init(void)
1078 {
1079 register_switch_driver(&bcm_sf2_switch_driver);
1080
1081 return 0;
1082 }
1083 module_init(bcm_sf2_init);
1084
1085 static void __exit bcm_sf2_exit(void)
1086 {
1087 unregister_switch_driver(&bcm_sf2_switch_driver);
1088 }
1089 module_exit(bcm_sf2_exit);
1090
1091 MODULE_AUTHOR("Broadcom Corporation");
1092 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1093 MODULE_LICENSE("GPL");
1094 MODULE_ALIAS("platform:brcm-sf2");
Linux kernel - Deliverables
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