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[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx / chip.c
1 /*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/netdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/phy.h>
30 #include <net/dsa.h>
31 #include <net/switchdev.h>
32
33 #include "mv88e6xxx.h"
34 #include "global2.h"
35
36 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
37 {
38 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
39 dev_err(chip->dev, "Switch registers lock not held!\n");
40 dump_stack();
41 }
42 }
43
44 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
45 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
46 *
47 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
48 * is the only device connected to the SMI master. In this mode it responds to
49 * all 32 possible SMI addresses, and thus maps directly the internal devices.
50 *
51 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
52 * multiple devices to share the SMI interface. In this mode it responds to only
53 * 2 registers, used to indirectly access the internal SMI devices.
54 */
55
56 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
57 int addr, int reg, u16 *val)
58 {
59 if (!chip->smi_ops)
60 return -EOPNOTSUPP;
61
62 return chip->smi_ops->read(chip, addr, reg, val);
63 }
64
65 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
66 int addr, int reg, u16 val)
67 {
68 if (!chip->smi_ops)
69 return -EOPNOTSUPP;
70
71 return chip->smi_ops->write(chip, addr, reg, val);
72 }
73
74 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
75 int addr, int reg, u16 *val)
76 {
77 int ret;
78
79 ret = mdiobus_read_nested(chip->bus, addr, reg);
80 if (ret < 0)
81 return ret;
82
83 *val = ret & 0xffff;
84
85 return 0;
86 }
87
88 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
89 int addr, int reg, u16 val)
90 {
91 int ret;
92
93 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
94 if (ret < 0)
95 return ret;
96
97 return 0;
98 }
99
100 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
101 .read = mv88e6xxx_smi_single_chip_read,
102 .write = mv88e6xxx_smi_single_chip_write,
103 };
104
105 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
106 {
107 int ret;
108 int i;
109
110 for (i = 0; i < 16; i++) {
111 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
112 if (ret < 0)
113 return ret;
114
115 if ((ret & SMI_CMD_BUSY) == 0)
116 return 0;
117 }
118
119 return -ETIMEDOUT;
120 }
121
122 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
123 int addr, int reg, u16 *val)
124 {
125 int ret;
126
127 /* Wait for the bus to become free. */
128 ret = mv88e6xxx_smi_multi_chip_wait(chip);
129 if (ret < 0)
130 return ret;
131
132 /* Transmit the read command. */
133 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
134 SMI_CMD_OP_22_READ | (addr << 5) | reg);
135 if (ret < 0)
136 return ret;
137
138 /* Wait for the read command to complete. */
139 ret = mv88e6xxx_smi_multi_chip_wait(chip);
140 if (ret < 0)
141 return ret;
142
143 /* Read the data. */
144 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
145 if (ret < 0)
146 return ret;
147
148 *val = ret & 0xffff;
149
150 return 0;
151 }
152
153 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
154 int addr, int reg, u16 val)
155 {
156 int ret;
157
158 /* Wait for the bus to become free. */
159 ret = mv88e6xxx_smi_multi_chip_wait(chip);
160 if (ret < 0)
161 return ret;
162
163 /* Transmit the data to write. */
164 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
165 if (ret < 0)
166 return ret;
167
168 /* Transmit the write command. */
169 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
170 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
171 if (ret < 0)
172 return ret;
173
174 /* Wait for the write command to complete. */
175 ret = mv88e6xxx_smi_multi_chip_wait(chip);
176 if (ret < 0)
177 return ret;
178
179 return 0;
180 }
181
182 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
183 .read = mv88e6xxx_smi_multi_chip_read,
184 .write = mv88e6xxx_smi_multi_chip_write,
185 };
186
187 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
188 {
189 int err;
190
191 assert_reg_lock(chip);
192
193 err = mv88e6xxx_smi_read(chip, addr, reg, val);
194 if (err)
195 return err;
196
197 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
198 addr, reg, *val);
199
200 return 0;
201 }
202
203 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
204 {
205 int err;
206
207 assert_reg_lock(chip);
208
209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
210 if (err)
211 return err;
212
213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
214 addr, reg, val);
215
216 return 0;
217 }
218
219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
220 int reg, u16 *val)
221 {
222 int addr = phy; /* PHY devices addresses start at 0x0 */
223
224 if (!chip->phy_ops)
225 return -EOPNOTSUPP;
226
227 return chip->phy_ops->read(chip, addr, reg, val);
228 }
229
230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
231 int reg, u16 val)
232 {
233 int addr = phy; /* PHY devices addresses start at 0x0 */
234
235 if (!chip->phy_ops)
236 return -EOPNOTSUPP;
237
238 return chip->phy_ops->write(chip, addr, reg, val);
239 }
240
241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
242 {
243 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
244 return -EOPNOTSUPP;
245
246 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
247 }
248
249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
250 {
251 int err;
252
253 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
254 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
255 if (unlikely(err)) {
256 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
257 phy, err);
258 }
259 }
260
261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
262 u8 page, int reg, u16 *val)
263 {
264 int err;
265
266 /* There is no paging for registers 22 */
267 if (reg == PHY_PAGE)
268 return -EINVAL;
269
270 err = mv88e6xxx_phy_page_get(chip, phy, page);
271 if (!err) {
272 err = mv88e6xxx_phy_read(chip, phy, reg, val);
273 mv88e6xxx_phy_page_put(chip, phy);
274 }
275
276 return err;
277 }
278
279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
280 u8 page, int reg, u16 val)
281 {
282 int err;
283
284 /* There is no paging for registers 22 */
285 if (reg == PHY_PAGE)
286 return -EINVAL;
287
288 err = mv88e6xxx_phy_page_get(chip, phy, page);
289 if (!err) {
290 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
291 mv88e6xxx_phy_page_put(chip, phy);
292 }
293
294 return err;
295 }
296
297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
298 {
299 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
300 reg, val);
301 }
302
303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
304 {
305 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307 }
308
309 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
310 {
311 int i;
312
313 for (i = 0; i < 16; i++) {
314 u16 val;
315 int err;
316
317 err = mv88e6xxx_read(chip, addr, reg, &val);
318 if (err)
319 return err;
320
321 if (!(val & mask))
322 return 0;
323
324 usleep_range(1000, 2000);
325 }
326
327 dev_err(chip->dev, "Timeout while waiting for switch\n");
328 return -ETIMEDOUT;
329 }
330
331 /* Indirect write to single pointer-data register with an Update bit */
332 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
333 {
334 u16 val;
335 int err;
336
337 /* Wait until the previous operation is completed */
338 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
339 if (err)
340 return err;
341
342 /* Set the Update bit to trigger a write operation */
343 val = BIT(15) | update;
344
345 return mv88e6xxx_write(chip, addr, reg, val);
346 }
347
348 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
349 {
350 u16 val;
351 int err;
352
353 err = mv88e6xxx_read(chip, addr, reg, &val);
354 if (err)
355 return err;
356
357 return val;
358 }
359
360 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
361 int reg, u16 val)
362 {
363 return mv88e6xxx_write(chip, addr, reg, val);
364 }
365
366 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
367 {
368 int ret;
369 int i;
370
371 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
372 if (ret < 0)
373 return ret;
374
375 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
376 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
377 if (ret)
378 return ret;
379
380 for (i = 0; i < 16; i++) {
381 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
382 if (ret < 0)
383 return ret;
384
385 usleep_range(1000, 2000);
386 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
387 GLOBAL_STATUS_PPU_POLLING)
388 return 0;
389 }
390
391 return -ETIMEDOUT;
392 }
393
394 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
395 {
396 int ret, err, i;
397
398 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
399 if (ret < 0)
400 return ret;
401
402 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
403 ret | GLOBAL_CONTROL_PPU_ENABLE);
404 if (err)
405 return err;
406
407 for (i = 0; i < 16; i++) {
408 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
409 if (ret < 0)
410 return ret;
411
412 usleep_range(1000, 2000);
413 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
414 GLOBAL_STATUS_PPU_POLLING)
415 return 0;
416 }
417
418 return -ETIMEDOUT;
419 }
420
421 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
422 {
423 struct mv88e6xxx_chip *chip;
424
425 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
426
427 mutex_lock(&chip->reg_lock);
428
429 if (mutex_trylock(&chip->ppu_mutex)) {
430 if (mv88e6xxx_ppu_enable(chip) == 0)
431 chip->ppu_disabled = 0;
432 mutex_unlock(&chip->ppu_mutex);
433 }
434
435 mutex_unlock(&chip->reg_lock);
436 }
437
438 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
439 {
440 struct mv88e6xxx_chip *chip = (void *)_ps;
441
442 schedule_work(&chip->ppu_work);
443 }
444
445 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
446 {
447 int ret;
448
449 mutex_lock(&chip->ppu_mutex);
450
451 /* If the PHY polling unit is enabled, disable it so that
452 * we can access the PHY registers. If it was already
453 * disabled, cancel the timer that is going to re-enable
454 * it.
455 */
456 if (!chip->ppu_disabled) {
457 ret = mv88e6xxx_ppu_disable(chip);
458 if (ret < 0) {
459 mutex_unlock(&chip->ppu_mutex);
460 return ret;
461 }
462 chip->ppu_disabled = 1;
463 } else {
464 del_timer(&chip->ppu_timer);
465 ret = 0;
466 }
467
468 return ret;
469 }
470
471 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
472 {
473 /* Schedule a timer to re-enable the PHY polling unit. */
474 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
475 mutex_unlock(&chip->ppu_mutex);
476 }
477
478 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
479 {
480 mutex_init(&chip->ppu_mutex);
481 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
482 init_timer(&chip->ppu_timer);
483 chip->ppu_timer.data = (unsigned long)chip;
484 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
485 }
486
487 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
488 {
489 del_timer_sync(&chip->ppu_timer);
490 }
491
492 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
493 int reg, u16 *val)
494 {
495 int err;
496
497 err = mv88e6xxx_ppu_access_get(chip);
498 if (!err) {
499 err = mv88e6xxx_read(chip, addr, reg, val);
500 mv88e6xxx_ppu_access_put(chip);
501 }
502
503 return err;
504 }
505
506 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
507 int reg, u16 val)
508 {
509 int err;
510
511 err = mv88e6xxx_ppu_access_get(chip);
512 if (!err) {
513 err = mv88e6xxx_write(chip, addr, reg, val);
514 mv88e6xxx_ppu_access_put(chip);
515 }
516
517 return err;
518 }
519
520 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
521 .read = mv88e6xxx_phy_ppu_read,
522 .write = mv88e6xxx_phy_ppu_write,
523 };
524
525 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
526 {
527 return chip->info->family == MV88E6XXX_FAMILY_6065;
528 }
529
530 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
531 {
532 return chip->info->family == MV88E6XXX_FAMILY_6095;
533 }
534
535 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
536 {
537 return chip->info->family == MV88E6XXX_FAMILY_6097;
538 }
539
540 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
541 {
542 return chip->info->family == MV88E6XXX_FAMILY_6165;
543 }
544
545 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
546 {
547 return chip->info->family == MV88E6XXX_FAMILY_6185;
548 }
549
550 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
551 {
552 return chip->info->family == MV88E6XXX_FAMILY_6320;
553 }
554
555 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
556 {
557 return chip->info->family == MV88E6XXX_FAMILY_6351;
558 }
559
560 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
561 {
562 return chip->info->family == MV88E6XXX_FAMILY_6352;
563 }
564
565 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
566 {
567 return chip->info->num_databases;
568 }
569
570 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
571 {
572 /* Does the device have dedicated FID registers for ATU and VTU ops? */
573 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
574 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
575 return true;
576
577 return false;
578 }
579
580 /* We expect the switch to perform auto negotiation if there is a real
581 * phy. However, in the case of a fixed link phy, we force the port
582 * settings from the fixed link settings.
583 */
584 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
585 struct phy_device *phydev)
586 {
587 struct mv88e6xxx_chip *chip = ds->priv;
588 u32 reg;
589 int ret;
590
591 if (!phy_is_pseudo_fixed_link(phydev))
592 return;
593
594 mutex_lock(&chip->reg_lock);
595
596 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
597 if (ret < 0)
598 goto out;
599
600 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
601 PORT_PCS_CTRL_FORCE_LINK |
602 PORT_PCS_CTRL_DUPLEX_FULL |
603 PORT_PCS_CTRL_FORCE_DUPLEX |
604 PORT_PCS_CTRL_UNFORCED);
605
606 reg |= PORT_PCS_CTRL_FORCE_LINK;
607 if (phydev->link)
608 reg |= PORT_PCS_CTRL_LINK_UP;
609
610 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
611 goto out;
612
613 switch (phydev->speed) {
614 case SPEED_1000:
615 reg |= PORT_PCS_CTRL_1000;
616 break;
617 case SPEED_100:
618 reg |= PORT_PCS_CTRL_100;
619 break;
620 case SPEED_10:
621 reg |= PORT_PCS_CTRL_10;
622 break;
623 default:
624 pr_info("Unknown speed");
625 goto out;
626 }
627
628 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
629 if (phydev->duplex == DUPLEX_FULL)
630 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
631
632 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
633 (port >= chip->info->num_ports - 2)) {
634 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
635 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
636 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
637 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
638 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
639 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
640 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
641 }
642 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
643
644 out:
645 mutex_unlock(&chip->reg_lock);
646 }
647
648 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
649 {
650 int ret;
651 int i;
652
653 for (i = 0; i < 10; i++) {
654 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
655 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
656 return 0;
657 }
658
659 return -ETIMEDOUT;
660 }
661
662 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
663 {
664 int ret;
665
666 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
667 port = (port + 1) << 5;
668
669 /* Snapshot the hardware statistics counters for this port. */
670 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
671 GLOBAL_STATS_OP_CAPTURE_PORT |
672 GLOBAL_STATS_OP_HIST_RX_TX | port);
673 if (ret < 0)
674 return ret;
675
676 /* Wait for the snapshotting to complete. */
677 ret = _mv88e6xxx_stats_wait(chip);
678 if (ret < 0)
679 return ret;
680
681 return 0;
682 }
683
684 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
685 int stat, u32 *val)
686 {
687 u32 _val;
688 int ret;
689
690 *val = 0;
691
692 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
693 GLOBAL_STATS_OP_READ_CAPTURED |
694 GLOBAL_STATS_OP_HIST_RX_TX | stat);
695 if (ret < 0)
696 return;
697
698 ret = _mv88e6xxx_stats_wait(chip);
699 if (ret < 0)
700 return;
701
702 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
703 if (ret < 0)
704 return;
705
706 _val = ret << 16;
707
708 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
709 if (ret < 0)
710 return;
711
712 *val = _val | ret;
713 }
714
715 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
716 { "in_good_octets", 8, 0x00, BANK0, },
717 { "in_bad_octets", 4, 0x02, BANK0, },
718 { "in_unicast", 4, 0x04, BANK0, },
719 { "in_broadcasts", 4, 0x06, BANK0, },
720 { "in_multicasts", 4, 0x07, BANK0, },
721 { "in_pause", 4, 0x16, BANK0, },
722 { "in_undersize", 4, 0x18, BANK0, },
723 { "in_fragments", 4, 0x19, BANK0, },
724 { "in_oversize", 4, 0x1a, BANK0, },
725 { "in_jabber", 4, 0x1b, BANK0, },
726 { "in_rx_error", 4, 0x1c, BANK0, },
727 { "in_fcs_error", 4, 0x1d, BANK0, },
728 { "out_octets", 8, 0x0e, BANK0, },
729 { "out_unicast", 4, 0x10, BANK0, },
730 { "out_broadcasts", 4, 0x13, BANK0, },
731 { "out_multicasts", 4, 0x12, BANK0, },
732 { "out_pause", 4, 0x15, BANK0, },
733 { "excessive", 4, 0x11, BANK0, },
734 { "collisions", 4, 0x1e, BANK0, },
735 { "deferred", 4, 0x05, BANK0, },
736 { "single", 4, 0x14, BANK0, },
737 { "multiple", 4, 0x17, BANK0, },
738 { "out_fcs_error", 4, 0x03, BANK0, },
739 { "late", 4, 0x1f, BANK0, },
740 { "hist_64bytes", 4, 0x08, BANK0, },
741 { "hist_65_127bytes", 4, 0x09, BANK0, },
742 { "hist_128_255bytes", 4, 0x0a, BANK0, },
743 { "hist_256_511bytes", 4, 0x0b, BANK0, },
744 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
745 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
746 { "sw_in_discards", 4, 0x10, PORT, },
747 { "sw_in_filtered", 2, 0x12, PORT, },
748 { "sw_out_filtered", 2, 0x13, PORT, },
749 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
750 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
751 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
752 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
753 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
754 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
755 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
756 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
757 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
758 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
759 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
760 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
761 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
762 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
763 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
764 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
765 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
766 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
767 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
768 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
769 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
770 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
771 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
772 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
773 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
774 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
775 };
776
777 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
778 struct mv88e6xxx_hw_stat *stat)
779 {
780 switch (stat->type) {
781 case BANK0:
782 return true;
783 case BANK1:
784 return mv88e6xxx_6320_family(chip);
785 case PORT:
786 return mv88e6xxx_6095_family(chip) ||
787 mv88e6xxx_6185_family(chip) ||
788 mv88e6xxx_6097_family(chip) ||
789 mv88e6xxx_6165_family(chip) ||
790 mv88e6xxx_6351_family(chip) ||
791 mv88e6xxx_6352_family(chip);
792 }
793 return false;
794 }
795
796 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
797 struct mv88e6xxx_hw_stat *s,
798 int port)
799 {
800 u32 low;
801 u32 high = 0;
802 int ret;
803 u64 value;
804
805 switch (s->type) {
806 case PORT:
807 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
808 if (ret < 0)
809 return UINT64_MAX;
810
811 low = ret;
812 if (s->sizeof_stat == 4) {
813 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
814 s->reg + 1);
815 if (ret < 0)
816 return UINT64_MAX;
817 high = ret;
818 }
819 break;
820 case BANK0:
821 case BANK1:
822 _mv88e6xxx_stats_read(chip, s->reg, &low);
823 if (s->sizeof_stat == 8)
824 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
825 }
826 value = (((u64)high) << 16) | low;
827 return value;
828 }
829
830 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
831 uint8_t *data)
832 {
833 struct mv88e6xxx_chip *chip = ds->priv;
834 struct mv88e6xxx_hw_stat *stat;
835 int i, j;
836
837 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
838 stat = &mv88e6xxx_hw_stats[i];
839 if (mv88e6xxx_has_stat(chip, stat)) {
840 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
841 ETH_GSTRING_LEN);
842 j++;
843 }
844 }
845 }
846
847 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
848 {
849 struct mv88e6xxx_chip *chip = ds->priv;
850 struct mv88e6xxx_hw_stat *stat;
851 int i, j;
852
853 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
854 stat = &mv88e6xxx_hw_stats[i];
855 if (mv88e6xxx_has_stat(chip, stat))
856 j++;
857 }
858 return j;
859 }
860
861 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
862 uint64_t *data)
863 {
864 struct mv88e6xxx_chip *chip = ds->priv;
865 struct mv88e6xxx_hw_stat *stat;
866 int ret;
867 int i, j;
868
869 mutex_lock(&chip->reg_lock);
870
871 ret = _mv88e6xxx_stats_snapshot(chip, port);
872 if (ret < 0) {
873 mutex_unlock(&chip->reg_lock);
874 return;
875 }
876 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
877 stat = &mv88e6xxx_hw_stats[i];
878 if (mv88e6xxx_has_stat(chip, stat)) {
879 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
880 j++;
881 }
882 }
883
884 mutex_unlock(&chip->reg_lock);
885 }
886
887 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
888 {
889 return 32 * sizeof(u16);
890 }
891
892 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
893 struct ethtool_regs *regs, void *_p)
894 {
895 struct mv88e6xxx_chip *chip = ds->priv;
896 u16 *p = _p;
897 int i;
898
899 regs->version = 0;
900
901 memset(p, 0xff, 32 * sizeof(u16));
902
903 mutex_lock(&chip->reg_lock);
904
905 for (i = 0; i < 32; i++) {
906 int ret;
907
908 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
909 if (ret >= 0)
910 p[i] = ret;
911 }
912
913 mutex_unlock(&chip->reg_lock);
914 }
915
916 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
917 {
918 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
919 GLOBAL_ATU_OP_BUSY);
920 }
921
922 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
923 struct ethtool_eee *e)
924 {
925 struct mv88e6xxx_chip *chip = ds->priv;
926 u16 reg;
927 int err;
928
929 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
930 return -EOPNOTSUPP;
931
932 mutex_lock(&chip->reg_lock);
933
934 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
935 if (err)
936 goto out;
937
938 e->eee_enabled = !!(reg & 0x0200);
939 e->tx_lpi_enabled = !!(reg & 0x0100);
940
941 err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
942 if (err)
943 goto out;
944
945 e->eee_active = !!(reg & PORT_STATUS_EEE);
946 out:
947 mutex_unlock(&chip->reg_lock);
948
949 return err;
950 }
951
952 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
953 struct phy_device *phydev, struct ethtool_eee *e)
954 {
955 struct mv88e6xxx_chip *chip = ds->priv;
956 u16 reg;
957 int err;
958
959 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
960 return -EOPNOTSUPP;
961
962 mutex_lock(&chip->reg_lock);
963
964 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
965 if (err)
966 goto out;
967
968 reg &= ~0x0300;
969 if (e->eee_enabled)
970 reg |= 0x0200;
971 if (e->tx_lpi_enabled)
972 reg |= 0x0100;
973
974 err = mv88e6xxx_phy_write(chip, port, 16, reg);
975 out:
976 mutex_unlock(&chip->reg_lock);
977
978 return err;
979 }
980
981 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
982 {
983 int ret;
984
985 if (mv88e6xxx_has_fid_reg(chip)) {
986 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
987 fid);
988 if (ret < 0)
989 return ret;
990 } else if (mv88e6xxx_num_databases(chip) == 256) {
991 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
992 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
993 if (ret < 0)
994 return ret;
995
996 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
997 (ret & 0xfff) |
998 ((fid << 8) & 0xf000));
999 if (ret < 0)
1000 return ret;
1001
1002 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1003 cmd |= fid & 0xf;
1004 }
1005
1006 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1007 if (ret < 0)
1008 return ret;
1009
1010 return _mv88e6xxx_atu_wait(chip);
1011 }
1012
1013 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1014 struct mv88e6xxx_atu_entry *entry)
1015 {
1016 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1017
1018 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1019 unsigned int mask, shift;
1020
1021 if (entry->trunk) {
1022 data |= GLOBAL_ATU_DATA_TRUNK;
1023 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1024 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1025 } else {
1026 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1027 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1028 }
1029
1030 data |= (entry->portv_trunkid << shift) & mask;
1031 }
1032
1033 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1034 }
1035
1036 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1037 struct mv88e6xxx_atu_entry *entry,
1038 bool static_too)
1039 {
1040 int op;
1041 int err;
1042
1043 err = _mv88e6xxx_atu_wait(chip);
1044 if (err)
1045 return err;
1046
1047 err = _mv88e6xxx_atu_data_write(chip, entry);
1048 if (err)
1049 return err;
1050
1051 if (entry->fid) {
1052 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1053 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1054 } else {
1055 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1056 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1057 }
1058
1059 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1060 }
1061
1062 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1063 u16 fid, bool static_too)
1064 {
1065 struct mv88e6xxx_atu_entry entry = {
1066 .fid = fid,
1067 .state = 0, /* EntryState bits must be 0 */
1068 };
1069
1070 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1071 }
1072
1073 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1074 int from_port, int to_port, bool static_too)
1075 {
1076 struct mv88e6xxx_atu_entry entry = {
1077 .trunk = false,
1078 .fid = fid,
1079 };
1080
1081 /* EntryState bits must be 0xF */
1082 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1083
1084 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1085 entry.portv_trunkid = (to_port & 0x0f) << 4;
1086 entry.portv_trunkid |= from_port & 0x0f;
1087
1088 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1089 }
1090
1091 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1092 int port, bool static_too)
1093 {
1094 /* Destination port 0xF means remove the entries */
1095 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1096 }
1097
1098 static const char * const mv88e6xxx_port_state_names[] = {
1099 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1100 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1101 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1102 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1103 };
1104
1105 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1106 u8 state)
1107 {
1108 struct dsa_switch *ds = chip->ds;
1109 int reg, ret = 0;
1110 u8 oldstate;
1111
1112 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1113 if (reg < 0)
1114 return reg;
1115
1116 oldstate = reg & PORT_CONTROL_STATE_MASK;
1117
1118 if (oldstate != state) {
1119 /* Flush forwarding database if we're moving a port
1120 * from Learning or Forwarding state to Disabled or
1121 * Blocking or Listening state.
1122 */
1123 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1124 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1125 (state == PORT_CONTROL_STATE_DISABLED ||
1126 state == PORT_CONTROL_STATE_BLOCKING)) {
1127 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1128 if (ret)
1129 return ret;
1130 }
1131
1132 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1133 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1134 reg);
1135 if (ret)
1136 return ret;
1137
1138 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1139 mv88e6xxx_port_state_names[state],
1140 mv88e6xxx_port_state_names[oldstate]);
1141 }
1142
1143 return ret;
1144 }
1145
1146 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1147 {
1148 struct net_device *bridge = chip->ports[port].bridge_dev;
1149 const u16 mask = (1 << chip->info->num_ports) - 1;
1150 struct dsa_switch *ds = chip->ds;
1151 u16 output_ports = 0;
1152 int reg;
1153 int i;
1154
1155 /* allow CPU port or DSA link(s) to send frames to every port */
1156 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1157 output_ports = mask;
1158 } else {
1159 for (i = 0; i < chip->info->num_ports; ++i) {
1160 /* allow sending frames to every group member */
1161 if (bridge && chip->ports[i].bridge_dev == bridge)
1162 output_ports |= BIT(i);
1163
1164 /* allow sending frames to CPU port and DSA link(s) */
1165 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1166 output_ports |= BIT(i);
1167 }
1168 }
1169
1170 /* prevent frames from going back out of the port they came in on */
1171 output_ports &= ~BIT(port);
1172
1173 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1174 if (reg < 0)
1175 return reg;
1176
1177 reg &= ~mask;
1178 reg |= output_ports & mask;
1179
1180 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1181 }
1182
1183 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1184 u8 state)
1185 {
1186 struct mv88e6xxx_chip *chip = ds->priv;
1187 int stp_state;
1188 int err;
1189
1190 switch (state) {
1191 case BR_STATE_DISABLED:
1192 stp_state = PORT_CONTROL_STATE_DISABLED;
1193 break;
1194 case BR_STATE_BLOCKING:
1195 case BR_STATE_LISTENING:
1196 stp_state = PORT_CONTROL_STATE_BLOCKING;
1197 break;
1198 case BR_STATE_LEARNING:
1199 stp_state = PORT_CONTROL_STATE_LEARNING;
1200 break;
1201 case BR_STATE_FORWARDING:
1202 default:
1203 stp_state = PORT_CONTROL_STATE_FORWARDING;
1204 break;
1205 }
1206
1207 mutex_lock(&chip->reg_lock);
1208 err = _mv88e6xxx_port_state(chip, port, stp_state);
1209 mutex_unlock(&chip->reg_lock);
1210
1211 if (err)
1212 netdev_err(ds->ports[port].netdev,
1213 "failed to update state to %s\n",
1214 mv88e6xxx_port_state_names[stp_state]);
1215 }
1216
1217 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1218 u16 *new, u16 *old)
1219 {
1220 struct dsa_switch *ds = chip->ds;
1221 u16 pvid;
1222 int ret;
1223
1224 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1225 if (ret < 0)
1226 return ret;
1227
1228 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1229
1230 if (new) {
1231 ret &= ~PORT_DEFAULT_VLAN_MASK;
1232 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1233
1234 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1235 PORT_DEFAULT_VLAN, ret);
1236 if (ret < 0)
1237 return ret;
1238
1239 netdev_dbg(ds->ports[port].netdev,
1240 "DefaultVID %d (was %d)\n", *new, pvid);
1241 }
1242
1243 if (old)
1244 *old = pvid;
1245
1246 return 0;
1247 }
1248
1249 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1250 int port, u16 *pvid)
1251 {
1252 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1253 }
1254
1255 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1256 int port, u16 pvid)
1257 {
1258 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1259 }
1260
1261 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1262 {
1263 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1264 GLOBAL_VTU_OP_BUSY);
1265 }
1266
1267 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1268 {
1269 int ret;
1270
1271 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1272 if (ret < 0)
1273 return ret;
1274
1275 return _mv88e6xxx_vtu_wait(chip);
1276 }
1277
1278 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1279 {
1280 int ret;
1281
1282 ret = _mv88e6xxx_vtu_wait(chip);
1283 if (ret < 0)
1284 return ret;
1285
1286 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1287 }
1288
1289 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1290 struct mv88e6xxx_vtu_stu_entry *entry,
1291 unsigned int nibble_offset)
1292 {
1293 u16 regs[3];
1294 int i;
1295 int ret;
1296
1297 for (i = 0; i < 3; ++i) {
1298 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1299 GLOBAL_VTU_DATA_0_3 + i);
1300 if (ret < 0)
1301 return ret;
1302
1303 regs[i] = ret;
1304 }
1305
1306 for (i = 0; i < chip->info->num_ports; ++i) {
1307 unsigned int shift = (i % 4) * 4 + nibble_offset;
1308 u16 reg = regs[i / 4];
1309
1310 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1311 }
1312
1313 return 0;
1314 }
1315
1316 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1317 struct mv88e6xxx_vtu_stu_entry *entry)
1318 {
1319 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1320 }
1321
1322 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1323 struct mv88e6xxx_vtu_stu_entry *entry)
1324 {
1325 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1326 }
1327
1328 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1329 struct mv88e6xxx_vtu_stu_entry *entry,
1330 unsigned int nibble_offset)
1331 {
1332 u16 regs[3] = { 0 };
1333 int i;
1334 int ret;
1335
1336 for (i = 0; i < chip->info->num_ports; ++i) {
1337 unsigned int shift = (i % 4) * 4 + nibble_offset;
1338 u8 data = entry->data[i];
1339
1340 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1341 }
1342
1343 for (i = 0; i < 3; ++i) {
1344 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1345 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1346 if (ret < 0)
1347 return ret;
1348 }
1349
1350 return 0;
1351 }
1352
1353 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1354 struct mv88e6xxx_vtu_stu_entry *entry)
1355 {
1356 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1357 }
1358
1359 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1360 struct mv88e6xxx_vtu_stu_entry *entry)
1361 {
1362 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1363 }
1364
1365 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1366 {
1367 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1368 vid & GLOBAL_VTU_VID_MASK);
1369 }
1370
1371 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1372 struct mv88e6xxx_vtu_stu_entry *entry)
1373 {
1374 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1375 int ret;
1376
1377 ret = _mv88e6xxx_vtu_wait(chip);
1378 if (ret < 0)
1379 return ret;
1380
1381 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1382 if (ret < 0)
1383 return ret;
1384
1385 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1386 if (ret < 0)
1387 return ret;
1388
1389 next.vid = ret & GLOBAL_VTU_VID_MASK;
1390 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1391
1392 if (next.valid) {
1393 ret = mv88e6xxx_vtu_data_read(chip, &next);
1394 if (ret < 0)
1395 return ret;
1396
1397 if (mv88e6xxx_has_fid_reg(chip)) {
1398 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1399 GLOBAL_VTU_FID);
1400 if (ret < 0)
1401 return ret;
1402
1403 next.fid = ret & GLOBAL_VTU_FID_MASK;
1404 } else if (mv88e6xxx_num_databases(chip) == 256) {
1405 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1406 * VTU DBNum[3:0] are located in VTU Operation 3:0
1407 */
1408 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1409 GLOBAL_VTU_OP);
1410 if (ret < 0)
1411 return ret;
1412
1413 next.fid = (ret & 0xf00) >> 4;
1414 next.fid |= ret & 0xf;
1415 }
1416
1417 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1418 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1419 GLOBAL_VTU_SID);
1420 if (ret < 0)
1421 return ret;
1422
1423 next.sid = ret & GLOBAL_VTU_SID_MASK;
1424 }
1425 }
1426
1427 *entry = next;
1428 return 0;
1429 }
1430
1431 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1432 struct switchdev_obj_port_vlan *vlan,
1433 int (*cb)(struct switchdev_obj *obj))
1434 {
1435 struct mv88e6xxx_chip *chip = ds->priv;
1436 struct mv88e6xxx_vtu_stu_entry next;
1437 u16 pvid;
1438 int err;
1439
1440 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1441 return -EOPNOTSUPP;
1442
1443 mutex_lock(&chip->reg_lock);
1444
1445 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1446 if (err)
1447 goto unlock;
1448
1449 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1450 if (err)
1451 goto unlock;
1452
1453 do {
1454 err = _mv88e6xxx_vtu_getnext(chip, &next);
1455 if (err)
1456 break;
1457
1458 if (!next.valid)
1459 break;
1460
1461 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1462 continue;
1463
1464 /* reinit and dump this VLAN obj */
1465 vlan->vid_begin = next.vid;
1466 vlan->vid_end = next.vid;
1467 vlan->flags = 0;
1468
1469 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1470 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1471
1472 if (next.vid == pvid)
1473 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1474
1475 err = cb(&vlan->obj);
1476 if (err)
1477 break;
1478 } while (next.vid < GLOBAL_VTU_VID_MASK);
1479
1480 unlock:
1481 mutex_unlock(&chip->reg_lock);
1482
1483 return err;
1484 }
1485
1486 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1487 struct mv88e6xxx_vtu_stu_entry *entry)
1488 {
1489 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1490 u16 reg = 0;
1491 int ret;
1492
1493 ret = _mv88e6xxx_vtu_wait(chip);
1494 if (ret < 0)
1495 return ret;
1496
1497 if (!entry->valid)
1498 goto loadpurge;
1499
1500 /* Write port member tags */
1501 ret = mv88e6xxx_vtu_data_write(chip, entry);
1502 if (ret < 0)
1503 return ret;
1504
1505 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1506 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1507 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1508 reg);
1509 if (ret < 0)
1510 return ret;
1511 }
1512
1513 if (mv88e6xxx_has_fid_reg(chip)) {
1514 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1515 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1516 reg);
1517 if (ret < 0)
1518 return ret;
1519 } else if (mv88e6xxx_num_databases(chip) == 256) {
1520 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1521 * VTU DBNum[3:0] are located in VTU Operation 3:0
1522 */
1523 op |= (entry->fid & 0xf0) << 8;
1524 op |= entry->fid & 0xf;
1525 }
1526
1527 reg = GLOBAL_VTU_VID_VALID;
1528 loadpurge:
1529 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1530 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1531 if (ret < 0)
1532 return ret;
1533
1534 return _mv88e6xxx_vtu_cmd(chip, op);
1535 }
1536
1537 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1538 struct mv88e6xxx_vtu_stu_entry *entry)
1539 {
1540 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1541 int ret;
1542
1543 ret = _mv88e6xxx_vtu_wait(chip);
1544 if (ret < 0)
1545 return ret;
1546
1547 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1548 sid & GLOBAL_VTU_SID_MASK);
1549 if (ret < 0)
1550 return ret;
1551
1552 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1553 if (ret < 0)
1554 return ret;
1555
1556 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1557 if (ret < 0)
1558 return ret;
1559
1560 next.sid = ret & GLOBAL_VTU_SID_MASK;
1561
1562 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1563 if (ret < 0)
1564 return ret;
1565
1566 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1567
1568 if (next.valid) {
1569 ret = mv88e6xxx_stu_data_read(chip, &next);
1570 if (ret < 0)
1571 return ret;
1572 }
1573
1574 *entry = next;
1575 return 0;
1576 }
1577
1578 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1579 struct mv88e6xxx_vtu_stu_entry *entry)
1580 {
1581 u16 reg = 0;
1582 int ret;
1583
1584 ret = _mv88e6xxx_vtu_wait(chip);
1585 if (ret < 0)
1586 return ret;
1587
1588 if (!entry->valid)
1589 goto loadpurge;
1590
1591 /* Write port states */
1592 ret = mv88e6xxx_stu_data_write(chip, entry);
1593 if (ret < 0)
1594 return ret;
1595
1596 reg = GLOBAL_VTU_VID_VALID;
1597 loadpurge:
1598 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1599 if (ret < 0)
1600 return ret;
1601
1602 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1603 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1604 if (ret < 0)
1605 return ret;
1606
1607 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1608 }
1609
1610 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1611 u16 *new, u16 *old)
1612 {
1613 struct dsa_switch *ds = chip->ds;
1614 u16 upper_mask;
1615 u16 fid;
1616 int ret;
1617
1618 if (mv88e6xxx_num_databases(chip) == 4096)
1619 upper_mask = 0xff;
1620 else if (mv88e6xxx_num_databases(chip) == 256)
1621 upper_mask = 0xf;
1622 else
1623 return -EOPNOTSUPP;
1624
1625 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1626 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1627 if (ret < 0)
1628 return ret;
1629
1630 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1631
1632 if (new) {
1633 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1634 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1635
1636 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1637 ret);
1638 if (ret < 0)
1639 return ret;
1640 }
1641
1642 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1643 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1644 if (ret < 0)
1645 return ret;
1646
1647 fid |= (ret & upper_mask) << 4;
1648
1649 if (new) {
1650 ret &= ~upper_mask;
1651 ret |= (*new >> 4) & upper_mask;
1652
1653 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1654 ret);
1655 if (ret < 0)
1656 return ret;
1657
1658 netdev_dbg(ds->ports[port].netdev,
1659 "FID %d (was %d)\n", *new, fid);
1660 }
1661
1662 if (old)
1663 *old = fid;
1664
1665 return 0;
1666 }
1667
1668 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1669 int port, u16 *fid)
1670 {
1671 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1672 }
1673
1674 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1675 int port, u16 fid)
1676 {
1677 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1678 }
1679
1680 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1681 {
1682 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1683 struct mv88e6xxx_vtu_stu_entry vlan;
1684 int i, err;
1685
1686 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1687
1688 /* Set every FID bit used by the (un)bridged ports */
1689 for (i = 0; i < chip->info->num_ports; ++i) {
1690 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1691 if (err)
1692 return err;
1693
1694 set_bit(*fid, fid_bitmap);
1695 }
1696
1697 /* Set every FID bit used by the VLAN entries */
1698 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1699 if (err)
1700 return err;
1701
1702 do {
1703 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1704 if (err)
1705 return err;
1706
1707 if (!vlan.valid)
1708 break;
1709
1710 set_bit(vlan.fid, fid_bitmap);
1711 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1712
1713 /* The reset value 0x000 is used to indicate that multiple address
1714 * databases are not needed. Return the next positive available.
1715 */
1716 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1717 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1718 return -ENOSPC;
1719
1720 /* Clear the database */
1721 return _mv88e6xxx_atu_flush(chip, *fid, true);
1722 }
1723
1724 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1725 struct mv88e6xxx_vtu_stu_entry *entry)
1726 {
1727 struct dsa_switch *ds = chip->ds;
1728 struct mv88e6xxx_vtu_stu_entry vlan = {
1729 .valid = true,
1730 .vid = vid,
1731 };
1732 int i, err;
1733
1734 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1735 if (err)
1736 return err;
1737
1738 /* exclude all ports except the CPU and DSA ports */
1739 for (i = 0; i < chip->info->num_ports; ++i)
1740 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1741 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1742 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1743
1744 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1745 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1746 struct mv88e6xxx_vtu_stu_entry vstp;
1747
1748 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1749 * implemented, only one STU entry is needed to cover all VTU
1750 * entries. Thus, validate the SID 0.
1751 */
1752 vlan.sid = 0;
1753 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1754 if (err)
1755 return err;
1756
1757 if (vstp.sid != vlan.sid || !vstp.valid) {
1758 memset(&vstp, 0, sizeof(vstp));
1759 vstp.valid = true;
1760 vstp.sid = vlan.sid;
1761
1762 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1763 if (err)
1764 return err;
1765 }
1766 }
1767
1768 *entry = vlan;
1769 return 0;
1770 }
1771
1772 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1773 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1774 {
1775 int err;
1776
1777 if (!vid)
1778 return -EINVAL;
1779
1780 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1781 if (err)
1782 return err;
1783
1784 err = _mv88e6xxx_vtu_getnext(chip, entry);
1785 if (err)
1786 return err;
1787
1788 if (entry->vid != vid || !entry->valid) {
1789 if (!creat)
1790 return -EOPNOTSUPP;
1791 /* -ENOENT would've been more appropriate, but switchdev expects
1792 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1793 */
1794
1795 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1796 }
1797
1798 return err;
1799 }
1800
1801 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1802 u16 vid_begin, u16 vid_end)
1803 {
1804 struct mv88e6xxx_chip *chip = ds->priv;
1805 struct mv88e6xxx_vtu_stu_entry vlan;
1806 int i, err;
1807
1808 if (!vid_begin)
1809 return -EOPNOTSUPP;
1810
1811 mutex_lock(&chip->reg_lock);
1812
1813 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1814 if (err)
1815 goto unlock;
1816
1817 do {
1818 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1819 if (err)
1820 goto unlock;
1821
1822 if (!vlan.valid)
1823 break;
1824
1825 if (vlan.vid > vid_end)
1826 break;
1827
1828 for (i = 0; i < chip->info->num_ports; ++i) {
1829 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1830 continue;
1831
1832 if (vlan.data[i] ==
1833 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1834 continue;
1835
1836 if (chip->ports[i].bridge_dev ==
1837 chip->ports[port].bridge_dev)
1838 break; /* same bridge, check next VLAN */
1839
1840 netdev_warn(ds->ports[port].netdev,
1841 "hardware VLAN %d already used by %s\n",
1842 vlan.vid,
1843 netdev_name(chip->ports[i].bridge_dev));
1844 err = -EOPNOTSUPP;
1845 goto unlock;
1846 }
1847 } while (vlan.vid < vid_end);
1848
1849 unlock:
1850 mutex_unlock(&chip->reg_lock);
1851
1852 return err;
1853 }
1854
1855 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1856 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1857 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1858 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1859 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1860 };
1861
1862 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1863 bool vlan_filtering)
1864 {
1865 struct mv88e6xxx_chip *chip = ds->priv;
1866 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1867 PORT_CONTROL_2_8021Q_DISABLED;
1868 int ret;
1869
1870 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1871 return -EOPNOTSUPP;
1872
1873 mutex_lock(&chip->reg_lock);
1874
1875 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1876 if (ret < 0)
1877 goto unlock;
1878
1879 old = ret & PORT_CONTROL_2_8021Q_MASK;
1880
1881 if (new != old) {
1882 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1883 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1884
1885 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1886 ret);
1887 if (ret < 0)
1888 goto unlock;
1889
1890 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1891 mv88e6xxx_port_8021q_mode_names[new],
1892 mv88e6xxx_port_8021q_mode_names[old]);
1893 }
1894
1895 ret = 0;
1896 unlock:
1897 mutex_unlock(&chip->reg_lock);
1898
1899 return ret;
1900 }
1901
1902 static int
1903 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1904 const struct switchdev_obj_port_vlan *vlan,
1905 struct switchdev_trans *trans)
1906 {
1907 struct mv88e6xxx_chip *chip = ds->priv;
1908 int err;
1909
1910 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1911 return -EOPNOTSUPP;
1912
1913 /* If the requested port doesn't belong to the same bridge as the VLAN
1914 * members, do not support it (yet) and fallback to software VLAN.
1915 */
1916 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1917 vlan->vid_end);
1918 if (err)
1919 return err;
1920
1921 /* We don't need any dynamic resource from the kernel (yet),
1922 * so skip the prepare phase.
1923 */
1924 return 0;
1925 }
1926
1927 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1928 u16 vid, bool untagged)
1929 {
1930 struct mv88e6xxx_vtu_stu_entry vlan;
1931 int err;
1932
1933 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1934 if (err)
1935 return err;
1936
1937 vlan.data[port] = untagged ?
1938 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1939 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1940
1941 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1942 }
1943
1944 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1945 const struct switchdev_obj_port_vlan *vlan,
1946 struct switchdev_trans *trans)
1947 {
1948 struct mv88e6xxx_chip *chip = ds->priv;
1949 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1950 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1951 u16 vid;
1952
1953 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1954 return;
1955
1956 mutex_lock(&chip->reg_lock);
1957
1958 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1959 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1960 netdev_err(ds->ports[port].netdev,
1961 "failed to add VLAN %d%c\n",
1962 vid, untagged ? 'u' : 't');
1963
1964 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1965 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1966 vlan->vid_end);
1967
1968 mutex_unlock(&chip->reg_lock);
1969 }
1970
1971 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1972 int port, u16 vid)
1973 {
1974 struct dsa_switch *ds = chip->ds;
1975 struct mv88e6xxx_vtu_stu_entry vlan;
1976 int i, err;
1977
1978 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1979 if (err)
1980 return err;
1981
1982 /* Tell switchdev if this VLAN is handled in software */
1983 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1984 return -EOPNOTSUPP;
1985
1986 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1987
1988 /* keep the VLAN unless all ports are excluded */
1989 vlan.valid = false;
1990 for (i = 0; i < chip->info->num_ports; ++i) {
1991 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1992 continue;
1993
1994 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1995 vlan.valid = true;
1996 break;
1997 }
1998 }
1999
2000 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2001 if (err)
2002 return err;
2003
2004 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2005 }
2006
2007 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2008 const struct switchdev_obj_port_vlan *vlan)
2009 {
2010 struct mv88e6xxx_chip *chip = ds->priv;
2011 u16 pvid, vid;
2012 int err = 0;
2013
2014 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2015 return -EOPNOTSUPP;
2016
2017 mutex_lock(&chip->reg_lock);
2018
2019 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2020 if (err)
2021 goto unlock;
2022
2023 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2024 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2025 if (err)
2026 goto unlock;
2027
2028 if (vid == pvid) {
2029 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2030 if (err)
2031 goto unlock;
2032 }
2033 }
2034
2035 unlock:
2036 mutex_unlock(&chip->reg_lock);
2037
2038 return err;
2039 }
2040
2041 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2042 const unsigned char *addr)
2043 {
2044 int i, ret;
2045
2046 for (i = 0; i < 3; i++) {
2047 ret = _mv88e6xxx_reg_write(
2048 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2049 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2050 if (ret < 0)
2051 return ret;
2052 }
2053
2054 return 0;
2055 }
2056
2057 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2058 unsigned char *addr)
2059 {
2060 int i, ret;
2061
2062 for (i = 0; i < 3; i++) {
2063 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2064 GLOBAL_ATU_MAC_01 + i);
2065 if (ret < 0)
2066 return ret;
2067 addr[i * 2] = ret >> 8;
2068 addr[i * 2 + 1] = ret & 0xff;
2069 }
2070
2071 return 0;
2072 }
2073
2074 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2075 struct mv88e6xxx_atu_entry *entry)
2076 {
2077 int ret;
2078
2079 ret = _mv88e6xxx_atu_wait(chip);
2080 if (ret < 0)
2081 return ret;
2082
2083 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2084 if (ret < 0)
2085 return ret;
2086
2087 ret = _mv88e6xxx_atu_data_write(chip, entry);
2088 if (ret < 0)
2089 return ret;
2090
2091 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2092 }
2093
2094 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2095 const unsigned char *addr, u16 vid,
2096 u8 state)
2097 {
2098 struct mv88e6xxx_atu_entry entry = { 0 };
2099 struct mv88e6xxx_vtu_stu_entry vlan;
2100 int err;
2101
2102 /* Null VLAN ID corresponds to the port private database */
2103 if (vid == 0)
2104 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2105 else
2106 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2107 if (err)
2108 return err;
2109
2110 entry.fid = vlan.fid;
2111 entry.state = state;
2112 ether_addr_copy(entry.mac, addr);
2113 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2114 entry.trunk = false;
2115 entry.portv_trunkid = BIT(port);
2116 }
2117
2118 return _mv88e6xxx_atu_load(chip, &entry);
2119 }
2120
2121 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2122 const struct switchdev_obj_port_fdb *fdb,
2123 struct switchdev_trans *trans)
2124 {
2125 /* We don't need any dynamic resource from the kernel (yet),
2126 * so skip the prepare phase.
2127 */
2128 return 0;
2129 }
2130
2131 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2132 const struct switchdev_obj_port_fdb *fdb,
2133 struct switchdev_trans *trans)
2134 {
2135 struct mv88e6xxx_chip *chip = ds->priv;
2136
2137 mutex_lock(&chip->reg_lock);
2138 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2139 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2140 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2141 mutex_unlock(&chip->reg_lock);
2142 }
2143
2144 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2145 const struct switchdev_obj_port_fdb *fdb)
2146 {
2147 struct mv88e6xxx_chip *chip = ds->priv;
2148 int err;
2149
2150 mutex_lock(&chip->reg_lock);
2151 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2152 GLOBAL_ATU_DATA_STATE_UNUSED);
2153 mutex_unlock(&chip->reg_lock);
2154
2155 return err;
2156 }
2157
2158 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2159 struct mv88e6xxx_atu_entry *entry)
2160 {
2161 struct mv88e6xxx_atu_entry next = { 0 };
2162 int ret;
2163
2164 next.fid = fid;
2165
2166 ret = _mv88e6xxx_atu_wait(chip);
2167 if (ret < 0)
2168 return ret;
2169
2170 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2171 if (ret < 0)
2172 return ret;
2173
2174 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2175 if (ret < 0)
2176 return ret;
2177
2178 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2179 if (ret < 0)
2180 return ret;
2181
2182 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2183 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2184 unsigned int mask, shift;
2185
2186 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2187 next.trunk = true;
2188 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2189 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2190 } else {
2191 next.trunk = false;
2192 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2193 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2194 }
2195
2196 next.portv_trunkid = (ret & mask) >> shift;
2197 }
2198
2199 *entry = next;
2200 return 0;
2201 }
2202
2203 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2204 u16 fid, u16 vid, int port,
2205 struct switchdev_obj *obj,
2206 int (*cb)(struct switchdev_obj *obj))
2207 {
2208 struct mv88e6xxx_atu_entry addr = {
2209 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2210 };
2211 int err;
2212
2213 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2214 if (err)
2215 return err;
2216
2217 do {
2218 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2219 if (err)
2220 return err;
2221
2222 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2223 break;
2224
2225 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2226 continue;
2227
2228 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2229 struct switchdev_obj_port_fdb *fdb;
2230
2231 if (!is_unicast_ether_addr(addr.mac))
2232 continue;
2233
2234 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2235 fdb->vid = vid;
2236 ether_addr_copy(fdb->addr, addr.mac);
2237 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2238 fdb->ndm_state = NUD_NOARP;
2239 else
2240 fdb->ndm_state = NUD_REACHABLE;
2241 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2242 struct switchdev_obj_port_mdb *mdb;
2243
2244 if (!is_multicast_ether_addr(addr.mac))
2245 continue;
2246
2247 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2248 mdb->vid = vid;
2249 ether_addr_copy(mdb->addr, addr.mac);
2250 } else {
2251 return -EOPNOTSUPP;
2252 }
2253
2254 err = cb(obj);
2255 if (err)
2256 return err;
2257 } while (!is_broadcast_ether_addr(addr.mac));
2258
2259 return err;
2260 }
2261
2262 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2263 struct switchdev_obj *obj,
2264 int (*cb)(struct switchdev_obj *obj))
2265 {
2266 struct mv88e6xxx_vtu_stu_entry vlan = {
2267 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2268 };
2269 u16 fid;
2270 int err;
2271
2272 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2273 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2274 if (err)
2275 return err;
2276
2277 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2278 if (err)
2279 return err;
2280
2281 /* Dump VLANs' Filtering Information Databases */
2282 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2283 if (err)
2284 return err;
2285
2286 do {
2287 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2288 if (err)
2289 return err;
2290
2291 if (!vlan.valid)
2292 break;
2293
2294 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2295 obj, cb);
2296 if (err)
2297 return err;
2298 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2299
2300 return err;
2301 }
2302
2303 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2304 struct switchdev_obj_port_fdb *fdb,
2305 int (*cb)(struct switchdev_obj *obj))
2306 {
2307 struct mv88e6xxx_chip *chip = ds->priv;
2308 int err;
2309
2310 mutex_lock(&chip->reg_lock);
2311 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2312 mutex_unlock(&chip->reg_lock);
2313
2314 return err;
2315 }
2316
2317 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2318 struct net_device *bridge)
2319 {
2320 struct mv88e6xxx_chip *chip = ds->priv;
2321 int i, err = 0;
2322
2323 mutex_lock(&chip->reg_lock);
2324
2325 /* Assign the bridge and remap each port's VLANTable */
2326 chip->ports[port].bridge_dev = bridge;
2327
2328 for (i = 0; i < chip->info->num_ports; ++i) {
2329 if (chip->ports[i].bridge_dev == bridge) {
2330 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2331 if (err)
2332 break;
2333 }
2334 }
2335
2336 mutex_unlock(&chip->reg_lock);
2337
2338 return err;
2339 }
2340
2341 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2342 {
2343 struct mv88e6xxx_chip *chip = ds->priv;
2344 struct net_device *bridge = chip->ports[port].bridge_dev;
2345 int i;
2346
2347 mutex_lock(&chip->reg_lock);
2348
2349 /* Unassign the bridge and remap each port's VLANTable */
2350 chip->ports[port].bridge_dev = NULL;
2351
2352 for (i = 0; i < chip->info->num_ports; ++i)
2353 if (i == port || chip->ports[i].bridge_dev == bridge)
2354 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2355 netdev_warn(ds->ports[i].netdev,
2356 "failed to remap\n");
2357
2358 mutex_unlock(&chip->reg_lock);
2359 }
2360
2361 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2362 {
2363 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2364 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2365 struct gpio_desc *gpiod = chip->reset;
2366 unsigned long timeout;
2367 int ret;
2368 int i;
2369
2370 /* Set all ports to the disabled state. */
2371 for (i = 0; i < chip->info->num_ports; i++) {
2372 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2373 if (ret < 0)
2374 return ret;
2375
2376 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2377 ret & 0xfffc);
2378 if (ret)
2379 return ret;
2380 }
2381
2382 /* Wait for transmit queues to drain. */
2383 usleep_range(2000, 4000);
2384
2385 /* If there is a gpio connected to the reset pin, toggle it */
2386 if (gpiod) {
2387 gpiod_set_value_cansleep(gpiod, 1);
2388 usleep_range(10000, 20000);
2389 gpiod_set_value_cansleep(gpiod, 0);
2390 usleep_range(10000, 20000);
2391 }
2392
2393 /* Reset the switch. Keep the PPU active if requested. The PPU
2394 * needs to be active to support indirect phy register access
2395 * through global registers 0x18 and 0x19.
2396 */
2397 if (ppu_active)
2398 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2399 else
2400 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2401 if (ret)
2402 return ret;
2403
2404 /* Wait up to one second for reset to complete. */
2405 timeout = jiffies + 1 * HZ;
2406 while (time_before(jiffies, timeout)) {
2407 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2408 if (ret < 0)
2409 return ret;
2410
2411 if ((ret & is_reset) == is_reset)
2412 break;
2413 usleep_range(1000, 2000);
2414 }
2415 if (time_after(jiffies, timeout))
2416 ret = -ETIMEDOUT;
2417 else
2418 ret = 0;
2419
2420 return ret;
2421 }
2422
2423 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2424 {
2425 u16 val;
2426 int err;
2427
2428 /* Clear Power Down bit */
2429 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2430 if (err)
2431 return err;
2432
2433 if (val & BMCR_PDOWN) {
2434 val &= ~BMCR_PDOWN;
2435 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2436 }
2437
2438 return err;
2439 }
2440
2441 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2442 int reg, u16 *val)
2443 {
2444 int addr = chip->info->port_base_addr + port;
2445
2446 if (port >= chip->info->num_ports)
2447 return -EINVAL;
2448
2449 return mv88e6xxx_read(chip, addr, reg, val);
2450 }
2451
2452 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2453 {
2454 struct dsa_switch *ds = chip->ds;
2455 int ret;
2456 u16 reg;
2457
2458 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2459 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2460 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2461 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2462 /* MAC Forcing register: don't force link, speed,
2463 * duplex or flow control state to any particular
2464 * values on physical ports, but force the CPU port
2465 * and all DSA ports to their maximum bandwidth and
2466 * full duplex.
2467 */
2468 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2469 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2470 reg &= ~PORT_PCS_CTRL_UNFORCED;
2471 reg |= PORT_PCS_CTRL_FORCE_LINK |
2472 PORT_PCS_CTRL_LINK_UP |
2473 PORT_PCS_CTRL_DUPLEX_FULL |
2474 PORT_PCS_CTRL_FORCE_DUPLEX;
2475 if (mv88e6xxx_6065_family(chip))
2476 reg |= PORT_PCS_CTRL_100;
2477 else
2478 reg |= PORT_PCS_CTRL_1000;
2479 } else {
2480 reg |= PORT_PCS_CTRL_UNFORCED;
2481 }
2482
2483 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2484 PORT_PCS_CTRL, reg);
2485 if (ret)
2486 return ret;
2487 }
2488
2489 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2490 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2491 * tunneling, determine priority by looking at 802.1p and IP
2492 * priority fields (IP prio has precedence), and set STP state
2493 * to Forwarding.
2494 *
2495 * If this is the CPU link, use DSA or EDSA tagging depending
2496 * on which tagging mode was configured.
2497 *
2498 * If this is a link to another switch, use DSA tagging mode.
2499 *
2500 * If this is the upstream port for this switch, enable
2501 * forwarding of unknown unicasts and multicasts.
2502 */
2503 reg = 0;
2504 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2505 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2506 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2507 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2508 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2509 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2510 PORT_CONTROL_STATE_FORWARDING;
2511 if (dsa_is_cpu_port(ds, port)) {
2512 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2513 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2514 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2515 else
2516 reg |= PORT_CONTROL_DSA_TAG;
2517 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2518 PORT_CONTROL_FORWARD_UNKNOWN;
2519 }
2520 if (dsa_is_dsa_port(ds, port)) {
2521 if (mv88e6xxx_6095_family(chip) ||
2522 mv88e6xxx_6185_family(chip))
2523 reg |= PORT_CONTROL_DSA_TAG;
2524 if (mv88e6xxx_6352_family(chip) ||
2525 mv88e6xxx_6351_family(chip) ||
2526 mv88e6xxx_6165_family(chip) ||
2527 mv88e6xxx_6097_family(chip) ||
2528 mv88e6xxx_6320_family(chip)) {
2529 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2530 }
2531
2532 if (port == dsa_upstream_port(ds))
2533 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2534 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2535 }
2536 if (reg) {
2537 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2538 PORT_CONTROL, reg);
2539 if (ret)
2540 return ret;
2541 }
2542
2543 /* If this port is connected to a SerDes, make sure the SerDes is not
2544 * powered down.
2545 */
2546 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2547 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2548 if (ret < 0)
2549 return ret;
2550 ret &= PORT_STATUS_CMODE_MASK;
2551 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2552 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2553 (ret == PORT_STATUS_CMODE_SGMII)) {
2554 ret = mv88e6xxx_serdes_power_on(chip);
2555 if (ret < 0)
2556 return ret;
2557 }
2558 }
2559
2560 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2561 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2562 * untagged frames on this port, do a destination address lookup on all
2563 * received packets as usual, disable ARP mirroring and don't send a
2564 * copy of all transmitted/received frames on this port to the CPU.
2565 */
2566 reg = 0;
2567 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2568 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2569 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2570 mv88e6xxx_6185_family(chip))
2571 reg = PORT_CONTROL_2_MAP_DA;
2572
2573 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2574 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2575 reg |= PORT_CONTROL_2_JUMBO_10240;
2576
2577 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2578 /* Set the upstream port this port should use */
2579 reg |= dsa_upstream_port(ds);
2580 /* enable forwarding of unknown multicast addresses to
2581 * the upstream port
2582 */
2583 if (port == dsa_upstream_port(ds))
2584 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2585 }
2586
2587 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2588
2589 if (reg) {
2590 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2591 PORT_CONTROL_2, reg);
2592 if (ret)
2593 return ret;
2594 }
2595
2596 /* Port Association Vector: when learning source addresses
2597 * of packets, add the address to the address database using
2598 * a port bitmap that has only the bit for this port set and
2599 * the other bits clear.
2600 */
2601 reg = 1 << port;
2602 /* Disable learning for CPU port */
2603 if (dsa_is_cpu_port(ds, port))
2604 reg = 0;
2605
2606 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2607 reg);
2608 if (ret)
2609 return ret;
2610
2611 /* Egress rate control 2: disable egress rate control. */
2612 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2613 0x0000);
2614 if (ret)
2615 return ret;
2616
2617 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2618 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2619 mv88e6xxx_6320_family(chip)) {
2620 /* Do not limit the period of time that this port can
2621 * be paused for by the remote end or the period of
2622 * time that this port can pause the remote end.
2623 */
2624 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2625 PORT_PAUSE_CTRL, 0x0000);
2626 if (ret)
2627 return ret;
2628
2629 /* Port ATU control: disable limiting the number of
2630 * address database entries that this port is allowed
2631 * to use.
2632 */
2633 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2634 PORT_ATU_CONTROL, 0x0000);
2635 /* Priority Override: disable DA, SA and VTU priority
2636 * override.
2637 */
2638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2639 PORT_PRI_OVERRIDE, 0x0000);
2640 if (ret)
2641 return ret;
2642
2643 /* Port Ethertype: use the Ethertype DSA Ethertype
2644 * value.
2645 */
2646 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2647 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2648 PORT_ETH_TYPE, ETH_P_EDSA);
2649 if (ret)
2650 return ret;
2651 }
2652
2653 /* Tag Remap: use an identity 802.1p prio -> switch
2654 * prio mapping.
2655 */
2656 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2657 PORT_TAG_REGMAP_0123, 0x3210);
2658 if (ret)
2659 return ret;
2660
2661 /* Tag Remap 2: use an identity 802.1p prio -> switch
2662 * prio mapping.
2663 */
2664 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2665 PORT_TAG_REGMAP_4567, 0x7654);
2666 if (ret)
2667 return ret;
2668 }
2669
2670 /* Rate Control: disable ingress rate limiting. */
2671 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2672 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2673 mv88e6xxx_6320_family(chip)) {
2674 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2675 PORT_RATE_CONTROL, 0x0001);
2676 if (ret)
2677 return ret;
2678 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2679 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2680 PORT_RATE_CONTROL, 0x0000);
2681 if (ret)
2682 return ret;
2683 }
2684
2685 /* Port Control 1: disable trunking, disable sending
2686 * learning messages to this port.
2687 */
2688 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2689 0x0000);
2690 if (ret)
2691 return ret;
2692
2693 /* Port based VLAN map: give each port the same default address
2694 * database, and allow bidirectional communication between the
2695 * CPU and DSA port(s), and the other ports.
2696 */
2697 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2698 if (ret)
2699 return ret;
2700
2701 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2702 if (ret)
2703 return ret;
2704
2705 /* Default VLAN ID and priority: don't set a default VLAN
2706 * ID, and set the default packet priority to zero.
2707 */
2708 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2709 0x0000);
2710 if (ret)
2711 return ret;
2712
2713 return 0;
2714 }
2715
2716 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2717 {
2718 int err;
2719
2720 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2721 (addr[0] << 8) | addr[1]);
2722 if (err)
2723 return err;
2724
2725 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2726 (addr[2] << 8) | addr[3]);
2727 if (err)
2728 return err;
2729
2730 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2731 (addr[4] << 8) | addr[5]);
2732 }
2733
2734 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2735 unsigned int msecs)
2736 {
2737 const unsigned int coeff = chip->info->age_time_coeff;
2738 const unsigned int min = 0x01 * coeff;
2739 const unsigned int max = 0xff * coeff;
2740 u8 age_time;
2741 u16 val;
2742 int err;
2743
2744 if (msecs < min || msecs > max)
2745 return -ERANGE;
2746
2747 /* Round to nearest multiple of coeff */
2748 age_time = (msecs + coeff / 2) / coeff;
2749
2750 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2751 if (err)
2752 return err;
2753
2754 /* AgeTime is 11:4 bits */
2755 val &= ~0xff0;
2756 val |= age_time << 4;
2757
2758 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2759 }
2760
2761 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2762 unsigned int ageing_time)
2763 {
2764 struct mv88e6xxx_chip *chip = ds->priv;
2765 int err;
2766
2767 mutex_lock(&chip->reg_lock);
2768 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2769 mutex_unlock(&chip->reg_lock);
2770
2771 return err;
2772 }
2773
2774 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2775 {
2776 struct dsa_switch *ds = chip->ds;
2777 u32 upstream_port = dsa_upstream_port(ds);
2778 u16 reg;
2779 int err;
2780
2781 /* Enable the PHY Polling Unit if present, don't discard any packets,
2782 * and mask all interrupt sources.
2783 */
2784 reg = 0;
2785 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2786 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2787 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2788
2789 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2790 if (err)
2791 return err;
2792
2793 /* Configure the upstream port, and configure it as the port to which
2794 * ingress and egress and ARP monitor frames are to be sent.
2795 */
2796 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2797 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2798 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2799 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2800 reg);
2801 if (err)
2802 return err;
2803
2804 /* Disable remote management, and set the switch's DSA device number. */
2805 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2806 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2807 (ds->index & 0x1f));
2808 if (err)
2809 return err;
2810
2811 /* Clear all the VTU and STU entries */
2812 err = _mv88e6xxx_vtu_stu_flush(chip);
2813 if (err < 0)
2814 return err;
2815
2816 /* Set the default address aging time to 5 minutes, and
2817 * enable address learn messages to be sent to all message
2818 * ports.
2819 */
2820 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2821 GLOBAL_ATU_CONTROL_LEARN2ALL);
2822 if (err)
2823 return err;
2824
2825 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2826 if (err)
2827 return err;
2828
2829 /* Clear all ATU entries */
2830 err = _mv88e6xxx_atu_flush(chip, 0, true);
2831 if (err)
2832 return err;
2833
2834 /* Configure the IP ToS mapping registers. */
2835 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2836 if (err)
2837 return err;
2838 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2839 if (err)
2840 return err;
2841 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2842 if (err)
2843 return err;
2844 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2845 if (err)
2846 return err;
2847 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2848 if (err)
2849 return err;
2850 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2851 if (err)
2852 return err;
2853 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2854 if (err)
2855 return err;
2856 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2857 if (err)
2858 return err;
2859
2860 /* Configure the IEEE 802.1p priority mapping register. */
2861 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2862 if (err)
2863 return err;
2864
2865 /* Clear the statistics counters for all ports */
2866 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2867 GLOBAL_STATS_OP_FLUSH_ALL);
2868 if (err)
2869 return err;
2870
2871 /* Wait for the flush to complete. */
2872 err = _mv88e6xxx_stats_wait(chip);
2873 if (err)
2874 return err;
2875
2876 return 0;
2877 }
2878
2879 static int mv88e6xxx_setup(struct dsa_switch *ds)
2880 {
2881 struct mv88e6xxx_chip *chip = ds->priv;
2882 int err;
2883 int i;
2884
2885 chip->ds = ds;
2886 ds->slave_mii_bus = chip->mdio_bus;
2887
2888 mutex_lock(&chip->reg_lock);
2889
2890 err = mv88e6xxx_switch_reset(chip);
2891 if (err)
2892 goto unlock;
2893
2894 /* Setup Switch Port Registers */
2895 for (i = 0; i < chip->info->num_ports; i++) {
2896 err = mv88e6xxx_setup_port(chip, i);
2897 if (err)
2898 goto unlock;
2899 }
2900
2901 /* Setup Switch Global 1 Registers */
2902 err = mv88e6xxx_g1_setup(chip);
2903 if (err)
2904 goto unlock;
2905
2906 /* Setup Switch Global 2 Registers */
2907 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2908 err = mv88e6xxx_g2_setup(chip);
2909 if (err)
2910 goto unlock;
2911 }
2912
2913 unlock:
2914 mutex_unlock(&chip->reg_lock);
2915
2916 return err;
2917 }
2918
2919 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2920 {
2921 struct mv88e6xxx_chip *chip = ds->priv;
2922 int err;
2923
2924 mutex_lock(&chip->reg_lock);
2925
2926 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2927 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
2928 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
2929 else
2930 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
2931
2932 mutex_unlock(&chip->reg_lock);
2933
2934 return err;
2935 }
2936
2937 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2938 {
2939 struct mv88e6xxx_chip *chip = bus->priv;
2940 u16 val;
2941 int err;
2942
2943 if (phy >= chip->info->num_ports)
2944 return 0xffff;
2945
2946 mutex_lock(&chip->reg_lock);
2947 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2948 mutex_unlock(&chip->reg_lock);
2949
2950 return err ? err : val;
2951 }
2952
2953 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2954 {
2955 struct mv88e6xxx_chip *chip = bus->priv;
2956 int err;
2957
2958 if (phy >= chip->info->num_ports)
2959 return 0xffff;
2960
2961 mutex_lock(&chip->reg_lock);
2962 err = mv88e6xxx_phy_write(chip, phy, reg, val);
2963 mutex_unlock(&chip->reg_lock);
2964
2965 return err;
2966 }
2967
2968 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2969 struct device_node *np)
2970 {
2971 static int index;
2972 struct mii_bus *bus;
2973 int err;
2974
2975 if (np)
2976 chip->mdio_np = of_get_child_by_name(np, "mdio");
2977
2978 bus = devm_mdiobus_alloc(chip->dev);
2979 if (!bus)
2980 return -ENOMEM;
2981
2982 bus->priv = (void *)chip;
2983 if (np) {
2984 bus->name = np->full_name;
2985 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2986 } else {
2987 bus->name = "mv88e6xxx SMI";
2988 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2989 }
2990
2991 bus->read = mv88e6xxx_mdio_read;
2992 bus->write = mv88e6xxx_mdio_write;
2993 bus->parent = chip->dev;
2994
2995 if (chip->mdio_np)
2996 err = of_mdiobus_register(bus, chip->mdio_np);
2997 else
2998 err = mdiobus_register(bus);
2999 if (err) {
3000 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3001 goto out;
3002 }
3003 chip->mdio_bus = bus;
3004
3005 return 0;
3006
3007 out:
3008 if (chip->mdio_np)
3009 of_node_put(chip->mdio_np);
3010
3011 return err;
3012 }
3013
3014 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3015
3016 {
3017 struct mii_bus *bus = chip->mdio_bus;
3018
3019 mdiobus_unregister(bus);
3020
3021 if (chip->mdio_np)
3022 of_node_put(chip->mdio_np);
3023 }
3024
3025 #ifdef CONFIG_NET_DSA_HWMON
3026
3027 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3028 {
3029 struct mv88e6xxx_chip *chip = ds->priv;
3030 u16 val;
3031 int ret;
3032
3033 *temp = 0;
3034
3035 mutex_lock(&chip->reg_lock);
3036
3037 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3038 if (ret < 0)
3039 goto error;
3040
3041 /* Enable temperature sensor */
3042 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3043 if (ret < 0)
3044 goto error;
3045
3046 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3047 if (ret < 0)
3048 goto error;
3049
3050 /* Wait for temperature to stabilize */
3051 usleep_range(10000, 12000);
3052
3053 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3054 if (ret < 0)
3055 goto error;
3056
3057 /* Disable temperature sensor */
3058 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3059 if (ret < 0)
3060 goto error;
3061
3062 *temp = ((val & 0x1f) - 5) * 5;
3063
3064 error:
3065 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3066 mutex_unlock(&chip->reg_lock);
3067 return ret;
3068 }
3069
3070 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3071 {
3072 struct mv88e6xxx_chip *chip = ds->priv;
3073 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3074 u16 val;
3075 int ret;
3076
3077 *temp = 0;
3078
3079 mutex_lock(&chip->reg_lock);
3080 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3081 mutex_unlock(&chip->reg_lock);
3082 if (ret < 0)
3083 return ret;
3084
3085 *temp = (val & 0xff) - 25;
3086
3087 return 0;
3088 }
3089
3090 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3091 {
3092 struct mv88e6xxx_chip *chip = ds->priv;
3093
3094 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3095 return -EOPNOTSUPP;
3096
3097 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3098 return mv88e63xx_get_temp(ds, temp);
3099
3100 return mv88e61xx_get_temp(ds, temp);
3101 }
3102
3103 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3104 {
3105 struct mv88e6xxx_chip *chip = ds->priv;
3106 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3107 u16 val;
3108 int ret;
3109
3110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3111 return -EOPNOTSUPP;
3112
3113 *temp = 0;
3114
3115 mutex_lock(&chip->reg_lock);
3116 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3117 mutex_unlock(&chip->reg_lock);
3118 if (ret < 0)
3119 return ret;
3120
3121 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3122
3123 return 0;
3124 }
3125
3126 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3127 {
3128 struct mv88e6xxx_chip *chip = ds->priv;
3129 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3130 u16 val;
3131 int err;
3132
3133 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3134 return -EOPNOTSUPP;
3135
3136 mutex_lock(&chip->reg_lock);
3137 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3138 if (err)
3139 goto unlock;
3140 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3141 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3142 (val & 0xe0ff) | (temp << 8));
3143 unlock:
3144 mutex_unlock(&chip->reg_lock);
3145
3146 return err;
3147 }
3148
3149 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3150 {
3151 struct mv88e6xxx_chip *chip = ds->priv;
3152 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3153 u16 val;
3154 int ret;
3155
3156 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3157 return -EOPNOTSUPP;
3158
3159 *alarm = false;
3160
3161 mutex_lock(&chip->reg_lock);
3162 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3163 mutex_unlock(&chip->reg_lock);
3164 if (ret < 0)
3165 return ret;
3166
3167 *alarm = !!(val & 0x40);
3168
3169 return 0;
3170 }
3171 #endif /* CONFIG_NET_DSA_HWMON */
3172
3173 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3174 {
3175 struct mv88e6xxx_chip *chip = ds->priv;
3176
3177 return chip->eeprom_len;
3178 }
3179
3180 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3181 struct ethtool_eeprom *eeprom, u8 *data)
3182 {
3183 struct mv88e6xxx_chip *chip = ds->priv;
3184 int err;
3185
3186 mutex_lock(&chip->reg_lock);
3187
3188 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3189 err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
3190 else
3191 err = -EOPNOTSUPP;
3192
3193 mutex_unlock(&chip->reg_lock);
3194
3195 if (err)
3196 return err;
3197
3198 eeprom->magic = 0xc3ec4951;
3199
3200 return 0;
3201 }
3202
3203 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3204 struct ethtool_eeprom *eeprom, u8 *data)
3205 {
3206 struct mv88e6xxx_chip *chip = ds->priv;
3207 int err;
3208
3209 if (eeprom->magic != 0xc3ec4951)
3210 return -EINVAL;
3211
3212 mutex_lock(&chip->reg_lock);
3213
3214 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3215 err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
3216 else
3217 err = -EOPNOTSUPP;
3218
3219 mutex_unlock(&chip->reg_lock);
3220
3221 return err;
3222 }
3223
3224 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3225 [MV88E6085] = {
3226 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3227 .family = MV88E6XXX_FAMILY_6097,
3228 .name = "Marvell 88E6085",
3229 .num_databases = 4096,
3230 .num_ports = 10,
3231 .port_base_addr = 0x10,
3232 .age_time_coeff = 15000,
3233 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3234 },
3235
3236 [MV88E6095] = {
3237 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3238 .family = MV88E6XXX_FAMILY_6095,
3239 .name = "Marvell 88E6095/88E6095F",
3240 .num_databases = 256,
3241 .num_ports = 11,
3242 .port_base_addr = 0x10,
3243 .age_time_coeff = 15000,
3244 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3245 },
3246
3247 [MV88E6123] = {
3248 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3249 .family = MV88E6XXX_FAMILY_6165,
3250 .name = "Marvell 88E6123",
3251 .num_databases = 4096,
3252 .num_ports = 3,
3253 .port_base_addr = 0x10,
3254 .age_time_coeff = 15000,
3255 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3256 },
3257
3258 [MV88E6131] = {
3259 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3260 .family = MV88E6XXX_FAMILY_6185,
3261 .name = "Marvell 88E6131",
3262 .num_databases = 256,
3263 .num_ports = 8,
3264 .port_base_addr = 0x10,
3265 .age_time_coeff = 15000,
3266 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3267 },
3268
3269 [MV88E6161] = {
3270 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3271 .family = MV88E6XXX_FAMILY_6165,
3272 .name = "Marvell 88E6161",
3273 .num_databases = 4096,
3274 .num_ports = 6,
3275 .port_base_addr = 0x10,
3276 .age_time_coeff = 15000,
3277 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3278 },
3279
3280 [MV88E6165] = {
3281 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3282 .family = MV88E6XXX_FAMILY_6165,
3283 .name = "Marvell 88E6165",
3284 .num_databases = 4096,
3285 .num_ports = 6,
3286 .port_base_addr = 0x10,
3287 .age_time_coeff = 15000,
3288 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3289 },
3290
3291 [MV88E6171] = {
3292 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3293 .family = MV88E6XXX_FAMILY_6351,
3294 .name = "Marvell 88E6171",
3295 .num_databases = 4096,
3296 .num_ports = 7,
3297 .port_base_addr = 0x10,
3298 .age_time_coeff = 15000,
3299 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3300 },
3301
3302 [MV88E6172] = {
3303 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3304 .family = MV88E6XXX_FAMILY_6352,
3305 .name = "Marvell 88E6172",
3306 .num_databases = 4096,
3307 .num_ports = 7,
3308 .port_base_addr = 0x10,
3309 .age_time_coeff = 15000,
3310 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3311 },
3312
3313 [MV88E6175] = {
3314 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3315 .family = MV88E6XXX_FAMILY_6351,
3316 .name = "Marvell 88E6175",
3317 .num_databases = 4096,
3318 .num_ports = 7,
3319 .port_base_addr = 0x10,
3320 .age_time_coeff = 15000,
3321 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3322 },
3323
3324 [MV88E6176] = {
3325 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3326 .family = MV88E6XXX_FAMILY_6352,
3327 .name = "Marvell 88E6176",
3328 .num_databases = 4096,
3329 .num_ports = 7,
3330 .port_base_addr = 0x10,
3331 .age_time_coeff = 15000,
3332 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3333 },
3334
3335 [MV88E6185] = {
3336 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3337 .family = MV88E6XXX_FAMILY_6185,
3338 .name = "Marvell 88E6185",
3339 .num_databases = 256,
3340 .num_ports = 10,
3341 .port_base_addr = 0x10,
3342 .age_time_coeff = 15000,
3343 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3344 },
3345
3346 [MV88E6240] = {
3347 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3348 .family = MV88E6XXX_FAMILY_6352,
3349 .name = "Marvell 88E6240",
3350 .num_databases = 4096,
3351 .num_ports = 7,
3352 .port_base_addr = 0x10,
3353 .age_time_coeff = 15000,
3354 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3355 },
3356
3357 [MV88E6320] = {
3358 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3359 .family = MV88E6XXX_FAMILY_6320,
3360 .name = "Marvell 88E6320",
3361 .num_databases = 4096,
3362 .num_ports = 7,
3363 .port_base_addr = 0x10,
3364 .age_time_coeff = 15000,
3365 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3366 },
3367
3368 [MV88E6321] = {
3369 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3370 .family = MV88E6XXX_FAMILY_6320,
3371 .name = "Marvell 88E6321",
3372 .num_databases = 4096,
3373 .num_ports = 7,
3374 .port_base_addr = 0x10,
3375 .age_time_coeff = 15000,
3376 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3377 },
3378
3379 [MV88E6350] = {
3380 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3381 .family = MV88E6XXX_FAMILY_6351,
3382 .name = "Marvell 88E6350",
3383 .num_databases = 4096,
3384 .num_ports = 7,
3385 .port_base_addr = 0x10,
3386 .age_time_coeff = 15000,
3387 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3388 },
3389
3390 [MV88E6351] = {
3391 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3392 .family = MV88E6XXX_FAMILY_6351,
3393 .name = "Marvell 88E6351",
3394 .num_databases = 4096,
3395 .num_ports = 7,
3396 .port_base_addr = 0x10,
3397 .age_time_coeff = 15000,
3398 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3399 },
3400
3401 [MV88E6352] = {
3402 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3403 .family = MV88E6XXX_FAMILY_6352,
3404 .name = "Marvell 88E6352",
3405 .num_databases = 4096,
3406 .num_ports = 7,
3407 .port_base_addr = 0x10,
3408 .age_time_coeff = 15000,
3409 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3410 },
3411 };
3412
3413 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3414 {
3415 int i;
3416
3417 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3418 if (mv88e6xxx_table[i].prod_num == prod_num)
3419 return &mv88e6xxx_table[i];
3420
3421 return NULL;
3422 }
3423
3424 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3425 {
3426 const struct mv88e6xxx_info *info;
3427 unsigned int prod_num, rev;
3428 u16 id;
3429 int err;
3430
3431 mutex_lock(&chip->reg_lock);
3432 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3433 mutex_unlock(&chip->reg_lock);
3434 if (err)
3435 return err;
3436
3437 prod_num = (id & 0xfff0) >> 4;
3438 rev = id & 0x000f;
3439
3440 info = mv88e6xxx_lookup_info(prod_num);
3441 if (!info)
3442 return -ENODEV;
3443
3444 /* Update the compatible info with the probed one */
3445 chip->info = info;
3446
3447 err = mv88e6xxx_g2_require(chip);
3448 if (err)
3449 return err;
3450
3451 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3452 chip->info->prod_num, chip->info->name, rev);
3453
3454 return 0;
3455 }
3456
3457 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3458 {
3459 struct mv88e6xxx_chip *chip;
3460
3461 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3462 if (!chip)
3463 return NULL;
3464
3465 chip->dev = dev;
3466
3467 mutex_init(&chip->reg_lock);
3468
3469 return chip;
3470 }
3471
3472 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3473 .read = mv88e6xxx_g2_smi_phy_read,
3474 .write = mv88e6xxx_g2_smi_phy_write,
3475 };
3476
3477 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3478 .read = mv88e6xxx_read,
3479 .write = mv88e6xxx_write,
3480 };
3481
3482 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3483 {
3484 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3485 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3486 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3487 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3488 mv88e6xxx_ppu_state_init(chip);
3489 } else {
3490 chip->phy_ops = &mv88e6xxx_phy_ops;
3491 }
3492 }
3493
3494 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3495 {
3496 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3497 mv88e6xxx_ppu_state_destroy(chip);
3498 }
3499 }
3500
3501 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3502 struct mii_bus *bus, int sw_addr)
3503 {
3504 /* ADDR[0] pin is unavailable externally and considered zero */
3505 if (sw_addr & 0x1)
3506 return -EINVAL;
3507
3508 if (sw_addr == 0)
3509 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3510 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3511 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3512 else
3513 return -EINVAL;
3514
3515 chip->bus = bus;
3516 chip->sw_addr = sw_addr;
3517
3518 return 0;
3519 }
3520
3521 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3522 {
3523 struct mv88e6xxx_chip *chip = ds->priv;
3524
3525 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3526 return DSA_TAG_PROTO_EDSA;
3527
3528 return DSA_TAG_PROTO_DSA;
3529 }
3530
3531 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3532 struct device *host_dev, int sw_addr,
3533 void **priv)
3534 {
3535 struct mv88e6xxx_chip *chip;
3536 struct mii_bus *bus;
3537 int err;
3538
3539 bus = dsa_host_dev_to_mii_bus(host_dev);
3540 if (!bus)
3541 return NULL;
3542
3543 chip = mv88e6xxx_alloc_chip(dsa_dev);
3544 if (!chip)
3545 return NULL;
3546
3547 /* Legacy SMI probing will only support chips similar to 88E6085 */
3548 chip->info = &mv88e6xxx_table[MV88E6085];
3549
3550 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3551 if (err)
3552 goto free;
3553
3554 err = mv88e6xxx_detect(chip);
3555 if (err)
3556 goto free;
3557
3558 mv88e6xxx_phy_init(chip);
3559
3560 err = mv88e6xxx_mdio_register(chip, NULL);
3561 if (err)
3562 goto free;
3563
3564 *priv = chip;
3565
3566 return chip->info->name;
3567 free:
3568 devm_kfree(dsa_dev, chip);
3569
3570 return NULL;
3571 }
3572
3573 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3574 const struct switchdev_obj_port_mdb *mdb,
3575 struct switchdev_trans *trans)
3576 {
3577 /* We don't need any dynamic resource from the kernel (yet),
3578 * so skip the prepare phase.
3579 */
3580
3581 return 0;
3582 }
3583
3584 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3585 const struct switchdev_obj_port_mdb *mdb,
3586 struct switchdev_trans *trans)
3587 {
3588 struct mv88e6xxx_chip *chip = ds->priv;
3589
3590 mutex_lock(&chip->reg_lock);
3591 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3592 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3593 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3594 mutex_unlock(&chip->reg_lock);
3595 }
3596
3597 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3598 const struct switchdev_obj_port_mdb *mdb)
3599 {
3600 struct mv88e6xxx_chip *chip = ds->priv;
3601 int err;
3602
3603 mutex_lock(&chip->reg_lock);
3604 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3605 GLOBAL_ATU_DATA_STATE_UNUSED);
3606 mutex_unlock(&chip->reg_lock);
3607
3608 return err;
3609 }
3610
3611 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3612 struct switchdev_obj_port_mdb *mdb,
3613 int (*cb)(struct switchdev_obj *obj))
3614 {
3615 struct mv88e6xxx_chip *chip = ds->priv;
3616 int err;
3617
3618 mutex_lock(&chip->reg_lock);
3619 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3620 mutex_unlock(&chip->reg_lock);
3621
3622 return err;
3623 }
3624
3625 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3626 .probe = mv88e6xxx_drv_probe,
3627 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3628 .setup = mv88e6xxx_setup,
3629 .set_addr = mv88e6xxx_set_addr,
3630 .adjust_link = mv88e6xxx_adjust_link,
3631 .get_strings = mv88e6xxx_get_strings,
3632 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3633 .get_sset_count = mv88e6xxx_get_sset_count,
3634 .set_eee = mv88e6xxx_set_eee,
3635 .get_eee = mv88e6xxx_get_eee,
3636 #ifdef CONFIG_NET_DSA_HWMON
3637 .get_temp = mv88e6xxx_get_temp,
3638 .get_temp_limit = mv88e6xxx_get_temp_limit,
3639 .set_temp_limit = mv88e6xxx_set_temp_limit,
3640 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3641 #endif
3642 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3643 .get_eeprom = mv88e6xxx_get_eeprom,
3644 .set_eeprom = mv88e6xxx_set_eeprom,
3645 .get_regs_len = mv88e6xxx_get_regs_len,
3646 .get_regs = mv88e6xxx_get_regs,
3647 .set_ageing_time = mv88e6xxx_set_ageing_time,
3648 .port_bridge_join = mv88e6xxx_port_bridge_join,
3649 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3650 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3651 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3652 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3653 .port_vlan_add = mv88e6xxx_port_vlan_add,
3654 .port_vlan_del = mv88e6xxx_port_vlan_del,
3655 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3656 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3657 .port_fdb_add = mv88e6xxx_port_fdb_add,
3658 .port_fdb_del = mv88e6xxx_port_fdb_del,
3659 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3660 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3661 .port_mdb_add = mv88e6xxx_port_mdb_add,
3662 .port_mdb_del = mv88e6xxx_port_mdb_del,
3663 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3664 };
3665
3666 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3667 struct device_node *np)
3668 {
3669 struct device *dev = chip->dev;
3670 struct dsa_switch *ds;
3671
3672 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3673 if (!ds)
3674 return -ENOMEM;
3675
3676 ds->dev = dev;
3677 ds->priv = chip;
3678 ds->ops = &mv88e6xxx_switch_ops;
3679
3680 dev_set_drvdata(dev, ds);
3681
3682 return dsa_register_switch(ds, np);
3683 }
3684
3685 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3686 {
3687 dsa_unregister_switch(chip->ds);
3688 }
3689
3690 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3691 {
3692 struct device *dev = &mdiodev->dev;
3693 struct device_node *np = dev->of_node;
3694 const struct mv88e6xxx_info *compat_info;
3695 struct mv88e6xxx_chip *chip;
3696 u32 eeprom_len;
3697 int err;
3698
3699 compat_info = of_device_get_match_data(dev);
3700 if (!compat_info)
3701 return -EINVAL;
3702
3703 chip = mv88e6xxx_alloc_chip(dev);
3704 if (!chip)
3705 return -ENOMEM;
3706
3707 chip->info = compat_info;
3708
3709 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3710 if (err)
3711 return err;
3712
3713 err = mv88e6xxx_detect(chip);
3714 if (err)
3715 return err;
3716
3717 mv88e6xxx_phy_init(chip);
3718
3719 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3720 if (IS_ERR(chip->reset))
3721 return PTR_ERR(chip->reset);
3722
3723 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
3724 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3725 chip->eeprom_len = eeprom_len;
3726
3727 err = mv88e6xxx_mdio_register(chip, np);
3728 if (err)
3729 return err;
3730
3731 err = mv88e6xxx_register_switch(chip, np);
3732 if (err) {
3733 mv88e6xxx_mdio_unregister(chip);
3734 return err;
3735 }
3736
3737 return 0;
3738 }
3739
3740 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3741 {
3742 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3743 struct mv88e6xxx_chip *chip = ds->priv;
3744
3745 mv88e6xxx_phy_destroy(chip);
3746 mv88e6xxx_unregister_switch(chip);
3747 mv88e6xxx_mdio_unregister(chip);
3748 }
3749
3750 static const struct of_device_id mv88e6xxx_of_match[] = {
3751 {
3752 .compatible = "marvell,mv88e6085",
3753 .data = &mv88e6xxx_table[MV88E6085],
3754 },
3755 { /* sentinel */ },
3756 };
3757
3758 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3759
3760 static struct mdio_driver mv88e6xxx_driver = {
3761 .probe = mv88e6xxx_probe,
3762 .remove = mv88e6xxx_remove,
3763 .mdiodrv.driver = {
3764 .name = "mv88e6085",
3765 .of_match_table = mv88e6xxx_of_match,
3766 },
3767 };
3768
3769 static int __init mv88e6xxx_init(void)
3770 {
3771 register_switch_driver(&mv88e6xxx_switch_ops);
3772 return mdio_driver_register(&mv88e6xxx_driver);
3773 }
3774 module_init(mv88e6xxx_init);
3775
3776 static void __exit mv88e6xxx_cleanup(void)
3777 {
3778 mdio_driver_unregister(&mv88e6xxx_driver);
3779 unregister_switch_driver(&mv88e6xxx_switch_ops);
3780 }
3781 module_exit(mv88e6xxx_cleanup);
3782
3783 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3784 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3785 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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