2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/netdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/phy.h>
31 #include <net/switchdev.h>
33 #include "mv88e6xxx.h"
36 static void assert_reg_lock(struct mv88e6xxx_chip
*chip
)
38 if (unlikely(!mutex_is_locked(&chip
->reg_lock
))) {
39 dev_err(chip
->dev
, "Switch registers lock not held!\n");
44 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
45 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
47 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
48 * is the only device connected to the SMI master. In this mode it responds to
49 * all 32 possible SMI addresses, and thus maps directly the internal devices.
51 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
52 * multiple devices to share the SMI interface. In this mode it responds to only
53 * 2 registers, used to indirectly access the internal SMI devices.
56 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip
*chip
,
57 int addr
, int reg
, u16
*val
)
62 return chip
->smi_ops
->read(chip
, addr
, reg
, val
);
65 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip
*chip
,
66 int addr
, int reg
, u16 val
)
71 return chip
->smi_ops
->write(chip
, addr
, reg
, val
);
74 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip
*chip
,
75 int addr
, int reg
, u16
*val
)
79 ret
= mdiobus_read_nested(chip
->bus
, addr
, reg
);
88 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip
*chip
,
89 int addr
, int reg
, u16 val
)
93 ret
= mdiobus_write_nested(chip
->bus
, addr
, reg
, val
);
100 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops
= {
101 .read
= mv88e6xxx_smi_single_chip_read
,
102 .write
= mv88e6xxx_smi_single_chip_write
,
105 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip
*chip
)
110 for (i
= 0; i
< 16; i
++) {
111 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
);
115 if ((ret
& SMI_CMD_BUSY
) == 0)
122 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip
*chip
,
123 int addr
, int reg
, u16
*val
)
127 /* Wait for the bus to become free. */
128 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
132 /* Transmit the read command. */
133 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
134 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
138 /* Wait for the read command to complete. */
139 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
144 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
);
153 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip
*chip
,
154 int addr
, int reg
, u16 val
)
158 /* Wait for the bus to become free. */
159 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
163 /* Transmit the data to write. */
164 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
, val
);
168 /* Transmit the write command. */
169 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
170 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
174 /* Wait for the write command to complete. */
175 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
182 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops
= {
183 .read
= mv88e6xxx_smi_multi_chip_read
,
184 .write
= mv88e6xxx_smi_multi_chip_write
,
187 int mv88e6xxx_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16
*val
)
191 assert_reg_lock(chip
);
193 err
= mv88e6xxx_smi_read(chip
, addr
, reg
, val
);
197 dev_dbg(chip
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
203 int mv88e6xxx_write(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 val
)
207 assert_reg_lock(chip
);
209 err
= mv88e6xxx_smi_write(chip
, addr
, reg
, val
);
213 dev_dbg(chip
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip
*chip
, int phy
,
222 int addr
= phy
; /* PHY devices addresses start at 0x0 */
227 return chip
->phy_ops
->read(chip
, addr
, reg
, val
);
230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip
*chip
, int phy
,
233 int addr
= phy
; /* PHY devices addresses start at 0x0 */
238 return chip
->phy_ops
->write(chip
, addr
, reg
, val
);
241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip
*chip
, int phy
, u8 page
)
243 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PHY_PAGE
))
246 return mv88e6xxx_phy_write(chip
, phy
, PHY_PAGE
, page
);
249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip
*chip
, int phy
)
253 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
254 err
= mv88e6xxx_phy_write(chip
, phy
, PHY_PAGE
, PHY_PAGE_COPPER
);
256 dev_err(chip
->dev
, "failed to restore PHY %d page Copper (%d)\n",
261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip
*chip
, int phy
,
262 u8 page
, int reg
, u16
*val
)
266 /* There is no paging for registers 22 */
270 err
= mv88e6xxx_phy_page_get(chip
, phy
, page
);
272 err
= mv88e6xxx_phy_read(chip
, phy
, reg
, val
);
273 mv88e6xxx_phy_page_put(chip
, phy
);
279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip
*chip
, int phy
,
280 u8 page
, int reg
, u16 val
)
284 /* There is no paging for registers 22 */
288 err
= mv88e6xxx_phy_page_get(chip
, phy
, page
);
290 err
= mv88e6xxx_phy_write(chip
, phy
, PHY_PAGE
, page
);
291 mv88e6xxx_phy_page_put(chip
, phy
);
297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip
*chip
, int reg
, u16
*val
)
299 return mv88e6xxx_phy_page_read(chip
, ADDR_SERDES
, SERDES_PAGE_FIBER
,
303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip
*chip
, int reg
, u16 val
)
305 return mv88e6xxx_phy_page_write(chip
, ADDR_SERDES
, SERDES_PAGE_FIBER
,
309 int mv88e6xxx_wait(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 mask
)
313 for (i
= 0; i
< 16; i
++) {
317 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
324 usleep_range(1000, 2000);
327 dev_err(chip
->dev
, "Timeout while waiting for switch\n");
331 /* Indirect write to single pointer-data register with an Update bit */
332 int mv88e6xxx_update(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 update
)
337 /* Wait until the previous operation is completed */
338 err
= mv88e6xxx_wait(chip
, addr
, reg
, BIT(15));
342 /* Set the Update bit to trigger a write operation */
343 val
= BIT(15) | update
;
345 return mv88e6xxx_write(chip
, addr
, reg
, val
);
348 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
)
353 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
360 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip
*chip
, int addr
,
363 return mv88e6xxx_write(chip
, addr
, reg
, val
);
366 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip
*chip
)
371 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_CONTROL
);
375 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL
,
376 ret
& ~GLOBAL_CONTROL_PPU_ENABLE
);
380 for (i
= 0; i
< 16; i
++) {
381 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATUS
);
385 usleep_range(1000, 2000);
386 if ((ret
& GLOBAL_STATUS_PPU_MASK
) !=
387 GLOBAL_STATUS_PPU_POLLING
)
394 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip
*chip
)
398 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_CONTROL
);
402 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL
,
403 ret
| GLOBAL_CONTROL_PPU_ENABLE
);
407 for (i
= 0; i
< 16; i
++) {
408 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATUS
);
412 usleep_range(1000, 2000);
413 if ((ret
& GLOBAL_STATUS_PPU_MASK
) ==
414 GLOBAL_STATUS_PPU_POLLING
)
421 static void mv88e6xxx_ppu_reenable_work(struct work_struct
*ugly
)
423 struct mv88e6xxx_chip
*chip
;
425 chip
= container_of(ugly
, struct mv88e6xxx_chip
, ppu_work
);
427 mutex_lock(&chip
->reg_lock
);
429 if (mutex_trylock(&chip
->ppu_mutex
)) {
430 if (mv88e6xxx_ppu_enable(chip
) == 0)
431 chip
->ppu_disabled
= 0;
432 mutex_unlock(&chip
->ppu_mutex
);
435 mutex_unlock(&chip
->reg_lock
);
438 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps
)
440 struct mv88e6xxx_chip
*chip
= (void *)_ps
;
442 schedule_work(&chip
->ppu_work
);
445 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip
*chip
)
449 mutex_lock(&chip
->ppu_mutex
);
451 /* If the PHY polling unit is enabled, disable it so that
452 * we can access the PHY registers. If it was already
453 * disabled, cancel the timer that is going to re-enable
456 if (!chip
->ppu_disabled
) {
457 ret
= mv88e6xxx_ppu_disable(chip
);
459 mutex_unlock(&chip
->ppu_mutex
);
462 chip
->ppu_disabled
= 1;
464 del_timer(&chip
->ppu_timer
);
471 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip
*chip
)
473 /* Schedule a timer to re-enable the PHY polling unit. */
474 mod_timer(&chip
->ppu_timer
, jiffies
+ msecs_to_jiffies(10));
475 mutex_unlock(&chip
->ppu_mutex
);
478 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip
*chip
)
480 mutex_init(&chip
->ppu_mutex
);
481 INIT_WORK(&chip
->ppu_work
, mv88e6xxx_ppu_reenable_work
);
482 init_timer(&chip
->ppu_timer
);
483 chip
->ppu_timer
.data
= (unsigned long)chip
;
484 chip
->ppu_timer
.function
= mv88e6xxx_ppu_reenable_timer
;
487 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip
*chip
)
489 del_timer_sync(&chip
->ppu_timer
);
492 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip
*chip
, int addr
,
497 err
= mv88e6xxx_ppu_access_get(chip
);
499 err
= mv88e6xxx_read(chip
, addr
, reg
, val
);
500 mv88e6xxx_ppu_access_put(chip
);
506 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip
*chip
, int addr
,
511 err
= mv88e6xxx_ppu_access_get(chip
);
513 err
= mv88e6xxx_write(chip
, addr
, reg
, val
);
514 mv88e6xxx_ppu_access_put(chip
);
520 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops
= {
521 .read
= mv88e6xxx_phy_ppu_read
,
522 .write
= mv88e6xxx_phy_ppu_write
,
525 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip
*chip
)
527 return chip
->info
->family
== MV88E6XXX_FAMILY_6065
;
530 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip
*chip
)
532 return chip
->info
->family
== MV88E6XXX_FAMILY_6095
;
535 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip
*chip
)
537 return chip
->info
->family
== MV88E6XXX_FAMILY_6097
;
540 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip
*chip
)
542 return chip
->info
->family
== MV88E6XXX_FAMILY_6165
;
545 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip
*chip
)
547 return chip
->info
->family
== MV88E6XXX_FAMILY_6185
;
550 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip
*chip
)
552 return chip
->info
->family
== MV88E6XXX_FAMILY_6320
;
555 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip
*chip
)
557 return chip
->info
->family
== MV88E6XXX_FAMILY_6351
;
560 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip
*chip
)
562 return chip
->info
->family
== MV88E6XXX_FAMILY_6352
;
565 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip
*chip
)
567 return chip
->info
->num_databases
;
570 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip
*chip
)
572 /* Does the device have dedicated FID registers for ATU and VTU ops? */
573 if (mv88e6xxx_6097_family(chip
) || mv88e6xxx_6165_family(chip
) ||
574 mv88e6xxx_6351_family(chip
) || mv88e6xxx_6352_family(chip
))
580 /* We expect the switch to perform auto negotiation if there is a real
581 * phy. However, in the case of a fixed link phy, we force the port
582 * settings from the fixed link settings.
584 static void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
585 struct phy_device
*phydev
)
587 struct mv88e6xxx_chip
*chip
= ds
->priv
;
591 if (!phy_is_pseudo_fixed_link(phydev
))
594 mutex_lock(&chip
->reg_lock
);
596 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_PCS_CTRL
);
600 reg
= ret
& ~(PORT_PCS_CTRL_LINK_UP
|
601 PORT_PCS_CTRL_FORCE_LINK
|
602 PORT_PCS_CTRL_DUPLEX_FULL
|
603 PORT_PCS_CTRL_FORCE_DUPLEX
|
604 PORT_PCS_CTRL_UNFORCED
);
606 reg
|= PORT_PCS_CTRL_FORCE_LINK
;
608 reg
|= PORT_PCS_CTRL_LINK_UP
;
610 if (mv88e6xxx_6065_family(chip
) && phydev
->speed
> SPEED_100
)
613 switch (phydev
->speed
) {
615 reg
|= PORT_PCS_CTRL_1000
;
618 reg
|= PORT_PCS_CTRL_100
;
621 reg
|= PORT_PCS_CTRL_10
;
624 pr_info("Unknown speed");
628 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
;
629 if (phydev
->duplex
== DUPLEX_FULL
)
630 reg
|= PORT_PCS_CTRL_DUPLEX_FULL
;
632 if ((mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
)) &&
633 (port
>= chip
->info
->num_ports
- 2)) {
634 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
635 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
;
636 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
637 reg
|= PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
638 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
639 reg
|= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
640 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
);
642 _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_PCS_CTRL
, reg
);
645 mutex_unlock(&chip
->reg_lock
);
648 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip
*chip
)
653 for (i
= 0; i
< 10; i
++) {
654 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
);
655 if ((ret
& GLOBAL_STATS_OP_BUSY
) == 0)
662 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
)
666 if (mv88e6xxx_6320_family(chip
) || mv88e6xxx_6352_family(chip
))
667 port
= (port
+ 1) << 5;
669 /* Snapshot the hardware statistics counters for this port. */
670 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
,
671 GLOBAL_STATS_OP_CAPTURE_PORT
|
672 GLOBAL_STATS_OP_HIST_RX_TX
| port
);
676 /* Wait for the snapshotting to complete. */
677 ret
= _mv88e6xxx_stats_wait(chip
);
684 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip
*chip
,
692 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
,
693 GLOBAL_STATS_OP_READ_CAPTURED
|
694 GLOBAL_STATS_OP_HIST_RX_TX
| stat
);
698 ret
= _mv88e6xxx_stats_wait(chip
);
702 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_32
);
708 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_01
);
715 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
716 { "in_good_octets", 8, 0x00, BANK0
, },
717 { "in_bad_octets", 4, 0x02, BANK0
, },
718 { "in_unicast", 4, 0x04, BANK0
, },
719 { "in_broadcasts", 4, 0x06, BANK0
, },
720 { "in_multicasts", 4, 0x07, BANK0
, },
721 { "in_pause", 4, 0x16, BANK0
, },
722 { "in_undersize", 4, 0x18, BANK0
, },
723 { "in_fragments", 4, 0x19, BANK0
, },
724 { "in_oversize", 4, 0x1a, BANK0
, },
725 { "in_jabber", 4, 0x1b, BANK0
, },
726 { "in_rx_error", 4, 0x1c, BANK0
, },
727 { "in_fcs_error", 4, 0x1d, BANK0
, },
728 { "out_octets", 8, 0x0e, BANK0
, },
729 { "out_unicast", 4, 0x10, BANK0
, },
730 { "out_broadcasts", 4, 0x13, BANK0
, },
731 { "out_multicasts", 4, 0x12, BANK0
, },
732 { "out_pause", 4, 0x15, BANK0
, },
733 { "excessive", 4, 0x11, BANK0
, },
734 { "collisions", 4, 0x1e, BANK0
, },
735 { "deferred", 4, 0x05, BANK0
, },
736 { "single", 4, 0x14, BANK0
, },
737 { "multiple", 4, 0x17, BANK0
, },
738 { "out_fcs_error", 4, 0x03, BANK0
, },
739 { "late", 4, 0x1f, BANK0
, },
740 { "hist_64bytes", 4, 0x08, BANK0
, },
741 { "hist_65_127bytes", 4, 0x09, BANK0
, },
742 { "hist_128_255bytes", 4, 0x0a, BANK0
, },
743 { "hist_256_511bytes", 4, 0x0b, BANK0
, },
744 { "hist_512_1023bytes", 4, 0x0c, BANK0
, },
745 { "hist_1024_max_bytes", 4, 0x0d, BANK0
, },
746 { "sw_in_discards", 4, 0x10, PORT
, },
747 { "sw_in_filtered", 2, 0x12, PORT
, },
748 { "sw_out_filtered", 2, 0x13, PORT
, },
749 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
750 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
751 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
752 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
753 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
754 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
755 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
756 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
757 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
758 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
759 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
760 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
761 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
762 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
763 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
764 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
765 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
766 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
767 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
768 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
769 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
770 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
771 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
772 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
773 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
774 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
777 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip
*chip
,
778 struct mv88e6xxx_hw_stat
*stat
)
780 switch (stat
->type
) {
784 return mv88e6xxx_6320_family(chip
);
786 return mv88e6xxx_6095_family(chip
) ||
787 mv88e6xxx_6185_family(chip
) ||
788 mv88e6xxx_6097_family(chip
) ||
789 mv88e6xxx_6165_family(chip
) ||
790 mv88e6xxx_6351_family(chip
) ||
791 mv88e6xxx_6352_family(chip
);
796 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip
*chip
,
797 struct mv88e6xxx_hw_stat
*s
,
807 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), s
->reg
);
812 if (s
->sizeof_stat
== 4) {
813 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
),
822 _mv88e6xxx_stats_read(chip
, s
->reg
, &low
);
823 if (s
->sizeof_stat
== 8)
824 _mv88e6xxx_stats_read(chip
, s
->reg
+ 1, &high
);
826 value
= (((u64
)high
) << 16) | low
;
830 static void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
,
833 struct mv88e6xxx_chip
*chip
= ds
->priv
;
834 struct mv88e6xxx_hw_stat
*stat
;
837 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
838 stat
= &mv88e6xxx_hw_stats
[i
];
839 if (mv88e6xxx_has_stat(chip
, stat
)) {
840 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
847 static int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
849 struct mv88e6xxx_chip
*chip
= ds
->priv
;
850 struct mv88e6xxx_hw_stat
*stat
;
853 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
854 stat
= &mv88e6xxx_hw_stats
[i
];
855 if (mv88e6xxx_has_stat(chip
, stat
))
861 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
864 struct mv88e6xxx_chip
*chip
= ds
->priv
;
865 struct mv88e6xxx_hw_stat
*stat
;
869 mutex_lock(&chip
->reg_lock
);
871 ret
= _mv88e6xxx_stats_snapshot(chip
, port
);
873 mutex_unlock(&chip
->reg_lock
);
876 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
877 stat
= &mv88e6xxx_hw_stats
[i
];
878 if (mv88e6xxx_has_stat(chip
, stat
)) {
879 data
[j
] = _mv88e6xxx_get_ethtool_stat(chip
, stat
, port
);
884 mutex_unlock(&chip
->reg_lock
);
887 static int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
889 return 32 * sizeof(u16
);
892 static void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
893 struct ethtool_regs
*regs
, void *_p
)
895 struct mv88e6xxx_chip
*chip
= ds
->priv
;
901 memset(p
, 0xff, 32 * sizeof(u16
));
903 mutex_lock(&chip
->reg_lock
);
905 for (i
= 0; i
< 32; i
++) {
908 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), i
);
913 mutex_unlock(&chip
->reg_lock
);
916 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip
*chip
)
918 return mv88e6xxx_wait(chip
, REG_GLOBAL
, GLOBAL_ATU_OP
,
922 static int mv88e6xxx_get_eee(struct dsa_switch
*ds
, int port
,
923 struct ethtool_eee
*e
)
925 struct mv88e6xxx_chip
*chip
= ds
->priv
;
929 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EEE
))
932 mutex_lock(&chip
->reg_lock
);
934 err
= mv88e6xxx_phy_read(chip
, port
, 16, ®
);
938 e
->eee_enabled
= !!(reg
& 0x0200);
939 e
->tx_lpi_enabled
= !!(reg
& 0x0100);
941 err
= mv88e6xxx_read(chip
, REG_PORT(port
), PORT_STATUS
, ®
);
945 e
->eee_active
= !!(reg
& PORT_STATUS_EEE
);
947 mutex_unlock(&chip
->reg_lock
);
952 static int mv88e6xxx_set_eee(struct dsa_switch
*ds
, int port
,
953 struct phy_device
*phydev
, struct ethtool_eee
*e
)
955 struct mv88e6xxx_chip
*chip
= ds
->priv
;
959 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EEE
))
962 mutex_lock(&chip
->reg_lock
);
964 err
= mv88e6xxx_phy_read(chip
, port
, 16, ®
);
971 if (e
->tx_lpi_enabled
)
974 err
= mv88e6xxx_phy_write(chip
, port
, 16, reg
);
976 mutex_unlock(&chip
->reg_lock
);
981 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip
*chip
, u16 fid
, u16 cmd
)
985 if (mv88e6xxx_has_fid_reg(chip
)) {
986 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_FID
,
990 } else if (mv88e6xxx_num_databases(chip
) == 256) {
991 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
992 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
);
996 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
998 ((fid
<< 8) & 0xf000));
1002 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1006 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_OP
, cmd
);
1010 return _mv88e6xxx_atu_wait(chip
);
1013 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip
*chip
,
1014 struct mv88e6xxx_atu_entry
*entry
)
1016 u16 data
= entry
->state
& GLOBAL_ATU_DATA_STATE_MASK
;
1018 if (entry
->state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
1019 unsigned int mask
, shift
;
1022 data
|= GLOBAL_ATU_DATA_TRUNK
;
1023 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
1024 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
1026 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
1027 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
1030 data
|= (entry
->portv_trunkid
<< shift
) & mask
;
1033 return _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_DATA
, data
);
1036 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip
*chip
,
1037 struct mv88e6xxx_atu_entry
*entry
,
1043 err
= _mv88e6xxx_atu_wait(chip
);
1047 err
= _mv88e6xxx_atu_data_write(chip
, entry
);
1052 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB
:
1053 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB
;
1055 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL
:
1056 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC
;
1059 return _mv88e6xxx_atu_cmd(chip
, entry
->fid
, op
);
1062 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip
*chip
,
1063 u16 fid
, bool static_too
)
1065 struct mv88e6xxx_atu_entry entry
= {
1067 .state
= 0, /* EntryState bits must be 0 */
1070 return _mv88e6xxx_atu_flush_move(chip
, &entry
, static_too
);
1073 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip
*chip
, u16 fid
,
1074 int from_port
, int to_port
, bool static_too
)
1076 struct mv88e6xxx_atu_entry entry
= {
1081 /* EntryState bits must be 0xF */
1082 entry
.state
= GLOBAL_ATU_DATA_STATE_MASK
;
1084 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1085 entry
.portv_trunkid
= (to_port
& 0x0f) << 4;
1086 entry
.portv_trunkid
|= from_port
& 0x0f;
1088 return _mv88e6xxx_atu_flush_move(chip
, &entry
, static_too
);
1091 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip
*chip
, u16 fid
,
1092 int port
, bool static_too
)
1094 /* Destination port 0xF means remove the entries */
1095 return _mv88e6xxx_atu_move(chip
, fid
, port
, 0x0f, static_too
);
1098 static const char * const mv88e6xxx_port_state_names
[] = {
1099 [PORT_CONTROL_STATE_DISABLED
] = "Disabled",
1100 [PORT_CONTROL_STATE_BLOCKING
] = "Blocking/Listening",
1101 [PORT_CONTROL_STATE_LEARNING
] = "Learning",
1102 [PORT_CONTROL_STATE_FORWARDING
] = "Forwarding",
1105 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip
*chip
, int port
,
1108 struct dsa_switch
*ds
= chip
->ds
;
1112 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_CONTROL
);
1116 oldstate
= reg
& PORT_CONTROL_STATE_MASK
;
1118 if (oldstate
!= state
) {
1119 /* Flush forwarding database if we're moving a port
1120 * from Learning or Forwarding state to Disabled or
1121 * Blocking or Listening state.
1123 if ((oldstate
== PORT_CONTROL_STATE_LEARNING
||
1124 oldstate
== PORT_CONTROL_STATE_FORWARDING
) &&
1125 (state
== PORT_CONTROL_STATE_DISABLED
||
1126 state
== PORT_CONTROL_STATE_BLOCKING
)) {
1127 ret
= _mv88e6xxx_atu_remove(chip
, 0, port
, false);
1132 reg
= (reg
& ~PORT_CONTROL_STATE_MASK
) | state
;
1133 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL
,
1138 netdev_dbg(ds
->ports
[port
].netdev
, "PortState %s (was %s)\n",
1139 mv88e6xxx_port_state_names
[state
],
1140 mv88e6xxx_port_state_names
[oldstate
]);
1146 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip
*chip
, int port
)
1148 struct net_device
*bridge
= chip
->ports
[port
].bridge_dev
;
1149 const u16 mask
= (1 << chip
->info
->num_ports
) - 1;
1150 struct dsa_switch
*ds
= chip
->ds
;
1151 u16 output_ports
= 0;
1155 /* allow CPU port or DSA link(s) to send frames to every port */
1156 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
1157 output_ports
= mask
;
1159 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1160 /* allow sending frames to every group member */
1161 if (bridge
&& chip
->ports
[i
].bridge_dev
== bridge
)
1162 output_ports
|= BIT(i
);
1164 /* allow sending frames to CPU port and DSA link(s) */
1165 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1166 output_ports
|= BIT(i
);
1170 /* prevent frames from going back out of the port they came in on */
1171 output_ports
&= ~BIT(port
);
1173 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_BASE_VLAN
);
1178 reg
|= output_ports
& mask
;
1180 return _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_BASE_VLAN
, reg
);
1183 static void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
,
1186 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1191 case BR_STATE_DISABLED
:
1192 stp_state
= PORT_CONTROL_STATE_DISABLED
;
1194 case BR_STATE_BLOCKING
:
1195 case BR_STATE_LISTENING
:
1196 stp_state
= PORT_CONTROL_STATE_BLOCKING
;
1198 case BR_STATE_LEARNING
:
1199 stp_state
= PORT_CONTROL_STATE_LEARNING
;
1201 case BR_STATE_FORWARDING
:
1203 stp_state
= PORT_CONTROL_STATE_FORWARDING
;
1207 mutex_lock(&chip
->reg_lock
);
1208 err
= _mv88e6xxx_port_state(chip
, port
, stp_state
);
1209 mutex_unlock(&chip
->reg_lock
);
1212 netdev_err(ds
->ports
[port
].netdev
,
1213 "failed to update state to %s\n",
1214 mv88e6xxx_port_state_names
[stp_state
]);
1217 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip
*chip
, int port
,
1220 struct dsa_switch
*ds
= chip
->ds
;
1224 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_DEFAULT_VLAN
);
1228 pvid
= ret
& PORT_DEFAULT_VLAN_MASK
;
1231 ret
&= ~PORT_DEFAULT_VLAN_MASK
;
1232 ret
|= *new & PORT_DEFAULT_VLAN_MASK
;
1234 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
1235 PORT_DEFAULT_VLAN
, ret
);
1239 netdev_dbg(ds
->ports
[port
].netdev
,
1240 "DefaultVID %d (was %d)\n", *new, pvid
);
1249 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip
*chip
,
1250 int port
, u16
*pvid
)
1252 return _mv88e6xxx_port_pvid(chip
, port
, NULL
, pvid
);
1255 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip
*chip
,
1258 return _mv88e6xxx_port_pvid(chip
, port
, &pvid
, NULL
);
1261 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip
*chip
)
1263 return mv88e6xxx_wait(chip
, REG_GLOBAL
, GLOBAL_VTU_OP
,
1264 GLOBAL_VTU_OP_BUSY
);
1267 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip
*chip
, u16 op
)
1271 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_OP
, op
);
1275 return _mv88e6xxx_vtu_wait(chip
);
1278 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip
*chip
)
1282 ret
= _mv88e6xxx_vtu_wait(chip
);
1286 return _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_FLUSH_ALL
);
1289 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip
*chip
,
1290 struct mv88e6xxx_vtu_stu_entry
*entry
,
1291 unsigned int nibble_offset
)
1297 for (i
= 0; i
< 3; ++i
) {
1298 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1299 GLOBAL_VTU_DATA_0_3
+ i
);
1306 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1307 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1308 u16 reg
= regs
[i
/ 4];
1310 entry
->data
[i
] = (reg
>> shift
) & GLOBAL_VTU_STU_DATA_MASK
;
1316 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip
*chip
,
1317 struct mv88e6xxx_vtu_stu_entry
*entry
)
1319 return _mv88e6xxx_vtu_stu_data_read(chip
, entry
, 0);
1322 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip
*chip
,
1323 struct mv88e6xxx_vtu_stu_entry
*entry
)
1325 return _mv88e6xxx_vtu_stu_data_read(chip
, entry
, 2);
1328 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip
*chip
,
1329 struct mv88e6xxx_vtu_stu_entry
*entry
,
1330 unsigned int nibble_offset
)
1332 u16 regs
[3] = { 0 };
1336 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1337 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1338 u8 data
= entry
->data
[i
];
1340 regs
[i
/ 4] |= (data
& GLOBAL_VTU_STU_DATA_MASK
) << shift
;
1343 for (i
= 0; i
< 3; ++i
) {
1344 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
,
1345 GLOBAL_VTU_DATA_0_3
+ i
, regs
[i
]);
1353 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip
*chip
,
1354 struct mv88e6xxx_vtu_stu_entry
*entry
)
1356 return _mv88e6xxx_vtu_stu_data_write(chip
, entry
, 0);
1359 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip
*chip
,
1360 struct mv88e6xxx_vtu_stu_entry
*entry
)
1362 return _mv88e6xxx_vtu_stu_data_write(chip
, entry
, 2);
1365 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip
*chip
, u16 vid
)
1367 return _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
,
1368 vid
& GLOBAL_VTU_VID_MASK
);
1371 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip
*chip
,
1372 struct mv88e6xxx_vtu_stu_entry
*entry
)
1374 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1377 ret
= _mv88e6xxx_vtu_wait(chip
);
1381 ret
= _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_VTU_GET_NEXT
);
1385 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1389 next
.vid
= ret
& GLOBAL_VTU_VID_MASK
;
1390 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1393 ret
= mv88e6xxx_vtu_data_read(chip
, &next
);
1397 if (mv88e6xxx_has_fid_reg(chip
)) {
1398 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1403 next
.fid
= ret
& GLOBAL_VTU_FID_MASK
;
1404 } else if (mv88e6xxx_num_databases(chip
) == 256) {
1405 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1406 * VTU DBNum[3:0] are located in VTU Operation 3:0
1408 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1413 next
.fid
= (ret
& 0xf00) >> 4;
1414 next
.fid
|= ret
& 0xf;
1417 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_STU
)) {
1418 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1423 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1431 static int mv88e6xxx_port_vlan_dump(struct dsa_switch
*ds
, int port
,
1432 struct switchdev_obj_port_vlan
*vlan
,
1433 int (*cb
)(struct switchdev_obj
*obj
))
1435 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1436 struct mv88e6xxx_vtu_stu_entry next
;
1440 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1443 mutex_lock(&chip
->reg_lock
);
1445 err
= _mv88e6xxx_port_pvid_get(chip
, port
, &pvid
);
1449 err
= _mv88e6xxx_vtu_vid_write(chip
, GLOBAL_VTU_VID_MASK
);
1454 err
= _mv88e6xxx_vtu_getnext(chip
, &next
);
1461 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1464 /* reinit and dump this VLAN obj */
1465 vlan
->vid_begin
= next
.vid
;
1466 vlan
->vid_end
= next
.vid
;
1469 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
)
1470 vlan
->flags
|= BRIDGE_VLAN_INFO_UNTAGGED
;
1472 if (next
.vid
== pvid
)
1473 vlan
->flags
|= BRIDGE_VLAN_INFO_PVID
;
1475 err
= cb(&vlan
->obj
);
1478 } while (next
.vid
< GLOBAL_VTU_VID_MASK
);
1481 mutex_unlock(&chip
->reg_lock
);
1486 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
1487 struct mv88e6xxx_vtu_stu_entry
*entry
)
1489 u16 op
= GLOBAL_VTU_OP_VTU_LOAD_PURGE
;
1493 ret
= _mv88e6xxx_vtu_wait(chip
);
1500 /* Write port member tags */
1501 ret
= mv88e6xxx_vtu_data_write(chip
, entry
);
1505 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_STU
)) {
1506 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1507 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1513 if (mv88e6xxx_has_fid_reg(chip
)) {
1514 reg
= entry
->fid
& GLOBAL_VTU_FID_MASK
;
1515 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_FID
,
1519 } else if (mv88e6xxx_num_databases(chip
) == 256) {
1520 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1521 * VTU DBNum[3:0] are located in VTU Operation 3:0
1523 op
|= (entry
->fid
& 0xf0) << 8;
1524 op
|= entry
->fid
& 0xf;
1527 reg
= GLOBAL_VTU_VID_VALID
;
1529 reg
|= entry
->vid
& GLOBAL_VTU_VID_MASK
;
1530 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1534 return _mv88e6xxx_vtu_cmd(chip
, op
);
1537 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip
*chip
, u8 sid
,
1538 struct mv88e6xxx_vtu_stu_entry
*entry
)
1540 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1543 ret
= _mv88e6xxx_vtu_wait(chip
);
1547 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1548 sid
& GLOBAL_VTU_SID_MASK
);
1552 ret
= _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_STU_GET_NEXT
);
1556 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
);
1560 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1562 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1566 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1569 ret
= mv88e6xxx_stu_data_read(chip
, &next
);
1578 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip
*chip
,
1579 struct mv88e6xxx_vtu_stu_entry
*entry
)
1584 ret
= _mv88e6xxx_vtu_wait(chip
);
1591 /* Write port states */
1592 ret
= mv88e6xxx_stu_data_write(chip
, entry
);
1596 reg
= GLOBAL_VTU_VID_VALID
;
1598 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1602 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1603 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1607 return _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_STU_LOAD_PURGE
);
1610 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip
*chip
, int port
,
1613 struct dsa_switch
*ds
= chip
->ds
;
1618 if (mv88e6xxx_num_databases(chip
) == 4096)
1620 else if (mv88e6xxx_num_databases(chip
) == 256)
1625 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1626 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_BASE_VLAN
);
1630 fid
= (ret
& PORT_BASE_VLAN_FID_3_0_MASK
) >> 12;
1633 ret
&= ~PORT_BASE_VLAN_FID_3_0_MASK
;
1634 ret
|= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK
;
1636 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_BASE_VLAN
,
1642 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1643 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_CONTROL_1
);
1647 fid
|= (ret
& upper_mask
) << 4;
1651 ret
|= (*new >> 4) & upper_mask
;
1653 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL_1
,
1658 netdev_dbg(ds
->ports
[port
].netdev
,
1659 "FID %d (was %d)\n", *new, fid
);
1668 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip
*chip
,
1671 return _mv88e6xxx_port_fid(chip
, port
, NULL
, fid
);
1674 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip
*chip
,
1677 return _mv88e6xxx_port_fid(chip
, port
, &fid
, NULL
);
1680 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip
*chip
, u16
*fid
)
1682 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1683 struct mv88e6xxx_vtu_stu_entry vlan
;
1686 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1688 /* Set every FID bit used by the (un)bridged ports */
1689 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1690 err
= _mv88e6xxx_port_fid_get(chip
, i
, fid
);
1694 set_bit(*fid
, fid_bitmap
);
1697 /* Set every FID bit used by the VLAN entries */
1698 err
= _mv88e6xxx_vtu_vid_write(chip
, GLOBAL_VTU_VID_MASK
);
1703 err
= _mv88e6xxx_vtu_getnext(chip
, &vlan
);
1710 set_bit(vlan
.fid
, fid_bitmap
);
1711 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
1713 /* The reset value 0x000 is used to indicate that multiple address
1714 * databases are not needed. Return the next positive available.
1716 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1717 if (unlikely(*fid
>= mv88e6xxx_num_databases(chip
)))
1720 /* Clear the database */
1721 return _mv88e6xxx_atu_flush(chip
, *fid
, true);
1724 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip
*chip
, u16 vid
,
1725 struct mv88e6xxx_vtu_stu_entry
*entry
)
1727 struct dsa_switch
*ds
= chip
->ds
;
1728 struct mv88e6xxx_vtu_stu_entry vlan
= {
1734 err
= _mv88e6xxx_fid_new(chip
, &vlan
.fid
);
1738 /* exclude all ports except the CPU and DSA ports */
1739 for (i
= 0; i
< chip
->info
->num_ports
; ++i
)
1740 vlan
.data
[i
] = dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
)
1741 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1742 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1744 if (mv88e6xxx_6097_family(chip
) || mv88e6xxx_6165_family(chip
) ||
1745 mv88e6xxx_6351_family(chip
) || mv88e6xxx_6352_family(chip
)) {
1746 struct mv88e6xxx_vtu_stu_entry vstp
;
1748 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1749 * implemented, only one STU entry is needed to cover all VTU
1750 * entries. Thus, validate the SID 0.
1753 err
= _mv88e6xxx_stu_getnext(chip
, GLOBAL_VTU_SID_MASK
, &vstp
);
1757 if (vstp
.sid
!= vlan
.sid
|| !vstp
.valid
) {
1758 memset(&vstp
, 0, sizeof(vstp
));
1760 vstp
.sid
= vlan
.sid
;
1762 err
= _mv88e6xxx_stu_loadpurge(chip
, &vstp
);
1772 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip
*chip
, u16 vid
,
1773 struct mv88e6xxx_vtu_stu_entry
*entry
, bool creat
)
1780 err
= _mv88e6xxx_vtu_vid_write(chip
, vid
- 1);
1784 err
= _mv88e6xxx_vtu_getnext(chip
, entry
);
1788 if (entry
->vid
!= vid
|| !entry
->valid
) {
1791 /* -ENOENT would've been more appropriate, but switchdev expects
1792 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1795 err
= _mv88e6xxx_vtu_new(chip
, vid
, entry
);
1801 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1802 u16 vid_begin
, u16 vid_end
)
1804 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1805 struct mv88e6xxx_vtu_stu_entry vlan
;
1811 mutex_lock(&chip
->reg_lock
);
1813 err
= _mv88e6xxx_vtu_vid_write(chip
, vid_begin
- 1);
1818 err
= _mv88e6xxx_vtu_getnext(chip
, &vlan
);
1825 if (vlan
.vid
> vid_end
)
1828 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1829 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1833 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1836 if (chip
->ports
[i
].bridge_dev
==
1837 chip
->ports
[port
].bridge_dev
)
1838 break; /* same bridge, check next VLAN */
1840 netdev_warn(ds
->ports
[port
].netdev
,
1841 "hardware VLAN %d already used by %s\n",
1843 netdev_name(chip
->ports
[i
].bridge_dev
));
1847 } while (vlan
.vid
< vid_end
);
1850 mutex_unlock(&chip
->reg_lock
);
1855 static const char * const mv88e6xxx_port_8021q_mode_names
[] = {
1856 [PORT_CONTROL_2_8021Q_DISABLED
] = "Disabled",
1857 [PORT_CONTROL_2_8021Q_FALLBACK
] = "Fallback",
1858 [PORT_CONTROL_2_8021Q_CHECK
] = "Check",
1859 [PORT_CONTROL_2_8021Q_SECURE
] = "Secure",
1862 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
1863 bool vlan_filtering
)
1865 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1866 u16 old
, new = vlan_filtering
? PORT_CONTROL_2_8021Q_SECURE
:
1867 PORT_CONTROL_2_8021Q_DISABLED
;
1870 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1873 mutex_lock(&chip
->reg_lock
);
1875 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_CONTROL_2
);
1879 old
= ret
& PORT_CONTROL_2_8021Q_MASK
;
1882 ret
&= ~PORT_CONTROL_2_8021Q_MASK
;
1883 ret
|= new & PORT_CONTROL_2_8021Q_MASK
;
1885 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL_2
,
1890 netdev_dbg(ds
->ports
[port
].netdev
, "802.1Q Mode %s (was %s)\n",
1891 mv88e6xxx_port_8021q_mode_names
[new],
1892 mv88e6xxx_port_8021q_mode_names
[old
]);
1897 mutex_unlock(&chip
->reg_lock
);
1903 mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1904 const struct switchdev_obj_port_vlan
*vlan
,
1905 struct switchdev_trans
*trans
)
1907 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1910 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1913 /* If the requested port doesn't belong to the same bridge as the VLAN
1914 * members, do not support it (yet) and fallback to software VLAN.
1916 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
1921 /* We don't need any dynamic resource from the kernel (yet),
1922 * so skip the prepare phase.
1927 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip
*chip
, int port
,
1928 u16 vid
, bool untagged
)
1930 struct mv88e6xxx_vtu_stu_entry vlan
;
1933 err
= _mv88e6xxx_vtu_get(chip
, vid
, &vlan
, true);
1937 vlan
.data
[port
] = untagged
?
1938 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
:
1939 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED
;
1941 return _mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1944 static void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
1945 const struct switchdev_obj_port_vlan
*vlan
,
1946 struct switchdev_trans
*trans
)
1948 struct mv88e6xxx_chip
*chip
= ds
->priv
;
1949 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1950 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1953 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1956 mutex_lock(&chip
->reg_lock
);
1958 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
1959 if (_mv88e6xxx_port_vlan_add(chip
, port
, vid
, untagged
))
1960 netdev_err(ds
->ports
[port
].netdev
,
1961 "failed to add VLAN %d%c\n",
1962 vid
, untagged
? 'u' : 't');
1964 if (pvid
&& _mv88e6xxx_port_pvid_set(chip
, port
, vlan
->vid_end
))
1965 netdev_err(ds
->ports
[port
].netdev
, "failed to set PVID %d\n",
1968 mutex_unlock(&chip
->reg_lock
);
1971 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip
*chip
,
1974 struct dsa_switch
*ds
= chip
->ds
;
1975 struct mv88e6xxx_vtu_stu_entry vlan
;
1978 err
= _mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1982 /* Tell switchdev if this VLAN is handled in software */
1983 if (vlan
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1986 vlan
.data
[port
] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1988 /* keep the VLAN unless all ports are excluded */
1990 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1991 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1994 if (vlan
.data
[i
] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
2000 err
= _mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
2004 return _mv88e6xxx_atu_remove(chip
, vlan
.fid
, port
, false);
2007 static int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
2008 const struct switchdev_obj_port_vlan
*vlan
)
2010 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2014 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
2017 mutex_lock(&chip
->reg_lock
);
2019 err
= _mv88e6xxx_port_pvid_get(chip
, port
, &pvid
);
2023 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
2024 err
= _mv88e6xxx_port_vlan_del(chip
, port
, vid
);
2029 err
= _mv88e6xxx_port_pvid_set(chip
, port
, 0);
2036 mutex_unlock(&chip
->reg_lock
);
2041 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip
*chip
,
2042 const unsigned char *addr
)
2046 for (i
= 0; i
< 3; i
++) {
2047 ret
= _mv88e6xxx_reg_write(
2048 chip
, REG_GLOBAL
, GLOBAL_ATU_MAC_01
+ i
,
2049 (addr
[i
* 2] << 8) | addr
[i
* 2 + 1]);
2057 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip
*chip
,
2058 unsigned char *addr
)
2062 for (i
= 0; i
< 3; i
++) {
2063 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
2064 GLOBAL_ATU_MAC_01
+ i
);
2067 addr
[i
* 2] = ret
>> 8;
2068 addr
[i
* 2 + 1] = ret
& 0xff;
2074 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip
*chip
,
2075 struct mv88e6xxx_atu_entry
*entry
)
2079 ret
= _mv88e6xxx_atu_wait(chip
);
2083 ret
= _mv88e6xxx_atu_mac_write(chip
, entry
->mac
);
2087 ret
= _mv88e6xxx_atu_data_write(chip
, entry
);
2091 return _mv88e6xxx_atu_cmd(chip
, entry
->fid
, GLOBAL_ATU_OP_LOAD_DB
);
2094 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip
*chip
, int port
,
2095 const unsigned char *addr
, u16 vid
,
2098 struct mv88e6xxx_atu_entry entry
= { 0 };
2099 struct mv88e6xxx_vtu_stu_entry vlan
;
2102 /* Null VLAN ID corresponds to the port private database */
2104 err
= _mv88e6xxx_port_fid_get(chip
, port
, &vlan
.fid
);
2106 err
= _mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
2110 entry
.fid
= vlan
.fid
;
2111 entry
.state
= state
;
2112 ether_addr_copy(entry
.mac
, addr
);
2113 if (state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2114 entry
.trunk
= false;
2115 entry
.portv_trunkid
= BIT(port
);
2118 return _mv88e6xxx_atu_load(chip
, &entry
);
2121 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch
*ds
, int port
,
2122 const struct switchdev_obj_port_fdb
*fdb
,
2123 struct switchdev_trans
*trans
)
2125 /* We don't need any dynamic resource from the kernel (yet),
2126 * so skip the prepare phase.
2131 static void mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
2132 const struct switchdev_obj_port_fdb
*fdb
,
2133 struct switchdev_trans
*trans
)
2135 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2137 mutex_lock(&chip
->reg_lock
);
2138 if (mv88e6xxx_port_db_load_purge(chip
, port
, fdb
->addr
, fdb
->vid
,
2139 GLOBAL_ATU_DATA_STATE_UC_STATIC
))
2140 netdev_err(ds
->ports
[port
].netdev
, "failed to load unicast MAC address\n");
2141 mutex_unlock(&chip
->reg_lock
);
2144 static int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
2145 const struct switchdev_obj_port_fdb
*fdb
)
2147 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2150 mutex_lock(&chip
->reg_lock
);
2151 err
= mv88e6xxx_port_db_load_purge(chip
, port
, fdb
->addr
, fdb
->vid
,
2152 GLOBAL_ATU_DATA_STATE_UNUSED
);
2153 mutex_unlock(&chip
->reg_lock
);
2158 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip
*chip
, u16 fid
,
2159 struct mv88e6xxx_atu_entry
*entry
)
2161 struct mv88e6xxx_atu_entry next
= { 0 };
2166 ret
= _mv88e6xxx_atu_wait(chip
);
2170 ret
= _mv88e6xxx_atu_cmd(chip
, fid
, GLOBAL_ATU_OP_GET_NEXT_DB
);
2174 ret
= _mv88e6xxx_atu_mac_read(chip
, next
.mac
);
2178 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_ATU_DATA
);
2182 next
.state
= ret
& GLOBAL_ATU_DATA_STATE_MASK
;
2183 if (next
.state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2184 unsigned int mask
, shift
;
2186 if (ret
& GLOBAL_ATU_DATA_TRUNK
) {
2188 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
2189 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
2192 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
2193 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
2196 next
.portv_trunkid
= (ret
& mask
) >> shift
;
2203 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip
*chip
,
2204 u16 fid
, u16 vid
, int port
,
2205 struct switchdev_obj
*obj
,
2206 int (*cb
)(struct switchdev_obj
*obj
))
2208 struct mv88e6xxx_atu_entry addr
= {
2209 .mac
= { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2213 err
= _mv88e6xxx_atu_mac_write(chip
, addr
.mac
);
2218 err
= _mv88e6xxx_atu_getnext(chip
, fid
, &addr
);
2222 if (addr
.state
== GLOBAL_ATU_DATA_STATE_UNUSED
)
2225 if (addr
.trunk
|| (addr
.portv_trunkid
& BIT(port
)) == 0)
2228 if (obj
->id
== SWITCHDEV_OBJ_ID_PORT_FDB
) {
2229 struct switchdev_obj_port_fdb
*fdb
;
2231 if (!is_unicast_ether_addr(addr
.mac
))
2234 fdb
= SWITCHDEV_OBJ_PORT_FDB(obj
);
2236 ether_addr_copy(fdb
->addr
, addr
.mac
);
2237 if (addr
.state
== GLOBAL_ATU_DATA_STATE_UC_STATIC
)
2238 fdb
->ndm_state
= NUD_NOARP
;
2240 fdb
->ndm_state
= NUD_REACHABLE
;
2241 } else if (obj
->id
== SWITCHDEV_OBJ_ID_PORT_MDB
) {
2242 struct switchdev_obj_port_mdb
*mdb
;
2244 if (!is_multicast_ether_addr(addr
.mac
))
2247 mdb
= SWITCHDEV_OBJ_PORT_MDB(obj
);
2249 ether_addr_copy(mdb
->addr
, addr
.mac
);
2257 } while (!is_broadcast_ether_addr(addr
.mac
));
2262 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip
*chip
, int port
,
2263 struct switchdev_obj
*obj
,
2264 int (*cb
)(struct switchdev_obj
*obj
))
2266 struct mv88e6xxx_vtu_stu_entry vlan
= {
2267 .vid
= GLOBAL_VTU_VID_MASK
, /* all ones */
2272 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2273 err
= _mv88e6xxx_port_fid_get(chip
, port
, &fid
);
2277 err
= mv88e6xxx_port_db_dump_fid(chip
, fid
, 0, port
, obj
, cb
);
2281 /* Dump VLANs' Filtering Information Databases */
2282 err
= _mv88e6xxx_vtu_vid_write(chip
, vlan
.vid
);
2287 err
= _mv88e6xxx_vtu_getnext(chip
, &vlan
);
2294 err
= mv88e6xxx_port_db_dump_fid(chip
, vlan
.fid
, vlan
.vid
, port
,
2298 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
2303 static int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
2304 struct switchdev_obj_port_fdb
*fdb
,
2305 int (*cb
)(struct switchdev_obj
*obj
))
2307 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2310 mutex_lock(&chip
->reg_lock
);
2311 err
= mv88e6xxx_port_db_dump(chip
, port
, &fdb
->obj
, cb
);
2312 mutex_unlock(&chip
->reg_lock
);
2317 static int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
2318 struct net_device
*bridge
)
2320 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2323 mutex_lock(&chip
->reg_lock
);
2325 /* Assign the bridge and remap each port's VLANTable */
2326 chip
->ports
[port
].bridge_dev
= bridge
;
2328 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
2329 if (chip
->ports
[i
].bridge_dev
== bridge
) {
2330 err
= _mv88e6xxx_port_based_vlan_map(chip
, i
);
2336 mutex_unlock(&chip
->reg_lock
);
2341 static void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
)
2343 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2344 struct net_device
*bridge
= chip
->ports
[port
].bridge_dev
;
2347 mutex_lock(&chip
->reg_lock
);
2349 /* Unassign the bridge and remap each port's VLANTable */
2350 chip
->ports
[port
].bridge_dev
= NULL
;
2352 for (i
= 0; i
< chip
->info
->num_ports
; ++i
)
2353 if (i
== port
|| chip
->ports
[i
].bridge_dev
== bridge
)
2354 if (_mv88e6xxx_port_based_vlan_map(chip
, i
))
2355 netdev_warn(ds
->ports
[i
].netdev
,
2356 "failed to remap\n");
2358 mutex_unlock(&chip
->reg_lock
);
2361 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip
*chip
)
2363 bool ppu_active
= mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU_ACTIVE
);
2364 u16 is_reset
= (ppu_active
? 0x8800 : 0xc800);
2365 struct gpio_desc
*gpiod
= chip
->reset
;
2366 unsigned long timeout
;
2370 /* Set all ports to the disabled state. */
2371 for (i
= 0; i
< chip
->info
->num_ports
; i
++) {
2372 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(i
), PORT_CONTROL
);
2376 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(i
), PORT_CONTROL
,
2382 /* Wait for transmit queues to drain. */
2383 usleep_range(2000, 4000);
2385 /* If there is a gpio connected to the reset pin, toggle it */
2387 gpiod_set_value_cansleep(gpiod
, 1);
2388 usleep_range(10000, 20000);
2389 gpiod_set_value_cansleep(gpiod
, 0);
2390 usleep_range(10000, 20000);
2393 /* Reset the switch. Keep the PPU active if requested. The PPU
2394 * needs to be active to support indirect phy register access
2395 * through global registers 0x18 and 0x19.
2398 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, 0x04, 0xc000);
2400 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, 0x04, 0xc400);
2404 /* Wait up to one second for reset to complete. */
2405 timeout
= jiffies
+ 1 * HZ
;
2406 while (time_before(jiffies
, timeout
)) {
2407 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, 0x00);
2411 if ((ret
& is_reset
) == is_reset
)
2413 usleep_range(1000, 2000);
2415 if (time_after(jiffies
, timeout
))
2423 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip
*chip
)
2428 /* Clear Power Down bit */
2429 err
= mv88e6xxx_serdes_read(chip
, MII_BMCR
, &val
);
2433 if (val
& BMCR_PDOWN
) {
2435 err
= mv88e6xxx_serdes_write(chip
, MII_BMCR
, val
);
2441 static int mv88e6xxx_port_read(struct mv88e6xxx_chip
*chip
, int port
,
2444 int addr
= chip
->info
->port_base_addr
+ port
;
2446 if (port
>= chip
->info
->num_ports
)
2449 return mv88e6xxx_read(chip
, addr
, reg
, val
);
2452 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip
, int port
)
2454 struct dsa_switch
*ds
= chip
->ds
;
2458 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2459 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2460 mv88e6xxx_6185_family(chip
) || mv88e6xxx_6095_family(chip
) ||
2461 mv88e6xxx_6065_family(chip
) || mv88e6xxx_6320_family(chip
)) {
2462 /* MAC Forcing register: don't force link, speed,
2463 * duplex or flow control state to any particular
2464 * values on physical ports, but force the CPU port
2465 * and all DSA ports to their maximum bandwidth and
2468 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_PCS_CTRL
);
2469 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
2470 reg
&= ~PORT_PCS_CTRL_UNFORCED
;
2471 reg
|= PORT_PCS_CTRL_FORCE_LINK
|
2472 PORT_PCS_CTRL_LINK_UP
|
2473 PORT_PCS_CTRL_DUPLEX_FULL
|
2474 PORT_PCS_CTRL_FORCE_DUPLEX
;
2475 if (mv88e6xxx_6065_family(chip
))
2476 reg
|= PORT_PCS_CTRL_100
;
2478 reg
|= PORT_PCS_CTRL_1000
;
2480 reg
|= PORT_PCS_CTRL_UNFORCED
;
2483 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2484 PORT_PCS_CTRL
, reg
);
2489 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2490 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2491 * tunneling, determine priority by looking at 802.1p and IP
2492 * priority fields (IP prio has precedence), and set STP state
2495 * If this is the CPU link, use DSA or EDSA tagging depending
2496 * on which tagging mode was configured.
2498 * If this is a link to another switch, use DSA tagging mode.
2500 * If this is the upstream port for this switch, enable
2501 * forwarding of unknown unicasts and multicasts.
2504 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2505 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2506 mv88e6xxx_6095_family(chip
) || mv88e6xxx_6065_family(chip
) ||
2507 mv88e6xxx_6185_family(chip
) || mv88e6xxx_6320_family(chip
))
2508 reg
= PORT_CONTROL_IGMP_MLD_SNOOP
|
2509 PORT_CONTROL_USE_TAG
| PORT_CONTROL_USE_IP
|
2510 PORT_CONTROL_STATE_FORWARDING
;
2511 if (dsa_is_cpu_port(ds
, port
)) {
2512 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EDSA
))
2513 reg
|= PORT_CONTROL_FRAME_ETHER_TYPE_DSA
|
2514 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2516 reg
|= PORT_CONTROL_DSA_TAG
;
2517 reg
|= PORT_CONTROL_EGRESS_ADD_TAG
|
2518 PORT_CONTROL_FORWARD_UNKNOWN
;
2520 if (dsa_is_dsa_port(ds
, port
)) {
2521 if (mv88e6xxx_6095_family(chip
) ||
2522 mv88e6xxx_6185_family(chip
))
2523 reg
|= PORT_CONTROL_DSA_TAG
;
2524 if (mv88e6xxx_6352_family(chip
) ||
2525 mv88e6xxx_6351_family(chip
) ||
2526 mv88e6xxx_6165_family(chip
) ||
2527 mv88e6xxx_6097_family(chip
) ||
2528 mv88e6xxx_6320_family(chip
)) {
2529 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2532 if (port
== dsa_upstream_port(ds
))
2533 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2534 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2537 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2543 /* If this port is connected to a SerDes, make sure the SerDes is not
2546 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_SERDES
)) {
2547 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_STATUS
);
2550 ret
&= PORT_STATUS_CMODE_MASK
;
2551 if ((ret
== PORT_STATUS_CMODE_100BASE_X
) ||
2552 (ret
== PORT_STATUS_CMODE_1000BASE_X
) ||
2553 (ret
== PORT_STATUS_CMODE_SGMII
)) {
2554 ret
= mv88e6xxx_serdes_power_on(chip
);
2560 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2561 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2562 * untagged frames on this port, do a destination address lookup on all
2563 * received packets as usual, disable ARP mirroring and don't send a
2564 * copy of all transmitted/received frames on this port to the CPU.
2567 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2568 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2569 mv88e6xxx_6095_family(chip
) || mv88e6xxx_6320_family(chip
) ||
2570 mv88e6xxx_6185_family(chip
))
2571 reg
= PORT_CONTROL_2_MAP_DA
;
2573 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2574 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6320_family(chip
))
2575 reg
|= PORT_CONTROL_2_JUMBO_10240
;
2577 if (mv88e6xxx_6095_family(chip
) || mv88e6xxx_6185_family(chip
)) {
2578 /* Set the upstream port this port should use */
2579 reg
|= dsa_upstream_port(ds
);
2580 /* enable forwarding of unknown multicast addresses to
2583 if (port
== dsa_upstream_port(ds
))
2584 reg
|= PORT_CONTROL_2_FORWARD_UNKNOWN
;
2587 reg
|= PORT_CONTROL_2_8021Q_DISABLED
;
2590 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2591 PORT_CONTROL_2
, reg
);
2596 /* Port Association Vector: when learning source addresses
2597 * of packets, add the address to the address database using
2598 * a port bitmap that has only the bit for this port set and
2599 * the other bits clear.
2602 /* Disable learning for CPU port */
2603 if (dsa_is_cpu_port(ds
, port
))
2606 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_ASSOC_VECTOR
,
2611 /* Egress rate control 2: disable egress rate control. */
2612 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_RATE_CONTROL_2
,
2617 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2618 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2619 mv88e6xxx_6320_family(chip
)) {
2620 /* Do not limit the period of time that this port can
2621 * be paused for by the remote end or the period of
2622 * time that this port can pause the remote end.
2624 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2625 PORT_PAUSE_CTRL
, 0x0000);
2629 /* Port ATU control: disable limiting the number of
2630 * address database entries that this port is allowed
2633 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2634 PORT_ATU_CONTROL
, 0x0000);
2635 /* Priority Override: disable DA, SA and VTU priority
2638 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2639 PORT_PRI_OVERRIDE
, 0x0000);
2643 /* Port Ethertype: use the Ethertype DSA Ethertype
2646 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EDSA
)) {
2647 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2648 PORT_ETH_TYPE
, ETH_P_EDSA
);
2653 /* Tag Remap: use an identity 802.1p prio -> switch
2656 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2657 PORT_TAG_REGMAP_0123
, 0x3210);
2661 /* Tag Remap 2: use an identity 802.1p prio -> switch
2664 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2665 PORT_TAG_REGMAP_4567
, 0x7654);
2670 /* Rate Control: disable ingress rate limiting. */
2671 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2672 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2673 mv88e6xxx_6320_family(chip
)) {
2674 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2675 PORT_RATE_CONTROL
, 0x0001);
2678 } else if (mv88e6xxx_6185_family(chip
) || mv88e6xxx_6095_family(chip
)) {
2679 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2680 PORT_RATE_CONTROL
, 0x0000);
2685 /* Port Control 1: disable trunking, disable sending
2686 * learning messages to this port.
2688 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL_1
,
2693 /* Port based VLAN map: give each port the same default address
2694 * database, and allow bidirectional communication between the
2695 * CPU and DSA port(s), and the other ports.
2697 ret
= _mv88e6xxx_port_fid_set(chip
, port
, 0);
2701 ret
= _mv88e6xxx_port_based_vlan_map(chip
, port
);
2705 /* Default VLAN ID and priority: don't set a default VLAN
2706 * ID, and set the default packet priority to zero.
2708 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_DEFAULT_VLAN
,
2716 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip
*chip
, u8
*addr
)
2720 err
= mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_MAC_01
,
2721 (addr
[0] << 8) | addr
[1]);
2725 err
= mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_MAC_23
,
2726 (addr
[2] << 8) | addr
[3]);
2730 return mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_MAC_45
,
2731 (addr
[4] << 8) | addr
[5]);
2734 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip
*chip
,
2737 const unsigned int coeff
= chip
->info
->age_time_coeff
;
2738 const unsigned int min
= 0x01 * coeff
;
2739 const unsigned int max
= 0xff * coeff
;
2744 if (msecs
< min
|| msecs
> max
)
2747 /* Round to nearest multiple of coeff */
2748 age_time
= (msecs
+ coeff
/ 2) / coeff
;
2750 err
= mv88e6xxx_read(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
, &val
);
2754 /* AgeTime is 11:4 bits */
2756 val
|= age_time
<< 4;
2758 return mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
, val
);
2761 static int mv88e6xxx_set_ageing_time(struct dsa_switch
*ds
,
2762 unsigned int ageing_time
)
2764 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2767 mutex_lock(&chip
->reg_lock
);
2768 err
= mv88e6xxx_g1_set_age_time(chip
, ageing_time
);
2769 mutex_unlock(&chip
->reg_lock
);
2774 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip
*chip
)
2776 struct dsa_switch
*ds
= chip
->ds
;
2777 u32 upstream_port
= dsa_upstream_port(ds
);
2781 /* Enable the PHY Polling Unit if present, don't discard any packets,
2782 * and mask all interrupt sources.
2785 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
) ||
2786 mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU_ACTIVE
))
2787 reg
|= GLOBAL_CONTROL_PPU_ENABLE
;
2789 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL
, reg
);
2793 /* Configure the upstream port, and configure it as the port to which
2794 * ingress and egress and ARP monitor frames are to be sent.
2796 reg
= upstream_port
<< GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT
|
2797 upstream_port
<< GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT
|
2798 upstream_port
<< GLOBAL_MONITOR_CONTROL_ARP_SHIFT
;
2799 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_MONITOR_CONTROL
,
2804 /* Disable remote management, and set the switch's DSA device number. */
2805 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL_2
,
2806 GLOBAL_CONTROL_2_MULTIPLE_CASCADE
|
2807 (ds
->index
& 0x1f));
2811 /* Clear all the VTU and STU entries */
2812 err
= _mv88e6xxx_vtu_stu_flush(chip
);
2816 /* Set the default address aging time to 5 minutes, and
2817 * enable address learn messages to be sent to all message
2820 err
= mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
2821 GLOBAL_ATU_CONTROL_LEARN2ALL
);
2825 err
= mv88e6xxx_g1_set_age_time(chip
, 300000);
2829 /* Clear all ATU entries */
2830 err
= _mv88e6xxx_atu_flush(chip
, 0, true);
2834 /* Configure the IP ToS mapping registers. */
2835 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_0
, 0x0000);
2838 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_1
, 0x0000);
2841 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_2
, 0x5555);
2844 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_3
, 0x5555);
2847 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_4
, 0xaaaa);
2850 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_5
, 0xaaaa);
2853 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_6
, 0xffff);
2856 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_7
, 0xffff);
2860 /* Configure the IEEE 802.1p priority mapping register. */
2861 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IEEE_PRI
, 0xfa41);
2865 /* Clear the statistics counters for all ports */
2866 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
,
2867 GLOBAL_STATS_OP_FLUSH_ALL
);
2871 /* Wait for the flush to complete. */
2872 err
= _mv88e6xxx_stats_wait(chip
);
2879 static int mv88e6xxx_setup(struct dsa_switch
*ds
)
2881 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2886 ds
->slave_mii_bus
= chip
->mdio_bus
;
2888 mutex_lock(&chip
->reg_lock
);
2890 err
= mv88e6xxx_switch_reset(chip
);
2894 /* Setup Switch Port Registers */
2895 for (i
= 0; i
< chip
->info
->num_ports
; i
++) {
2896 err
= mv88e6xxx_setup_port(chip
, i
);
2901 /* Setup Switch Global 1 Registers */
2902 err
= mv88e6xxx_g1_setup(chip
);
2906 /* Setup Switch Global 2 Registers */
2907 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_GLOBAL2
)) {
2908 err
= mv88e6xxx_g2_setup(chip
);
2914 mutex_unlock(&chip
->reg_lock
);
2919 static int mv88e6xxx_set_addr(struct dsa_switch
*ds
, u8
*addr
)
2921 struct mv88e6xxx_chip
*chip
= ds
->priv
;
2924 mutex_lock(&chip
->reg_lock
);
2926 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2927 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_SWITCH_MAC
))
2928 err
= mv88e6xxx_g2_set_switch_mac(chip
, addr
);
2930 err
= mv88e6xxx_g1_set_switch_mac(chip
, addr
);
2932 mutex_unlock(&chip
->reg_lock
);
2937 static int mv88e6xxx_mdio_read(struct mii_bus
*bus
, int phy
, int reg
)
2939 struct mv88e6xxx_chip
*chip
= bus
->priv
;
2943 if (phy
>= chip
->info
->num_ports
)
2946 mutex_lock(&chip
->reg_lock
);
2947 err
= mv88e6xxx_phy_read(chip
, phy
, reg
, &val
);
2948 mutex_unlock(&chip
->reg_lock
);
2950 return err
? err
: val
;
2953 static int mv88e6xxx_mdio_write(struct mii_bus
*bus
, int phy
, int reg
, u16 val
)
2955 struct mv88e6xxx_chip
*chip
= bus
->priv
;
2958 if (phy
>= chip
->info
->num_ports
)
2961 mutex_lock(&chip
->reg_lock
);
2962 err
= mv88e6xxx_phy_write(chip
, phy
, reg
, val
);
2963 mutex_unlock(&chip
->reg_lock
);
2968 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip
*chip
,
2969 struct device_node
*np
)
2972 struct mii_bus
*bus
;
2976 chip
->mdio_np
= of_get_child_by_name(np
, "mdio");
2978 bus
= devm_mdiobus_alloc(chip
->dev
);
2982 bus
->priv
= (void *)chip
;
2984 bus
->name
= np
->full_name
;
2985 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s", np
->full_name
);
2987 bus
->name
= "mv88e6xxx SMI";
2988 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "mv88e6xxx-%d", index
++);
2991 bus
->read
= mv88e6xxx_mdio_read
;
2992 bus
->write
= mv88e6xxx_mdio_write
;
2993 bus
->parent
= chip
->dev
;
2996 err
= of_mdiobus_register(bus
, chip
->mdio_np
);
2998 err
= mdiobus_register(bus
);
3000 dev_err(chip
->dev
, "Cannot register MDIO bus (%d)\n", err
);
3003 chip
->mdio_bus
= bus
;
3009 of_node_put(chip
->mdio_np
);
3014 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip
*chip
)
3017 struct mii_bus
*bus
= chip
->mdio_bus
;
3019 mdiobus_unregister(bus
);
3022 of_node_put(chip
->mdio_np
);
3025 #ifdef CONFIG_NET_DSA_HWMON
3027 static int mv88e61xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3029 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3035 mutex_lock(&chip
->reg_lock
);
3037 ret
= mv88e6xxx_phy_write(chip
, 0x0, 0x16, 0x6);
3041 /* Enable temperature sensor */
3042 ret
= mv88e6xxx_phy_read(chip
, 0x0, 0x1a, &val
);
3046 ret
= mv88e6xxx_phy_write(chip
, 0x0, 0x1a, val
| (1 << 5));
3050 /* Wait for temperature to stabilize */
3051 usleep_range(10000, 12000);
3053 ret
= mv88e6xxx_phy_read(chip
, 0x0, 0x1a, &val
);
3057 /* Disable temperature sensor */
3058 ret
= mv88e6xxx_phy_write(chip
, 0x0, 0x1a, val
& ~(1 << 5));
3062 *temp
= ((val
& 0x1f) - 5) * 5;
3065 mv88e6xxx_phy_write(chip
, 0x0, 0x16, 0x0);
3066 mutex_unlock(&chip
->reg_lock
);
3070 static int mv88e63xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3072 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3073 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3079 mutex_lock(&chip
->reg_lock
);
3080 ret
= mv88e6xxx_phy_page_read(chip
, phy
, 6, 27, &val
);
3081 mutex_unlock(&chip
->reg_lock
);
3085 *temp
= (val
& 0xff) - 25;
3090 static int mv88e6xxx_get_temp(struct dsa_switch
*ds
, int *temp
)
3092 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3094 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP
))
3097 if (mv88e6xxx_6320_family(chip
) || mv88e6xxx_6352_family(chip
))
3098 return mv88e63xx_get_temp(ds
, temp
);
3100 return mv88e61xx_get_temp(ds
, temp
);
3103 static int mv88e6xxx_get_temp_limit(struct dsa_switch
*ds
, int *temp
)
3105 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3106 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3110 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3115 mutex_lock(&chip
->reg_lock
);
3116 ret
= mv88e6xxx_phy_page_read(chip
, phy
, 6, 26, &val
);
3117 mutex_unlock(&chip
->reg_lock
);
3121 *temp
= (((val
>> 8) & 0x1f) * 5) - 25;
3126 static int mv88e6xxx_set_temp_limit(struct dsa_switch
*ds
, int temp
)
3128 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3129 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3133 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3136 mutex_lock(&chip
->reg_lock
);
3137 err
= mv88e6xxx_phy_page_read(chip
, phy
, 6, 26, &val
);
3140 temp
= clamp_val(DIV_ROUND_CLOSEST(temp
, 5) + 5, 0, 0x1f);
3141 err
= mv88e6xxx_phy_page_write(chip
, phy
, 6, 26,
3142 (val
& 0xe0ff) | (temp
<< 8));
3144 mutex_unlock(&chip
->reg_lock
);
3149 static int mv88e6xxx_get_temp_alarm(struct dsa_switch
*ds
, bool *alarm
)
3151 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3152 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3156 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3161 mutex_lock(&chip
->reg_lock
);
3162 ret
= mv88e6xxx_phy_page_read(chip
, phy
, 6, 26, &val
);
3163 mutex_unlock(&chip
->reg_lock
);
3167 *alarm
= !!(val
& 0x40);
3171 #endif /* CONFIG_NET_DSA_HWMON */
3173 static int mv88e6xxx_get_eeprom_len(struct dsa_switch
*ds
)
3175 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3177 return chip
->eeprom_len
;
3180 static int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
,
3181 struct ethtool_eeprom
*eeprom
, u8
*data
)
3183 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3186 mutex_lock(&chip
->reg_lock
);
3188 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_EEPROM16
))
3189 err
= mv88e6xxx_g2_get_eeprom16(chip
, eeprom
, data
);
3193 mutex_unlock(&chip
->reg_lock
);
3198 eeprom
->magic
= 0xc3ec4951;
3203 static int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
,
3204 struct ethtool_eeprom
*eeprom
, u8
*data
)
3206 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3209 if (eeprom
->magic
!= 0xc3ec4951)
3212 mutex_lock(&chip
->reg_lock
);
3214 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_EEPROM16
))
3215 err
= mv88e6xxx_g2_set_eeprom16(chip
, eeprom
, data
);
3219 mutex_unlock(&chip
->reg_lock
);
3224 static const struct mv88e6xxx_info mv88e6xxx_table
[] = {
3226 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6085
,
3227 .family
= MV88E6XXX_FAMILY_6097
,
3228 .name
= "Marvell 88E6085",
3229 .num_databases
= 4096,
3231 .port_base_addr
= 0x10,
3232 .age_time_coeff
= 15000,
3233 .flags
= MV88E6XXX_FLAGS_FAMILY_6097
,
3237 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6095
,
3238 .family
= MV88E6XXX_FAMILY_6095
,
3239 .name
= "Marvell 88E6095/88E6095F",
3240 .num_databases
= 256,
3242 .port_base_addr
= 0x10,
3243 .age_time_coeff
= 15000,
3244 .flags
= MV88E6XXX_FLAGS_FAMILY_6095
,
3248 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6123
,
3249 .family
= MV88E6XXX_FAMILY_6165
,
3250 .name
= "Marvell 88E6123",
3251 .num_databases
= 4096,
3253 .port_base_addr
= 0x10,
3254 .age_time_coeff
= 15000,
3255 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3259 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6131
,
3260 .family
= MV88E6XXX_FAMILY_6185
,
3261 .name
= "Marvell 88E6131",
3262 .num_databases
= 256,
3264 .port_base_addr
= 0x10,
3265 .age_time_coeff
= 15000,
3266 .flags
= MV88E6XXX_FLAGS_FAMILY_6185
,
3270 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6161
,
3271 .family
= MV88E6XXX_FAMILY_6165
,
3272 .name
= "Marvell 88E6161",
3273 .num_databases
= 4096,
3275 .port_base_addr
= 0x10,
3276 .age_time_coeff
= 15000,
3277 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3281 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6165
,
3282 .family
= MV88E6XXX_FAMILY_6165
,
3283 .name
= "Marvell 88E6165",
3284 .num_databases
= 4096,
3286 .port_base_addr
= 0x10,
3287 .age_time_coeff
= 15000,
3288 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3292 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6171
,
3293 .family
= MV88E6XXX_FAMILY_6351
,
3294 .name
= "Marvell 88E6171",
3295 .num_databases
= 4096,
3297 .port_base_addr
= 0x10,
3298 .age_time_coeff
= 15000,
3299 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3303 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6172
,
3304 .family
= MV88E6XXX_FAMILY_6352
,
3305 .name
= "Marvell 88E6172",
3306 .num_databases
= 4096,
3308 .port_base_addr
= 0x10,
3309 .age_time_coeff
= 15000,
3310 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3314 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6175
,
3315 .family
= MV88E6XXX_FAMILY_6351
,
3316 .name
= "Marvell 88E6175",
3317 .num_databases
= 4096,
3319 .port_base_addr
= 0x10,
3320 .age_time_coeff
= 15000,
3321 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3325 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6176
,
3326 .family
= MV88E6XXX_FAMILY_6352
,
3327 .name
= "Marvell 88E6176",
3328 .num_databases
= 4096,
3330 .port_base_addr
= 0x10,
3331 .age_time_coeff
= 15000,
3332 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3336 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6185
,
3337 .family
= MV88E6XXX_FAMILY_6185
,
3338 .name
= "Marvell 88E6185",
3339 .num_databases
= 256,
3341 .port_base_addr
= 0x10,
3342 .age_time_coeff
= 15000,
3343 .flags
= MV88E6XXX_FLAGS_FAMILY_6185
,
3347 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6240
,
3348 .family
= MV88E6XXX_FAMILY_6352
,
3349 .name
= "Marvell 88E6240",
3350 .num_databases
= 4096,
3352 .port_base_addr
= 0x10,
3353 .age_time_coeff
= 15000,
3354 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3358 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6320
,
3359 .family
= MV88E6XXX_FAMILY_6320
,
3360 .name
= "Marvell 88E6320",
3361 .num_databases
= 4096,
3363 .port_base_addr
= 0x10,
3364 .age_time_coeff
= 15000,
3365 .flags
= MV88E6XXX_FLAGS_FAMILY_6320
,
3369 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6321
,
3370 .family
= MV88E6XXX_FAMILY_6320
,
3371 .name
= "Marvell 88E6321",
3372 .num_databases
= 4096,
3374 .port_base_addr
= 0x10,
3375 .age_time_coeff
= 15000,
3376 .flags
= MV88E6XXX_FLAGS_FAMILY_6320
,
3380 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6350
,
3381 .family
= MV88E6XXX_FAMILY_6351
,
3382 .name
= "Marvell 88E6350",
3383 .num_databases
= 4096,
3385 .port_base_addr
= 0x10,
3386 .age_time_coeff
= 15000,
3387 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3391 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6351
,
3392 .family
= MV88E6XXX_FAMILY_6351
,
3393 .name
= "Marvell 88E6351",
3394 .num_databases
= 4096,
3396 .port_base_addr
= 0x10,
3397 .age_time_coeff
= 15000,
3398 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3402 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6352
,
3403 .family
= MV88E6XXX_FAMILY_6352
,
3404 .name
= "Marvell 88E6352",
3405 .num_databases
= 4096,
3407 .port_base_addr
= 0x10,
3408 .age_time_coeff
= 15000,
3409 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3413 static const struct mv88e6xxx_info
*mv88e6xxx_lookup_info(unsigned int prod_num
)
3417 for (i
= 0; i
< ARRAY_SIZE(mv88e6xxx_table
); ++i
)
3418 if (mv88e6xxx_table
[i
].prod_num
== prod_num
)
3419 return &mv88e6xxx_table
[i
];
3424 static int mv88e6xxx_detect(struct mv88e6xxx_chip
*chip
)
3426 const struct mv88e6xxx_info
*info
;
3427 unsigned int prod_num
, rev
;
3431 mutex_lock(&chip
->reg_lock
);
3432 err
= mv88e6xxx_port_read(chip
, 0, PORT_SWITCH_ID
, &id
);
3433 mutex_unlock(&chip
->reg_lock
);
3437 prod_num
= (id
& 0xfff0) >> 4;
3440 info
= mv88e6xxx_lookup_info(prod_num
);
3444 /* Update the compatible info with the probed one */
3447 err
= mv88e6xxx_g2_require(chip
);
3451 dev_info(chip
->dev
, "switch 0x%x detected: %s, revision %u\n",
3452 chip
->info
->prod_num
, chip
->info
->name
, rev
);
3457 static struct mv88e6xxx_chip
*mv88e6xxx_alloc_chip(struct device
*dev
)
3459 struct mv88e6xxx_chip
*chip
;
3461 chip
= devm_kzalloc(dev
, sizeof(*chip
), GFP_KERNEL
);
3467 mutex_init(&chip
->reg_lock
);
3472 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops
= {
3473 .read
= mv88e6xxx_g2_smi_phy_read
,
3474 .write
= mv88e6xxx_g2_smi_phy_write
,
3477 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops
= {
3478 .read
= mv88e6xxx_read
,
3479 .write
= mv88e6xxx_write
,
3482 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip
*chip
)
3484 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_SMI_PHY
)) {
3485 chip
->phy_ops
= &mv88e6xxx_g2_smi_phy_ops
;
3486 } else if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
)) {
3487 chip
->phy_ops
= &mv88e6xxx_phy_ppu_ops
;
3488 mv88e6xxx_ppu_state_init(chip
);
3490 chip
->phy_ops
= &mv88e6xxx_phy_ops
;
3494 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip
*chip
)
3496 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
)) {
3497 mv88e6xxx_ppu_state_destroy(chip
);
3501 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip
*chip
,
3502 struct mii_bus
*bus
, int sw_addr
)
3504 /* ADDR[0] pin is unavailable externally and considered zero */
3509 chip
->smi_ops
= &mv88e6xxx_smi_single_chip_ops
;
3510 else if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_MULTI_CHIP
))
3511 chip
->smi_ops
= &mv88e6xxx_smi_multi_chip_ops
;
3516 chip
->sw_addr
= sw_addr
;
3521 static enum dsa_tag_protocol
mv88e6xxx_get_tag_protocol(struct dsa_switch
*ds
)
3523 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3525 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EDSA
))
3526 return DSA_TAG_PROTO_EDSA
;
3528 return DSA_TAG_PROTO_DSA
;
3531 static const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
,
3532 struct device
*host_dev
, int sw_addr
,
3535 struct mv88e6xxx_chip
*chip
;
3536 struct mii_bus
*bus
;
3539 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3543 chip
= mv88e6xxx_alloc_chip(dsa_dev
);
3547 /* Legacy SMI probing will only support chips similar to 88E6085 */
3548 chip
->info
= &mv88e6xxx_table
[MV88E6085
];
3550 err
= mv88e6xxx_smi_init(chip
, bus
, sw_addr
);
3554 err
= mv88e6xxx_detect(chip
);
3558 mv88e6xxx_phy_init(chip
);
3560 err
= mv88e6xxx_mdio_register(chip
, NULL
);
3566 return chip
->info
->name
;
3568 devm_kfree(dsa_dev
, chip
);
3573 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch
*ds
, int port
,
3574 const struct switchdev_obj_port_mdb
*mdb
,
3575 struct switchdev_trans
*trans
)
3577 /* We don't need any dynamic resource from the kernel (yet),
3578 * so skip the prepare phase.
3584 static void mv88e6xxx_port_mdb_add(struct dsa_switch
*ds
, int port
,
3585 const struct switchdev_obj_port_mdb
*mdb
,
3586 struct switchdev_trans
*trans
)
3588 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3590 mutex_lock(&chip
->reg_lock
);
3591 if (mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3592 GLOBAL_ATU_DATA_STATE_MC_STATIC
))
3593 netdev_err(ds
->ports
[port
].netdev
, "failed to load multicast MAC address\n");
3594 mutex_unlock(&chip
->reg_lock
);
3597 static int mv88e6xxx_port_mdb_del(struct dsa_switch
*ds
, int port
,
3598 const struct switchdev_obj_port_mdb
*mdb
)
3600 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3603 mutex_lock(&chip
->reg_lock
);
3604 err
= mv88e6xxx_port_db_load_purge(chip
, port
, mdb
->addr
, mdb
->vid
,
3605 GLOBAL_ATU_DATA_STATE_UNUSED
);
3606 mutex_unlock(&chip
->reg_lock
);
3611 static int mv88e6xxx_port_mdb_dump(struct dsa_switch
*ds
, int port
,
3612 struct switchdev_obj_port_mdb
*mdb
,
3613 int (*cb
)(struct switchdev_obj
*obj
))
3615 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3618 mutex_lock(&chip
->reg_lock
);
3619 err
= mv88e6xxx_port_db_dump(chip
, port
, &mdb
->obj
, cb
);
3620 mutex_unlock(&chip
->reg_lock
);
3625 static struct dsa_switch_ops mv88e6xxx_switch_ops
= {
3626 .probe
= mv88e6xxx_drv_probe
,
3627 .get_tag_protocol
= mv88e6xxx_get_tag_protocol
,
3628 .setup
= mv88e6xxx_setup
,
3629 .set_addr
= mv88e6xxx_set_addr
,
3630 .adjust_link
= mv88e6xxx_adjust_link
,
3631 .get_strings
= mv88e6xxx_get_strings
,
3632 .get_ethtool_stats
= mv88e6xxx_get_ethtool_stats
,
3633 .get_sset_count
= mv88e6xxx_get_sset_count
,
3634 .set_eee
= mv88e6xxx_set_eee
,
3635 .get_eee
= mv88e6xxx_get_eee
,
3636 #ifdef CONFIG_NET_DSA_HWMON
3637 .get_temp
= mv88e6xxx_get_temp
,
3638 .get_temp_limit
= mv88e6xxx_get_temp_limit
,
3639 .set_temp_limit
= mv88e6xxx_set_temp_limit
,
3640 .get_temp_alarm
= mv88e6xxx_get_temp_alarm
,
3642 .get_eeprom_len
= mv88e6xxx_get_eeprom_len
,
3643 .get_eeprom
= mv88e6xxx_get_eeprom
,
3644 .set_eeprom
= mv88e6xxx_set_eeprom
,
3645 .get_regs_len
= mv88e6xxx_get_regs_len
,
3646 .get_regs
= mv88e6xxx_get_regs
,
3647 .set_ageing_time
= mv88e6xxx_set_ageing_time
,
3648 .port_bridge_join
= mv88e6xxx_port_bridge_join
,
3649 .port_bridge_leave
= mv88e6xxx_port_bridge_leave
,
3650 .port_stp_state_set
= mv88e6xxx_port_stp_state_set
,
3651 .port_vlan_filtering
= mv88e6xxx_port_vlan_filtering
,
3652 .port_vlan_prepare
= mv88e6xxx_port_vlan_prepare
,
3653 .port_vlan_add
= mv88e6xxx_port_vlan_add
,
3654 .port_vlan_del
= mv88e6xxx_port_vlan_del
,
3655 .port_vlan_dump
= mv88e6xxx_port_vlan_dump
,
3656 .port_fdb_prepare
= mv88e6xxx_port_fdb_prepare
,
3657 .port_fdb_add
= mv88e6xxx_port_fdb_add
,
3658 .port_fdb_del
= mv88e6xxx_port_fdb_del
,
3659 .port_fdb_dump
= mv88e6xxx_port_fdb_dump
,
3660 .port_mdb_prepare
= mv88e6xxx_port_mdb_prepare
,
3661 .port_mdb_add
= mv88e6xxx_port_mdb_add
,
3662 .port_mdb_del
= mv88e6xxx_port_mdb_del
,
3663 .port_mdb_dump
= mv88e6xxx_port_mdb_dump
,
3666 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip
*chip
,
3667 struct device_node
*np
)
3669 struct device
*dev
= chip
->dev
;
3670 struct dsa_switch
*ds
;
3672 ds
= devm_kzalloc(dev
, sizeof(*ds
), GFP_KERNEL
);
3678 ds
->ops
= &mv88e6xxx_switch_ops
;
3680 dev_set_drvdata(dev
, ds
);
3682 return dsa_register_switch(ds
, np
);
3685 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip
*chip
)
3687 dsa_unregister_switch(chip
->ds
);
3690 static int mv88e6xxx_probe(struct mdio_device
*mdiodev
)
3692 struct device
*dev
= &mdiodev
->dev
;
3693 struct device_node
*np
= dev
->of_node
;
3694 const struct mv88e6xxx_info
*compat_info
;
3695 struct mv88e6xxx_chip
*chip
;
3699 compat_info
= of_device_get_match_data(dev
);
3703 chip
= mv88e6xxx_alloc_chip(dev
);
3707 chip
->info
= compat_info
;
3709 err
= mv88e6xxx_smi_init(chip
, mdiodev
->bus
, mdiodev
->addr
);
3713 err
= mv88e6xxx_detect(chip
);
3717 mv88e6xxx_phy_init(chip
);
3719 chip
->reset
= devm_gpiod_get_optional(dev
, "reset", GPIOD_ASIS
);
3720 if (IS_ERR(chip
->reset
))
3721 return PTR_ERR(chip
->reset
);
3723 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_EEPROM16
) &&
3724 !of_property_read_u32(np
, "eeprom-length", &eeprom_len
))
3725 chip
->eeprom_len
= eeprom_len
;
3727 err
= mv88e6xxx_mdio_register(chip
, np
);
3731 err
= mv88e6xxx_register_switch(chip
, np
);
3733 mv88e6xxx_mdio_unregister(chip
);
3740 static void mv88e6xxx_remove(struct mdio_device
*mdiodev
)
3742 struct dsa_switch
*ds
= dev_get_drvdata(&mdiodev
->dev
);
3743 struct mv88e6xxx_chip
*chip
= ds
->priv
;
3745 mv88e6xxx_phy_destroy(chip
);
3746 mv88e6xxx_unregister_switch(chip
);
3747 mv88e6xxx_mdio_unregister(chip
);
3750 static const struct of_device_id mv88e6xxx_of_match
[] = {
3752 .compatible
= "marvell,mv88e6085",
3753 .data
= &mv88e6xxx_table
[MV88E6085
],
3758 MODULE_DEVICE_TABLE(of
, mv88e6xxx_of_match
);
3760 static struct mdio_driver mv88e6xxx_driver
= {
3761 .probe
= mv88e6xxx_probe
,
3762 .remove
= mv88e6xxx_remove
,
3764 .name
= "mv88e6085",
3765 .of_match_table
= mv88e6xxx_of_match
,
3769 static int __init
mv88e6xxx_init(void)
3771 register_switch_driver(&mv88e6xxx_switch_ops
);
3772 return mdio_driver_register(&mv88e6xxx_driver
);
3774 module_init(mv88e6xxx_init
);
3776 static void __exit
mv88e6xxx_cleanup(void)
3778 mdio_driver_unregister(&mv88e6xxx_driver
);
3779 unregister_switch_driver(&mv88e6xxx_switch_ops
);
3781 module_exit(mv88e6xxx_cleanup
);
3783 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3784 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3785 MODULE_LICENSE("GPL");