2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/netdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/phy.h>
31 #include <net/switchdev.h>
32 #include "mv88e6xxx.h"
34 static void assert_reg_lock(struct mv88e6xxx_chip
*chip
)
36 if (unlikely(!mutex_is_locked(&chip
->reg_lock
))) {
37 dev_err(chip
->dev
, "Switch registers lock not held!\n");
42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip
*chip
,
55 int addr
, int reg
, u16
*val
)
60 return chip
->smi_ops
->read(chip
, addr
, reg
, val
);
63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip
*chip
,
64 int addr
, int reg
, u16 val
)
69 return chip
->smi_ops
->write(chip
, addr
, reg
, val
);
72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip
*chip
,
73 int addr
, int reg
, u16
*val
)
77 ret
= mdiobus_read_nested(chip
->bus
, addr
, reg
);
86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip
*chip
,
87 int addr
, int reg
, u16 val
)
91 ret
= mdiobus_write_nested(chip
->bus
, addr
, reg
, val
);
98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops
= {
99 .read
= mv88e6xxx_smi_single_chip_read
,
100 .write
= mv88e6xxx_smi_single_chip_write
,
103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip
*chip
)
108 for (i
= 0; i
< 16; i
++) {
109 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
);
113 if ((ret
& SMI_CMD_BUSY
) == 0)
120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip
*chip
,
121 int addr
, int reg
, u16
*val
)
125 /* Wait for the bus to become free. */
126 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
130 /* Transmit the read command. */
131 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
132 SMI_CMD_OP_22_READ
| (addr
<< 5) | reg
);
136 /* Wait for the read command to complete. */
137 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
142 ret
= mdiobus_read_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
);
151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip
*chip
,
152 int addr
, int reg
, u16 val
)
156 /* Wait for the bus to become free. */
157 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
161 /* Transmit the data to write. */
162 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_DATA
, val
);
166 /* Transmit the write command. */
167 ret
= mdiobus_write_nested(chip
->bus
, chip
->sw_addr
, SMI_CMD
,
168 SMI_CMD_OP_22_WRITE
| (addr
<< 5) | reg
);
172 /* Wait for the write command to complete. */
173 ret
= mv88e6xxx_smi_multi_chip_wait(chip
);
180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops
= {
181 .read
= mv88e6xxx_smi_multi_chip_read
,
182 .write
= mv88e6xxx_smi_multi_chip_write
,
185 static int mv88e6xxx_read(struct mv88e6xxx_chip
*chip
,
186 int addr
, int reg
, u16
*val
)
190 assert_reg_lock(chip
);
192 err
= mv88e6xxx_smi_read(chip
, addr
, reg
, val
);
196 dev_dbg(chip
->dev
, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
202 static int mv88e6xxx_write(struct mv88e6xxx_chip
*chip
,
203 int addr
, int reg
, u16 val
)
207 assert_reg_lock(chip
);
209 err
= mv88e6xxx_smi_write(chip
, addr
, reg
, val
);
213 dev_dbg(chip
->dev
, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
219 /* Indirect write to single pointer-data register with an Update bit */
220 static int mv88e6xxx_update(struct mv88e6xxx_chip
*chip
, int addr
, int reg
,
226 /* Wait until the previous operation is completed */
227 for (i
= 0; i
< 16; ++i
) {
228 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
232 if (!(val
& BIT(15)))
239 /* Set the Update bit to trigger a write operation */
240 val
= BIT(15) | update
;
242 return mv88e6xxx_write(chip
, addr
, reg
, val
);
245 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
)
250 err
= mv88e6xxx_read(chip
, addr
, reg
, &val
);
257 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip
*chip
, int addr
,
260 return mv88e6xxx_write(chip
, addr
, reg
, val
);
263 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip
*chip
,
264 int addr
, int regnum
)
267 return _mv88e6xxx_reg_read(chip
, addr
, regnum
);
271 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip
*chip
,
272 int addr
, int regnum
, u16 val
)
275 return _mv88e6xxx_reg_write(chip
, addr
, regnum
, val
);
279 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip
*chip
)
282 unsigned long timeout
;
284 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_CONTROL
);
288 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL
,
289 ret
& ~GLOBAL_CONTROL_PPU_ENABLE
);
293 timeout
= jiffies
+ 1 * HZ
;
294 while (time_before(jiffies
, timeout
)) {
295 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATUS
);
299 usleep_range(1000, 2000);
300 if ((ret
& GLOBAL_STATUS_PPU_MASK
) !=
301 GLOBAL_STATUS_PPU_POLLING
)
308 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip
*chip
)
311 unsigned long timeout
;
313 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_CONTROL
);
317 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL
,
318 ret
| GLOBAL_CONTROL_PPU_ENABLE
);
322 timeout
= jiffies
+ 1 * HZ
;
323 while (time_before(jiffies
, timeout
)) {
324 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATUS
);
328 usleep_range(1000, 2000);
329 if ((ret
& GLOBAL_STATUS_PPU_MASK
) ==
330 GLOBAL_STATUS_PPU_POLLING
)
337 static void mv88e6xxx_ppu_reenable_work(struct work_struct
*ugly
)
339 struct mv88e6xxx_chip
*chip
;
341 chip
= container_of(ugly
, struct mv88e6xxx_chip
, ppu_work
);
343 mutex_lock(&chip
->reg_lock
);
345 if (mutex_trylock(&chip
->ppu_mutex
)) {
346 if (mv88e6xxx_ppu_enable(chip
) == 0)
347 chip
->ppu_disabled
= 0;
348 mutex_unlock(&chip
->ppu_mutex
);
351 mutex_unlock(&chip
->reg_lock
);
354 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps
)
356 struct mv88e6xxx_chip
*chip
= (void *)_ps
;
358 schedule_work(&chip
->ppu_work
);
361 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip
*chip
)
365 mutex_lock(&chip
->ppu_mutex
);
367 /* If the PHY polling unit is enabled, disable it so that
368 * we can access the PHY registers. If it was already
369 * disabled, cancel the timer that is going to re-enable
372 if (!chip
->ppu_disabled
) {
373 ret
= mv88e6xxx_ppu_disable(chip
);
375 mutex_unlock(&chip
->ppu_mutex
);
378 chip
->ppu_disabled
= 1;
380 del_timer(&chip
->ppu_timer
);
387 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip
*chip
)
389 /* Schedule a timer to re-enable the PHY polling unit. */
390 mod_timer(&chip
->ppu_timer
, jiffies
+ msecs_to_jiffies(10));
391 mutex_unlock(&chip
->ppu_mutex
);
394 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip
*chip
)
396 mutex_init(&chip
->ppu_mutex
);
397 INIT_WORK(&chip
->ppu_work
, mv88e6xxx_ppu_reenable_work
);
398 init_timer(&chip
->ppu_timer
);
399 chip
->ppu_timer
.data
= (unsigned long)chip
;
400 chip
->ppu_timer
.function
= mv88e6xxx_ppu_reenable_timer
;
403 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip
*chip
, int addr
,
408 ret
= mv88e6xxx_ppu_access_get(chip
);
410 ret
= _mv88e6xxx_reg_read(chip
, addr
, regnum
);
411 mv88e6xxx_ppu_access_put(chip
);
417 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip
*chip
, int addr
,
422 ret
= mv88e6xxx_ppu_access_get(chip
);
424 ret
= _mv88e6xxx_reg_write(chip
, addr
, regnum
, val
);
425 mv88e6xxx_ppu_access_put(chip
);
431 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip
*chip
)
433 return chip
->info
->family
== MV88E6XXX_FAMILY_6065
;
436 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip
*chip
)
438 return chip
->info
->family
== MV88E6XXX_FAMILY_6095
;
441 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip
*chip
)
443 return chip
->info
->family
== MV88E6XXX_FAMILY_6097
;
446 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip
*chip
)
448 return chip
->info
->family
== MV88E6XXX_FAMILY_6165
;
451 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip
*chip
)
453 return chip
->info
->family
== MV88E6XXX_FAMILY_6185
;
456 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip
*chip
)
458 return chip
->info
->family
== MV88E6XXX_FAMILY_6320
;
461 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip
*chip
)
463 return chip
->info
->family
== MV88E6XXX_FAMILY_6351
;
466 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip
*chip
)
468 return chip
->info
->family
== MV88E6XXX_FAMILY_6352
;
471 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip
*chip
)
473 return chip
->info
->num_databases
;
476 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip
*chip
)
478 /* Does the device have dedicated FID registers for ATU and VTU ops? */
479 if (mv88e6xxx_6097_family(chip
) || mv88e6xxx_6165_family(chip
) ||
480 mv88e6xxx_6351_family(chip
) || mv88e6xxx_6352_family(chip
))
486 /* We expect the switch to perform auto negotiation if there is a real
487 * phy. However, in the case of a fixed link phy, we force the port
488 * settings from the fixed link settings.
490 static void mv88e6xxx_adjust_link(struct dsa_switch
*ds
, int port
,
491 struct phy_device
*phydev
)
493 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
497 if (!phy_is_pseudo_fixed_link(phydev
))
500 mutex_lock(&chip
->reg_lock
);
502 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_PCS_CTRL
);
506 reg
= ret
& ~(PORT_PCS_CTRL_LINK_UP
|
507 PORT_PCS_CTRL_FORCE_LINK
|
508 PORT_PCS_CTRL_DUPLEX_FULL
|
509 PORT_PCS_CTRL_FORCE_DUPLEX
|
510 PORT_PCS_CTRL_UNFORCED
);
512 reg
|= PORT_PCS_CTRL_FORCE_LINK
;
514 reg
|= PORT_PCS_CTRL_LINK_UP
;
516 if (mv88e6xxx_6065_family(chip
) && phydev
->speed
> SPEED_100
)
519 switch (phydev
->speed
) {
521 reg
|= PORT_PCS_CTRL_1000
;
524 reg
|= PORT_PCS_CTRL_100
;
527 reg
|= PORT_PCS_CTRL_10
;
530 pr_info("Unknown speed");
534 reg
|= PORT_PCS_CTRL_FORCE_DUPLEX
;
535 if (phydev
->duplex
== DUPLEX_FULL
)
536 reg
|= PORT_PCS_CTRL_DUPLEX_FULL
;
538 if ((mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
)) &&
539 (port
>= chip
->info
->num_ports
- 2)) {
540 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
541 reg
|= PORT_PCS_CTRL_RGMII_DELAY_RXCLK
;
542 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
543 reg
|= PORT_PCS_CTRL_RGMII_DELAY_TXCLK
;
544 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
545 reg
|= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK
|
546 PORT_PCS_CTRL_RGMII_DELAY_TXCLK
);
548 _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_PCS_CTRL
, reg
);
551 mutex_unlock(&chip
->reg_lock
);
554 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip
*chip
)
559 for (i
= 0; i
< 10; i
++) {
560 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
);
561 if ((ret
& GLOBAL_STATS_OP_BUSY
) == 0)
568 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip
*chip
, int port
)
572 if (mv88e6xxx_6320_family(chip
) || mv88e6xxx_6352_family(chip
))
573 port
= (port
+ 1) << 5;
575 /* Snapshot the hardware statistics counters for this port. */
576 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
,
577 GLOBAL_STATS_OP_CAPTURE_PORT
|
578 GLOBAL_STATS_OP_HIST_RX_TX
| port
);
582 /* Wait for the snapshotting to complete. */
583 ret
= _mv88e6xxx_stats_wait(chip
);
590 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip
*chip
,
598 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
,
599 GLOBAL_STATS_OP_READ_CAPTURED
|
600 GLOBAL_STATS_OP_HIST_RX_TX
| stat
);
604 ret
= _mv88e6xxx_stats_wait(chip
);
608 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_32
);
614 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_STATS_COUNTER_01
);
621 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats
[] = {
622 { "in_good_octets", 8, 0x00, BANK0
, },
623 { "in_bad_octets", 4, 0x02, BANK0
, },
624 { "in_unicast", 4, 0x04, BANK0
, },
625 { "in_broadcasts", 4, 0x06, BANK0
, },
626 { "in_multicasts", 4, 0x07, BANK0
, },
627 { "in_pause", 4, 0x16, BANK0
, },
628 { "in_undersize", 4, 0x18, BANK0
, },
629 { "in_fragments", 4, 0x19, BANK0
, },
630 { "in_oversize", 4, 0x1a, BANK0
, },
631 { "in_jabber", 4, 0x1b, BANK0
, },
632 { "in_rx_error", 4, 0x1c, BANK0
, },
633 { "in_fcs_error", 4, 0x1d, BANK0
, },
634 { "out_octets", 8, 0x0e, BANK0
, },
635 { "out_unicast", 4, 0x10, BANK0
, },
636 { "out_broadcasts", 4, 0x13, BANK0
, },
637 { "out_multicasts", 4, 0x12, BANK0
, },
638 { "out_pause", 4, 0x15, BANK0
, },
639 { "excessive", 4, 0x11, BANK0
, },
640 { "collisions", 4, 0x1e, BANK0
, },
641 { "deferred", 4, 0x05, BANK0
, },
642 { "single", 4, 0x14, BANK0
, },
643 { "multiple", 4, 0x17, BANK0
, },
644 { "out_fcs_error", 4, 0x03, BANK0
, },
645 { "late", 4, 0x1f, BANK0
, },
646 { "hist_64bytes", 4, 0x08, BANK0
, },
647 { "hist_65_127bytes", 4, 0x09, BANK0
, },
648 { "hist_128_255bytes", 4, 0x0a, BANK0
, },
649 { "hist_256_511bytes", 4, 0x0b, BANK0
, },
650 { "hist_512_1023bytes", 4, 0x0c, BANK0
, },
651 { "hist_1024_max_bytes", 4, 0x0d, BANK0
, },
652 { "sw_in_discards", 4, 0x10, PORT
, },
653 { "sw_in_filtered", 2, 0x12, PORT
, },
654 { "sw_out_filtered", 2, 0x13, PORT
, },
655 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
656 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
657 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
658 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
659 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
660 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
661 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
662 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
663 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
664 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
665 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
666 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
667 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
668 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
669 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
670 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
671 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
672 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
673 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
674 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
675 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
676 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
677 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
678 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
679 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
680 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1
, BANK1
, },
683 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip
*chip
,
684 struct mv88e6xxx_hw_stat
*stat
)
686 switch (stat
->type
) {
690 return mv88e6xxx_6320_family(chip
);
692 return mv88e6xxx_6095_family(chip
) ||
693 mv88e6xxx_6185_family(chip
) ||
694 mv88e6xxx_6097_family(chip
) ||
695 mv88e6xxx_6165_family(chip
) ||
696 mv88e6xxx_6351_family(chip
) ||
697 mv88e6xxx_6352_family(chip
);
702 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip
*chip
,
703 struct mv88e6xxx_hw_stat
*s
,
713 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), s
->reg
);
718 if (s
->sizeof_stat
== 4) {
719 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
),
728 _mv88e6xxx_stats_read(chip
, s
->reg
, &low
);
729 if (s
->sizeof_stat
== 8)
730 _mv88e6xxx_stats_read(chip
, s
->reg
+ 1, &high
);
732 value
= (((u64
)high
) << 16) | low
;
736 static void mv88e6xxx_get_strings(struct dsa_switch
*ds
, int port
,
739 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
740 struct mv88e6xxx_hw_stat
*stat
;
743 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
744 stat
= &mv88e6xxx_hw_stats
[i
];
745 if (mv88e6xxx_has_stat(chip
, stat
)) {
746 memcpy(data
+ j
* ETH_GSTRING_LEN
, stat
->string
,
753 static int mv88e6xxx_get_sset_count(struct dsa_switch
*ds
)
755 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
756 struct mv88e6xxx_hw_stat
*stat
;
759 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
760 stat
= &mv88e6xxx_hw_stats
[i
];
761 if (mv88e6xxx_has_stat(chip
, stat
))
767 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
770 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
771 struct mv88e6xxx_hw_stat
*stat
;
775 mutex_lock(&chip
->reg_lock
);
777 ret
= _mv88e6xxx_stats_snapshot(chip
, port
);
779 mutex_unlock(&chip
->reg_lock
);
782 for (i
= 0, j
= 0; i
< ARRAY_SIZE(mv88e6xxx_hw_stats
); i
++) {
783 stat
= &mv88e6xxx_hw_stats
[i
];
784 if (mv88e6xxx_has_stat(chip
, stat
)) {
785 data
[j
] = _mv88e6xxx_get_ethtool_stat(chip
, stat
, port
);
790 mutex_unlock(&chip
->reg_lock
);
793 static int mv88e6xxx_get_regs_len(struct dsa_switch
*ds
, int port
)
795 return 32 * sizeof(u16
);
798 static void mv88e6xxx_get_regs(struct dsa_switch
*ds
, int port
,
799 struct ethtool_regs
*regs
, void *_p
)
801 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
807 memset(p
, 0xff, 32 * sizeof(u16
));
809 mutex_lock(&chip
->reg_lock
);
811 for (i
= 0; i
< 32; i
++) {
814 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), i
);
819 mutex_unlock(&chip
->reg_lock
);
822 static int _mv88e6xxx_wait(struct mv88e6xxx_chip
*chip
, int reg
, int offset
,
825 unsigned long timeout
= jiffies
+ HZ
/ 10;
827 while (time_before(jiffies
, timeout
)) {
830 ret
= _mv88e6xxx_reg_read(chip
, reg
, offset
);
836 usleep_range(1000, 2000);
841 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip
*chip
)
843 return _mv88e6xxx_wait(chip
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
844 GLOBAL2_SMI_OP_BUSY
);
847 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip
*chip
)
849 return _mv88e6xxx_wait(chip
, REG_GLOBAL
, GLOBAL_ATU_OP
,
853 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip
*chip
,
854 int addr
, int regnum
)
858 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
859 GLOBAL2_SMI_OP_22_READ
| (addr
<< 5) |
864 ret
= mv88e6xxx_mdio_wait(chip
);
868 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
);
873 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip
*chip
,
874 int addr
, int regnum
, u16 val
)
878 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL2
, GLOBAL2_SMI_DATA
, val
);
882 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL2
, GLOBAL2_SMI_OP
,
883 GLOBAL2_SMI_OP_22_WRITE
| (addr
<< 5) |
886 return mv88e6xxx_mdio_wait(chip
);
889 static int mv88e6xxx_get_eee(struct dsa_switch
*ds
, int port
,
890 struct ethtool_eee
*e
)
892 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
895 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EEE
))
898 mutex_lock(&chip
->reg_lock
);
900 reg
= mv88e6xxx_mdio_read_indirect(chip
, port
, 16);
904 e
->eee_enabled
= !!(reg
& 0x0200);
905 e
->tx_lpi_enabled
= !!(reg
& 0x0100);
907 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_STATUS
);
911 e
->eee_active
= !!(reg
& PORT_STATUS_EEE
);
915 mutex_unlock(&chip
->reg_lock
);
919 static int mv88e6xxx_set_eee(struct dsa_switch
*ds
, int port
,
920 struct phy_device
*phydev
, struct ethtool_eee
*e
)
922 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
926 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_EEE
))
929 mutex_lock(&chip
->reg_lock
);
931 ret
= mv88e6xxx_mdio_read_indirect(chip
, port
, 16);
938 if (e
->tx_lpi_enabled
)
941 ret
= mv88e6xxx_mdio_write_indirect(chip
, port
, 16, reg
);
943 mutex_unlock(&chip
->reg_lock
);
948 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip
*chip
, u16 fid
, u16 cmd
)
952 if (mv88e6xxx_has_fid_reg(chip
)) {
953 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_FID
,
957 } else if (mv88e6xxx_num_databases(chip
) == 256) {
958 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
959 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
);
963 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
965 ((fid
<< 8) & 0xf000));
969 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
973 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_OP
, cmd
);
977 return _mv88e6xxx_atu_wait(chip
);
980 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip
*chip
,
981 struct mv88e6xxx_atu_entry
*entry
)
983 u16 data
= entry
->state
& GLOBAL_ATU_DATA_STATE_MASK
;
985 if (entry
->state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
986 unsigned int mask
, shift
;
989 data
|= GLOBAL_ATU_DATA_TRUNK
;
990 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
991 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
993 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
994 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
997 data
|= (entry
->portv_trunkid
<< shift
) & mask
;
1000 return _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_ATU_DATA
, data
);
1003 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip
*chip
,
1004 struct mv88e6xxx_atu_entry
*entry
,
1010 err
= _mv88e6xxx_atu_wait(chip
);
1014 err
= _mv88e6xxx_atu_data_write(chip
, entry
);
1019 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB
:
1020 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB
;
1022 op
= static_too
? GLOBAL_ATU_OP_FLUSH_MOVE_ALL
:
1023 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC
;
1026 return _mv88e6xxx_atu_cmd(chip
, entry
->fid
, op
);
1029 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip
*chip
,
1030 u16 fid
, bool static_too
)
1032 struct mv88e6xxx_atu_entry entry
= {
1034 .state
= 0, /* EntryState bits must be 0 */
1037 return _mv88e6xxx_atu_flush_move(chip
, &entry
, static_too
);
1040 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip
*chip
, u16 fid
,
1041 int from_port
, int to_port
, bool static_too
)
1043 struct mv88e6xxx_atu_entry entry
= {
1048 /* EntryState bits must be 0xF */
1049 entry
.state
= GLOBAL_ATU_DATA_STATE_MASK
;
1051 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1052 entry
.portv_trunkid
= (to_port
& 0x0f) << 4;
1053 entry
.portv_trunkid
|= from_port
& 0x0f;
1055 return _mv88e6xxx_atu_flush_move(chip
, &entry
, static_too
);
1058 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip
*chip
, u16 fid
,
1059 int port
, bool static_too
)
1061 /* Destination port 0xF means remove the entries */
1062 return _mv88e6xxx_atu_move(chip
, fid
, port
, 0x0f, static_too
);
1065 static const char * const mv88e6xxx_port_state_names
[] = {
1066 [PORT_CONTROL_STATE_DISABLED
] = "Disabled",
1067 [PORT_CONTROL_STATE_BLOCKING
] = "Blocking/Listening",
1068 [PORT_CONTROL_STATE_LEARNING
] = "Learning",
1069 [PORT_CONTROL_STATE_FORWARDING
] = "Forwarding",
1072 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip
*chip
, int port
,
1075 struct dsa_switch
*ds
= chip
->ds
;
1079 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_CONTROL
);
1083 oldstate
= reg
& PORT_CONTROL_STATE_MASK
;
1085 if (oldstate
!= state
) {
1086 /* Flush forwarding database if we're moving a port
1087 * from Learning or Forwarding state to Disabled or
1088 * Blocking or Listening state.
1090 if ((oldstate
== PORT_CONTROL_STATE_LEARNING
||
1091 oldstate
== PORT_CONTROL_STATE_FORWARDING
) &&
1092 (state
== PORT_CONTROL_STATE_DISABLED
||
1093 state
== PORT_CONTROL_STATE_BLOCKING
)) {
1094 ret
= _mv88e6xxx_atu_remove(chip
, 0, port
, false);
1099 reg
= (reg
& ~PORT_CONTROL_STATE_MASK
) | state
;
1100 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL
,
1105 netdev_dbg(ds
->ports
[port
].netdev
, "PortState %s (was %s)\n",
1106 mv88e6xxx_port_state_names
[state
],
1107 mv88e6xxx_port_state_names
[oldstate
]);
1113 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip
*chip
, int port
)
1115 struct net_device
*bridge
= chip
->ports
[port
].bridge_dev
;
1116 const u16 mask
= (1 << chip
->info
->num_ports
) - 1;
1117 struct dsa_switch
*ds
= chip
->ds
;
1118 u16 output_ports
= 0;
1122 /* allow CPU port or DSA link(s) to send frames to every port */
1123 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
1124 output_ports
= mask
;
1126 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1127 /* allow sending frames to every group member */
1128 if (bridge
&& chip
->ports
[i
].bridge_dev
== bridge
)
1129 output_ports
|= BIT(i
);
1131 /* allow sending frames to CPU port and DSA link(s) */
1132 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1133 output_ports
|= BIT(i
);
1137 /* prevent frames from going back out of the port they came in on */
1138 output_ports
&= ~BIT(port
);
1140 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_BASE_VLAN
);
1145 reg
|= output_ports
& mask
;
1147 return _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_BASE_VLAN
, reg
);
1150 static void mv88e6xxx_port_stp_state_set(struct dsa_switch
*ds
, int port
,
1153 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1158 case BR_STATE_DISABLED
:
1159 stp_state
= PORT_CONTROL_STATE_DISABLED
;
1161 case BR_STATE_BLOCKING
:
1162 case BR_STATE_LISTENING
:
1163 stp_state
= PORT_CONTROL_STATE_BLOCKING
;
1165 case BR_STATE_LEARNING
:
1166 stp_state
= PORT_CONTROL_STATE_LEARNING
;
1168 case BR_STATE_FORWARDING
:
1170 stp_state
= PORT_CONTROL_STATE_FORWARDING
;
1174 mutex_lock(&chip
->reg_lock
);
1175 err
= _mv88e6xxx_port_state(chip
, port
, stp_state
);
1176 mutex_unlock(&chip
->reg_lock
);
1179 netdev_err(ds
->ports
[port
].netdev
,
1180 "failed to update state to %s\n",
1181 mv88e6xxx_port_state_names
[stp_state
]);
1184 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip
*chip
, int port
,
1187 struct dsa_switch
*ds
= chip
->ds
;
1191 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_DEFAULT_VLAN
);
1195 pvid
= ret
& PORT_DEFAULT_VLAN_MASK
;
1198 ret
&= ~PORT_DEFAULT_VLAN_MASK
;
1199 ret
|= *new & PORT_DEFAULT_VLAN_MASK
;
1201 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
1202 PORT_DEFAULT_VLAN
, ret
);
1206 netdev_dbg(ds
->ports
[port
].netdev
,
1207 "DefaultVID %d (was %d)\n", *new, pvid
);
1216 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip
*chip
,
1217 int port
, u16
*pvid
)
1219 return _mv88e6xxx_port_pvid(chip
, port
, NULL
, pvid
);
1222 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip
*chip
,
1225 return _mv88e6xxx_port_pvid(chip
, port
, &pvid
, NULL
);
1228 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip
*chip
)
1230 return _mv88e6xxx_wait(chip
, REG_GLOBAL
, GLOBAL_VTU_OP
,
1231 GLOBAL_VTU_OP_BUSY
);
1234 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip
*chip
, u16 op
)
1238 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_OP
, op
);
1242 return _mv88e6xxx_vtu_wait(chip
);
1245 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip
*chip
)
1249 ret
= _mv88e6xxx_vtu_wait(chip
);
1253 return _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_FLUSH_ALL
);
1256 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip
*chip
,
1257 struct mv88e6xxx_vtu_stu_entry
*entry
,
1258 unsigned int nibble_offset
)
1264 for (i
= 0; i
< 3; ++i
) {
1265 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1266 GLOBAL_VTU_DATA_0_3
+ i
);
1273 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1274 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1275 u16 reg
= regs
[i
/ 4];
1277 entry
->data
[i
] = (reg
>> shift
) & GLOBAL_VTU_STU_DATA_MASK
;
1283 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip
*chip
,
1284 struct mv88e6xxx_vtu_stu_entry
*entry
)
1286 return _mv88e6xxx_vtu_stu_data_read(chip
, entry
, 0);
1289 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip
*chip
,
1290 struct mv88e6xxx_vtu_stu_entry
*entry
)
1292 return _mv88e6xxx_vtu_stu_data_read(chip
, entry
, 2);
1295 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip
*chip
,
1296 struct mv88e6xxx_vtu_stu_entry
*entry
,
1297 unsigned int nibble_offset
)
1299 u16 regs
[3] = { 0 };
1303 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1304 unsigned int shift
= (i
% 4) * 4 + nibble_offset
;
1305 u8 data
= entry
->data
[i
];
1307 regs
[i
/ 4] |= (data
& GLOBAL_VTU_STU_DATA_MASK
) << shift
;
1310 for (i
= 0; i
< 3; ++i
) {
1311 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
,
1312 GLOBAL_VTU_DATA_0_3
+ i
, regs
[i
]);
1320 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip
*chip
,
1321 struct mv88e6xxx_vtu_stu_entry
*entry
)
1323 return _mv88e6xxx_vtu_stu_data_write(chip
, entry
, 0);
1326 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip
*chip
,
1327 struct mv88e6xxx_vtu_stu_entry
*entry
)
1329 return _mv88e6xxx_vtu_stu_data_write(chip
, entry
, 2);
1332 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip
*chip
, u16 vid
)
1334 return _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
,
1335 vid
& GLOBAL_VTU_VID_MASK
);
1338 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip
*chip
,
1339 struct mv88e6xxx_vtu_stu_entry
*entry
)
1341 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1344 ret
= _mv88e6xxx_vtu_wait(chip
);
1348 ret
= _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_VTU_GET_NEXT
);
1352 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1356 next
.vid
= ret
& GLOBAL_VTU_VID_MASK
;
1357 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1360 ret
= mv88e6xxx_vtu_data_read(chip
, &next
);
1364 if (mv88e6xxx_has_fid_reg(chip
)) {
1365 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1370 next
.fid
= ret
& GLOBAL_VTU_FID_MASK
;
1371 } else if (mv88e6xxx_num_databases(chip
) == 256) {
1372 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1373 * VTU DBNum[3:0] are located in VTU Operation 3:0
1375 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1380 next
.fid
= (ret
& 0xf00) >> 4;
1381 next
.fid
|= ret
& 0xf;
1384 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_STU
)) {
1385 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
1390 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1398 static int mv88e6xxx_port_vlan_dump(struct dsa_switch
*ds
, int port
,
1399 struct switchdev_obj_port_vlan
*vlan
,
1400 int (*cb
)(struct switchdev_obj
*obj
))
1402 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1403 struct mv88e6xxx_vtu_stu_entry next
;
1407 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1410 mutex_lock(&chip
->reg_lock
);
1412 err
= _mv88e6xxx_port_pvid_get(chip
, port
, &pvid
);
1416 err
= _mv88e6xxx_vtu_vid_write(chip
, GLOBAL_VTU_VID_MASK
);
1421 err
= _mv88e6xxx_vtu_getnext(chip
, &next
);
1428 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1431 /* reinit and dump this VLAN obj */
1432 vlan
->vid_begin
= next
.vid
;
1433 vlan
->vid_end
= next
.vid
;
1436 if (next
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
)
1437 vlan
->flags
|= BRIDGE_VLAN_INFO_UNTAGGED
;
1439 if (next
.vid
== pvid
)
1440 vlan
->flags
|= BRIDGE_VLAN_INFO_PVID
;
1442 err
= cb(&vlan
->obj
);
1445 } while (next
.vid
< GLOBAL_VTU_VID_MASK
);
1448 mutex_unlock(&chip
->reg_lock
);
1453 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip
*chip
,
1454 struct mv88e6xxx_vtu_stu_entry
*entry
)
1456 u16 op
= GLOBAL_VTU_OP_VTU_LOAD_PURGE
;
1460 ret
= _mv88e6xxx_vtu_wait(chip
);
1467 /* Write port member tags */
1468 ret
= mv88e6xxx_vtu_data_write(chip
, entry
);
1472 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_STU
)) {
1473 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1474 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1480 if (mv88e6xxx_has_fid_reg(chip
)) {
1481 reg
= entry
->fid
& GLOBAL_VTU_FID_MASK
;
1482 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_FID
,
1486 } else if (mv88e6xxx_num_databases(chip
) == 256) {
1487 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1488 * VTU DBNum[3:0] are located in VTU Operation 3:0
1490 op
|= (entry
->fid
& 0xf0) << 8;
1491 op
|= entry
->fid
& 0xf;
1494 reg
= GLOBAL_VTU_VID_VALID
;
1496 reg
|= entry
->vid
& GLOBAL_VTU_VID_MASK
;
1497 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1501 return _mv88e6xxx_vtu_cmd(chip
, op
);
1504 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip
*chip
, u8 sid
,
1505 struct mv88e6xxx_vtu_stu_entry
*entry
)
1507 struct mv88e6xxx_vtu_stu_entry next
= { 0 };
1510 ret
= _mv88e6xxx_vtu_wait(chip
);
1514 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
,
1515 sid
& GLOBAL_VTU_SID_MASK
);
1519 ret
= _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_STU_GET_NEXT
);
1523 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
);
1527 next
.sid
= ret
& GLOBAL_VTU_SID_MASK
;
1529 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
);
1533 next
.valid
= !!(ret
& GLOBAL_VTU_VID_VALID
);
1536 ret
= mv88e6xxx_stu_data_read(chip
, &next
);
1545 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip
*chip
,
1546 struct mv88e6xxx_vtu_stu_entry
*entry
)
1551 ret
= _mv88e6xxx_vtu_wait(chip
);
1558 /* Write port states */
1559 ret
= mv88e6xxx_stu_data_write(chip
, entry
);
1563 reg
= GLOBAL_VTU_VID_VALID
;
1565 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_VID
, reg
);
1569 reg
= entry
->sid
& GLOBAL_VTU_SID_MASK
;
1570 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_VTU_SID
, reg
);
1574 return _mv88e6xxx_vtu_cmd(chip
, GLOBAL_VTU_OP_STU_LOAD_PURGE
);
1577 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip
*chip
, int port
,
1580 struct dsa_switch
*ds
= chip
->ds
;
1585 if (mv88e6xxx_num_databases(chip
) == 4096)
1587 else if (mv88e6xxx_num_databases(chip
) == 256)
1592 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1593 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_BASE_VLAN
);
1597 fid
= (ret
& PORT_BASE_VLAN_FID_3_0_MASK
) >> 12;
1600 ret
&= ~PORT_BASE_VLAN_FID_3_0_MASK
;
1601 ret
|= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK
;
1603 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_BASE_VLAN
,
1609 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1610 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_CONTROL_1
);
1614 fid
|= (ret
& upper_mask
) << 4;
1618 ret
|= (*new >> 4) & upper_mask
;
1620 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL_1
,
1625 netdev_dbg(ds
->ports
[port
].netdev
,
1626 "FID %d (was %d)\n", *new, fid
);
1635 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip
*chip
,
1638 return _mv88e6xxx_port_fid(chip
, port
, NULL
, fid
);
1641 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip
*chip
,
1644 return _mv88e6xxx_port_fid(chip
, port
, &fid
, NULL
);
1647 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip
*chip
, u16
*fid
)
1649 DECLARE_BITMAP(fid_bitmap
, MV88E6XXX_N_FID
);
1650 struct mv88e6xxx_vtu_stu_entry vlan
;
1653 bitmap_zero(fid_bitmap
, MV88E6XXX_N_FID
);
1655 /* Set every FID bit used by the (un)bridged ports */
1656 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1657 err
= _mv88e6xxx_port_fid_get(chip
, i
, fid
);
1661 set_bit(*fid
, fid_bitmap
);
1664 /* Set every FID bit used by the VLAN entries */
1665 err
= _mv88e6xxx_vtu_vid_write(chip
, GLOBAL_VTU_VID_MASK
);
1670 err
= _mv88e6xxx_vtu_getnext(chip
, &vlan
);
1677 set_bit(vlan
.fid
, fid_bitmap
);
1678 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
1680 /* The reset value 0x000 is used to indicate that multiple address
1681 * databases are not needed. Return the next positive available.
1683 *fid
= find_next_zero_bit(fid_bitmap
, MV88E6XXX_N_FID
, 1);
1684 if (unlikely(*fid
>= mv88e6xxx_num_databases(chip
)))
1687 /* Clear the database */
1688 return _mv88e6xxx_atu_flush(chip
, *fid
, true);
1691 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip
*chip
, u16 vid
,
1692 struct mv88e6xxx_vtu_stu_entry
*entry
)
1694 struct dsa_switch
*ds
= chip
->ds
;
1695 struct mv88e6xxx_vtu_stu_entry vlan
= {
1701 err
= _mv88e6xxx_fid_new(chip
, &vlan
.fid
);
1705 /* exclude all ports except the CPU and DSA ports */
1706 for (i
= 0; i
< chip
->info
->num_ports
; ++i
)
1707 vlan
.data
[i
] = dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
)
1708 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1709 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1711 if (mv88e6xxx_6097_family(chip
) || mv88e6xxx_6165_family(chip
) ||
1712 mv88e6xxx_6351_family(chip
) || mv88e6xxx_6352_family(chip
)) {
1713 struct mv88e6xxx_vtu_stu_entry vstp
;
1715 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1716 * implemented, only one STU entry is needed to cover all VTU
1717 * entries. Thus, validate the SID 0.
1720 err
= _mv88e6xxx_stu_getnext(chip
, GLOBAL_VTU_SID_MASK
, &vstp
);
1724 if (vstp
.sid
!= vlan
.sid
|| !vstp
.valid
) {
1725 memset(&vstp
, 0, sizeof(vstp
));
1727 vstp
.sid
= vlan
.sid
;
1729 err
= _mv88e6xxx_stu_loadpurge(chip
, &vstp
);
1739 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip
*chip
, u16 vid
,
1740 struct mv88e6xxx_vtu_stu_entry
*entry
, bool creat
)
1747 err
= _mv88e6xxx_vtu_vid_write(chip
, vid
- 1);
1751 err
= _mv88e6xxx_vtu_getnext(chip
, entry
);
1755 if (entry
->vid
!= vid
|| !entry
->valid
) {
1758 /* -ENOENT would've been more appropriate, but switchdev expects
1759 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1762 err
= _mv88e6xxx_vtu_new(chip
, vid
, entry
);
1768 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch
*ds
, int port
,
1769 u16 vid_begin
, u16 vid_end
)
1771 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1772 struct mv88e6xxx_vtu_stu_entry vlan
;
1778 mutex_lock(&chip
->reg_lock
);
1780 err
= _mv88e6xxx_vtu_vid_write(chip
, vid_begin
- 1);
1785 err
= _mv88e6xxx_vtu_getnext(chip
, &vlan
);
1792 if (vlan
.vid
> vid_end
)
1795 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1796 if (dsa_is_dsa_port(ds
, i
) || dsa_is_cpu_port(ds
, i
))
1800 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1803 if (chip
->ports
[i
].bridge_dev
==
1804 chip
->ports
[port
].bridge_dev
)
1805 break; /* same bridge, check next VLAN */
1807 netdev_warn(ds
->ports
[port
].netdev
,
1808 "hardware VLAN %d already used by %s\n",
1810 netdev_name(chip
->ports
[i
].bridge_dev
));
1814 } while (vlan
.vid
< vid_end
);
1817 mutex_unlock(&chip
->reg_lock
);
1822 static const char * const mv88e6xxx_port_8021q_mode_names
[] = {
1823 [PORT_CONTROL_2_8021Q_DISABLED
] = "Disabled",
1824 [PORT_CONTROL_2_8021Q_FALLBACK
] = "Fallback",
1825 [PORT_CONTROL_2_8021Q_CHECK
] = "Check",
1826 [PORT_CONTROL_2_8021Q_SECURE
] = "Secure",
1829 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch
*ds
, int port
,
1830 bool vlan_filtering
)
1832 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1833 u16 old
, new = vlan_filtering
? PORT_CONTROL_2_8021Q_SECURE
:
1834 PORT_CONTROL_2_8021Q_DISABLED
;
1837 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1840 mutex_lock(&chip
->reg_lock
);
1842 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_CONTROL_2
);
1846 old
= ret
& PORT_CONTROL_2_8021Q_MASK
;
1849 ret
&= ~PORT_CONTROL_2_8021Q_MASK
;
1850 ret
|= new & PORT_CONTROL_2_8021Q_MASK
;
1852 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL_2
,
1857 netdev_dbg(ds
->ports
[port
].netdev
, "802.1Q Mode %s (was %s)\n",
1858 mv88e6xxx_port_8021q_mode_names
[new],
1859 mv88e6xxx_port_8021q_mode_names
[old
]);
1864 mutex_unlock(&chip
->reg_lock
);
1870 mv88e6xxx_port_vlan_prepare(struct dsa_switch
*ds
, int port
,
1871 const struct switchdev_obj_port_vlan
*vlan
,
1872 struct switchdev_trans
*trans
)
1874 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1877 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1880 /* If the requested port doesn't belong to the same bridge as the VLAN
1881 * members, do not support it (yet) and fallback to software VLAN.
1883 err
= mv88e6xxx_port_check_hw_vlan(ds
, port
, vlan
->vid_begin
,
1888 /* We don't need any dynamic resource from the kernel (yet),
1889 * so skip the prepare phase.
1894 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip
*chip
, int port
,
1895 u16 vid
, bool untagged
)
1897 struct mv88e6xxx_vtu_stu_entry vlan
;
1900 err
= _mv88e6xxx_vtu_get(chip
, vid
, &vlan
, true);
1904 vlan
.data
[port
] = untagged
?
1905 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED
:
1906 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED
;
1908 return _mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1911 static void mv88e6xxx_port_vlan_add(struct dsa_switch
*ds
, int port
,
1912 const struct switchdev_obj_port_vlan
*vlan
,
1913 struct switchdev_trans
*trans
)
1915 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1916 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1917 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1920 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1923 mutex_lock(&chip
->reg_lock
);
1925 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
)
1926 if (_mv88e6xxx_port_vlan_add(chip
, port
, vid
, untagged
))
1927 netdev_err(ds
->ports
[port
].netdev
,
1928 "failed to add VLAN %d%c\n",
1929 vid
, untagged
? 'u' : 't');
1931 if (pvid
&& _mv88e6xxx_port_pvid_set(chip
, port
, vlan
->vid_end
))
1932 netdev_err(ds
->ports
[port
].netdev
, "failed to set PVID %d\n",
1935 mutex_unlock(&chip
->reg_lock
);
1938 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip
*chip
,
1941 struct dsa_switch
*ds
= chip
->ds
;
1942 struct mv88e6xxx_vtu_stu_entry vlan
;
1945 err
= _mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
1949 /* Tell switchdev if this VLAN is handled in software */
1950 if (vlan
.data
[port
] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
)
1953 vlan
.data
[port
] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
;
1955 /* keep the VLAN unless all ports are excluded */
1957 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
1958 if (dsa_is_cpu_port(ds
, i
) || dsa_is_dsa_port(ds
, i
))
1961 if (vlan
.data
[i
] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER
) {
1967 err
= _mv88e6xxx_vtu_loadpurge(chip
, &vlan
);
1971 return _mv88e6xxx_atu_remove(chip
, vlan
.fid
, port
, false);
1974 static int mv88e6xxx_port_vlan_del(struct dsa_switch
*ds
, int port
,
1975 const struct switchdev_obj_port_vlan
*vlan
)
1977 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
1981 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_VTU
))
1984 mutex_lock(&chip
->reg_lock
);
1986 err
= _mv88e6xxx_port_pvid_get(chip
, port
, &pvid
);
1990 for (vid
= vlan
->vid_begin
; vid
<= vlan
->vid_end
; ++vid
) {
1991 err
= _mv88e6xxx_port_vlan_del(chip
, port
, vid
);
1996 err
= _mv88e6xxx_port_pvid_set(chip
, port
, 0);
2003 mutex_unlock(&chip
->reg_lock
);
2008 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip
*chip
,
2009 const unsigned char *addr
)
2013 for (i
= 0; i
< 3; i
++) {
2014 ret
= _mv88e6xxx_reg_write(
2015 chip
, REG_GLOBAL
, GLOBAL_ATU_MAC_01
+ i
,
2016 (addr
[i
* 2] << 8) | addr
[i
* 2 + 1]);
2024 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip
*chip
,
2025 unsigned char *addr
)
2029 for (i
= 0; i
< 3; i
++) {
2030 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
,
2031 GLOBAL_ATU_MAC_01
+ i
);
2034 addr
[i
* 2] = ret
>> 8;
2035 addr
[i
* 2 + 1] = ret
& 0xff;
2041 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip
*chip
,
2042 struct mv88e6xxx_atu_entry
*entry
)
2046 ret
= _mv88e6xxx_atu_wait(chip
);
2050 ret
= _mv88e6xxx_atu_mac_write(chip
, entry
->mac
);
2054 ret
= _mv88e6xxx_atu_data_write(chip
, entry
);
2058 return _mv88e6xxx_atu_cmd(chip
, entry
->fid
, GLOBAL_ATU_OP_LOAD_DB
);
2061 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip
*chip
, int port
,
2062 const unsigned char *addr
, u16 vid
,
2065 struct mv88e6xxx_atu_entry entry
= { 0 };
2066 struct mv88e6xxx_vtu_stu_entry vlan
;
2069 /* Null VLAN ID corresponds to the port private database */
2071 err
= _mv88e6xxx_port_fid_get(chip
, port
, &vlan
.fid
);
2073 err
= _mv88e6xxx_vtu_get(chip
, vid
, &vlan
, false);
2077 entry
.fid
= vlan
.fid
;
2078 entry
.state
= state
;
2079 ether_addr_copy(entry
.mac
, addr
);
2080 if (state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2081 entry
.trunk
= false;
2082 entry
.portv_trunkid
= BIT(port
);
2085 return _mv88e6xxx_atu_load(chip
, &entry
);
2088 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch
*ds
, int port
,
2089 const struct switchdev_obj_port_fdb
*fdb
,
2090 struct switchdev_trans
*trans
)
2092 /* We don't need any dynamic resource from the kernel (yet),
2093 * so skip the prepare phase.
2098 static void mv88e6xxx_port_fdb_add(struct dsa_switch
*ds
, int port
,
2099 const struct switchdev_obj_port_fdb
*fdb
,
2100 struct switchdev_trans
*trans
)
2102 int state
= is_multicast_ether_addr(fdb
->addr
) ?
2103 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
2104 GLOBAL_ATU_DATA_STATE_UC_STATIC
;
2105 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
2107 mutex_lock(&chip
->reg_lock
);
2108 if (_mv88e6xxx_port_fdb_load(chip
, port
, fdb
->addr
, fdb
->vid
, state
))
2109 netdev_err(ds
->ports
[port
].netdev
,
2110 "failed to load MAC address\n");
2111 mutex_unlock(&chip
->reg_lock
);
2114 static int mv88e6xxx_port_fdb_del(struct dsa_switch
*ds
, int port
,
2115 const struct switchdev_obj_port_fdb
*fdb
)
2117 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
2120 mutex_lock(&chip
->reg_lock
);
2121 ret
= _mv88e6xxx_port_fdb_load(chip
, port
, fdb
->addr
, fdb
->vid
,
2122 GLOBAL_ATU_DATA_STATE_UNUSED
);
2123 mutex_unlock(&chip
->reg_lock
);
2128 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip
*chip
, u16 fid
,
2129 struct mv88e6xxx_atu_entry
*entry
)
2131 struct mv88e6xxx_atu_entry next
= { 0 };
2136 ret
= _mv88e6xxx_atu_wait(chip
);
2140 ret
= _mv88e6xxx_atu_cmd(chip
, fid
, GLOBAL_ATU_OP_GET_NEXT_DB
);
2144 ret
= _mv88e6xxx_atu_mac_read(chip
, next
.mac
);
2148 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, GLOBAL_ATU_DATA
);
2152 next
.state
= ret
& GLOBAL_ATU_DATA_STATE_MASK
;
2153 if (next
.state
!= GLOBAL_ATU_DATA_STATE_UNUSED
) {
2154 unsigned int mask
, shift
;
2156 if (ret
& GLOBAL_ATU_DATA_TRUNK
) {
2158 mask
= GLOBAL_ATU_DATA_TRUNK_ID_MASK
;
2159 shift
= GLOBAL_ATU_DATA_TRUNK_ID_SHIFT
;
2162 mask
= GLOBAL_ATU_DATA_PORT_VECTOR_MASK
;
2163 shift
= GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
;
2166 next
.portv_trunkid
= (ret
& mask
) >> shift
;
2173 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip
*chip
,
2174 u16 fid
, u16 vid
, int port
,
2175 struct switchdev_obj_port_fdb
*fdb
,
2176 int (*cb
)(struct switchdev_obj
*obj
))
2178 struct mv88e6xxx_atu_entry addr
= {
2179 .mac
= { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2183 err
= _mv88e6xxx_atu_mac_write(chip
, addr
.mac
);
2188 err
= _mv88e6xxx_atu_getnext(chip
, fid
, &addr
);
2192 if (addr
.state
== GLOBAL_ATU_DATA_STATE_UNUSED
)
2195 if (!addr
.trunk
&& addr
.portv_trunkid
& BIT(port
)) {
2196 bool is_static
= addr
.state
==
2197 (is_multicast_ether_addr(addr
.mac
) ?
2198 GLOBAL_ATU_DATA_STATE_MC_STATIC
:
2199 GLOBAL_ATU_DATA_STATE_UC_STATIC
);
2202 ether_addr_copy(fdb
->addr
, addr
.mac
);
2203 fdb
->ndm_state
= is_static
? NUD_NOARP
: NUD_REACHABLE
;
2205 err
= cb(&fdb
->obj
);
2209 } while (!is_broadcast_ether_addr(addr
.mac
));
2214 static int mv88e6xxx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
2215 struct switchdev_obj_port_fdb
*fdb
,
2216 int (*cb
)(struct switchdev_obj
*obj
))
2218 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
2219 struct mv88e6xxx_vtu_stu_entry vlan
= {
2220 .vid
= GLOBAL_VTU_VID_MASK
, /* all ones */
2225 mutex_lock(&chip
->reg_lock
);
2227 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2228 err
= _mv88e6xxx_port_fid_get(chip
, port
, &fid
);
2232 err
= _mv88e6xxx_port_fdb_dump_one(chip
, fid
, 0, port
, fdb
, cb
);
2236 /* Dump VLANs' Filtering Information Databases */
2237 err
= _mv88e6xxx_vtu_vid_write(chip
, vlan
.vid
);
2242 err
= _mv88e6xxx_vtu_getnext(chip
, &vlan
);
2249 err
= _mv88e6xxx_port_fdb_dump_one(chip
, vlan
.fid
, vlan
.vid
,
2253 } while (vlan
.vid
< GLOBAL_VTU_VID_MASK
);
2256 mutex_unlock(&chip
->reg_lock
);
2261 static int mv88e6xxx_port_bridge_join(struct dsa_switch
*ds
, int port
,
2262 struct net_device
*bridge
)
2264 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
2267 mutex_lock(&chip
->reg_lock
);
2269 /* Assign the bridge and remap each port's VLANTable */
2270 chip
->ports
[port
].bridge_dev
= bridge
;
2272 for (i
= 0; i
< chip
->info
->num_ports
; ++i
) {
2273 if (chip
->ports
[i
].bridge_dev
== bridge
) {
2274 err
= _mv88e6xxx_port_based_vlan_map(chip
, i
);
2280 mutex_unlock(&chip
->reg_lock
);
2285 static void mv88e6xxx_port_bridge_leave(struct dsa_switch
*ds
, int port
)
2287 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
2288 struct net_device
*bridge
= chip
->ports
[port
].bridge_dev
;
2291 mutex_lock(&chip
->reg_lock
);
2293 /* Unassign the bridge and remap each port's VLANTable */
2294 chip
->ports
[port
].bridge_dev
= NULL
;
2296 for (i
= 0; i
< chip
->info
->num_ports
; ++i
)
2297 if (i
== port
|| chip
->ports
[i
].bridge_dev
== bridge
)
2298 if (_mv88e6xxx_port_based_vlan_map(chip
, i
))
2299 netdev_warn(ds
->ports
[i
].netdev
,
2300 "failed to remap\n");
2302 mutex_unlock(&chip
->reg_lock
);
2305 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip
*chip
,
2306 int port
, int page
, int reg
, int val
)
2310 ret
= mv88e6xxx_mdio_write_indirect(chip
, port
, 0x16, page
);
2312 goto restore_page_0
;
2314 ret
= mv88e6xxx_mdio_write_indirect(chip
, port
, reg
, val
);
2316 mv88e6xxx_mdio_write_indirect(chip
, port
, 0x16, 0x0);
2321 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip
*chip
,
2322 int port
, int page
, int reg
)
2326 ret
= mv88e6xxx_mdio_write_indirect(chip
, port
, 0x16, page
);
2328 goto restore_page_0
;
2330 ret
= mv88e6xxx_mdio_read_indirect(chip
, port
, reg
);
2332 mv88e6xxx_mdio_write_indirect(chip
, port
, 0x16, 0x0);
2337 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip
*chip
)
2339 bool ppu_active
= mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU_ACTIVE
);
2340 u16 is_reset
= (ppu_active
? 0x8800 : 0xc800);
2341 struct gpio_desc
*gpiod
= chip
->reset
;
2342 unsigned long timeout
;
2346 /* Set all ports to the disabled state. */
2347 for (i
= 0; i
< chip
->info
->num_ports
; i
++) {
2348 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(i
), PORT_CONTROL
);
2352 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(i
), PORT_CONTROL
,
2358 /* Wait for transmit queues to drain. */
2359 usleep_range(2000, 4000);
2361 /* If there is a gpio connected to the reset pin, toggle it */
2363 gpiod_set_value_cansleep(gpiod
, 1);
2364 usleep_range(10000, 20000);
2365 gpiod_set_value_cansleep(gpiod
, 0);
2366 usleep_range(10000, 20000);
2369 /* Reset the switch. Keep the PPU active if requested. The PPU
2370 * needs to be active to support indirect phy register access
2371 * through global registers 0x18 and 0x19.
2374 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, 0x04, 0xc000);
2376 ret
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, 0x04, 0xc400);
2380 /* Wait up to one second for reset to complete. */
2381 timeout
= jiffies
+ 1 * HZ
;
2382 while (time_before(jiffies
, timeout
)) {
2383 ret
= _mv88e6xxx_reg_read(chip
, REG_GLOBAL
, 0x00);
2387 if ((ret
& is_reset
) == is_reset
)
2389 usleep_range(1000, 2000);
2391 if (time_after(jiffies
, timeout
))
2399 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip
*chip
)
2403 ret
= _mv88e6xxx_mdio_page_read(chip
, REG_FIBER_SERDES
,
2404 PAGE_FIBER_SERDES
, MII_BMCR
);
2408 if (ret
& BMCR_PDOWN
) {
2410 ret
= _mv88e6xxx_mdio_page_write(chip
, REG_FIBER_SERDES
,
2411 PAGE_FIBER_SERDES
, MII_BMCR
,
2418 static int mv88e6xxx_port_read(struct mv88e6xxx_chip
*chip
, int port
,
2421 int addr
= chip
->info
->port_base_addr
+ port
;
2423 if (port
>= chip
->info
->num_ports
)
2426 return mv88e6xxx_read(chip
, addr
, reg
, val
);
2429 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip
, int port
)
2431 struct dsa_switch
*ds
= chip
->ds
;
2435 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2436 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2437 mv88e6xxx_6185_family(chip
) || mv88e6xxx_6095_family(chip
) ||
2438 mv88e6xxx_6065_family(chip
) || mv88e6xxx_6320_family(chip
)) {
2439 /* MAC Forcing register: don't force link, speed,
2440 * duplex or flow control state to any particular
2441 * values on physical ports, but force the CPU port
2442 * and all DSA ports to their maximum bandwidth and
2445 reg
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_PCS_CTRL
);
2446 if (dsa_is_cpu_port(ds
, port
) || dsa_is_dsa_port(ds
, port
)) {
2447 reg
&= ~PORT_PCS_CTRL_UNFORCED
;
2448 reg
|= PORT_PCS_CTRL_FORCE_LINK
|
2449 PORT_PCS_CTRL_LINK_UP
|
2450 PORT_PCS_CTRL_DUPLEX_FULL
|
2451 PORT_PCS_CTRL_FORCE_DUPLEX
;
2452 if (mv88e6xxx_6065_family(chip
))
2453 reg
|= PORT_PCS_CTRL_100
;
2455 reg
|= PORT_PCS_CTRL_1000
;
2457 reg
|= PORT_PCS_CTRL_UNFORCED
;
2460 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2461 PORT_PCS_CTRL
, reg
);
2466 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2467 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2468 * tunneling, determine priority by looking at 802.1p and IP
2469 * priority fields (IP prio has precedence), and set STP state
2472 * If this is the CPU link, use DSA or EDSA tagging depending
2473 * on which tagging mode was configured.
2475 * If this is a link to another switch, use DSA tagging mode.
2477 * If this is the upstream port for this switch, enable
2478 * forwarding of unknown unicasts and multicasts.
2481 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2482 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2483 mv88e6xxx_6095_family(chip
) || mv88e6xxx_6065_family(chip
) ||
2484 mv88e6xxx_6185_family(chip
) || mv88e6xxx_6320_family(chip
))
2485 reg
= PORT_CONTROL_IGMP_MLD_SNOOP
|
2486 PORT_CONTROL_USE_TAG
| PORT_CONTROL_USE_IP
|
2487 PORT_CONTROL_STATE_FORWARDING
;
2488 if (dsa_is_cpu_port(ds
, port
)) {
2489 if (mv88e6xxx_6095_family(chip
) || mv88e6xxx_6185_family(chip
))
2490 reg
|= PORT_CONTROL_DSA_TAG
;
2491 if (mv88e6xxx_6352_family(chip
) ||
2492 mv88e6xxx_6351_family(chip
) ||
2493 mv88e6xxx_6165_family(chip
) ||
2494 mv88e6xxx_6097_family(chip
) ||
2495 mv88e6xxx_6320_family(chip
)) {
2496 reg
|= PORT_CONTROL_FRAME_ETHER_TYPE_DSA
|
2497 PORT_CONTROL_FORWARD_UNKNOWN
|
2498 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2501 if (mv88e6xxx_6352_family(chip
) ||
2502 mv88e6xxx_6351_family(chip
) ||
2503 mv88e6xxx_6165_family(chip
) ||
2504 mv88e6xxx_6097_family(chip
) ||
2505 mv88e6xxx_6095_family(chip
) ||
2506 mv88e6xxx_6065_family(chip
) ||
2507 mv88e6xxx_6185_family(chip
) ||
2508 mv88e6xxx_6320_family(chip
)) {
2509 reg
|= PORT_CONTROL_EGRESS_ADD_TAG
;
2512 if (dsa_is_dsa_port(ds
, port
)) {
2513 if (mv88e6xxx_6095_family(chip
) ||
2514 mv88e6xxx_6185_family(chip
))
2515 reg
|= PORT_CONTROL_DSA_TAG
;
2516 if (mv88e6xxx_6352_family(chip
) ||
2517 mv88e6xxx_6351_family(chip
) ||
2518 mv88e6xxx_6165_family(chip
) ||
2519 mv88e6xxx_6097_family(chip
) ||
2520 mv88e6xxx_6320_family(chip
)) {
2521 reg
|= PORT_CONTROL_FRAME_MODE_DSA
;
2524 if (port
== dsa_upstream_port(ds
))
2525 reg
|= PORT_CONTROL_FORWARD_UNKNOWN
|
2526 PORT_CONTROL_FORWARD_UNKNOWN_MC
;
2529 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2535 /* If this port is connected to a SerDes, make sure the SerDes is not
2538 if (mv88e6xxx_6352_family(chip
)) {
2539 ret
= _mv88e6xxx_reg_read(chip
, REG_PORT(port
), PORT_STATUS
);
2542 ret
&= PORT_STATUS_CMODE_MASK
;
2543 if ((ret
== PORT_STATUS_CMODE_100BASE_X
) ||
2544 (ret
== PORT_STATUS_CMODE_1000BASE_X
) ||
2545 (ret
== PORT_STATUS_CMODE_SGMII
)) {
2546 ret
= mv88e6xxx_power_on_serdes(chip
);
2552 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2553 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2554 * untagged frames on this port, do a destination address lookup on all
2555 * received packets as usual, disable ARP mirroring and don't send a
2556 * copy of all transmitted/received frames on this port to the CPU.
2559 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2560 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2561 mv88e6xxx_6095_family(chip
) || mv88e6xxx_6320_family(chip
) ||
2562 mv88e6xxx_6185_family(chip
))
2563 reg
= PORT_CONTROL_2_MAP_DA
;
2565 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2566 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6320_family(chip
))
2567 reg
|= PORT_CONTROL_2_JUMBO_10240
;
2569 if (mv88e6xxx_6095_family(chip
) || mv88e6xxx_6185_family(chip
)) {
2570 /* Set the upstream port this port should use */
2571 reg
|= dsa_upstream_port(ds
);
2572 /* enable forwarding of unknown multicast addresses to
2575 if (port
== dsa_upstream_port(ds
))
2576 reg
|= PORT_CONTROL_2_FORWARD_UNKNOWN
;
2579 reg
|= PORT_CONTROL_2_8021Q_DISABLED
;
2582 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2583 PORT_CONTROL_2
, reg
);
2588 /* Port Association Vector: when learning source addresses
2589 * of packets, add the address to the address database using
2590 * a port bitmap that has only the bit for this port set and
2591 * the other bits clear.
2594 /* Disable learning for CPU port */
2595 if (dsa_is_cpu_port(ds
, port
))
2598 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_ASSOC_VECTOR
,
2603 /* Egress rate control 2: disable egress rate control. */
2604 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_RATE_CONTROL_2
,
2609 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2610 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2611 mv88e6xxx_6320_family(chip
)) {
2612 /* Do not limit the period of time that this port can
2613 * be paused for by the remote end or the period of
2614 * time that this port can pause the remote end.
2616 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2617 PORT_PAUSE_CTRL
, 0x0000);
2621 /* Port ATU control: disable limiting the number of
2622 * address database entries that this port is allowed
2625 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2626 PORT_ATU_CONTROL
, 0x0000);
2627 /* Priority Override: disable DA, SA and VTU priority
2630 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2631 PORT_PRI_OVERRIDE
, 0x0000);
2635 /* Port Ethertype: use the Ethertype DSA Ethertype
2638 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2639 PORT_ETH_TYPE
, ETH_P_EDSA
);
2642 /* Tag Remap: use an identity 802.1p prio -> switch
2645 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2646 PORT_TAG_REGMAP_0123
, 0x3210);
2650 /* Tag Remap 2: use an identity 802.1p prio -> switch
2653 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2654 PORT_TAG_REGMAP_4567
, 0x7654);
2659 if (mv88e6xxx_6352_family(chip
) || mv88e6xxx_6351_family(chip
) ||
2660 mv88e6xxx_6165_family(chip
) || mv88e6xxx_6097_family(chip
) ||
2661 mv88e6xxx_6185_family(chip
) || mv88e6xxx_6095_family(chip
) ||
2662 mv88e6xxx_6320_family(chip
)) {
2663 /* Rate Control: disable ingress rate limiting. */
2664 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
),
2665 PORT_RATE_CONTROL
, 0x0001);
2670 /* Port Control 1: disable trunking, disable sending
2671 * learning messages to this port.
2673 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_CONTROL_1
,
2678 /* Port based VLAN map: give each port the same default address
2679 * database, and allow bidirectional communication between the
2680 * CPU and DSA port(s), and the other ports.
2682 ret
= _mv88e6xxx_port_fid_set(chip
, port
, 0);
2686 ret
= _mv88e6xxx_port_based_vlan_map(chip
, port
);
2690 /* Default VLAN ID and priority: don't set a default VLAN
2691 * ID, and set the default packet priority to zero.
2693 ret
= _mv88e6xxx_reg_write(chip
, REG_PORT(port
), PORT_DEFAULT_VLAN
,
2701 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip
*chip
, u8
*addr
)
2705 err
= mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_MAC_01
,
2706 (addr
[0] << 8) | addr
[1]);
2710 err
= mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_MAC_23
,
2711 (addr
[2] << 8) | addr
[3]);
2715 return mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_MAC_45
,
2716 (addr
[4] << 8) | addr
[5]);
2719 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip
*chip
,
2722 const unsigned int coeff
= chip
->info
->age_time_coeff
;
2723 const unsigned int min
= 0x01 * coeff
;
2724 const unsigned int max
= 0xff * coeff
;
2729 if (msecs
< min
|| msecs
> max
)
2732 /* Round to nearest multiple of coeff */
2733 age_time
= (msecs
+ coeff
/ 2) / coeff
;
2735 err
= mv88e6xxx_read(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
, &val
);
2739 /* AgeTime is 11:4 bits */
2741 val
|= age_time
<< 4;
2743 return mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
, val
);
2746 static int mv88e6xxx_set_ageing_time(struct dsa_switch
*ds
,
2747 unsigned int ageing_time
)
2749 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
2752 mutex_lock(&chip
->reg_lock
);
2753 err
= mv88e6xxx_g1_set_age_time(chip
, ageing_time
);
2754 mutex_unlock(&chip
->reg_lock
);
2759 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip
*chip
)
2761 struct dsa_switch
*ds
= chip
->ds
;
2762 u32 upstream_port
= dsa_upstream_port(ds
);
2766 /* Enable the PHY Polling Unit if present, don't discard any packets,
2767 * and mask all interrupt sources.
2770 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
) ||
2771 mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU_ACTIVE
))
2772 reg
|= GLOBAL_CONTROL_PPU_ENABLE
;
2774 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL
, reg
);
2778 /* Configure the upstream port, and configure it as the port to which
2779 * ingress and egress and ARP monitor frames are to be sent.
2781 reg
= upstream_port
<< GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT
|
2782 upstream_port
<< GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT
|
2783 upstream_port
<< GLOBAL_MONITOR_CONTROL_ARP_SHIFT
;
2784 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_MONITOR_CONTROL
,
2789 /* Disable remote management, and set the switch's DSA device number. */
2790 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_CONTROL_2
,
2791 GLOBAL_CONTROL_2_MULTIPLE_CASCADE
|
2792 (ds
->index
& 0x1f));
2796 /* Clear all the VTU and STU entries */
2797 err
= _mv88e6xxx_vtu_stu_flush(chip
);
2801 /* Set the default address aging time to 5 minutes, and
2802 * enable address learn messages to be sent to all message
2805 err
= mv88e6xxx_write(chip
, REG_GLOBAL
, GLOBAL_ATU_CONTROL
,
2806 GLOBAL_ATU_CONTROL_LEARN2ALL
);
2810 err
= mv88e6xxx_g1_set_age_time(chip
, 300000);
2814 /* Clear all ATU entries */
2815 err
= _mv88e6xxx_atu_flush(chip
, 0, true);
2819 /* Configure the IP ToS mapping registers. */
2820 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_0
, 0x0000);
2823 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_1
, 0x0000);
2826 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_2
, 0x5555);
2829 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_3
, 0x5555);
2832 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_4
, 0xaaaa);
2835 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_5
, 0xaaaa);
2838 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_6
, 0xffff);
2841 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IP_PRI_7
, 0xffff);
2845 /* Configure the IEEE 802.1p priority mapping register. */
2846 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_IEEE_PRI
, 0xfa41);
2850 /* Clear the statistics counters for all ports */
2851 err
= _mv88e6xxx_reg_write(chip
, REG_GLOBAL
, GLOBAL_STATS_OP
,
2852 GLOBAL_STATS_OP_FLUSH_ALL
);
2856 /* Wait for the flush to complete. */
2857 err
= _mv88e6xxx_stats_wait(chip
);
2864 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip
*chip
,
2865 int target
, int port
)
2867 u16 val
= (target
<< 8) | (port
& 0xf);
2869 return mv88e6xxx_update(chip
, REG_GLOBAL2
, GLOBAL2_DEVICE_MAPPING
, val
);
2872 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip
*chip
)
2877 /* Initialize the routing port to the 32 possible target devices */
2878 for (target
= 0; target
< 32; ++target
) {
2881 if (target
< DSA_MAX_SWITCHES
) {
2882 port
= chip
->ds
->rtable
[target
];
2883 if (port
== DSA_RTABLE_NONE
)
2887 err
= mv88e6xxx_g2_device_mapping_write(chip
, target
, port
);
2895 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip
*chip
, int num
,
2896 bool hask
, u16 mask
)
2898 const u16 port_mask
= BIT(chip
->info
->num_ports
) - 1;
2899 u16 val
= (num
<< 12) | (mask
& port_mask
);
2902 val
|= GLOBAL2_TRUNK_MASK_HASK
;
2904 return mv88e6xxx_update(chip
, REG_GLOBAL2
, GLOBAL2_TRUNK_MASK
, val
);
2907 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip
*chip
, int id
,
2910 const u16 port_mask
= BIT(chip
->info
->num_ports
) - 1;
2911 u16 val
= (id
<< 11) | (map
& port_mask
);
2913 return mv88e6xxx_update(chip
, REG_GLOBAL2
, GLOBAL2_TRUNK_MAPPING
, val
);
2916 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip
*chip
)
2918 const u16 port_mask
= BIT(chip
->info
->num_ports
) - 1;
2921 /* Clear all eight possible Trunk Mask vectors */
2922 for (i
= 0; i
< 8; ++i
) {
2923 err
= mv88e6xxx_g2_trunk_mask_write(chip
, i
, false, port_mask
);
2928 /* Clear all sixteen possible Trunk ID routing vectors */
2929 for (i
= 0; i
< 16; ++i
) {
2930 err
= mv88e6xxx_g2_trunk_mapping_write(chip
, i
, 0);
2938 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip
*chip
)
2942 /* Init all Ingress Rate Limit resources of all ports */
2943 for (port
= 0; port
< chip
->info
->num_ports
; ++port
) {
2944 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2945 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_IRL_CMD
,
2946 GLOBAL2_IRL_CMD_OP_INIT_ALL
|
2951 /* Wait for the operation to complete */
2952 err
= _mv88e6xxx_wait(chip
, REG_GLOBAL2
, GLOBAL2_IRL_CMD
,
2953 GLOBAL2_IRL_CMD_BUSY
);
2961 /* Indirect write to the Switch MAC/WoL/WoF register */
2962 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip
*chip
,
2963 unsigned int pointer
, u8 data
)
2965 u16 val
= (pointer
<< 8) | data
;
2967 return mv88e6xxx_update(chip
, REG_GLOBAL2
, GLOBAL2_SWITCH_MAC
, val
);
2970 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip
*chip
, u8
*addr
)
2974 for (i
= 0; i
< 6; i
++) {
2975 err
= mv88e6xxx_g2_switch_mac_write(chip
, i
, addr
[i
]);
2983 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip
*chip
, int pointer
,
2986 u16 val
= (pointer
<< 8) | (data
& 0x7);
2988 return mv88e6xxx_update(chip
, REG_GLOBAL2
, GLOBAL2_PRIO_OVERRIDE
, val
);
2991 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip
*chip
)
2995 /* Clear all sixteen possible Priority Override entries */
2996 for (i
= 0; i
< 16; i
++) {
2997 err
= mv88e6xxx_g2_pot_write(chip
, i
, 0);
3005 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip
*chip
)
3007 return _mv88e6xxx_wait(chip
, REG_GLOBAL2
, GLOBAL2_EEPROM_CMD
,
3008 GLOBAL2_EEPROM_CMD_BUSY
|
3009 GLOBAL2_EEPROM_CMD_RUNNING
);
3012 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip
*chip
, u16 cmd
)
3016 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_EEPROM_CMD
, cmd
);
3020 return mv88e6xxx_g2_eeprom_wait(chip
);
3023 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip
*chip
,
3026 u16 cmd
= GLOBAL2_EEPROM_CMD_OP_READ
| addr
;
3029 err
= mv88e6xxx_g2_eeprom_wait(chip
);
3033 err
= mv88e6xxx_g2_eeprom_cmd(chip
, cmd
);
3037 return mv88e6xxx_read(chip
, REG_GLOBAL2
, GLOBAL2_EEPROM_DATA
, data
);
3040 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip
*chip
,
3043 u16 cmd
= GLOBAL2_EEPROM_CMD_OP_WRITE
| addr
;
3046 err
= mv88e6xxx_g2_eeprom_wait(chip
);
3050 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_EEPROM_DATA
, data
);
3054 return mv88e6xxx_g2_eeprom_cmd(chip
, cmd
);
3057 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip
*chip
)
3062 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_MGMT_EN_2X
)) {
3063 /* Consider the frames with reserved multicast destination
3064 * addresses matching 01:80:c2:00:00:2x as MGMT.
3066 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_MGMT_EN_2X
,
3072 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_MGMT_EN_0X
)) {
3073 /* Consider the frames with reserved multicast destination
3074 * addresses matching 01:80:c2:00:00:0x as MGMT.
3076 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_MGMT_EN_0X
,
3082 /* Ignore removed tag data on doubly tagged packets, disable
3083 * flow control messages, force flow control priority to the
3084 * highest, and send all special multicast frames to the CPU
3085 * port at the highest priority.
3087 reg
= GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI
| (0x7 << 4);
3088 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_MGMT_EN_0X
) ||
3089 mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_MGMT_EN_2X
))
3090 reg
|= GLOBAL2_SWITCH_MGMT_RSVD2CPU
| 0x7;
3091 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_SWITCH_MGMT
, reg
);
3095 /* Program the DSA routing table. */
3096 err
= mv88e6xxx_g2_set_device_mapping(chip
);
3100 /* Clear all trunk masks and mapping. */
3101 err
= mv88e6xxx_g2_clear_trunk(chip
);
3105 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_IRL
)) {
3106 /* Disable ingress rate limiting by resetting all per port
3107 * ingress rate limit resources to their initial state.
3109 err
= mv88e6xxx_g2_clear_irl(chip
);
3114 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_PVT
)) {
3115 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3116 err
= mv88e6xxx_write(chip
, REG_GLOBAL2
, GLOBAL2_PVT_ADDR
,
3117 GLOBAL2_PVT_ADDR_OP_INIT_ONES
);
3122 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_POT
)) {
3123 /* Clear the priority override table. */
3124 err
= mv88e6xxx_g2_clear_pot(chip
);
3132 static int mv88e6xxx_setup(struct dsa_switch
*ds
)
3134 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3139 ds
->slave_mii_bus
= chip
->mdio_bus
;
3141 mutex_lock(&chip
->reg_lock
);
3143 err
= mv88e6xxx_switch_reset(chip
);
3147 /* Setup Switch Port Registers */
3148 for (i
= 0; i
< chip
->info
->num_ports
; i
++) {
3149 err
= mv88e6xxx_setup_port(chip
, i
);
3154 /* Setup Switch Global 1 Registers */
3155 err
= mv88e6xxx_g1_setup(chip
);
3159 /* Setup Switch Global 2 Registers */
3160 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_GLOBAL2
)) {
3161 err
= mv88e6xxx_g2_setup(chip
);
3167 mutex_unlock(&chip
->reg_lock
);
3172 static int mv88e6xxx_set_addr(struct dsa_switch
*ds
, u8
*addr
)
3174 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3177 mutex_lock(&chip
->reg_lock
);
3179 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3180 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_G2_SWITCH_MAC
))
3181 err
= mv88e6xxx_g2_set_switch_mac(chip
, addr
);
3183 err
= mv88e6xxx_g1_set_switch_mac(chip
, addr
);
3185 mutex_unlock(&chip
->reg_lock
);
3190 #ifdef CONFIG_NET_DSA_HWMON
3191 static int mv88e6xxx_mdio_page_read(struct dsa_switch
*ds
, int port
, int page
,
3194 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3197 mutex_lock(&chip
->reg_lock
);
3198 ret
= _mv88e6xxx_mdio_page_read(chip
, port
, page
, reg
);
3199 mutex_unlock(&chip
->reg_lock
);
3204 static int mv88e6xxx_mdio_page_write(struct dsa_switch
*ds
, int port
, int page
,
3207 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3210 mutex_lock(&chip
->reg_lock
);
3211 ret
= _mv88e6xxx_mdio_page_write(chip
, port
, page
, reg
, val
);
3212 mutex_unlock(&chip
->reg_lock
);
3218 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip
*chip
, int port
)
3220 if (port
>= 0 && port
< chip
->info
->num_ports
)
3225 static int mv88e6xxx_mdio_read(struct mii_bus
*bus
, int port
, int regnum
)
3227 struct mv88e6xxx_chip
*chip
= bus
->priv
;
3228 int addr
= mv88e6xxx_port_to_mdio_addr(chip
, port
);
3234 mutex_lock(&chip
->reg_lock
);
3236 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
))
3237 ret
= mv88e6xxx_mdio_read_ppu(chip
, addr
, regnum
);
3238 else if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_SMI_PHY
))
3239 ret
= mv88e6xxx_mdio_read_indirect(chip
, addr
, regnum
);
3241 ret
= mv88e6xxx_mdio_read_direct(chip
, addr
, regnum
);
3243 mutex_unlock(&chip
->reg_lock
);
3247 static int mv88e6xxx_mdio_write(struct mii_bus
*bus
, int port
, int regnum
,
3250 struct mv88e6xxx_chip
*chip
= bus
->priv
;
3251 int addr
= mv88e6xxx_port_to_mdio_addr(chip
, port
);
3257 mutex_lock(&chip
->reg_lock
);
3259 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
))
3260 ret
= mv88e6xxx_mdio_write_ppu(chip
, addr
, regnum
, val
);
3261 else if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_SMI_PHY
))
3262 ret
= mv88e6xxx_mdio_write_indirect(chip
, addr
, regnum
, val
);
3264 ret
= mv88e6xxx_mdio_write_direct(chip
, addr
, regnum
, val
);
3266 mutex_unlock(&chip
->reg_lock
);
3270 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip
*chip
,
3271 struct device_node
*np
)
3274 struct mii_bus
*bus
;
3277 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_PPU
))
3278 mv88e6xxx_ppu_state_init(chip
);
3281 chip
->mdio_np
= of_get_child_by_name(np
, "mdio");
3283 bus
= devm_mdiobus_alloc(chip
->dev
);
3287 bus
->priv
= (void *)chip
;
3289 bus
->name
= np
->full_name
;
3290 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s", np
->full_name
);
3292 bus
->name
= "mv88e6xxx SMI";
3293 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "mv88e6xxx-%d", index
++);
3296 bus
->read
= mv88e6xxx_mdio_read
;
3297 bus
->write
= mv88e6xxx_mdio_write
;
3298 bus
->parent
= chip
->dev
;
3301 err
= of_mdiobus_register(bus
, chip
->mdio_np
);
3303 err
= mdiobus_register(bus
);
3305 dev_err(chip
->dev
, "Cannot register MDIO bus (%d)\n", err
);
3308 chip
->mdio_bus
= bus
;
3314 of_node_put(chip
->mdio_np
);
3319 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip
*chip
)
3322 struct mii_bus
*bus
= chip
->mdio_bus
;
3324 mdiobus_unregister(bus
);
3327 of_node_put(chip
->mdio_np
);
3330 #ifdef CONFIG_NET_DSA_HWMON
3332 static int mv88e61xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3334 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3340 mutex_lock(&chip
->reg_lock
);
3342 ret
= mv88e6xxx_mdio_write_direct(chip
, 0x0, 0x16, 0x6);
3346 /* Enable temperature sensor */
3347 ret
= mv88e6xxx_mdio_read_direct(chip
, 0x0, 0x1a);
3351 ret
= mv88e6xxx_mdio_write_direct(chip
, 0x0, 0x1a, ret
| (1 << 5));
3355 /* Wait for temperature to stabilize */
3356 usleep_range(10000, 12000);
3358 val
= mv88e6xxx_mdio_read_direct(chip
, 0x0, 0x1a);
3364 /* Disable temperature sensor */
3365 ret
= mv88e6xxx_mdio_write_direct(chip
, 0x0, 0x1a, ret
& ~(1 << 5));
3369 *temp
= ((val
& 0x1f) - 5) * 5;
3372 mv88e6xxx_mdio_write_direct(chip
, 0x0, 0x16, 0x0);
3373 mutex_unlock(&chip
->reg_lock
);
3377 static int mv88e63xx_get_temp(struct dsa_switch
*ds
, int *temp
)
3379 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3380 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3385 ret
= mv88e6xxx_mdio_page_read(ds
, phy
, 6, 27);
3389 *temp
= (ret
& 0xff) - 25;
3394 static int mv88e6xxx_get_temp(struct dsa_switch
*ds
, int *temp
)
3396 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3398 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP
))
3401 if (mv88e6xxx_6320_family(chip
) || mv88e6xxx_6352_family(chip
))
3402 return mv88e63xx_get_temp(ds
, temp
);
3404 return mv88e61xx_get_temp(ds
, temp
);
3407 static int mv88e6xxx_get_temp_limit(struct dsa_switch
*ds
, int *temp
)
3409 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3410 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3413 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3418 ret
= mv88e6xxx_mdio_page_read(ds
, phy
, 6, 26);
3422 *temp
= (((ret
>> 8) & 0x1f) * 5) - 25;
3427 static int mv88e6xxx_set_temp_limit(struct dsa_switch
*ds
, int temp
)
3429 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3430 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3433 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3436 ret
= mv88e6xxx_mdio_page_read(ds
, phy
, 6, 26);
3439 temp
= clamp_val(DIV_ROUND_CLOSEST(temp
, 5) + 5, 0, 0x1f);
3440 return mv88e6xxx_mdio_page_write(ds
, phy
, 6, 26,
3441 (ret
& 0xe0ff) | (temp
<< 8));
3444 static int mv88e6xxx_get_temp_alarm(struct dsa_switch
*ds
, bool *alarm
)
3446 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3447 int phy
= mv88e6xxx_6320_family(chip
) ? 3 : 0;
3450 if (!mv88e6xxx_has(chip
, MV88E6XXX_FLAG_TEMP_LIMIT
))
3455 ret
= mv88e6xxx_mdio_page_read(ds
, phy
, 6, 26);
3459 *alarm
= !!(ret
& 0x40);
3463 #endif /* CONFIG_NET_DSA_HWMON */
3465 static int mv88e6xxx_get_eeprom_len(struct dsa_switch
*ds
)
3467 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3469 return chip
->eeprom_len
;
3472 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip
*chip
,
3473 struct ethtool_eeprom
*eeprom
, u8
*data
)
3475 unsigned int offset
= eeprom
->offset
;
3476 unsigned int len
= eeprom
->len
;
3483 err
= mv88e6xxx_g2_eeprom_read16(chip
, offset
>> 1, &val
);
3487 *data
++ = (val
>> 8) & 0xff;
3495 err
= mv88e6xxx_g2_eeprom_read16(chip
, offset
>> 1, &val
);
3499 *data
++ = val
& 0xff;
3500 *data
++ = (val
>> 8) & 0xff;
3508 err
= mv88e6xxx_g2_eeprom_read16(chip
, offset
>> 1, &val
);
3512 *data
++ = val
& 0xff;
3522 static int mv88e6xxx_get_eeprom(struct dsa_switch
*ds
,
3523 struct ethtool_eeprom
*eeprom
, u8
*data
)
3525 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3528 mutex_lock(&chip
->reg_lock
);
3530 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_EEPROM16
))
3531 err
= mv88e6xxx_get_eeprom16(chip
, eeprom
, data
);
3535 mutex_unlock(&chip
->reg_lock
);
3540 eeprom
->magic
= 0xc3ec4951;
3545 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip
*chip
,
3546 struct ethtool_eeprom
*eeprom
, u8
*data
)
3548 unsigned int offset
= eeprom
->offset
;
3549 unsigned int len
= eeprom
->len
;
3553 /* Ensure the RO WriteEn bit is set */
3554 err
= mv88e6xxx_read(chip
, REG_GLOBAL2
, GLOBAL2_EEPROM_CMD
, &val
);
3558 if (!(val
& GLOBAL2_EEPROM_CMD_WRITE_EN
))
3564 err
= mv88e6xxx_g2_eeprom_read16(chip
, offset
>> 1, &val
);
3568 val
= (*data
++ << 8) | (val
& 0xff);
3570 err
= mv88e6xxx_g2_eeprom_write16(chip
, offset
>> 1, val
);
3581 val
|= *data
++ << 8;
3583 err
= mv88e6xxx_g2_eeprom_write16(chip
, offset
>> 1, val
);
3593 err
= mv88e6xxx_g2_eeprom_read16(chip
, offset
>> 1, &val
);
3597 val
= (val
& 0xff00) | *data
++;
3599 err
= mv88e6xxx_g2_eeprom_write16(chip
, offset
>> 1, val
);
3611 static int mv88e6xxx_set_eeprom(struct dsa_switch
*ds
,
3612 struct ethtool_eeprom
*eeprom
, u8
*data
)
3614 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
3617 if (eeprom
->magic
!= 0xc3ec4951)
3620 mutex_lock(&chip
->reg_lock
);
3622 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_EEPROM16
))
3623 err
= mv88e6xxx_set_eeprom16(chip
, eeprom
, data
);
3627 mutex_unlock(&chip
->reg_lock
);
3632 static const struct mv88e6xxx_info mv88e6xxx_table
[] = {
3634 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6085
,
3635 .family
= MV88E6XXX_FAMILY_6097
,
3636 .name
= "Marvell 88E6085",
3637 .num_databases
= 4096,
3639 .port_base_addr
= 0x10,
3640 .age_time_coeff
= 15000,
3641 .flags
= MV88E6XXX_FLAGS_FAMILY_6097
,
3645 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6095
,
3646 .family
= MV88E6XXX_FAMILY_6095
,
3647 .name
= "Marvell 88E6095/88E6095F",
3648 .num_databases
= 256,
3650 .port_base_addr
= 0x10,
3651 .age_time_coeff
= 15000,
3652 .flags
= MV88E6XXX_FLAGS_FAMILY_6095
,
3656 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6123
,
3657 .family
= MV88E6XXX_FAMILY_6165
,
3658 .name
= "Marvell 88E6123",
3659 .num_databases
= 4096,
3661 .port_base_addr
= 0x10,
3662 .age_time_coeff
= 15000,
3663 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3667 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6131
,
3668 .family
= MV88E6XXX_FAMILY_6185
,
3669 .name
= "Marvell 88E6131",
3670 .num_databases
= 256,
3672 .port_base_addr
= 0x10,
3673 .age_time_coeff
= 15000,
3674 .flags
= MV88E6XXX_FLAGS_FAMILY_6185
,
3678 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6161
,
3679 .family
= MV88E6XXX_FAMILY_6165
,
3680 .name
= "Marvell 88E6161",
3681 .num_databases
= 4096,
3683 .port_base_addr
= 0x10,
3684 .age_time_coeff
= 15000,
3685 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3689 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6165
,
3690 .family
= MV88E6XXX_FAMILY_6165
,
3691 .name
= "Marvell 88E6165",
3692 .num_databases
= 4096,
3694 .port_base_addr
= 0x10,
3695 .age_time_coeff
= 15000,
3696 .flags
= MV88E6XXX_FLAGS_FAMILY_6165
,
3700 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6171
,
3701 .family
= MV88E6XXX_FAMILY_6351
,
3702 .name
= "Marvell 88E6171",
3703 .num_databases
= 4096,
3705 .port_base_addr
= 0x10,
3706 .age_time_coeff
= 15000,
3707 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3711 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6172
,
3712 .family
= MV88E6XXX_FAMILY_6352
,
3713 .name
= "Marvell 88E6172",
3714 .num_databases
= 4096,
3716 .port_base_addr
= 0x10,
3717 .age_time_coeff
= 15000,
3718 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3722 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6175
,
3723 .family
= MV88E6XXX_FAMILY_6351
,
3724 .name
= "Marvell 88E6175",
3725 .num_databases
= 4096,
3727 .port_base_addr
= 0x10,
3728 .age_time_coeff
= 15000,
3729 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3733 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6176
,
3734 .family
= MV88E6XXX_FAMILY_6352
,
3735 .name
= "Marvell 88E6176",
3736 .num_databases
= 4096,
3738 .port_base_addr
= 0x10,
3739 .age_time_coeff
= 15000,
3740 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3744 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6185
,
3745 .family
= MV88E6XXX_FAMILY_6185
,
3746 .name
= "Marvell 88E6185",
3747 .num_databases
= 256,
3749 .port_base_addr
= 0x10,
3750 .age_time_coeff
= 15000,
3751 .flags
= MV88E6XXX_FLAGS_FAMILY_6185
,
3755 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6240
,
3756 .family
= MV88E6XXX_FAMILY_6352
,
3757 .name
= "Marvell 88E6240",
3758 .num_databases
= 4096,
3760 .port_base_addr
= 0x10,
3761 .age_time_coeff
= 15000,
3762 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3766 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6320
,
3767 .family
= MV88E6XXX_FAMILY_6320
,
3768 .name
= "Marvell 88E6320",
3769 .num_databases
= 4096,
3771 .port_base_addr
= 0x10,
3772 .age_time_coeff
= 15000,
3773 .flags
= MV88E6XXX_FLAGS_FAMILY_6320
,
3777 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6321
,
3778 .family
= MV88E6XXX_FAMILY_6320
,
3779 .name
= "Marvell 88E6321",
3780 .num_databases
= 4096,
3782 .port_base_addr
= 0x10,
3783 .age_time_coeff
= 15000,
3784 .flags
= MV88E6XXX_FLAGS_FAMILY_6320
,
3788 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6350
,
3789 .family
= MV88E6XXX_FAMILY_6351
,
3790 .name
= "Marvell 88E6350",
3791 .num_databases
= 4096,
3793 .port_base_addr
= 0x10,
3794 .age_time_coeff
= 15000,
3795 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3799 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6351
,
3800 .family
= MV88E6XXX_FAMILY_6351
,
3801 .name
= "Marvell 88E6351",
3802 .num_databases
= 4096,
3804 .port_base_addr
= 0x10,
3805 .age_time_coeff
= 15000,
3806 .flags
= MV88E6XXX_FLAGS_FAMILY_6351
,
3810 .prod_num
= PORT_SWITCH_ID_PROD_NUM_6352
,
3811 .family
= MV88E6XXX_FAMILY_6352
,
3812 .name
= "Marvell 88E6352",
3813 .num_databases
= 4096,
3815 .port_base_addr
= 0x10,
3816 .age_time_coeff
= 15000,
3817 .flags
= MV88E6XXX_FLAGS_FAMILY_6352
,
3821 static const struct mv88e6xxx_info
*mv88e6xxx_lookup_info(unsigned int prod_num
)
3825 for (i
= 0; i
< ARRAY_SIZE(mv88e6xxx_table
); ++i
)
3826 if (mv88e6xxx_table
[i
].prod_num
== prod_num
)
3827 return &mv88e6xxx_table
[i
];
3832 static int mv88e6xxx_detect(struct mv88e6xxx_chip
*chip
)
3834 const struct mv88e6xxx_info
*info
;
3835 unsigned int prod_num
, rev
;
3839 mutex_lock(&chip
->reg_lock
);
3840 err
= mv88e6xxx_port_read(chip
, 0, PORT_SWITCH_ID
, &id
);
3841 mutex_unlock(&chip
->reg_lock
);
3845 prod_num
= (id
& 0xfff0) >> 4;
3848 info
= mv88e6xxx_lookup_info(prod_num
);
3852 /* Update the compatible info with the probed one */
3855 dev_info(chip
->dev
, "switch 0x%x detected: %s, revision %u\n",
3856 chip
->info
->prod_num
, chip
->info
->name
, rev
);
3861 static struct mv88e6xxx_chip
*mv88e6xxx_alloc_chip(struct device
*dev
)
3863 struct mv88e6xxx_chip
*chip
;
3865 chip
= devm_kzalloc(dev
, sizeof(*chip
), GFP_KERNEL
);
3871 mutex_init(&chip
->reg_lock
);
3876 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip
*chip
,
3877 struct mii_bus
*bus
, int sw_addr
)
3879 /* ADDR[0] pin is unavailable externally and considered zero */
3884 chip
->smi_ops
= &mv88e6xxx_smi_single_chip_ops
;
3885 else if (mv88e6xxx_has(chip
, MV88E6XXX_FLAG_MULTI_CHIP
))
3886 chip
->smi_ops
= &mv88e6xxx_smi_multi_chip_ops
;
3891 chip
->sw_addr
= sw_addr
;
3896 static const char *mv88e6xxx_drv_probe(struct device
*dsa_dev
,
3897 struct device
*host_dev
, int sw_addr
,
3900 struct mv88e6xxx_chip
*chip
;
3901 struct mii_bus
*bus
;
3904 bus
= dsa_host_dev_to_mii_bus(host_dev
);
3908 chip
= mv88e6xxx_alloc_chip(dsa_dev
);
3912 /* Legacy SMI probing will only support chips similar to 88E6085 */
3913 chip
->info
= &mv88e6xxx_table
[MV88E6085
];
3915 err
= mv88e6xxx_smi_init(chip
, bus
, sw_addr
);
3919 err
= mv88e6xxx_detect(chip
);
3923 err
= mv88e6xxx_mdio_register(chip
, NULL
);
3929 return chip
->info
->name
;
3931 devm_kfree(dsa_dev
, chip
);
3936 static struct dsa_switch_driver mv88e6xxx_switch_driver
= {
3937 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
3938 .probe
= mv88e6xxx_drv_probe
,
3939 .setup
= mv88e6xxx_setup
,
3940 .set_addr
= mv88e6xxx_set_addr
,
3941 .adjust_link
= mv88e6xxx_adjust_link
,
3942 .get_strings
= mv88e6xxx_get_strings
,
3943 .get_ethtool_stats
= mv88e6xxx_get_ethtool_stats
,
3944 .get_sset_count
= mv88e6xxx_get_sset_count
,
3945 .set_eee
= mv88e6xxx_set_eee
,
3946 .get_eee
= mv88e6xxx_get_eee
,
3947 #ifdef CONFIG_NET_DSA_HWMON
3948 .get_temp
= mv88e6xxx_get_temp
,
3949 .get_temp_limit
= mv88e6xxx_get_temp_limit
,
3950 .set_temp_limit
= mv88e6xxx_set_temp_limit
,
3951 .get_temp_alarm
= mv88e6xxx_get_temp_alarm
,
3953 .get_eeprom_len
= mv88e6xxx_get_eeprom_len
,
3954 .get_eeprom
= mv88e6xxx_get_eeprom
,
3955 .set_eeprom
= mv88e6xxx_set_eeprom
,
3956 .get_regs_len
= mv88e6xxx_get_regs_len
,
3957 .get_regs
= mv88e6xxx_get_regs
,
3958 .set_ageing_time
= mv88e6xxx_set_ageing_time
,
3959 .port_bridge_join
= mv88e6xxx_port_bridge_join
,
3960 .port_bridge_leave
= mv88e6xxx_port_bridge_leave
,
3961 .port_stp_state_set
= mv88e6xxx_port_stp_state_set
,
3962 .port_vlan_filtering
= mv88e6xxx_port_vlan_filtering
,
3963 .port_vlan_prepare
= mv88e6xxx_port_vlan_prepare
,
3964 .port_vlan_add
= mv88e6xxx_port_vlan_add
,
3965 .port_vlan_del
= mv88e6xxx_port_vlan_del
,
3966 .port_vlan_dump
= mv88e6xxx_port_vlan_dump
,
3967 .port_fdb_prepare
= mv88e6xxx_port_fdb_prepare
,
3968 .port_fdb_add
= mv88e6xxx_port_fdb_add
,
3969 .port_fdb_del
= mv88e6xxx_port_fdb_del
,
3970 .port_fdb_dump
= mv88e6xxx_port_fdb_dump
,
3973 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip
*chip
,
3974 struct device_node
*np
)
3976 struct device
*dev
= chip
->dev
;
3977 struct dsa_switch
*ds
;
3979 ds
= devm_kzalloc(dev
, sizeof(*ds
), GFP_KERNEL
);
3985 ds
->drv
= &mv88e6xxx_switch_driver
;
3987 dev_set_drvdata(dev
, ds
);
3989 return dsa_register_switch(ds
, np
);
3992 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip
*chip
)
3994 dsa_unregister_switch(chip
->ds
);
3997 static int mv88e6xxx_probe(struct mdio_device
*mdiodev
)
3999 struct device
*dev
= &mdiodev
->dev
;
4000 struct device_node
*np
= dev
->of_node
;
4001 const struct mv88e6xxx_info
*compat_info
;
4002 struct mv88e6xxx_chip
*chip
;
4006 compat_info
= of_device_get_match_data(dev
);
4010 chip
= mv88e6xxx_alloc_chip(dev
);
4014 chip
->info
= compat_info
;
4016 err
= mv88e6xxx_smi_init(chip
, mdiodev
->bus
, mdiodev
->addr
);
4020 err
= mv88e6xxx_detect(chip
);
4024 chip
->reset
= devm_gpiod_get_optional(dev
, "reset", GPIOD_ASIS
);
4025 if (IS_ERR(chip
->reset
))
4026 return PTR_ERR(chip
->reset
);
4028 if (mv88e6xxx_has(chip
, MV88E6XXX_FLAGS_EEPROM16
) &&
4029 !of_property_read_u32(np
, "eeprom-length", &eeprom_len
))
4030 chip
->eeprom_len
= eeprom_len
;
4032 err
= mv88e6xxx_mdio_register(chip
, np
);
4036 err
= mv88e6xxx_register_switch(chip
, np
);
4038 mv88e6xxx_mdio_unregister(chip
);
4045 static void mv88e6xxx_remove(struct mdio_device
*mdiodev
)
4047 struct dsa_switch
*ds
= dev_get_drvdata(&mdiodev
->dev
);
4048 struct mv88e6xxx_chip
*chip
= ds_to_priv(ds
);
4050 mv88e6xxx_unregister_switch(chip
);
4051 mv88e6xxx_mdio_unregister(chip
);
4054 static const struct of_device_id mv88e6xxx_of_match
[] = {
4056 .compatible
= "marvell,mv88e6085",
4057 .data
= &mv88e6xxx_table
[MV88E6085
],
4062 MODULE_DEVICE_TABLE(of
, mv88e6xxx_of_match
);
4064 static struct mdio_driver mv88e6xxx_driver
= {
4065 .probe
= mv88e6xxx_probe
,
4066 .remove
= mv88e6xxx_remove
,
4068 .name
= "mv88e6085",
4069 .of_match_table
= mv88e6xxx_of_match
,
4073 static int __init
mv88e6xxx_init(void)
4075 register_switch_driver(&mv88e6xxx_switch_driver
);
4076 return mdio_driver_register(&mv88e6xxx_driver
);
4078 module_init(mv88e6xxx_init
);
4080 static void __exit
mv88e6xxx_cleanup(void)
4082 mdio_driver_unregister(&mv88e6xxx_driver
);
4083 unregister_switch_driver(&mv88e6xxx_switch_driver
);
4085 module_exit(mv88e6xxx_cleanup
);
4087 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4088 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4089 MODULE_LICENSE("GPL");