drivers/net/dsa/mv88e6xxx/mv88e6xxx.h

   1 /*
   2  * Marvell 88e6xxx common definitions
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #ifndef __MV88E6XXX_H
  13 #define __MV88E6XXX_H
  14
  15 #include <linux/if_vlan.h>
  16 #include <linux/gpio/consumer.h>
  17
  18 #ifndef UINT64_MAX
  19 #define UINT64_MAX              (u64)(~((u64)0))
  20 #endif
  21
  22 #define SMI_CMD                 0x00
  23 #define SMI_CMD_BUSY            BIT(15)
  24 #define SMI_CMD_CLAUSE_22       BIT(12)
  25 #define SMI_CMD_OP_22_WRITE     ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
  26 #define SMI_CMD_OP_22_READ      ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
  27 #define SMI_CMD_OP_45_WRITE_ADDR        ((0 << 10) | SMI_CMD_BUSY)
  28 #define SMI_CMD_OP_45_WRITE_DATA        ((1 << 10) | SMI_CMD_BUSY)
  29 #define SMI_CMD_OP_45_READ_DATA         ((2 << 10) | SMI_CMD_BUSY)
  30 #define SMI_CMD_OP_45_READ_DATA_INC     ((3 << 10) | SMI_CMD_BUSY)
  31 #define SMI_DATA                0x01
  32
  33 /* Fiber/SERDES Registers are located at SMI address F, page 1 */
  34 #define REG_FIBER_SERDES        0x0f
  35 #define PAGE_FIBER_SERDES       0x01
  36
  37 #define REG_PORT(p)             (0x10 + (p))
  38 #define PORT_STATUS             0x00
  39 #define PORT_STATUS_PAUSE_EN    BIT(15)
  40 #define PORT_STATUS_MY_PAUSE    BIT(14)
  41 #define PORT_STATUS_HD_FLOW     BIT(13)
  42 #define PORT_STATUS_PHY_DETECT  BIT(12)
  43 #define PORT_STATUS_LINK        BIT(11)
  44 #define PORT_STATUS_DUPLEX      BIT(10)
  45 #define PORT_STATUS_SPEED_MASK  0x0300
  46 #define PORT_STATUS_SPEED_10    0x0000
  47 #define PORT_STATUS_SPEED_100   0x0100
  48 #define PORT_STATUS_SPEED_1000  0x0200
  49 #define PORT_STATUS_EEE         BIT(6) /* 6352 */
  50 #define PORT_STATUS_AM_DIS      BIT(6) /* 6165 */
  51 #define PORT_STATUS_MGMII       BIT(6) /* 6185 */
  52 #define PORT_STATUS_TX_PAUSED   BIT(5)
  53 #define PORT_STATUS_FLOW_CTRL   BIT(4)
  54 #define PORT_STATUS_CMODE_MASK  0x0f
  55 #define PORT_STATUS_CMODE_100BASE_X     0x8
  56 #define PORT_STATUS_CMODE_1000BASE_X    0x9
  57 #define PORT_STATUS_CMODE_SGMII         0xa
  58 #define PORT_PCS_CTRL           0x01
  59 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
  60 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
  61 #define PORT_PCS_CTRL_FC                BIT(7)
  62 #define PORT_PCS_CTRL_FORCE_FC          BIT(6)
  63 #define PORT_PCS_CTRL_LINK_UP           BIT(5)
  64 #define PORT_PCS_CTRL_FORCE_LINK        BIT(4)
  65 #define PORT_PCS_CTRL_DUPLEX_FULL       BIT(3)
  66 #define PORT_PCS_CTRL_FORCE_DUPLEX      BIT(2)
  67 #define PORT_PCS_CTRL_10                0x00
  68 #define PORT_PCS_CTRL_100               0x01
  69 #define PORT_PCS_CTRL_1000              0x02
  70 #define PORT_PCS_CTRL_UNFORCED          0x03
  71 #define PORT_PAUSE_CTRL         0x02
  72 #define PORT_SWITCH_ID          0x03
  73 #define PORT_SWITCH_ID_PROD_NUM_6085    0x04a
  74 #define PORT_SWITCH_ID_PROD_NUM_6095    0x095
  75 #define PORT_SWITCH_ID_PROD_NUM_6131    0x106
  76 #define PORT_SWITCH_ID_PROD_NUM_6320    0x115
  77 #define PORT_SWITCH_ID_PROD_NUM_6123    0x121
  78 #define PORT_SWITCH_ID_PROD_NUM_6161    0x161
  79 #define PORT_SWITCH_ID_PROD_NUM_6165    0x165
  80 #define PORT_SWITCH_ID_PROD_NUM_6171    0x171
  81 #define PORT_SWITCH_ID_PROD_NUM_6172    0x172
  82 #define PORT_SWITCH_ID_PROD_NUM_6175    0x175
  83 #define PORT_SWITCH_ID_PROD_NUM_6176    0x176
  84 #define PORT_SWITCH_ID_PROD_NUM_6185    0x1a7
  85 #define PORT_SWITCH_ID_PROD_NUM_6240    0x240
  86 #define PORT_SWITCH_ID_PROD_NUM_6321    0x310
  87 #define PORT_SWITCH_ID_PROD_NUM_6352    0x352
  88 #define PORT_SWITCH_ID_PROD_NUM_6350    0x371
  89 #define PORT_SWITCH_ID_PROD_NUM_6351    0x375
  90 #define PORT_CONTROL            0x04
  91 #define PORT_CONTROL_USE_CORE_TAG       BIT(15)
  92 #define PORT_CONTROL_DROP_ON_LOCK       BIT(14)
  93 #define PORT_CONTROL_EGRESS_UNMODIFIED  (0x0 << 12)
  94 #define PORT_CONTROL_EGRESS_UNTAGGED    (0x1 << 12)
  95 #define PORT_CONTROL_EGRESS_TAGGED      (0x2 << 12)
  96 #define PORT_CONTROL_EGRESS_ADD_TAG     (0x3 << 12)
  97 #define PORT_CONTROL_HEADER             BIT(11)
  98 #define PORT_CONTROL_IGMP_MLD_SNOOP     BIT(10)
  99 #define PORT_CONTROL_DOUBLE_TAG         BIT(9)
 100 #define PORT_CONTROL_FRAME_MODE_NORMAL          (0x0 << 8)
 101 #define PORT_CONTROL_FRAME_MODE_DSA             (0x1 << 8)
 102 #define PORT_CONTROL_FRAME_MODE_PROVIDER        (0x2 << 8)
 103 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA       (0x3 << 8)
 104 #define PORT_CONTROL_DSA_TAG            BIT(8)
 105 #define PORT_CONTROL_VLAN_TUNNEL        BIT(7)
 106 #define PORT_CONTROL_TAG_IF_BOTH        BIT(6)
 107 #define PORT_CONTROL_USE_IP             BIT(5)
 108 #define PORT_CONTROL_USE_TAG            BIT(4)
 109 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
 110 #define PORT_CONTROL_FORWARD_UNKNOWN    BIT(2)
 111 #define PORT_CONTROL_STATE_MASK         0x03
 112 #define PORT_CONTROL_STATE_DISABLED     0x00
 113 #define PORT_CONTROL_STATE_BLOCKING     0x01
 114 #define PORT_CONTROL_STATE_LEARNING     0x02
 115 #define PORT_CONTROL_STATE_FORWARDING   0x03
 116 #define PORT_CONTROL_1          0x05
 117 #define PORT_CONTROL_1_FID_11_4_MASK    (0xff << 0)
 118 #define PORT_BASE_VLAN          0x06
 119 #define PORT_BASE_VLAN_FID_3_0_MASK     (0xf << 12)
 120 #define PORT_DEFAULT_VLAN       0x07
 121 #define PORT_DEFAULT_VLAN_MASK  0xfff
 122 #define PORT_CONTROL_2          0x08
 123 #define PORT_CONTROL_2_IGNORE_FCS       BIT(15)
 124 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
 125 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
 126 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
 127 #define PORT_CONTROL_2_JUMBO_1522       (0x00 << 12)
 128 #define PORT_CONTROL_2_JUMBO_2048       (0x01 << 12)
 129 #define PORT_CONTROL_2_JUMBO_10240      (0x02 << 12)
 130 #define PORT_CONTROL_2_8021Q_MASK       (0x03 << 10)
 131 #define PORT_CONTROL_2_8021Q_DISABLED   (0x00 << 10)
 132 #define PORT_CONTROL_2_8021Q_FALLBACK   (0x01 << 10)
 133 #define PORT_CONTROL_2_8021Q_CHECK      (0x02 << 10)
 134 #define PORT_CONTROL_2_8021Q_SECURE     (0x03 << 10)
 135 #define PORT_CONTROL_2_DISCARD_TAGGED   BIT(9)
 136 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
 137 #define PORT_CONTROL_2_MAP_DA           BIT(7)
 138 #define PORT_CONTROL_2_DEFAULT_FORWARD  BIT(6)
 139 #define PORT_CONTROL_2_FORWARD_UNKNOWN  BIT(6)
 140 #define PORT_CONTROL_2_EGRESS_MONITOR   BIT(5)
 141 #define PORT_CONTROL_2_INGRESS_MONITOR  BIT(4)
 142 #define PORT_RATE_CONTROL       0x09
 143 #define PORT_RATE_CONTROL_2     0x0a
 144 #define PORT_ASSOC_VECTOR       0x0b
 145 #define PORT_ASSOC_VECTOR_HOLD_AT_1             BIT(15)
 146 #define PORT_ASSOC_VECTOR_INT_AGE_OUT           BIT(14)
 147 #define PORT_ASSOC_VECTOR_LOCKED_PORT           BIT(13)
 148 #define PORT_ASSOC_VECTOR_IGNORE_WRONG          BIT(12)
 149 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED        BIT(11)
 150 #define PORT_ATU_CONTROL        0x0c
 151 #define PORT_PRI_OVERRIDE       0x0d
 152 #define PORT_ETH_TYPE           0x0f
 153 #define PORT_IN_DISCARD_LO      0x10
 154 #define PORT_IN_DISCARD_HI      0x11
 155 #define PORT_IN_FILTERED        0x12
 156 #define PORT_OUT_FILTERED       0x13
 157 #define PORT_TAG_REGMAP_0123    0x18
 158 #define PORT_TAG_REGMAP_4567    0x19
 159
 160 #define REG_GLOBAL              0x1b
 161 #define GLOBAL_STATUS           0x00
 162 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
 163 /* Two bits for 6165, 6185 etc */
 164 #define GLOBAL_STATUS_PPU_MASK          (0x3 << 14)
 165 #define GLOBAL_STATUS_PPU_DISABLED_RST  (0x0 << 14)
 166 #define GLOBAL_STATUS_PPU_INITIALIZING  (0x1 << 14)
 167 #define GLOBAL_STATUS_PPU_DISABLED      (0x2 << 14)
 168 #define GLOBAL_STATUS_PPU_POLLING       (0x3 << 14)
 169 #define GLOBAL_MAC_01           0x01
 170 #define GLOBAL_MAC_23           0x02
 171 #define GLOBAL_MAC_45           0x03
 172 #define GLOBAL_ATU_FID          0x01    /* 6097 6165 6351 6352 */
 173 #define GLOBAL_VTU_FID          0x02    /* 6097 6165 6351 6352 */
 174 #define GLOBAL_VTU_FID_MASK     0xfff
 175 #define GLOBAL_VTU_SID          0x03    /* 6097 6165 6351 6352 */
 176 #define GLOBAL_VTU_SID_MASK     0x3f
 177 #define GLOBAL_CONTROL          0x04
 178 #define GLOBAL_CONTROL_SW_RESET         BIT(15)
 179 #define GLOBAL_CONTROL_PPU_ENABLE       BIT(14)
 180 #define GLOBAL_CONTROL_DISCARD_EXCESS   BIT(13) /* 6352 */
 181 #define GLOBAL_CONTROL_SCHED_PRIO       BIT(11) /* 6152 */
 182 #define GLOBAL_CONTROL_MAX_FRAME_1632   BIT(10) /* 6152 */
 183 #define GLOBAL_CONTROL_RELOAD_EEPROM    BIT(9)  /* 6152 */
 184 #define GLOBAL_CONTROL_DEVICE_EN        BIT(7)
 185 #define GLOBAL_CONTROL_STATS_DONE_EN    BIT(6)
 186 #define GLOBAL_CONTROL_VTU_PROBLEM_EN   BIT(5)
 187 #define GLOBAL_CONTROL_VTU_DONE_EN      BIT(4)
 188 #define GLOBAL_CONTROL_ATU_PROBLEM_EN   BIT(3)
 189 #define GLOBAL_CONTROL_ATU_DONE_EN      BIT(2)
 190 #define GLOBAL_CONTROL_TCAM_EN          BIT(1)
 191 #define GLOBAL_CONTROL_EEPROM_DONE_EN   BIT(0)
 192 #define GLOBAL_VTU_OP           0x05
 193 #define GLOBAL_VTU_OP_BUSY      BIT(15)
 194 #define GLOBAL_VTU_OP_FLUSH_ALL         ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
 195 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE    ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
 196 #define GLOBAL_VTU_OP_VTU_GET_NEXT      ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
 197 #define GLOBAL_VTU_OP_STU_LOAD_PURGE    ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
 198 #define GLOBAL_VTU_OP_STU_GET_NEXT      ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
 199 #define GLOBAL_VTU_VID          0x06
 200 #define GLOBAL_VTU_VID_MASK     0xfff
 201 #define GLOBAL_VTU_VID_VALID    BIT(12)
 202 #define GLOBAL_VTU_DATA_0_3     0x07
 203 #define GLOBAL_VTU_DATA_4_7     0x08
 204 #define GLOBAL_VTU_DATA_8_11    0x09
 205 #define GLOBAL_VTU_STU_DATA_MASK                0x03
 206 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED   0x00
 207 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED     0x01
 208 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED       0x02
 209 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER   0x03
 210 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED     0x00
 211 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING     0x01
 212 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING     0x02
 213 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING   0x03
 214 #define GLOBAL_ATU_CONTROL      0x0a
 215 #define GLOBAL_ATU_CONTROL_LEARN2ALL    BIT(3)
 216 #define GLOBAL_ATU_OP           0x0b
 217 #define GLOBAL_ATU_OP_BUSY      BIT(15)
 218 #define GLOBAL_ATU_OP_NOP               (0 << 12)
 219 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL            ((1 << 12) | GLOBAL_ATU_OP_BUSY)
 220 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC     ((2 << 12) | GLOBAL_ATU_OP_BUSY)
 221 #define GLOBAL_ATU_OP_LOAD_DB           ((3 << 12) | GLOBAL_ATU_OP_BUSY)
 222 #define GLOBAL_ATU_OP_GET_NEXT_DB       ((4 << 12) | GLOBAL_ATU_OP_BUSY)
 223 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB         ((5 << 12) | GLOBAL_ATU_OP_BUSY)
 224 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
 225 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION   ((7 << 12) | GLOBAL_ATU_OP_BUSY)
 226 #define GLOBAL_ATU_DATA         0x0c
 227 #define GLOBAL_ATU_DATA_TRUNK                   BIT(15)
 228 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK           0x00f0
 229 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT          4
 230 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK        0x3ff0
 231 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT       4
 232 #define GLOBAL_ATU_DATA_STATE_MASK              0x0f
 233 #define GLOBAL_ATU_DATA_STATE_UNUSED            0x00
 234 #define GLOBAL_ATU_DATA_STATE_UC_MGMT           0x0d
 235 #define GLOBAL_ATU_DATA_STATE_UC_STATIC         0x0e
 236 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER      0x0f
 237 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE      0x05
 238 #define GLOBAL_ATU_DATA_STATE_MC_STATIC         0x07
 239 #define GLOBAL_ATU_DATA_STATE_MC_MGMT           0x0e
 240 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER      0x0f
 241 #define GLOBAL_ATU_MAC_01       0x0d
 242 #define GLOBAL_ATU_MAC_23       0x0e
 243 #define GLOBAL_ATU_MAC_45       0x0f
 244 #define GLOBAL_IP_PRI_0         0x10
 245 #define GLOBAL_IP_PRI_1         0x11
 246 #define GLOBAL_IP_PRI_2         0x12
 247 #define GLOBAL_IP_PRI_3         0x13
 248 #define GLOBAL_IP_PRI_4         0x14
 249 #define GLOBAL_IP_PRI_5         0x15
 250 #define GLOBAL_IP_PRI_6         0x16
 251 #define GLOBAL_IP_PRI_7         0x17
 252 #define GLOBAL_IEEE_PRI         0x18
 253 #define GLOBAL_CORE_TAG_TYPE    0x19
 254 #define GLOBAL_MONITOR_CONTROL  0x1a
 255 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT    12
 256 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT     8
 257 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT        4
 258 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT     0
 259 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED     (0xf0)
 260 #define GLOBAL_CONTROL_2        0x1c
 261 #define GLOBAL_CONTROL_2_NO_CASCADE             0xe000
 262 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE       0xf000
 263
 264 #define GLOBAL_STATS_OP         0x1d
 265 #define GLOBAL_STATS_OP_BUSY    BIT(15)
 266 #define GLOBAL_STATS_OP_NOP             (0 << 12)
 267 #define GLOBAL_STATS_OP_FLUSH_ALL       ((1 << 12) | GLOBAL_STATS_OP_BUSY)
 268 #define GLOBAL_STATS_OP_FLUSH_PORT      ((2 << 12) | GLOBAL_STATS_OP_BUSY)
 269 #define GLOBAL_STATS_OP_READ_CAPTURED   ((4 << 12) | GLOBAL_STATS_OP_BUSY)
 270 #define GLOBAL_STATS_OP_CAPTURE_PORT    ((5 << 12) | GLOBAL_STATS_OP_BUSY)
 271 #define GLOBAL_STATS_OP_HIST_RX         ((1 << 10) | GLOBAL_STATS_OP_BUSY)
 272 #define GLOBAL_STATS_OP_HIST_TX         ((2 << 10) | GLOBAL_STATS_OP_BUSY)
 273 #define GLOBAL_STATS_OP_HIST_RX_TX      ((3 << 10) | GLOBAL_STATS_OP_BUSY)
 274 #define GLOBAL_STATS_OP_BANK_1  BIT(9)
 275 #define GLOBAL_STATS_COUNTER_32 0x1e
 276 #define GLOBAL_STATS_COUNTER_01 0x1f
 277
 278 #define REG_GLOBAL2             0x1c
 279 #define GLOBAL2_INT_SOURCE      0x00
 280 #define GLOBAL2_INT_MASK        0x01
 281 #define GLOBAL2_MGMT_EN_2X      0x02
 282 #define GLOBAL2_MGMT_EN_0X      0x03
 283 #define GLOBAL2_FLOW_CONTROL    0x04
 284 #define GLOBAL2_SWITCH_MGMT     0x05
 285 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
 286 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS       BIT(14)
 287 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG    BIT(13)
 288 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
 289 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU            BIT(3)
 290 #define GLOBAL2_DEVICE_MAPPING  0x06
 291 #define GLOBAL2_DEVICE_MAPPING_UPDATE           BIT(15)
 292 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT     8
 293 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK        0x0f
 294 #define GLOBAL2_TRUNK_MASK      0x07
 295 #define GLOBAL2_TRUNK_MASK_UPDATE               BIT(15)
 296 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT            12
 297 #define GLOBAL2_TRUNK_MASK_HASK                 BIT(11)
 298 #define GLOBAL2_TRUNK_MAPPING   0x08
 299 #define GLOBAL2_TRUNK_MAPPING_UPDATE            BIT(15)
 300 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT          11
 301 #define GLOBAL2_IRL_CMD         0x09
 302 #define GLOBAL2_IRL_CMD_BUSY    BIT(15)
 303 #define GLOBAL2_IRL_CMD_OP_INIT_ALL     ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
 304 #define GLOBAL2_IRL_CMD_OP_INIT_SEL     ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
 305 #define GLOBAL2_IRL_CMD_OP_WRITE_SEL    ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
 306 #define GLOBAL2_IRL_CMD_OP_READ_SEL     ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
 307 #define GLOBAL2_IRL_DATA        0x0a
 308 #define GLOBAL2_PVT_ADDR        0x0b
 309 #define GLOBAL2_PVT_ADDR_BUSY   BIT(15)
 310 #define GLOBAL2_PVT_ADDR_OP_INIT_ONES   ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
 311 #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)
 312 #define GLOBAL2_PVT_ADDR_OP_READ        ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)
 313 #define GLOBAL2_PVT_DATA        0x0c
 314 #define GLOBAL2_SWITCH_MAC      0x0d
 315 #define GLOBAL2_ATU_STATS       0x0e
 316 #define GLOBAL2_PRIO_OVERRIDE   0x0f
 317 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP       BIT(7)
 318 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT       4
 319 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP         BIT(3)
 320 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT         0
 321 #define GLOBAL2_EEPROM_CMD              0x14
 322 #define GLOBAL2_EEPROM_CMD_BUSY         BIT(15)
 323 #define GLOBAL2_EEPROM_CMD_OP_WRITE     ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
 324 #define GLOBAL2_EEPROM_CMD_OP_READ      ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
 325 #define GLOBAL2_EEPROM_CMD_OP_LOAD      ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
 326 #define GLOBAL2_EEPROM_CMD_RUNNING      BIT(11)
 327 #define GLOBAL2_EEPROM_CMD_WRITE_EN     BIT(10)
 328 #define GLOBAL2_EEPROM_CMD_ADDR_MASK    0xff
 329 #define GLOBAL2_EEPROM_DATA     0x15
 330 #define GLOBAL2_PTP_AVB_OP      0x16
 331 #define GLOBAL2_PTP_AVB_DATA    0x17
 332 #define GLOBAL2_SMI_OP          0x18
 333 #define GLOBAL2_SMI_OP_BUSY             BIT(15)
 334 #define GLOBAL2_SMI_OP_CLAUSE_22        BIT(12)
 335 #define GLOBAL2_SMI_OP_22_WRITE         ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
 336                                          GLOBAL2_SMI_OP_CLAUSE_22)
 337 #define GLOBAL2_SMI_OP_22_READ          ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
 338                                          GLOBAL2_SMI_OP_CLAUSE_22)
 339 #define GLOBAL2_SMI_OP_45_WRITE_ADDR    ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
 340 #define GLOBAL2_SMI_OP_45_WRITE_DATA    ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
 341 #define GLOBAL2_SMI_OP_45_READ_DATA     ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
 342 #define GLOBAL2_SMI_DATA        0x19
 343 #define GLOBAL2_SCRATCH_MISC    0x1a
 344 #define GLOBAL2_SCRATCH_BUSY            BIT(15)
 345 #define GLOBAL2_SCRATCH_REGISTER_SHIFT  8
 346 #define GLOBAL2_SCRATCH_VALUE_MASK      0xff
 347 #define GLOBAL2_WDOG_CONTROL    0x1b
 348 #define GLOBAL2_QOS_WEIGHT      0x1c
 349 #define GLOBAL2_MISC            0x1d
 350
 351 #define MV88E6XXX_N_FID         4096
 352
 353 /* List of supported models */
 354 enum mv88e6xxx_model {
 355         MV88E6085,
 356         MV88E6095,
 357         MV88E6123,
 358         MV88E6131,
 359         MV88E6161,
 360         MV88E6165,
 361         MV88E6171,
 362         MV88E6172,
 363         MV88E6175,
 364         MV88E6176,
 365         MV88E6185,
 366         MV88E6240,
 367         MV88E6320,
 368         MV88E6321,
 369         MV88E6350,
 370         MV88E6351,
 371         MV88E6352,
 372 };
 373
 374 enum mv88e6xxx_family {
 375         MV88E6XXX_FAMILY_NONE,
 376         MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
 377         MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
 378         MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
 379         MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
 380         MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
 381         MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
 382         MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
 383         MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
 384 };
 385
 386 enum mv88e6xxx_cap {
 387         /* Energy Efficient Ethernet.
 388          */
 389         MV88E6XXX_CAP_EEE,
 390
 391         /* Switch Global 2 Registers.
 392          * The device contains a second set of global 16-bit registers.
 393          */
 394         MV88E6XXX_CAP_GLOBAL2,
 395         MV88E6XXX_CAP_G2_MGMT_EN_2X,    /* (0x02) MGMT Enable Register 2x */
 396         MV88E6XXX_CAP_G2_MGMT_EN_0X,    /* (0x03) MGMT Enable Register 0x */
 397         MV88E6XXX_CAP_G2_IRL_CMD,       /* (0x09) Ingress Rate Command */
 398         MV88E6XXX_CAP_G2_IRL_DATA,      /* (0x0a) Ingress Rate Data */
 399         MV88E6XXX_CAP_G2_PVT_ADDR,      /* (0x0b) Cross Chip Port VLAN Addr */
 400         MV88E6XXX_CAP_G2_PVT_DATA,      /* (0x0c) Cross Chip Port VLAN Data */
 401         MV88E6XXX_CAP_G2_SWITCH_MAC,    /* (0x0d) Switch MAC/WoL/WoF */
 402         MV88E6XXX_CAP_G2_POT,           /* (0x0f) Priority Override Table */
 403         MV88E6XXX_CAP_G2_EEPROM_CMD,    /* (0x14) EEPROM Command */
 404         MV88E6XXX_CAP_G2_EEPROM_DATA,   /* (0x15) EEPROM Data */
 405
 406         /* Multi-chip Addressing Mode.
 407          * Some chips require an indirect SMI access when their SMI device
 408          * address is not zero. See SMI_CMD and SMI_DATA.
 409          */
 410         MV88E6XXX_CAP_MULTI_CHIP,
 411
 412         /* PHY Polling Unit.
 413          * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
 414          */
 415         MV88E6XXX_CAP_PPU,
 416         MV88E6XXX_CAP_PPU_ACTIVE,
 417
 418         /* SMI PHY Command and Data registers.
 419          * This requires an indirect access to PHY registers through
 420          * GLOBAL2_SMI_OP, otherwise direct access to PHY registers is done.
 421          */
 422         MV88E6XXX_CAP_SMI_PHY,
 423
 424         /* Per VLAN Spanning Tree Unit (STU).
 425          * The Port State database, if present, is accessed through VTU
 426          * operations and dedicated SID registers. See GLOBAL_VTU_SID.
 427          */
 428         MV88E6XXX_CAP_STU,
 429
 430         /* Internal temperature sensor.
 431          * Available from any enabled port's PHY register 26, page 6.
 432          */
 433         MV88E6XXX_CAP_TEMP,
 434         MV88E6XXX_CAP_TEMP_LIMIT,
 435
 436         /* VLAN Table Unit.
 437          * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP.
 438          */
 439         MV88E6XXX_CAP_VTU,
 440 };
 441
 442 /* Bitmask of capabilities */
 443 #define MV88E6XXX_FLAG_EEE              BIT(MV88E6XXX_CAP_EEE)
 444 #define MV88E6XXX_FLAG_GLOBAL2          BIT(MV88E6XXX_CAP_GLOBAL2)
 445 #define MV88E6XXX_FLAG_G2_MGMT_EN_2X    BIT(MV88E6XXX_CAP_G2_MGMT_EN_2X)
 446 #define MV88E6XXX_FLAG_G2_MGMT_EN_0X    BIT(MV88E6XXX_CAP_G2_MGMT_EN_0X)
 447 #define MV88E6XXX_FLAG_G2_IRL_CMD       BIT(MV88E6XXX_CAP_G2_IRL_CMD)
 448 #define MV88E6XXX_FLAG_G2_IRL_DATA      BIT(MV88E6XXX_CAP_G2_IRL_DATA)
 449 #define MV88E6XXX_FLAG_G2_PVT_ADDR      BIT(MV88E6XXX_CAP_G2_PVT_ADDR)
 450 #define MV88E6XXX_FLAG_G2_PVT_DATA      BIT(MV88E6XXX_CAP_G2_PVT_DATA)
 451 #define MV88E6XXX_FLAG_G2_SWITCH_MAC    BIT(MV88E6XXX_CAP_G2_SWITCH_MAC)
 452 #define MV88E6XXX_FLAG_G2_POT           BIT(MV88E6XXX_CAP_G2_POT)
 453 #define MV88E6XXX_FLAG_G2_EEPROM_CMD    BIT(MV88E6XXX_CAP_G2_EEPROM_CMD)
 454 #define MV88E6XXX_FLAG_G2_EEPROM_DATA   BIT(MV88E6XXX_CAP_G2_EEPROM_DATA)
 455 #define MV88E6XXX_FLAG_MULTI_CHIP       BIT(MV88E6XXX_CAP_MULTI_CHIP)
 456 #define MV88E6XXX_FLAG_PPU              BIT(MV88E6XXX_CAP_PPU)
 457 #define MV88E6XXX_FLAG_PPU_ACTIVE       BIT(MV88E6XXX_CAP_PPU_ACTIVE)
 458 #define MV88E6XXX_FLAG_SMI_PHY          BIT(MV88E6XXX_CAP_SMI_PHY)
 459 #define MV88E6XXX_FLAG_STU              BIT(MV88E6XXX_CAP_STU)
 460 #define MV88E6XXX_FLAG_TEMP             BIT(MV88E6XXX_CAP_TEMP)
 461 #define MV88E6XXX_FLAG_TEMP_LIMIT       BIT(MV88E6XXX_CAP_TEMP_LIMIT)
 462 #define MV88E6XXX_FLAG_VTU              BIT(MV88E6XXX_CAP_VTU)
 463
 464 /* EEPROM Programming via Global2 with 16-bit data */
 465 #define MV88E6XXX_FLAGS_EEPROM16        \
 466         (MV88E6XXX_FLAG_G2_EEPROM_CMD | \
 467          MV88E6XXX_FLAG_G2_EEPROM_DATA)
 468
 469 /* Ingress Rate Limit unit */
 470 #define MV88E6XXX_FLAGS_IRL             \
 471         (MV88E6XXX_FLAG_G2_IRL_CMD |    \
 472          MV88E6XXX_FLAG_G2_IRL_DATA)
 473
 474 /* Cross-chip Port VLAN Table */
 475 #define MV88E6XXX_FLAGS_PVT             \
 476         (MV88E6XXX_FLAG_G2_PVT_ADDR |   \
 477          MV88E6XXX_FLAG_G2_PVT_DATA)
 478
 479 #define MV88E6XXX_FLAGS_FAMILY_6095     \
 480         (MV88E6XXX_FLAG_GLOBAL2 |       \
 481          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 482          MV88E6XXX_FLAG_MULTI_CHIP |    \
 483          MV88E6XXX_FLAG_PPU |           \
 484          MV88E6XXX_FLAG_VTU)
 485
 486 #define MV88E6XXX_FLAGS_FAMILY_6097     \
 487         (MV88E6XXX_FLAG_GLOBAL2 |       \
 488          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 489          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 490          MV88E6XXX_FLAG_G2_POT |        \
 491          MV88E6XXX_FLAG_MULTI_CHIP |    \
 492          MV88E6XXX_FLAG_PPU |           \
 493          MV88E6XXX_FLAG_STU |           \
 494          MV88E6XXX_FLAG_VTU |           \
 495          MV88E6XXX_FLAGS_IRL |          \
 496          MV88E6XXX_FLAGS_PVT)
 497
 498 #define MV88E6XXX_FLAGS_FAMILY_6165     \
 499         (MV88E6XXX_FLAG_GLOBAL2 |       \
 500          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 501          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 502          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 503          MV88E6XXX_FLAG_G2_POT |        \
 504          MV88E6XXX_FLAG_MULTI_CHIP |    \
 505          MV88E6XXX_FLAG_STU |           \
 506          MV88E6XXX_FLAG_TEMP |          \
 507          MV88E6XXX_FLAG_VTU |           \
 508          MV88E6XXX_FLAGS_IRL |          \
 509          MV88E6XXX_FLAGS_PVT)
 510
 511 #define MV88E6XXX_FLAGS_FAMILY_6185     \
 512         (MV88E6XXX_FLAG_GLOBAL2 |       \
 513          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 514          MV88E6XXX_FLAG_MULTI_CHIP |    \
 515          MV88E6XXX_FLAG_PPU |           \
 516          MV88E6XXX_FLAG_VTU)
 517
 518 #define MV88E6XXX_FLAGS_FAMILY_6320     \
 519         (MV88E6XXX_FLAG_EEE |           \
 520          MV88E6XXX_FLAG_GLOBAL2 |       \
 521          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 522          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 523          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 524          MV88E6XXX_FLAG_G2_POT |        \
 525          MV88E6XXX_FLAG_MULTI_CHIP |    \
 526          MV88E6XXX_FLAG_PPU_ACTIVE |    \
 527          MV88E6XXX_FLAG_SMI_PHY |       \
 528          MV88E6XXX_FLAG_TEMP |          \
 529          MV88E6XXX_FLAG_TEMP_LIMIT |    \
 530          MV88E6XXX_FLAG_VTU |           \
 531          MV88E6XXX_FLAGS_EEPROM16 |     \
 532          MV88E6XXX_FLAGS_IRL |          \
 533          MV88E6XXX_FLAGS_PVT)
 534
 535 #define MV88E6XXX_FLAGS_FAMILY_6351     \
 536         (MV88E6XXX_FLAG_GLOBAL2 |       \
 537          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 538          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 539          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 540          MV88E6XXX_FLAG_G2_POT |        \
 541          MV88E6XXX_FLAG_MULTI_CHIP |    \
 542          MV88E6XXX_FLAG_PPU_ACTIVE |    \
 543          MV88E6XXX_FLAG_SMI_PHY |       \
 544          MV88E6XXX_FLAG_STU |           \
 545          MV88E6XXX_FLAG_TEMP |          \
 546          MV88E6XXX_FLAG_VTU |           \
 547          MV88E6XXX_FLAGS_IRL |          \
 548          MV88E6XXX_FLAGS_PVT)
 549
 550 #define MV88E6XXX_FLAGS_FAMILY_6352     \
 551         (MV88E6XXX_FLAG_EEE |           \
 552          MV88E6XXX_FLAG_GLOBAL2 |       \
 553          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 554          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 555          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 556          MV88E6XXX_FLAG_G2_POT |        \
 557          MV88E6XXX_FLAG_MULTI_CHIP |    \
 558          MV88E6XXX_FLAG_PPU_ACTIVE |    \
 559          MV88E6XXX_FLAG_SMI_PHY |       \
 560          MV88E6XXX_FLAG_STU |           \
 561          MV88E6XXX_FLAG_TEMP |          \
 562          MV88E6XXX_FLAG_TEMP_LIMIT |    \
 563          MV88E6XXX_FLAG_VTU |           \
 564          MV88E6XXX_FLAGS_EEPROM16 |     \
 565          MV88E6XXX_FLAGS_IRL |          \
 566          MV88E6XXX_FLAGS_PVT)
 567
 568 struct mv88e6xxx_info {
 569         enum mv88e6xxx_family family;
 570         u16 prod_num;
 571         const char *name;
 572         unsigned int num_databases;
 573         unsigned int num_ports;
 574         unsigned int port_base_addr;
 575         unsigned int age_time_coeff;
 576         unsigned long flags;
 577 };
 578
 579 struct mv88e6xxx_atu_entry {
 580         u16     fid;
 581         u8      state;
 582         bool    trunk;
 583         u16     portv_trunkid;
 584         u8      mac[ETH_ALEN];
 585 };
 586
 587 struct mv88e6xxx_vtu_stu_entry {
 588         /* VTU only */
 589         u16     vid;
 590         u16     fid;
 591
 592         /* VTU and STU */
 593         u8      sid;
 594         bool    valid;
 595         u8      data[DSA_MAX_PORTS];
 596 };
 597
 598 struct mv88e6xxx_ops;
 599
 600 struct mv88e6xxx_priv_port {
 601         struct net_device *bridge_dev;
 602 };
 603
 604 struct mv88e6xxx_chip {
 605         const struct mv88e6xxx_info *info;
 606
 607         /* The dsa_switch this private structure is related to */
 608         struct dsa_switch *ds;
 609
 610         /* The device this structure is associated to */
 611         struct device *dev;
 612
 613         /* This mutex protects the access to the switch registers */
 614         struct mutex reg_lock;
 615
 616         /* The MII bus and the address on the bus that is used to
 617          * communication with the switch
 618          */
 619         const struct mv88e6xxx_ops *smi_ops;
 620         struct mii_bus *bus;
 621         int sw_addr;
 622
 623         /* Handles automatic disabling and re-enabling of the PHY
 624          * polling unit.
 625          */
 626         struct mutex            ppu_mutex;
 627         int                     ppu_disabled;
 628         struct work_struct      ppu_work;
 629         struct timer_list       ppu_timer;
 630
 631         /* This mutex serialises access to the statistics unit.
 632          * Hold this mutex over snapshot + dump sequences.
 633          */
 634         struct mutex    stats_mutex;
 635
 636         struct mv88e6xxx_priv_port      ports[DSA_MAX_PORTS];
 637
 638         /* A switch may have a GPIO line tied to its reset pin. Parse
 639          * this from the device tree, and use it before performing
 640          * switch soft reset.
 641          */
 642         struct gpio_desc *reset;
 643
 644         /* set to size of eeprom if supported by the switch */
 645         int             eeprom_len;
 646
 647         /* Device node for the MDIO bus */
 648         struct device_node *mdio_np;
 649
 650         /* And the MDIO bus itself */
 651         struct mii_bus *mdio_bus;
 652 };
 653
 654 struct mv88e6xxx_ops {
 655         int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 656         int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 657 };
 658
 659 enum stat_type {
 660         BANK0,
 661         BANK1,
 662         PORT,
 663 };
 664
 665 struct mv88e6xxx_hw_stat {
 666         char string[ETH_GSTRING_LEN];
 667         int sizeof_stat;
 668         int reg;
 669         enum stat_type type;
 670 };
 671
 672 static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
 673                                  unsigned long flags)
 674 {
 675         return (chip->info->flags & flags) == flags;
 676 }
 677
 678 #endif