drivers/net/dsa/mv88e6xxx/mv88e6xxx.h

   1 /*
   2  * Marvell 88e6xxx common definitions
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #ifndef __MV88E6XXX_H
  13 #define __MV88E6XXX_H
  14
  15 #include <linux/if_vlan.h>
  16 #include <linux/gpio/consumer.h>
  17
  18 #ifndef UINT64_MAX
  19 #define UINT64_MAX              (u64)(~((u64)0))
  20 #endif
  21
  22 #define SMI_CMD                 0x00
  23 #define SMI_CMD_BUSY            BIT(15)
  24 #define SMI_CMD_CLAUSE_22       BIT(12)
  25 #define SMI_CMD_OP_22_WRITE     ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
  26 #define SMI_CMD_OP_22_READ      ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
  27 #define SMI_CMD_OP_45_WRITE_ADDR        ((0 << 10) | SMI_CMD_BUSY)
  28 #define SMI_CMD_OP_45_WRITE_DATA        ((1 << 10) | SMI_CMD_BUSY)
  29 #define SMI_CMD_OP_45_READ_DATA         ((2 << 10) | SMI_CMD_BUSY)
  30 #define SMI_CMD_OP_45_READ_DATA_INC     ((3 << 10) | SMI_CMD_BUSY)
  31 #define SMI_DATA                0x01
  32
  33 /* PHY Registers */
  34 #define PHY_PAGE                0x16
  35 #define PHY_PAGE_COPPER         0x00
  36
  37 #define ADDR_SERDES             0x0f
  38 #define SERDES_PAGE_FIBER       0x01
  39
  40 #define REG_PORT(p)             (0x10 + (p))
  41 #define PORT_STATUS             0x00
  42 #define PORT_STATUS_PAUSE_EN    BIT(15)
  43 #define PORT_STATUS_MY_PAUSE    BIT(14)
  44 #define PORT_STATUS_HD_FLOW     BIT(13)
  45 #define PORT_STATUS_PHY_DETECT  BIT(12)
  46 #define PORT_STATUS_LINK        BIT(11)
  47 #define PORT_STATUS_DUPLEX      BIT(10)
  48 #define PORT_STATUS_SPEED_MASK  0x0300
  49 #define PORT_STATUS_SPEED_10    0x0000
  50 #define PORT_STATUS_SPEED_100   0x0100
  51 #define PORT_STATUS_SPEED_1000  0x0200
  52 #define PORT_STATUS_EEE         BIT(6) /* 6352 */
  53 #define PORT_STATUS_AM_DIS      BIT(6) /* 6165 */
  54 #define PORT_STATUS_MGMII       BIT(6) /* 6185 */
  55 #define PORT_STATUS_TX_PAUSED   BIT(5)
  56 #define PORT_STATUS_FLOW_CTRL   BIT(4)
  57 #define PORT_STATUS_CMODE_MASK  0x0f
  58 #define PORT_STATUS_CMODE_100BASE_X     0x8
  59 #define PORT_STATUS_CMODE_1000BASE_X    0x9
  60 #define PORT_STATUS_CMODE_SGMII         0xa
  61 #define PORT_PCS_CTRL           0x01
  62 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
  63 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
  64 #define PORT_PCS_CTRL_FC                BIT(7)
  65 #define PORT_PCS_CTRL_FORCE_FC          BIT(6)
  66 #define PORT_PCS_CTRL_LINK_UP           BIT(5)
  67 #define PORT_PCS_CTRL_FORCE_LINK        BIT(4)
  68 #define PORT_PCS_CTRL_DUPLEX_FULL       BIT(3)
  69 #define PORT_PCS_CTRL_FORCE_DUPLEX      BIT(2)
  70 #define PORT_PCS_CTRL_10                0x00
  71 #define PORT_PCS_CTRL_100               0x01
  72 #define PORT_PCS_CTRL_1000              0x02
  73 #define PORT_PCS_CTRL_UNFORCED          0x03
  74 #define PORT_PAUSE_CTRL         0x02
  75 #define PORT_SWITCH_ID          0x03
  76 #define PORT_SWITCH_ID_PROD_NUM_6085    0x04a
  77 #define PORT_SWITCH_ID_PROD_NUM_6095    0x095
  78 #define PORT_SWITCH_ID_PROD_NUM_6131    0x106
  79 #define PORT_SWITCH_ID_PROD_NUM_6320    0x115
  80 #define PORT_SWITCH_ID_PROD_NUM_6123    0x121
  81 #define PORT_SWITCH_ID_PROD_NUM_6161    0x161
  82 #define PORT_SWITCH_ID_PROD_NUM_6165    0x165
  83 #define PORT_SWITCH_ID_PROD_NUM_6171    0x171
  84 #define PORT_SWITCH_ID_PROD_NUM_6172    0x172
  85 #define PORT_SWITCH_ID_PROD_NUM_6175    0x175
  86 #define PORT_SWITCH_ID_PROD_NUM_6176    0x176
  87 #define PORT_SWITCH_ID_PROD_NUM_6185    0x1a7
  88 #define PORT_SWITCH_ID_PROD_NUM_6240    0x240
  89 #define PORT_SWITCH_ID_PROD_NUM_6321    0x310
  90 #define PORT_SWITCH_ID_PROD_NUM_6352    0x352
  91 #define PORT_SWITCH_ID_PROD_NUM_6350    0x371
  92 #define PORT_SWITCH_ID_PROD_NUM_6351    0x375
  93 #define PORT_CONTROL            0x04
  94 #define PORT_CONTROL_USE_CORE_TAG       BIT(15)
  95 #define PORT_CONTROL_DROP_ON_LOCK       BIT(14)
  96 #define PORT_CONTROL_EGRESS_UNMODIFIED  (0x0 << 12)
  97 #define PORT_CONTROL_EGRESS_UNTAGGED    (0x1 << 12)
  98 #define PORT_CONTROL_EGRESS_TAGGED      (0x2 << 12)
  99 #define PORT_CONTROL_EGRESS_ADD_TAG     (0x3 << 12)
 100 #define PORT_CONTROL_HEADER             BIT(11)
 101 #define PORT_CONTROL_IGMP_MLD_SNOOP     BIT(10)
 102 #define PORT_CONTROL_DOUBLE_TAG         BIT(9)
 103 #define PORT_CONTROL_FRAME_MODE_NORMAL          (0x0 << 8)
 104 #define PORT_CONTROL_FRAME_MODE_DSA             (0x1 << 8)
 105 #define PORT_CONTROL_FRAME_MODE_PROVIDER        (0x2 << 8)
 106 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA       (0x3 << 8)
 107 #define PORT_CONTROL_DSA_TAG            BIT(8)
 108 #define PORT_CONTROL_VLAN_TUNNEL        BIT(7)
 109 #define PORT_CONTROL_TAG_IF_BOTH        BIT(6)
 110 #define PORT_CONTROL_USE_IP             BIT(5)
 111 #define PORT_CONTROL_USE_TAG            BIT(4)
 112 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
 113 #define PORT_CONTROL_FORWARD_UNKNOWN    BIT(2)
 114 #define PORT_CONTROL_STATE_MASK         0x03
 115 #define PORT_CONTROL_STATE_DISABLED     0x00
 116 #define PORT_CONTROL_STATE_BLOCKING     0x01
 117 #define PORT_CONTROL_STATE_LEARNING     0x02
 118 #define PORT_CONTROL_STATE_FORWARDING   0x03
 119 #define PORT_CONTROL_1          0x05
 120 #define PORT_CONTROL_1_FID_11_4_MASK    (0xff << 0)
 121 #define PORT_BASE_VLAN          0x06
 122 #define PORT_BASE_VLAN_FID_3_0_MASK     (0xf << 12)
 123 #define PORT_DEFAULT_VLAN       0x07
 124 #define PORT_DEFAULT_VLAN_MASK  0xfff
 125 #define PORT_CONTROL_2          0x08
 126 #define PORT_CONTROL_2_IGNORE_FCS       BIT(15)
 127 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
 128 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
 129 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
 130 #define PORT_CONTROL_2_JUMBO_1522       (0x00 << 12)
 131 #define PORT_CONTROL_2_JUMBO_2048       (0x01 << 12)
 132 #define PORT_CONTROL_2_JUMBO_10240      (0x02 << 12)
 133 #define PORT_CONTROL_2_8021Q_MASK       (0x03 << 10)
 134 #define PORT_CONTROL_2_8021Q_DISABLED   (0x00 << 10)
 135 #define PORT_CONTROL_2_8021Q_FALLBACK   (0x01 << 10)
 136 #define PORT_CONTROL_2_8021Q_CHECK      (0x02 << 10)
 137 #define PORT_CONTROL_2_8021Q_SECURE     (0x03 << 10)
 138 #define PORT_CONTROL_2_DISCARD_TAGGED   BIT(9)
 139 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
 140 #define PORT_CONTROL_2_MAP_DA           BIT(7)
 141 #define PORT_CONTROL_2_DEFAULT_FORWARD  BIT(6)
 142 #define PORT_CONTROL_2_FORWARD_UNKNOWN  BIT(6)
 143 #define PORT_CONTROL_2_EGRESS_MONITOR   BIT(5)
 144 #define PORT_CONTROL_2_INGRESS_MONITOR  BIT(4)
 145 #define PORT_RATE_CONTROL       0x09
 146 #define PORT_RATE_CONTROL_2     0x0a
 147 #define PORT_ASSOC_VECTOR       0x0b
 148 #define PORT_ASSOC_VECTOR_HOLD_AT_1             BIT(15)
 149 #define PORT_ASSOC_VECTOR_INT_AGE_OUT           BIT(14)
 150 #define PORT_ASSOC_VECTOR_LOCKED_PORT           BIT(13)
 151 #define PORT_ASSOC_VECTOR_IGNORE_WRONG          BIT(12)
 152 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED        BIT(11)
 153 #define PORT_ATU_CONTROL        0x0c
 154 #define PORT_PRI_OVERRIDE       0x0d
 155 #define PORT_ETH_TYPE           0x0f
 156 #define PORT_IN_DISCARD_LO      0x10
 157 #define PORT_IN_DISCARD_HI      0x11
 158 #define PORT_IN_FILTERED        0x12
 159 #define PORT_OUT_FILTERED       0x13
 160 #define PORT_TAG_REGMAP_0123    0x18
 161 #define PORT_TAG_REGMAP_4567    0x19
 162
 163 #define REG_GLOBAL              0x1b
 164 #define GLOBAL_STATUS           0x00
 165 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
 166 /* Two bits for 6165, 6185 etc */
 167 #define GLOBAL_STATUS_PPU_MASK          (0x3 << 14)
 168 #define GLOBAL_STATUS_PPU_DISABLED_RST  (0x0 << 14)
 169 #define GLOBAL_STATUS_PPU_INITIALIZING  (0x1 << 14)
 170 #define GLOBAL_STATUS_PPU_DISABLED      (0x2 << 14)
 171 #define GLOBAL_STATUS_PPU_POLLING       (0x3 << 14)
 172 #define GLOBAL_MAC_01           0x01
 173 #define GLOBAL_MAC_23           0x02
 174 #define GLOBAL_MAC_45           0x03
 175 #define GLOBAL_ATU_FID          0x01    /* 6097 6165 6351 6352 */
 176 #define GLOBAL_VTU_FID          0x02    /* 6097 6165 6351 6352 */
 177 #define GLOBAL_VTU_FID_MASK     0xfff
 178 #define GLOBAL_VTU_SID          0x03    /* 6097 6165 6351 6352 */
 179 #define GLOBAL_VTU_SID_MASK     0x3f
 180 #define GLOBAL_CONTROL          0x04
 181 #define GLOBAL_CONTROL_SW_RESET         BIT(15)
 182 #define GLOBAL_CONTROL_PPU_ENABLE       BIT(14)
 183 #define GLOBAL_CONTROL_DISCARD_EXCESS   BIT(13) /* 6352 */
 184 #define GLOBAL_CONTROL_SCHED_PRIO       BIT(11) /* 6152 */
 185 #define GLOBAL_CONTROL_MAX_FRAME_1632   BIT(10) /* 6152 */
 186 #define GLOBAL_CONTROL_RELOAD_EEPROM    BIT(9)  /* 6152 */
 187 #define GLOBAL_CONTROL_DEVICE_EN        BIT(7)
 188 #define GLOBAL_CONTROL_STATS_DONE_EN    BIT(6)
 189 #define GLOBAL_CONTROL_VTU_PROBLEM_EN   BIT(5)
 190 #define GLOBAL_CONTROL_VTU_DONE_EN      BIT(4)
 191 #define GLOBAL_CONTROL_ATU_PROBLEM_EN   BIT(3)
 192 #define GLOBAL_CONTROL_ATU_DONE_EN      BIT(2)
 193 #define GLOBAL_CONTROL_TCAM_EN          BIT(1)
 194 #define GLOBAL_CONTROL_EEPROM_DONE_EN   BIT(0)
 195 #define GLOBAL_VTU_OP           0x05
 196 #define GLOBAL_VTU_OP_BUSY      BIT(15)
 197 #define GLOBAL_VTU_OP_FLUSH_ALL         ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
 198 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE    ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
 199 #define GLOBAL_VTU_OP_VTU_GET_NEXT      ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
 200 #define GLOBAL_VTU_OP_STU_LOAD_PURGE    ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
 201 #define GLOBAL_VTU_OP_STU_GET_NEXT      ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
 202 #define GLOBAL_VTU_VID          0x06
 203 #define GLOBAL_VTU_VID_MASK     0xfff
 204 #define GLOBAL_VTU_VID_VALID    BIT(12)
 205 #define GLOBAL_VTU_DATA_0_3     0x07
 206 #define GLOBAL_VTU_DATA_4_7     0x08
 207 #define GLOBAL_VTU_DATA_8_11    0x09
 208 #define GLOBAL_VTU_STU_DATA_MASK                0x03
 209 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED   0x00
 210 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED     0x01
 211 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED       0x02
 212 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER   0x03
 213 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED     0x00
 214 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING     0x01
 215 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING     0x02
 216 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING   0x03
 217 #define GLOBAL_ATU_CONTROL      0x0a
 218 #define GLOBAL_ATU_CONTROL_LEARN2ALL    BIT(3)
 219 #define GLOBAL_ATU_OP           0x0b
 220 #define GLOBAL_ATU_OP_BUSY      BIT(15)
 221 #define GLOBAL_ATU_OP_NOP               (0 << 12)
 222 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL            ((1 << 12) | GLOBAL_ATU_OP_BUSY)
 223 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC     ((2 << 12) | GLOBAL_ATU_OP_BUSY)
 224 #define GLOBAL_ATU_OP_LOAD_DB           ((3 << 12) | GLOBAL_ATU_OP_BUSY)
 225 #define GLOBAL_ATU_OP_GET_NEXT_DB       ((4 << 12) | GLOBAL_ATU_OP_BUSY)
 226 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB         ((5 << 12) | GLOBAL_ATU_OP_BUSY)
 227 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
 228 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION   ((7 << 12) | GLOBAL_ATU_OP_BUSY)
 229 #define GLOBAL_ATU_DATA         0x0c
 230 #define GLOBAL_ATU_DATA_TRUNK                   BIT(15)
 231 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK           0x00f0
 232 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT          4
 233 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK        0x3ff0
 234 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT       4
 235 #define GLOBAL_ATU_DATA_STATE_MASK              0x0f
 236 #define GLOBAL_ATU_DATA_STATE_UNUSED            0x00
 237 #define GLOBAL_ATU_DATA_STATE_UC_MGMT           0x0d
 238 #define GLOBAL_ATU_DATA_STATE_UC_STATIC         0x0e
 239 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER      0x0f
 240 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE      0x05
 241 #define GLOBAL_ATU_DATA_STATE_MC_STATIC         0x07
 242 #define GLOBAL_ATU_DATA_STATE_MC_MGMT           0x0e
 243 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER      0x0f
 244 #define GLOBAL_ATU_MAC_01       0x0d
 245 #define GLOBAL_ATU_MAC_23       0x0e
 246 #define GLOBAL_ATU_MAC_45       0x0f
 247 #define GLOBAL_IP_PRI_0         0x10
 248 #define GLOBAL_IP_PRI_1         0x11
 249 #define GLOBAL_IP_PRI_2         0x12
 250 #define GLOBAL_IP_PRI_3         0x13
 251 #define GLOBAL_IP_PRI_4         0x14
 252 #define GLOBAL_IP_PRI_5         0x15
 253 #define GLOBAL_IP_PRI_6         0x16
 254 #define GLOBAL_IP_PRI_7         0x17
 255 #define GLOBAL_IEEE_PRI         0x18
 256 #define GLOBAL_CORE_TAG_TYPE    0x19
 257 #define GLOBAL_MONITOR_CONTROL  0x1a
 258 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT    12
 259 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT     8
 260 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT        4
 261 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT     0
 262 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED     (0xf0)
 263 #define GLOBAL_CONTROL_2        0x1c
 264 #define GLOBAL_CONTROL_2_NO_CASCADE             0xe000
 265 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE       0xf000
 266
 267 #define GLOBAL_STATS_OP         0x1d
 268 #define GLOBAL_STATS_OP_BUSY    BIT(15)
 269 #define GLOBAL_STATS_OP_NOP             (0 << 12)
 270 #define GLOBAL_STATS_OP_FLUSH_ALL       ((1 << 12) | GLOBAL_STATS_OP_BUSY)
 271 #define GLOBAL_STATS_OP_FLUSH_PORT      ((2 << 12) | GLOBAL_STATS_OP_BUSY)
 272 #define GLOBAL_STATS_OP_READ_CAPTURED   ((4 << 12) | GLOBAL_STATS_OP_BUSY)
 273 #define GLOBAL_STATS_OP_CAPTURE_PORT    ((5 << 12) | GLOBAL_STATS_OP_BUSY)
 274 #define GLOBAL_STATS_OP_HIST_RX         ((1 << 10) | GLOBAL_STATS_OP_BUSY)
 275 #define GLOBAL_STATS_OP_HIST_TX         ((2 << 10) | GLOBAL_STATS_OP_BUSY)
 276 #define GLOBAL_STATS_OP_HIST_RX_TX      ((3 << 10) | GLOBAL_STATS_OP_BUSY)
 277 #define GLOBAL_STATS_OP_BANK_1  BIT(9)
 278 #define GLOBAL_STATS_COUNTER_32 0x1e
 279 #define GLOBAL_STATS_COUNTER_01 0x1f
 280
 281 #define REG_GLOBAL2             0x1c
 282 #define GLOBAL2_INT_SOURCE      0x00
 283 #define GLOBAL2_INT_MASK        0x01
 284 #define GLOBAL2_MGMT_EN_2X      0x02
 285 #define GLOBAL2_MGMT_EN_0X      0x03
 286 #define GLOBAL2_FLOW_CONTROL    0x04
 287 #define GLOBAL2_SWITCH_MGMT     0x05
 288 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
 289 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS       BIT(14)
 290 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG    BIT(13)
 291 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
 292 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU            BIT(3)
 293 #define GLOBAL2_DEVICE_MAPPING  0x06
 294 #define GLOBAL2_DEVICE_MAPPING_UPDATE           BIT(15)
 295 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT     8
 296 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK        0x0f
 297 #define GLOBAL2_TRUNK_MASK      0x07
 298 #define GLOBAL2_TRUNK_MASK_UPDATE               BIT(15)
 299 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT            12
 300 #define GLOBAL2_TRUNK_MASK_HASK                 BIT(11)
 301 #define GLOBAL2_TRUNK_MAPPING   0x08
 302 #define GLOBAL2_TRUNK_MAPPING_UPDATE            BIT(15)
 303 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT          11
 304 #define GLOBAL2_IRL_CMD         0x09
 305 #define GLOBAL2_IRL_CMD_BUSY    BIT(15)
 306 #define GLOBAL2_IRL_CMD_OP_INIT_ALL     ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
 307 #define GLOBAL2_IRL_CMD_OP_INIT_SEL     ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
 308 #define GLOBAL2_IRL_CMD_OP_WRITE_SEL    ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
 309 #define GLOBAL2_IRL_CMD_OP_READ_SEL     ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
 310 #define GLOBAL2_IRL_DATA        0x0a
 311 #define GLOBAL2_PVT_ADDR        0x0b
 312 #define GLOBAL2_PVT_ADDR_BUSY   BIT(15)
 313 #define GLOBAL2_PVT_ADDR_OP_INIT_ONES   ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
 314 #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)
 315 #define GLOBAL2_PVT_ADDR_OP_READ        ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)
 316 #define GLOBAL2_PVT_DATA        0x0c
 317 #define GLOBAL2_SWITCH_MAC      0x0d
 318 #define GLOBAL2_ATU_STATS       0x0e
 319 #define GLOBAL2_PRIO_OVERRIDE   0x0f
 320 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP       BIT(7)
 321 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT       4
 322 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP         BIT(3)
 323 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT         0
 324 #define GLOBAL2_EEPROM_CMD              0x14
 325 #define GLOBAL2_EEPROM_CMD_BUSY         BIT(15)
 326 #define GLOBAL2_EEPROM_CMD_OP_WRITE     ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
 327 #define GLOBAL2_EEPROM_CMD_OP_READ      ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
 328 #define GLOBAL2_EEPROM_CMD_OP_LOAD      ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
 329 #define GLOBAL2_EEPROM_CMD_RUNNING      BIT(11)
 330 #define GLOBAL2_EEPROM_CMD_WRITE_EN     BIT(10)
 331 #define GLOBAL2_EEPROM_CMD_ADDR_MASK    0xff
 332 #define GLOBAL2_EEPROM_DATA     0x15
 333 #define GLOBAL2_PTP_AVB_OP      0x16
 334 #define GLOBAL2_PTP_AVB_DATA    0x17
 335 #define GLOBAL2_SMI_PHY_CMD                     0x18
 336 #define GLOBAL2_SMI_PHY_CMD_BUSY                BIT(15)
 337 #define GLOBAL2_SMI_PHY_CMD_MODE_22             BIT(12)
 338 #define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA    ((0x1 << 10) | \
 339                                                  GLOBAL2_SMI_PHY_CMD_MODE_22 | \
 340                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
 341 #define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA     ((0x2 << 10) | \
 342                                                  GLOBAL2_SMI_PHY_CMD_MODE_22 | \
 343                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
 344 #define GLOBAL2_SMI_PHY_DATA                    0x19
 345 #define GLOBAL2_SCRATCH_MISC    0x1a
 346 #define GLOBAL2_SCRATCH_BUSY            BIT(15)
 347 #define GLOBAL2_SCRATCH_REGISTER_SHIFT  8
 348 #define GLOBAL2_SCRATCH_VALUE_MASK      0xff
 349 #define GLOBAL2_WDOG_CONTROL    0x1b
 350 #define GLOBAL2_QOS_WEIGHT      0x1c
 351 #define GLOBAL2_MISC            0x1d
 352
 353 #define MV88E6XXX_N_FID         4096
 354
 355 /* List of supported models */
 356 enum mv88e6xxx_model {
 357         MV88E6085,
 358         MV88E6095,
 359         MV88E6123,
 360         MV88E6131,
 361         MV88E6161,
 362         MV88E6165,
 363         MV88E6171,
 364         MV88E6172,
 365         MV88E6175,
 366         MV88E6176,
 367         MV88E6185,
 368         MV88E6240,
 369         MV88E6320,
 370         MV88E6321,
 371         MV88E6350,
 372         MV88E6351,
 373         MV88E6352,
 374 };
 375
 376 enum mv88e6xxx_family {
 377         MV88E6XXX_FAMILY_NONE,
 378         MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
 379         MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
 380         MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
 381         MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
 382         MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
 383         MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
 384         MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
 385         MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
 386 };
 387
 388 enum mv88e6xxx_cap {
 389         /* Two different tag protocols can be used by the driver. All
 390          * switches support DSA, but only later generations support
 391          * EDSA.
 392          */
 393         MV88E6XXX_CAP_EDSA,
 394
 395         /* Energy Efficient Ethernet.
 396          */
 397         MV88E6XXX_CAP_EEE,
 398
 399         /* Multi-chip Addressing Mode.
 400          * Some chips respond to only 2 registers of its own SMI device address
 401          * when it is non-zero, and use indirect access to internal registers.
 402          */
 403         MV88E6XXX_CAP_SMI_CMD,          /* (0x00) SMI Command */
 404         MV88E6XXX_CAP_SMI_DATA,         /* (0x01) SMI Data */
 405
 406         /* PHY Registers.
 407          */
 408         MV88E6XXX_CAP_PHY_PAGE,         /* (0x16) Page Register */
 409
 410         /* Fiber/SERDES Registers (SMI address F).
 411          */
 412         MV88E6XXX_CAP_SERDES,
 413
 414         /* Switch Global 2 Registers.
 415          * The device contains a second set of global 16-bit registers.
 416          */
 417         MV88E6XXX_CAP_GLOBAL2,
 418         MV88E6XXX_CAP_G2_MGMT_EN_2X,    /* (0x02) MGMT Enable Register 2x */
 419         MV88E6XXX_CAP_G2_MGMT_EN_0X,    /* (0x03) MGMT Enable Register 0x */
 420         MV88E6XXX_CAP_G2_IRL_CMD,       /* (0x09) Ingress Rate Command */
 421         MV88E6XXX_CAP_G2_IRL_DATA,      /* (0x0a) Ingress Rate Data */
 422         MV88E6XXX_CAP_G2_PVT_ADDR,      /* (0x0b) Cross Chip Port VLAN Addr */
 423         MV88E6XXX_CAP_G2_PVT_DATA,      /* (0x0c) Cross Chip Port VLAN Data */
 424         MV88E6XXX_CAP_G2_SWITCH_MAC,    /* (0x0d) Switch MAC/WoL/WoF */
 425         MV88E6XXX_CAP_G2_POT,           /* (0x0f) Priority Override Table */
 426         MV88E6XXX_CAP_G2_EEPROM_CMD,    /* (0x14) EEPROM Command */
 427         MV88E6XXX_CAP_G2_EEPROM_DATA,   /* (0x15) EEPROM Data */
 428         MV88E6XXX_CAP_G2_SMI_PHY_CMD,   /* (0x18) SMI PHY Command */
 429         MV88E6XXX_CAP_G2_SMI_PHY_DATA,  /* (0x19) SMI PHY Data */
 430
 431         /* PHY Polling Unit.
 432          * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
 433          */
 434         MV88E6XXX_CAP_PPU,
 435         MV88E6XXX_CAP_PPU_ACTIVE,
 436
 437         /* Per VLAN Spanning Tree Unit (STU).
 438          * The Port State database, if present, is accessed through VTU
 439          * operations and dedicated SID registers. See GLOBAL_VTU_SID.
 440          */
 441         MV88E6XXX_CAP_STU,
 442
 443         /* Internal temperature sensor.
 444          * Available from any enabled port's PHY register 26, page 6.
 445          */
 446         MV88E6XXX_CAP_TEMP,
 447         MV88E6XXX_CAP_TEMP_LIMIT,
 448
 449         /* VLAN Table Unit.
 450          * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP.
 451          */
 452         MV88E6XXX_CAP_VTU,
 453 };
 454
 455 /* Bitmask of capabilities */
 456 #define MV88E6XXX_FLAG_EDSA             BIT(MV88E6XXX_CAP_EDSA)
 457 #define MV88E6XXX_FLAG_EEE              BIT(MV88E6XXX_CAP_EEE)
 458
 459 #define MV88E6XXX_FLAG_SMI_CMD          BIT(MV88E6XXX_CAP_SMI_CMD)
 460 #define MV88E6XXX_FLAG_SMI_DATA         BIT(MV88E6XXX_CAP_SMI_DATA)
 461
 462 #define MV88E6XXX_FLAG_PHY_PAGE         BIT(MV88E6XXX_CAP_PHY_PAGE)
 463
 464 #define MV88E6XXX_FLAG_SERDES           BIT(MV88E6XXX_CAP_SERDES)
 465
 466 #define MV88E6XXX_FLAG_GLOBAL2          BIT(MV88E6XXX_CAP_GLOBAL2)
 467 #define MV88E6XXX_FLAG_G2_MGMT_EN_2X    BIT(MV88E6XXX_CAP_G2_MGMT_EN_2X)
 468 #define MV88E6XXX_FLAG_G2_MGMT_EN_0X    BIT(MV88E6XXX_CAP_G2_MGMT_EN_0X)
 469 #define MV88E6XXX_FLAG_G2_IRL_CMD       BIT(MV88E6XXX_CAP_G2_IRL_CMD)
 470 #define MV88E6XXX_FLAG_G2_IRL_DATA      BIT(MV88E6XXX_CAP_G2_IRL_DATA)
 471 #define MV88E6XXX_FLAG_G2_PVT_ADDR      BIT(MV88E6XXX_CAP_G2_PVT_ADDR)
 472 #define MV88E6XXX_FLAG_G2_PVT_DATA      BIT(MV88E6XXX_CAP_G2_PVT_DATA)
 473 #define MV88E6XXX_FLAG_G2_SWITCH_MAC    BIT(MV88E6XXX_CAP_G2_SWITCH_MAC)
 474 #define MV88E6XXX_FLAG_G2_POT           BIT(MV88E6XXX_CAP_G2_POT)
 475 #define MV88E6XXX_FLAG_G2_EEPROM_CMD    BIT(MV88E6XXX_CAP_G2_EEPROM_CMD)
 476 #define MV88E6XXX_FLAG_G2_EEPROM_DATA   BIT(MV88E6XXX_CAP_G2_EEPROM_DATA)
 477 #define MV88E6XXX_FLAG_G2_SMI_PHY_CMD   BIT(MV88E6XXX_CAP_G2_SMI_PHY_CMD)
 478 #define MV88E6XXX_FLAG_G2_SMI_PHY_DATA  BIT(MV88E6XXX_CAP_G2_SMI_PHY_DATA)
 479
 480 #define MV88E6XXX_FLAG_PPU              BIT(MV88E6XXX_CAP_PPU)
 481 #define MV88E6XXX_FLAG_PPU_ACTIVE       BIT(MV88E6XXX_CAP_PPU_ACTIVE)
 482 #define MV88E6XXX_FLAG_STU              BIT(MV88E6XXX_CAP_STU)
 483 #define MV88E6XXX_FLAG_TEMP             BIT(MV88E6XXX_CAP_TEMP)
 484 #define MV88E6XXX_FLAG_TEMP_LIMIT       BIT(MV88E6XXX_CAP_TEMP_LIMIT)
 485 #define MV88E6XXX_FLAG_VTU              BIT(MV88E6XXX_CAP_VTU)
 486
 487 /* EEPROM Programming via Global2 with 16-bit data */
 488 #define MV88E6XXX_FLAGS_EEPROM16        \
 489         (MV88E6XXX_FLAG_G2_EEPROM_CMD | \
 490          MV88E6XXX_FLAG_G2_EEPROM_DATA)
 491
 492 /* Ingress Rate Limit unit */
 493 #define MV88E6XXX_FLAGS_IRL             \
 494         (MV88E6XXX_FLAG_G2_IRL_CMD |    \
 495          MV88E6XXX_FLAG_G2_IRL_DATA)
 496
 497 /* Multi-chip Addressing Mode */
 498 #define MV88E6XXX_FLAGS_MULTI_CHIP      \
 499         (MV88E6XXX_FLAG_SMI_CMD |       \
 500          MV88E6XXX_FLAG_SMI_DATA)
 501
 502 /* Cross-chip Port VLAN Table */
 503 #define MV88E6XXX_FLAGS_PVT             \
 504         (MV88E6XXX_FLAG_G2_PVT_ADDR |   \
 505          MV88E6XXX_FLAG_G2_PVT_DATA)
 506
 507 /* Fiber/SERDES Registers at SMI address F, page 1 */
 508 #define MV88E6XXX_FLAGS_SERDES          \
 509         (MV88E6XXX_FLAG_PHY_PAGE |      \
 510          MV88E6XXX_FLAG_SERDES)
 511
 512 /* Indirect PHY access via Global2 SMI PHY registers */
 513 #define MV88E6XXX_FLAGS_SMI_PHY         \
 514         (MV88E6XXX_FLAG_G2_SMI_PHY_CMD |\
 515          MV88E6XXX_FLAG_G2_SMI_PHY_DATA)
 516
 517 #define MV88E6XXX_FLAGS_FAMILY_6095     \
 518         (MV88E6XXX_FLAG_GLOBAL2 |       \
 519          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 520          MV88E6XXX_FLAG_PPU |           \
 521          MV88E6XXX_FLAG_VTU |           \
 522          MV88E6XXX_FLAGS_MULTI_CHIP)
 523
 524 #define MV88E6XXX_FLAGS_FAMILY_6097     \
 525         (MV88E6XXX_FLAG_GLOBAL2 |       \
 526          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 527          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 528          MV88E6XXX_FLAG_G2_POT |        \
 529          MV88E6XXX_FLAG_PPU |           \
 530          MV88E6XXX_FLAG_STU |           \
 531          MV88E6XXX_FLAG_VTU |           \
 532          MV88E6XXX_FLAGS_IRL |          \
 533          MV88E6XXX_FLAGS_MULTI_CHIP |   \
 534          MV88E6XXX_FLAGS_PVT)
 535
 536 #define MV88E6XXX_FLAGS_FAMILY_6165     \
 537         (MV88E6XXX_FLAG_GLOBAL2 |       \
 538          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 539          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 540          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 541          MV88E6XXX_FLAG_G2_POT |        \
 542          MV88E6XXX_FLAG_STU |           \
 543          MV88E6XXX_FLAG_TEMP |          \
 544          MV88E6XXX_FLAG_VTU |           \
 545          MV88E6XXX_FLAGS_IRL |          \
 546          MV88E6XXX_FLAGS_MULTI_CHIP |   \
 547          MV88E6XXX_FLAGS_PVT)
 548
 549 #define MV88E6XXX_FLAGS_FAMILY_6185     \
 550         (MV88E6XXX_FLAG_GLOBAL2 |       \
 551          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 552          MV88E6XXX_FLAGS_MULTI_CHIP |   \
 553          MV88E6XXX_FLAG_PPU |           \
 554          MV88E6XXX_FLAG_VTU)
 555
 556 #define MV88E6XXX_FLAGS_FAMILY_6320     \
 557         (MV88E6XXX_FLAG_EDSA |          \
 558          MV88E6XXX_FLAG_EEE |           \
 559          MV88E6XXX_FLAG_GLOBAL2 |       \
 560          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 561          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 562          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 563          MV88E6XXX_FLAG_G2_POT |        \
 564          MV88E6XXX_FLAG_PPU_ACTIVE |    \
 565          MV88E6XXX_FLAG_TEMP |          \
 566          MV88E6XXX_FLAG_TEMP_LIMIT |    \
 567          MV88E6XXX_FLAG_VTU |           \
 568          MV88E6XXX_FLAGS_EEPROM16 |     \
 569          MV88E6XXX_FLAGS_IRL |          \
 570          MV88E6XXX_FLAGS_MULTI_CHIP |   \
 571          MV88E6XXX_FLAGS_PVT |          \
 572          MV88E6XXX_FLAGS_SMI_PHY)
 573
 574 #define MV88E6XXX_FLAGS_FAMILY_6351     \
 575         (MV88E6XXX_FLAG_EDSA |          \
 576          MV88E6XXX_FLAG_GLOBAL2 |       \
 577          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 578          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 579          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 580          MV88E6XXX_FLAG_G2_POT |        \
 581          MV88E6XXX_FLAG_PPU_ACTIVE |    \
 582          MV88E6XXX_FLAG_STU |           \
 583          MV88E6XXX_FLAG_TEMP |          \
 584          MV88E6XXX_FLAG_VTU |           \
 585          MV88E6XXX_FLAGS_IRL |          \
 586          MV88E6XXX_FLAGS_MULTI_CHIP |   \
 587          MV88E6XXX_FLAGS_PVT |          \
 588          MV88E6XXX_FLAGS_SMI_PHY)
 589
 590 #define MV88E6XXX_FLAGS_FAMILY_6352     \
 591         (MV88E6XXX_FLAG_EDSA |          \
 592          MV88E6XXX_FLAG_EEE |           \
 593          MV88E6XXX_FLAG_GLOBAL2 |       \
 594          MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
 595          MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
 596          MV88E6XXX_FLAG_G2_SWITCH_MAC | \
 597          MV88E6XXX_FLAG_G2_POT |        \
 598          MV88E6XXX_FLAG_PPU_ACTIVE |    \
 599          MV88E6XXX_FLAG_STU |           \
 600          MV88E6XXX_FLAG_TEMP |          \
 601          MV88E6XXX_FLAG_TEMP_LIMIT |    \
 602          MV88E6XXX_FLAG_VTU |           \
 603          MV88E6XXX_FLAGS_EEPROM16 |     \
 604          MV88E6XXX_FLAGS_IRL |          \
 605          MV88E6XXX_FLAGS_MULTI_CHIP |   \
 606          MV88E6XXX_FLAGS_PVT |          \
 607          MV88E6XXX_FLAGS_SERDES |       \
 608          MV88E6XXX_FLAGS_SMI_PHY)
 609
 610 struct mv88e6xxx_info {
 611         enum mv88e6xxx_family family;
 612         u16 prod_num;
 613         const char *name;
 614         unsigned int num_databases;
 615         unsigned int num_ports;
 616         unsigned int port_base_addr;
 617         unsigned int age_time_coeff;
 618         unsigned long flags;
 619 };
 620
 621 struct mv88e6xxx_atu_entry {
 622         u16     fid;
 623         u8      state;
 624         bool    trunk;
 625         u16     portv_trunkid;
 626         u8      mac[ETH_ALEN];
 627 };
 628
 629 struct mv88e6xxx_vtu_stu_entry {
 630         /* VTU only */
 631         u16     vid;
 632         u16     fid;
 633
 634         /* VTU and STU */
 635         u8      sid;
 636         bool    valid;
 637         u8      data[DSA_MAX_PORTS];
 638 };
 639
 640 struct mv88e6xxx_ops;
 641
 642 struct mv88e6xxx_priv_port {
 643         struct net_device *bridge_dev;
 644 };
 645
 646 struct mv88e6xxx_chip {
 647         const struct mv88e6xxx_info *info;
 648
 649         /* The dsa_switch this private structure is related to */
 650         struct dsa_switch *ds;
 651
 652         /* The device this structure is associated to */
 653         struct device *dev;
 654
 655         /* This mutex protects the access to the switch registers */
 656         struct mutex reg_lock;
 657
 658         /* The MII bus and the address on the bus that is used to
 659          * communication with the switch
 660          */
 661         const struct mv88e6xxx_ops *smi_ops;
 662         struct mii_bus *bus;
 663         int sw_addr;
 664
 665         /* Handles automatic disabling and re-enabling of the PHY
 666          * polling unit.
 667          */
 668         const struct mv88e6xxx_ops *phy_ops;
 669         struct mutex            ppu_mutex;
 670         int                     ppu_disabled;
 671         struct work_struct      ppu_work;
 672         struct timer_list       ppu_timer;
 673
 674         /* This mutex serialises access to the statistics unit.
 675          * Hold this mutex over snapshot + dump sequences.
 676          */
 677         struct mutex    stats_mutex;
 678
 679         struct mv88e6xxx_priv_port      ports[DSA_MAX_PORTS];
 680
 681         /* A switch may have a GPIO line tied to its reset pin. Parse
 682          * this from the device tree, and use it before performing
 683          * switch soft reset.
 684          */
 685         struct gpio_desc *reset;
 686
 687         /* set to size of eeprom if supported by the switch */
 688         int             eeprom_len;
 689
 690         /* Device node for the MDIO bus */
 691         struct device_node *mdio_np;
 692
 693         /* And the MDIO bus itself */
 694         struct mii_bus *mdio_bus;
 695 };
 696
 697 struct mv88e6xxx_ops {
 698         int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 699         int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 700 };
 701
 702 enum stat_type {
 703         BANK0,
 704         BANK1,
 705         PORT,
 706 };
 707
 708 struct mv88e6xxx_hw_stat {
 709         char string[ETH_GSTRING_LEN];
 710         int sizeof_stat;
 711         int reg;
 712         enum stat_type type;
 713 };
 714
 715 static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
 716                                  unsigned long flags)
 717 {
 718         return (chip->info->flags & flags) == flags;
 719 }
 720
 721 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 722 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 723 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 724                      u16 update);
 725 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
 726
 727 #endif