drivers/net/ethernet/apm/xgene/xgene_enet_cle.h

   1 /* Applied Micro X-Gene SoC Ethernet Classifier structures
   2  *
   3  * Copyright (c) 2016, Applied Micro Circuits Corporation
   4  * Authors: Khuong Dinh <kdinh@apm.com>
   5  *          Tanmay Inamdar <tinamdar@apm.com>
   6  *          Iyappan Subramanian <isubramanian@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef __XGENE_ENET_CLE_H__
  23 #define __XGENE_ENET_CLE_H__
  24
  25 #include <linux/io.h>
  26 #include <linux/random.h>
  27
  28 /* Register offsets */
  29 #define INDADDR                 0x04
  30 #define INDCMD                  0x08
  31 #define INDCMD_STATUS           0x0c
  32 #define DATA_RAM0               0x10
  33 #define SNPTR0                  0x0100
  34 #define SPPTR0                  0x0104
  35 #define DFCLSRESDBPTR0          0x0108
  36 #define DFCLSRESDB00            0x010c
  37 #define RSS_CTRL0               0x0000013c
  38
  39 #define CLE_CMD_TO              10      /* ms */
  40 #define CLE_PKTRAM_SIZE         256     /* bytes */
  41 #define CLE_PORT_OFFSET         0x200
  42 #define CLE_DRAM_REGS           17
  43
  44 #define CLE_DN_TYPE_LEN         2
  45 #define CLE_DN_TYPE_POS         0
  46 #define CLE_DN_LASTN_LEN        1
  47 #define CLE_DN_LASTN_POS        2
  48 #define CLE_DN_HLS_LEN          1
  49 #define CLE_DN_HLS_POS          3
  50 #define CLE_DN_EXT_LEN          2
  51 #define CLE_DN_EXT_POS          4
  52 #define CLE_DN_BSTOR_LEN        2
  53 #define CLE_DN_BSTOR_POS        6
  54 #define CLE_DN_SBSTOR_LEN       2
  55 #define CLE_DN_SBSTOR_POS       8
  56 #define CLE_DN_RPTR_LEN         12
  57 #define CLE_DN_RPTR_POS         12
  58
  59 #define CLE_BR_VALID_LEN        1
  60 #define CLE_BR_VALID_POS        0
  61 #define CLE_BR_NPPTR_LEN        9
  62 #define CLE_BR_NPPTR_POS        1
  63 #define CLE_BR_JB_LEN           1
  64 #define CLE_BR_JB_POS           10
  65 #define CLE_BR_JR_LEN           1
  66 #define CLE_BR_JR_POS           11
  67 #define CLE_BR_OP_LEN           3
  68 #define CLE_BR_OP_POS           12
  69 #define CLE_BR_NNODE_LEN        9
  70 #define CLE_BR_NNODE_POS        15
  71 #define CLE_BR_NBR_LEN          5
  72 #define CLE_BR_NBR_POS          24
  73
  74 #define CLE_BR_DATA_LEN         16
  75 #define CLE_BR_DATA_POS         0
  76 #define CLE_BR_MASK_LEN         16
  77 #define CLE_BR_MASK_POS         16
  78
  79 #define CLE_KN_PRIO_POS         0
  80 #define CLE_KN_PRIO_LEN         3
  81 #define CLE_KN_RPTR_POS         3
  82 #define CLE_KN_RPTR_LEN         10
  83 #define CLE_TYPE_POS            0
  84 #define CLE_TYPE_LEN            2
  85
  86 #define CLE_DROP_POS            28
  87 #define CLE_DROP_LEN            1
  88 #define CLE_DSTQIDL_POS         25
  89 #define CLE_DSTQIDL_LEN         7
  90 #define CLE_DSTQIDH_POS         0
  91 #define CLE_DSTQIDH_LEN         5
  92 #define CLE_FPSEL_POS           21
  93 #define CLE_FPSEL_LEN           4
  94 #define CLE_PRIORITY_POS        5
  95 #define CLE_PRIORITY_LEN        3
  96
  97 #define JMP_ABS                 0
  98 #define JMP_REL                 1
  99 #define JMP_FW                  0
 100 #define JMP_BW                  1
 101
 102 enum xgene_cle_ptree_nodes {
 103         PKT_TYPE_NODE,
 104         PKT_PROT_NODE,
 105         RSS_IPV4_TCP_NODE,
 106         RSS_IPV4_UDP_NODE,
 107         LAST_NODE,
 108         MAX_NODES
 109 };
 110
 111 enum xgene_cle_byte_store {
 112         NO_BYTE,
 113         FIRST_BYTE,
 114         SECOND_BYTE,
 115         BOTH_BYTES
 116 };
 117
 118 /* Preclassification operation types */
 119 enum xgene_cle_node_type {
 120         INV,
 121         KN,
 122         EWDN,
 123         RES_NODE
 124 };
 125
 126 /* Preclassification operation types */
 127 enum xgene_cle_op_type {
 128         EQT,
 129         NEQT,
 130         LTEQT,
 131         GTEQT,
 132         AND,
 133         NAND
 134 };
 135
 136 enum xgene_cle_parser {
 137         PARSER0,
 138         PARSER1,
 139         PARSER2,
 140         PARSER_ALL
 141 };
 142
 143 #define XGENE_CLE_DRAM(type)    (((type) & 0xf) << 28)
 144 enum xgene_cle_dram_type {
 145         PKT_RAM,
 146         RSS_IDT,
 147         RSS_IPV4_HASH_SKEY,
 148         PTREE_RAM = 0xc,
 149         AVL_RAM,
 150         DB_RAM
 151 };
 152
 153 enum xgene_cle_cmd_type {
 154         CLE_CMD_WR = 1,
 155         CLE_CMD_RD = 2,
 156         CLE_CMD_AVL_ADD = 8,
 157         CLE_CMD_AVL_DEL = 16,
 158         CLE_CMD_AVL_SRCH = 32
 159 };
 160
 161 enum xgene_cle_ipv4_rss_hashtype {
 162         RSS_IPV4_8B,
 163         RSS_IPV4_12B,
 164 };
 165
 166 enum xgene_cle_prot_type {
 167         XGENE_CLE_TCP,
 168         XGENE_CLE_UDP,
 169         XGENE_CLE_ESP,
 170         XGENE_CLE_OTHER
 171 };
 172
 173 enum xgene_cle_prot_version {
 174         XGENE_CLE_IPV4,
 175 };
 176
 177 enum xgene_cle_ptree_dbptrs {
 178         DB_RES_DROP,
 179         DB_RES_DEF,
 180         DB_RES_ACCEPT,
 181         DB_MAX_PTRS
 182 };
 183
 184 /* RSS sideband signal info */
 185 #define SB_IPFRAG_POS   0
 186 #define SB_IPFRAG_LEN   1
 187 #define SB_IPPROT_POS   1
 188 #define SB_IPPROT_LEN   2
 189 #define SB_IPVER_POS    3
 190 #define SB_IPVER_LEN    1
 191 #define SB_HDRLEN_POS   4
 192 #define SB_HDRLEN_LEN   12
 193
 194 /* RSS indirection table */
 195 #define XGENE_CLE_IDT_ENTRIES   128
 196 #define IDT_DSTQID_POS          0
 197 #define IDT_DSTQID_LEN          12
 198 #define IDT_FPSEL_POS           12
 199 #define IDT_FPSEL_LEN           5
 200 #define IDT_NFPSEL_POS          17
 201 #define IDT_NFPSEL_LEN          5
 202 #define IDT_FPSEL1_POS          12
 203 #define IDT_FPSEL1_LEN          4
 204 #define IDT_NFPSEL1_POS         16
 205 #define IDT_NFPSEL1_LEN         4
 206
 207 struct xgene_cle_ptree_branch {
 208         bool valid;
 209         u16 next_packet_pointer;
 210         bool jump_bw;
 211         bool jump_rel;
 212         u8 operation;
 213         u16 next_node;
 214         u8 next_branch;
 215         u16 data;
 216         u16 mask;
 217 };
 218
 219 struct xgene_cle_ptree_ewdn {
 220         u8 node_type;
 221         bool last_node;
 222         bool hdr_len_store;
 223         u8 hdr_extn;
 224         u8 byte_store;
 225         u8 search_byte_store;
 226         u16 result_pointer;
 227         u8 num_branches;
 228         struct xgene_cle_ptree_branch branch[6];
 229 };
 230
 231 struct xgene_cle_ptree_key {
 232         u8 priority;
 233         u16 result_pointer;
 234 };
 235
 236 struct xgene_cle_ptree_kn {
 237         u8 node_type;
 238         u8 num_keys;
 239         struct xgene_cle_ptree_key key[32];
 240 };
 241
 242 struct xgene_cle_dbptr {
 243         u8 split_boundary;
 244         u8 mirror_nxtfpsel;
 245         u8 mirror_fpsel;
 246         u16 mirror_dstqid;
 247         u8 drop;
 248         u8 mirror;
 249         u8 hdr_data_split;
 250         u64 hopinfomsbs;
 251         u8 DR;
 252         u8 HR;
 253         u64 hopinfomlsbs;
 254         u16 h0enq_num;
 255         u8 h0fpsel;
 256         u8 nxtfpsel;
 257         u8 fpsel;
 258         u16 dstqid;
 259         u8 cle_priority;
 260         u8 cle_flowgroup;
 261         u8 cle_perflow;
 262         u8 cle_insert_timestamp;
 263         u8 stash;
 264         u8 in;
 265         u8 perprioen;
 266         u8 perflowgroupen;
 267         u8 perflowen;
 268         u8 selhash;
 269         u8 selhdrext;
 270         u8 mirror_nxtfpsel_msb;
 271         u8 mirror_fpsel_msb;
 272         u8 hfpsel_msb;
 273         u8 nxtfpsel_msb;
 274         u8 fpsel_msb;
 275 };
 276
 277 struct xgene_cle_ptree {
 278         struct xgene_cle_ptree_ewdn *dn;
 279         struct xgene_cle_ptree_kn *kn;
 280         struct xgene_cle_dbptr *dbptr;
 281         u32 num_dn;
 282         u32 num_kn;
 283         u32 num_dbptr;
 284         u32 start_node;
 285         u32 start_pkt;
 286         u32 start_dbptr;
 287 };
 288
 289 struct xgene_enet_cle {
 290         void __iomem *base;
 291         struct xgene_cle_ptree ptree;
 292         enum xgene_cle_parser active_parser;
 293         u32 parsers;
 294         u32 max_nodes;
 295         u32 max_dbptrs;
 296         u32 jump_bytes;
 297 };
 298
 299 extern const struct xgene_cle_ops xgene_cle3in_ops;
 300
 301 #endif /* __XGENE_ENET_CLE_H__ */