drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Keyur Chudgar <kchudgar@apm.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "xgene_enet_main.h"
  22 #include "xgene_enet_hw.h"
  23 #include "xgene_enet_xgmac.h"
  24
  25 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
  26                               u32 offset, u32 val)
  27 {
  28         void __iomem *addr = pdata->eth_csr_addr + offset;
  29
  30         iowrite32(val, addr);
  31 }
  32
  33 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
  34                                   u32 offset, u32 val)
  35 {
  36         void __iomem *addr = pdata->eth_ring_if_addr + offset;
  37
  38         iowrite32(val, addr);
  39 }
  40
  41 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
  42                                    u32 offset, u32 val)
  43 {
  44         void __iomem *addr = pdata->eth_diag_csr_addr + offset;
  45
  46         iowrite32(val, addr);
  47 }
  48
  49 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
  50                                    void __iomem *cmd, void __iomem *cmd_done,
  51                                    u32 wr_addr, u32 wr_data)
  52 {
  53         u32 done;
  54         u8 wait = 10;
  55
  56         iowrite32(wr_addr, addr);
  57         iowrite32(wr_data, wr);
  58         iowrite32(XGENE_ENET_WR_CMD, cmd);
  59
  60         /* wait for write command to complete */
  61         while (!(done = ioread32(cmd_done)) && wait--)
  62                 udelay(1);
  63
  64         if (!done)
  65                 return false;
  66
  67         iowrite32(0, cmd);
  68
  69         return true;
  70 }
  71
  72 static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
  73                               u32 wr_addr, u32 wr_data)
  74 {
  75         void __iomem *addr, *wr, *cmd, *cmd_done;
  76
  77         addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
  78         wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
  79         cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
  80         cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
  81
  82         if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
  83                 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
  84                            wr_addr);
  85 }
  86
  87 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
  88                               u32 offset, u32 *val)
  89 {
  90         void __iomem *addr = pdata->eth_csr_addr + offset;
  91
  92         *val = ioread32(addr);
  93 }
  94
  95 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
  96                                    u32 offset, u32 *val)
  97 {
  98         void __iomem *addr = pdata->eth_diag_csr_addr + offset;
  99
 100         *val = ioread32(addr);
 101 }
 102
 103 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
 104                                    void __iomem *cmd, void __iomem *cmd_done,
 105                                    u32 rd_addr, u32 *rd_data)
 106 {
 107         u32 done;
 108         u8 wait = 10;
 109
 110         iowrite32(rd_addr, addr);
 111         iowrite32(XGENE_ENET_RD_CMD, cmd);
 112
 113         /* wait for read command to complete */
 114         while (!(done = ioread32(cmd_done)) && wait--)
 115                 udelay(1);
 116
 117         if (!done)
 118                 return false;
 119
 120         *rd_data = ioread32(rd);
 121         iowrite32(0, cmd);
 122
 123         return true;
 124 }
 125 static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
 126                               u32 rd_addr, u32 *rd_data)
 127 {
 128         void __iomem *addr, *rd, *cmd, *cmd_done;
 129
 130         addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
 131         rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
 132         cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
 133         cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
 134
 135         if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
 136                 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
 137                            rd_addr);
 138 }
 139
 140 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
 141 {
 142         struct net_device *ndev = pdata->ndev;
 143         u32 data;
 144         u8 wait = 10;
 145
 146         xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
 147         do {
 148                 usleep_range(100, 110);
 149                 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
 150         } while ((data != 0xffffffff) && wait--);
 151
 152         if (data != 0xffffffff) {
 153                 netdev_err(ndev, "Failed to release memory from shutdown\n");
 154                 return -ENODEV;
 155         }
 156
 157         return 0;
 158 }
 159
 160 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
 161 {
 162         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
 163         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
 164         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
 165         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
 166 }
 167
 168 static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
 169 {
 170         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
 171         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
 172 }
 173
 174 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
 175 {
 176         u32 addr0, addr1;
 177         u8 *dev_addr = pdata->ndev->dev_addr;
 178
 179         addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
 180                 (dev_addr[1] << 8) | dev_addr[0];
 181         addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
 182
 183         xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
 184         xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
 185 }
 186
 187 static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata)
 188 {
 189         xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR, pdata->mss);
 190 }
 191
 192 static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
 193 {
 194         u32 data;
 195
 196         xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);
 197
 198         return data;
 199 }
 200
 201 static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
 202 {
 203         u32 data;
 204
 205         xgene_xgmac_reset(pdata);
 206
 207         xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
 208         data |= HSTPPEN;
 209         data &= ~HSTLENCHK;
 210         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
 211
 212         xgene_xgmac_set_mac_addr(pdata);
 213         xgene_xgmac_set_mss(pdata);
 214
 215         xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
 216         data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
 217         xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
 218
 219         xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
 220         xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
 221         xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
 222         data |= BIT(12);
 223         xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
 224         xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
 225 }
 226
 227 static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
 228 {
 229         u32 data;
 230
 231         xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
 232         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);
 233 }
 234
 235 static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
 236 {
 237         u32 data;
 238
 239         xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
 240         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);
 241 }
 242
 243 static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
 244 {
 245         u32 data;
 246
 247         xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
 248         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
 249 }
 250
 251 static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
 252 {
 253         u32 data;
 254
 255         xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
 256         xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
 257 }
 258
 259 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
 260 {
 261         struct device *dev = &pdata->pdev->dev;
 262
 263         if (!xgene_ring_mgr_init(pdata))
 264                 return -ENODEV;
 265
 266         if (dev->of_node) {
 267                 clk_prepare_enable(pdata->clk);
 268                 udelay(5);
 269                 clk_disable_unprepare(pdata->clk);
 270                 udelay(5);
 271                 clk_prepare_enable(pdata->clk);
 272                 udelay(5);
 273         } else {
 274 #ifdef CONFIG_ACPI
 275                 if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) {
 276                         acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
 277                                              "_RST", NULL, NULL);
 278                 } else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev),
 279                                            "_INI")) {
 280                         acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
 281                                              "_INI", NULL, NULL);
 282                 }
 283 #endif
 284         }
 285
 286         xgene_enet_ecc_init(pdata);
 287         xgene_enet_config_ring_if_assoc(pdata);
 288
 289         return 0;
 290 }
 291
 292 static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
 293                                     u32 dst_ring_num, u16 bufpool_id)
 294 {
 295         u32 cb, fpsel;
 296
 297         xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
 298         cb |= CFG_CLE_BYPASS_EN0;
 299         CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
 300         xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
 301
 302         fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
 303         xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
 304         CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
 305         CFG_CLE_FPSEL0_SET(&cb, fpsel);
 306         xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
 307 }
 308
 309 static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
 310 {
 311         struct device *dev = &pdata->pdev->dev;
 312         struct xgene_enet_desc_ring *ring;
 313         u32 pb, val;
 314         int i;
 315
 316         pb = 0;
 317         for (i = 0; i < pdata->rxq_cnt; i++) {
 318                 ring = pdata->rx_ring[i]->buf_pool;
 319
 320                 val = xgene_enet_ring_bufnum(ring->id);
 321                 pb |= BIT(val - 0x20);
 322         }
 323         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);
 324
 325         pb = 0;
 326         for (i = 0; i < pdata->txq_cnt; i++) {
 327                 ring = pdata->tx_ring[i];
 328
 329                 val = xgene_enet_ring_bufnum(ring->id);
 330                 pb |= BIT(val);
 331         }
 332         xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb);
 333
 334         if (dev->of_node) {
 335                 if (!IS_ERR(pdata->clk))
 336                         clk_disable_unprepare(pdata->clk);
 337         }
 338 }
 339
 340 static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
 341                              struct xgene_enet_desc_ring *ring)
 342 {
 343         u32 addr, val, data;
 344
 345         val = xgene_enet_ring_bufnum(ring->id);
 346
 347         if (xgene_enet_is_bufpool(ring->id)) {
 348                 addr = ENET_CFGSSQMIFPRESET_ADDR;
 349                 data = BIT(val - 0x20);
 350         } else {
 351                 addr = ENET_CFGSSQMIWQRESET_ADDR;
 352                 data = BIT(val);
 353         }
 354
 355         xgene_enet_wr_ring_if(pdata, addr, data);
 356 }
 357
 358 static void xgene_enet_link_state(struct work_struct *work)
 359 {
 360         struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
 361                                          struct xgene_enet_pdata, link_work);
 362         struct net_device *ndev = pdata->ndev;
 363         u32 link_status, poll_interval;
 364
 365         link_status = xgene_enet_link_status(pdata);
 366         if (link_status) {
 367                 if (!netif_carrier_ok(ndev)) {
 368                         netif_carrier_on(ndev);
 369                         xgene_xgmac_init(pdata);
 370                         xgene_xgmac_rx_enable(pdata);
 371                         xgene_xgmac_tx_enable(pdata);
 372                         netdev_info(ndev, "Link is Up - 10Gbps\n");
 373                 }
 374                 poll_interval = PHY_POLL_LINK_ON;
 375         } else {
 376                 if (netif_carrier_ok(ndev)) {
 377                         xgene_xgmac_rx_disable(pdata);
 378                         xgene_xgmac_tx_disable(pdata);
 379                         netif_carrier_off(ndev);
 380                         netdev_info(ndev, "Link is Down\n");
 381                 }
 382                 poll_interval = PHY_POLL_LINK_OFF;
 383         }
 384
 385         schedule_delayed_work(&pdata->link_work, poll_interval);
 386 }
 387
 388 const struct xgene_mac_ops xgene_xgmac_ops = {
 389         .init = xgene_xgmac_init,
 390         .reset = xgene_xgmac_reset,
 391         .rx_enable = xgene_xgmac_rx_enable,
 392         .tx_enable = xgene_xgmac_tx_enable,
 393         .rx_disable = xgene_xgmac_rx_disable,
 394         .tx_disable = xgene_xgmac_tx_disable,
 395         .set_mac_addr = xgene_xgmac_set_mac_addr,
 396         .set_mss = xgene_xgmac_set_mss,
 397         .link_state = xgene_enet_link_state
 398 };
 399
 400 const struct xgene_port_ops xgene_xgport_ops = {
 401         .reset = xgene_enet_reset,
 402         .clear = xgene_enet_clear,
 403         .cle_bypass = xgene_enet_xgcle_bypass,
 404         .shutdown = xgene_enet_shutdown,
 405 };