drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Keyur Chudgar <kchudgar@apm.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __XGENE_ENET_XGMAC_H__
  22 #define __XGENE_ENET_XGMAC_H__
  23
  24 #define X2_BLOCK_ETH_MAC_CSR_OFFSET     0x3000
  25 #define BLOCK_AXG_MAC_OFFSET            0x0800
  26 #define BLOCK_AXG_MAC_CSR_OFFSET        0x2000
  27 #define BLOCK_PCS_OFFSET                0x3800
  28
  29 #define XGENET_CONFIG_REG_ADDR          0x20
  30 #define XGENET_SRST_ADDR                0x00
  31 #define XGENET_CLKEN_ADDR               0x08
  32
  33 #define CSR_CLK         BIT(0)
  34 #define XGENET_CLK      BIT(1)
  35 #define PCS_CLK         BIT(3)
  36 #define AN_REF_CLK      BIT(4)
  37 #define AN_CLK          BIT(5)
  38 #define AD_CLK          BIT(6)
  39
  40 #define CSR_RST         BIT(0)
  41 #define XGENET_RST      BIT(1)
  42 #define PCS_RST         BIT(3)
  43 #define AN_REF_RST      BIT(4)
  44 #define AN_RST          BIT(5)
  45 #define AD_RST          BIT(6)
  46
  47 #define AXGMAC_CONFIG_0                 0x0000
  48 #define AXGMAC_CONFIG_1                 0x0004
  49 #define HSTMACRST                       BIT(31)
  50 #define HSTTCTLEN                       BIT(31)
  51 #define HSTTFEN                         BIT(30)
  52 #define HSTRCTLEN                       BIT(29)
  53 #define HSTRFEN                         BIT(28)
  54 #define HSTPPEN                         BIT(7)
  55 #define HSTDRPLT64                      BIT(5)
  56 #define HSTLENCHK                       BIT(3)
  57 #define HSTMACADR_LSW_ADDR              0x0010
  58 #define HSTMACADR_MSW_ADDR              0x0014
  59 #define HSTMAXFRAME_LENGTH_ADDR         0x0020
  60
  61 #define XG_MCX_RX_DV_GATE_REG_0_ADDR    0x0004
  62 #define XG_RSIF_CONFIG_REG_ADDR         0x00a0
  63 #define XCLE_BYPASS_REG0_ADDR           0x0160
  64 #define XCLE_BYPASS_REG1_ADDR           0x0164
  65 #define XG_CFG_BYPASS_ADDR              0x0204
  66 #define XG_CFG_LINK_AGGR_RESUME_0_ADDR  0x0214
  67 #define XG_LINK_STATUS_ADDR             0x0228
  68 #define XG_TSIF_MSS_REG0_ADDR           0x02a4
  69 #define XG_DEBUG_REG_ADDR               0x0400
  70 #define XG_ENET_SPARE_CFG_REG_ADDR      0x040c
  71 #define XG_ENET_SPARE_CFG_REG_1_ADDR    0x0410
  72 #define XGENET_RX_DV_GATE_REG_0_ADDR    0x0804
  73 #define XG_MCX_ICM_CONFIG0_REG_0_ADDR   0x00e0
  74 #define XG_MCX_ICM_CONFIG2_REG_0_ADDR   0x00e8
  75
  76 #define PCS_CONTROL_1                   0x0000
  77 #define PCS_CTRL_PCS_RST                BIT(15)
  78
  79 extern const struct xgene_mac_ops xgene_xgmac_ops;
  80 extern const struct xgene_port_ops xgene_xgport_ops;
  81
  82 #endif /* __XGENE_ENET_XGMAC_H__ */