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arm/xen: fix SMP guests boot
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bcmsysport.c
1 /*
2 * Broadcom BCM7xxx System Port Ethernet MAC driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/of.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/phy.h>
24 #include <linux/phy_fixed.h>
25 #include <net/ip.h>
26 #include <net/ipv6.h>
27
28 #include "bcmsysport.h"
29
30 /* I/O accessors register helpers */
31 #define BCM_SYSPORT_IO_MACRO(name, offset) \
32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
33 { \
34 u32 reg = __raw_readl(priv->base + offset + off); \
35 return reg; \
36 } \
37 static inline void name##_writel(struct bcm_sysport_priv *priv, \
38 u32 val, u32 off) \
39 { \
40 __raw_writel(val, priv->base + offset + off); \
41 } \
42
43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
46 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
47 BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET);
48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
53
54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
56 */
57 #define BCM_SYSPORT_INTR_L2(which) \
58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
59 u32 mask) \
60 { \
61 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
62 priv->irq##which##_mask &= ~(mask); \
63 } \
64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
65 u32 mask) \
66 { \
67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
68 priv->irq##which##_mask |= (mask); \
69 } \
70
71 BCM_SYSPORT_INTR_L2(0)
72 BCM_SYSPORT_INTR_L2(1)
73
74 /* Register accesses to GISB/RBUS registers are expensive (few hundred
75 * nanoseconds), so keep the check for 64-bits explicit here to save
76 * one register write per-packet on 32-bits platforms.
77 */
78 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
79 void __iomem *d,
80 dma_addr_t addr)
81 {
82 #ifdef CONFIG_PHYS_ADDR_T_64BIT
83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
84 d + DESC_ADDR_HI_STATUS_LEN);
85 #endif
86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO);
87 }
88
89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
90 struct dma_desc *desc,
91 unsigned int port)
92 {
93 /* Ports are latched, so write upper address first */
94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
96 }
97
98 /* Ethtool operations */
99 static int bcm_sysport_set_rx_csum(struct net_device *dev,
100 netdev_features_t wanted)
101 {
102 struct bcm_sysport_priv *priv = netdev_priv(dev);
103 u32 reg;
104
105 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
106 reg = rxchk_readl(priv, RXCHK_CONTROL);
107 if (priv->rx_chk_en)
108 reg |= RXCHK_EN;
109 else
110 reg &= ~RXCHK_EN;
111
112 /* If UniMAC forwards CRC, we need to skip over it to get
113 * a valid CHK bit to be set in the per-packet status word
114 */
115 if (priv->rx_chk_en && priv->crc_fwd)
116 reg |= RXCHK_SKIP_FCS;
117 else
118 reg &= ~RXCHK_SKIP_FCS;
119
120 /* If Broadcom tags are enabled (e.g: using a switch), make
121 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
122 * tag after the Ethernet MAC Source Address.
123 */
124 if (netdev_uses_dsa(dev))
125 reg |= RXCHK_BRCM_TAG_EN;
126 else
127 reg &= ~RXCHK_BRCM_TAG_EN;
128
129 rxchk_writel(priv, reg, RXCHK_CONTROL);
130
131 return 0;
132 }
133
134 static int bcm_sysport_set_tx_csum(struct net_device *dev,
135 netdev_features_t wanted)
136 {
137 struct bcm_sysport_priv *priv = netdev_priv(dev);
138 u32 reg;
139
140 /* Hardware transmit checksum requires us to enable the Transmit status
141 * block prepended to the packet contents
142 */
143 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
144 reg = tdma_readl(priv, TDMA_CONTROL);
145 if (priv->tsb_en)
146 reg |= TSB_EN;
147 else
148 reg &= ~TSB_EN;
149 tdma_writel(priv, reg, TDMA_CONTROL);
150
151 return 0;
152 }
153
154 static int bcm_sysport_set_features(struct net_device *dev,
155 netdev_features_t features)
156 {
157 netdev_features_t changed = features ^ dev->features;
158 netdev_features_t wanted = dev->wanted_features;
159 int ret = 0;
160
161 if (changed & NETIF_F_RXCSUM)
162 ret = bcm_sysport_set_rx_csum(dev, wanted);
163 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
164 ret = bcm_sysport_set_tx_csum(dev, wanted);
165
166 return ret;
167 }
168
169 /* Hardware counters must be kept in sync because the order/offset
170 * is important here (order in structure declaration = order in hardware)
171 */
172 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
173 /* general stats */
174 STAT_NETDEV(rx_packets),
175 STAT_NETDEV(tx_packets),
176 STAT_NETDEV(rx_bytes),
177 STAT_NETDEV(tx_bytes),
178 STAT_NETDEV(rx_errors),
179 STAT_NETDEV(tx_errors),
180 STAT_NETDEV(rx_dropped),
181 STAT_NETDEV(tx_dropped),
182 STAT_NETDEV(multicast),
183 /* UniMAC RSV counters */
184 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
185 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
186 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
187 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
188 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
189 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
190 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
191 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
192 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
193 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
194 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
195 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
196 STAT_MIB_RX("rx_multicast", mib.rx.mca),
197 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
198 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
199 STAT_MIB_RX("rx_control", mib.rx.cf),
200 STAT_MIB_RX("rx_pause", mib.rx.pf),
201 STAT_MIB_RX("rx_unknown", mib.rx.uo),
202 STAT_MIB_RX("rx_align", mib.rx.aln),
203 STAT_MIB_RX("rx_outrange", mib.rx.flr),
204 STAT_MIB_RX("rx_code", mib.rx.cde),
205 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
206 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
207 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
208 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
209 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
210 STAT_MIB_RX("rx_unicast", mib.rx.uc),
211 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
212 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
213 /* UniMAC TSV counters */
214 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
215 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
216 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
217 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
218 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
219 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
220 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
221 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
222 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
223 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
224 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
225 STAT_MIB_TX("tx_multicast", mib.tx.mca),
226 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
227 STAT_MIB_TX("tx_pause", mib.tx.pf),
228 STAT_MIB_TX("tx_control", mib.tx.cf),
229 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
230 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
231 STAT_MIB_TX("tx_defer", mib.tx.drf),
232 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
233 STAT_MIB_TX("tx_single_col", mib.tx.scl),
234 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
235 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
236 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
237 STAT_MIB_TX("tx_frags", mib.tx.frg),
238 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
239 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
240 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
241 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
242 STAT_MIB_TX("tx_unicast", mib.tx.uc),
243 /* UniMAC RUNT counters */
244 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
245 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
246 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
247 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
248 /* RXCHK misc statistics */
249 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
250 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
251 RXCHK_OTHER_DISC_CNTR),
252 /* RBUF misc statistics */
253 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
254 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
255 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
256 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
257 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
258 };
259
260 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
261
262 static void bcm_sysport_get_drvinfo(struct net_device *dev,
263 struct ethtool_drvinfo *info)
264 {
265 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
266 strlcpy(info->version, "0.1", sizeof(info->version));
267 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
268 }
269
270 static u32 bcm_sysport_get_msglvl(struct net_device *dev)
271 {
272 struct bcm_sysport_priv *priv = netdev_priv(dev);
273
274 return priv->msg_enable;
275 }
276
277 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
278 {
279 struct bcm_sysport_priv *priv = netdev_priv(dev);
280
281 priv->msg_enable = enable;
282 }
283
284 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
285 {
286 switch (string_set) {
287 case ETH_SS_STATS:
288 return BCM_SYSPORT_STATS_LEN;
289 default:
290 return -EOPNOTSUPP;
291 }
292 }
293
294 static void bcm_sysport_get_strings(struct net_device *dev,
295 u32 stringset, u8 *data)
296 {
297 int i;
298
299 switch (stringset) {
300 case ETH_SS_STATS:
301 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
302 memcpy(data + i * ETH_GSTRING_LEN,
303 bcm_sysport_gstrings_stats[i].stat_string,
304 ETH_GSTRING_LEN);
305 }
306 break;
307 default:
308 break;
309 }
310 }
311
312 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
313 {
314 int i, j = 0;
315
316 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
317 const struct bcm_sysport_stats *s;
318 u8 offset = 0;
319 u32 val = 0;
320 char *p;
321
322 s = &bcm_sysport_gstrings_stats[i];
323 switch (s->type) {
324 case BCM_SYSPORT_STAT_NETDEV:
325 case BCM_SYSPORT_STAT_SOFT:
326 continue;
327 case BCM_SYSPORT_STAT_MIB_RX:
328 case BCM_SYSPORT_STAT_MIB_TX:
329 case BCM_SYSPORT_STAT_RUNT:
330 if (s->type != BCM_SYSPORT_STAT_MIB_RX)
331 offset = UMAC_MIB_STAT_OFFSET;
332 val = umac_readl(priv, UMAC_MIB_START + j + offset);
333 break;
334 case BCM_SYSPORT_STAT_RXCHK:
335 val = rxchk_readl(priv, s->reg_offset);
336 if (val == ~0)
337 rxchk_writel(priv, 0, s->reg_offset);
338 break;
339 case BCM_SYSPORT_STAT_RBUF:
340 val = rbuf_readl(priv, s->reg_offset);
341 if (val == ~0)
342 rbuf_writel(priv, 0, s->reg_offset);
343 break;
344 }
345
346 j += s->stat_sizeof;
347 p = (char *)priv + s->stat_offset;
348 *(u32 *)p = val;
349 }
350
351 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
352 }
353
354 static void bcm_sysport_get_stats(struct net_device *dev,
355 struct ethtool_stats *stats, u64 *data)
356 {
357 struct bcm_sysport_priv *priv = netdev_priv(dev);
358 int i;
359
360 if (netif_running(dev))
361 bcm_sysport_update_mib_counters(priv);
362
363 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
364 const struct bcm_sysport_stats *s;
365 char *p;
366
367 s = &bcm_sysport_gstrings_stats[i];
368 if (s->type == BCM_SYSPORT_STAT_NETDEV)
369 p = (char *)&dev->stats;
370 else
371 p = (char *)priv;
372 p += s->stat_offset;
373 data[i] = *(unsigned long *)p;
374 }
375 }
376
377 static void bcm_sysport_get_wol(struct net_device *dev,
378 struct ethtool_wolinfo *wol)
379 {
380 struct bcm_sysport_priv *priv = netdev_priv(dev);
381 u32 reg;
382
383 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
384 wol->wolopts = priv->wolopts;
385
386 if (!(priv->wolopts & WAKE_MAGICSECURE))
387 return;
388
389 /* Return the programmed SecureOn password */
390 reg = umac_readl(priv, UMAC_PSW_MS);
391 put_unaligned_be16(reg, &wol->sopass[0]);
392 reg = umac_readl(priv, UMAC_PSW_LS);
393 put_unaligned_be32(reg, &wol->sopass[2]);
394 }
395
396 static int bcm_sysport_set_wol(struct net_device *dev,
397 struct ethtool_wolinfo *wol)
398 {
399 struct bcm_sysport_priv *priv = netdev_priv(dev);
400 struct device *kdev = &priv->pdev->dev;
401 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE;
402
403 if (!device_can_wakeup(kdev))
404 return -ENOTSUPP;
405
406 if (wol->wolopts & ~supported)
407 return -EINVAL;
408
409 /* Program the SecureOn password */
410 if (wol->wolopts & WAKE_MAGICSECURE) {
411 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
412 UMAC_PSW_MS);
413 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
414 UMAC_PSW_LS);
415 }
416
417 /* Flag the device and relevant IRQ as wakeup capable */
418 if (wol->wolopts) {
419 device_set_wakeup_enable(kdev, 1);
420 if (priv->wol_irq_disabled)
421 enable_irq_wake(priv->wol_irq);
422 priv->wol_irq_disabled = 0;
423 } else {
424 device_set_wakeup_enable(kdev, 0);
425 /* Avoid unbalanced disable_irq_wake calls */
426 if (!priv->wol_irq_disabled)
427 disable_irq_wake(priv->wol_irq);
428 priv->wol_irq_disabled = 1;
429 }
430
431 priv->wolopts = wol->wolopts;
432
433 return 0;
434 }
435
436 static int bcm_sysport_get_coalesce(struct net_device *dev,
437 struct ethtool_coalesce *ec)
438 {
439 struct bcm_sysport_priv *priv = netdev_priv(dev);
440 u32 reg;
441
442 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
443
444 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
445 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
446
447 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
448
449 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
450 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
451
452 return 0;
453 }
454
455 static int bcm_sysport_set_coalesce(struct net_device *dev,
456 struct ethtool_coalesce *ec)
457 {
458 struct bcm_sysport_priv *priv = netdev_priv(dev);
459 unsigned int i;
460 u32 reg;
461
462 /* Base system clock is 125Mhz, DMA timeout is this reference clock
463 * divided by 1024, which yield roughly 8.192 us, our maximum value has
464 * to fit in the RING_TIMEOUT_MASK (16 bits).
465 */
466 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
467 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
468 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
469 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
470 return -EINVAL;
471
472 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
473 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
474 return -EINVAL;
475
476 for (i = 0; i < dev->num_tx_queues; i++) {
477 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i));
478 reg &= ~(RING_INTR_THRESH_MASK |
479 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
480 reg |= ec->tx_max_coalesced_frames;
481 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
482 RING_TIMEOUT_SHIFT;
483 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i));
484 }
485
486 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
487 reg &= ~(RDMA_INTR_THRESH_MASK |
488 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
489 reg |= ec->rx_max_coalesced_frames;
490 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) <<
491 RDMA_TIMEOUT_SHIFT;
492 rdma_writel(priv, reg, RDMA_MBDONE_INTR);
493
494 return 0;
495 }
496
497 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
498 {
499 dev_kfree_skb_any(cb->skb);
500 cb->skb = NULL;
501 dma_unmap_addr_set(cb, dma_addr, 0);
502 }
503
504 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
505 struct bcm_sysport_cb *cb)
506 {
507 struct device *kdev = &priv->pdev->dev;
508 struct net_device *ndev = priv->netdev;
509 struct sk_buff *skb, *rx_skb;
510 dma_addr_t mapping;
511
512 /* Allocate a new SKB for a new packet */
513 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH);
514 if (!skb) {
515 priv->mib.alloc_rx_buff_failed++;
516 netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
517 return NULL;
518 }
519
520 mapping = dma_map_single(kdev, skb->data,
521 RX_BUF_LENGTH, DMA_FROM_DEVICE);
522 if (dma_mapping_error(kdev, mapping)) {
523 priv->mib.rx_dma_failed++;
524 dev_kfree_skb_any(skb);
525 netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
526 return NULL;
527 }
528
529 /* Grab the current SKB on the ring */
530 rx_skb = cb->skb;
531 if (likely(rx_skb))
532 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
533 RX_BUF_LENGTH, DMA_FROM_DEVICE);
534
535 /* Put the new SKB on the ring */
536 cb->skb = skb;
537 dma_unmap_addr_set(cb, dma_addr, mapping);
538 dma_desc_set_addr(priv, cb->bd_addr, mapping);
539
540 netif_dbg(priv, rx_status, ndev, "RX refill\n");
541
542 /* Return the current SKB to the caller */
543 return rx_skb;
544 }
545
546 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
547 {
548 struct bcm_sysport_cb *cb;
549 struct sk_buff *skb;
550 unsigned int i;
551
552 for (i = 0; i < priv->num_rx_bds; i++) {
553 cb = &priv->rx_cbs[i];
554 skb = bcm_sysport_rx_refill(priv, cb);
555 if (skb)
556 dev_kfree_skb(skb);
557 if (!cb->skb)
558 return -ENOMEM;
559 }
560
561 return 0;
562 }
563
564 /* Poll the hardware for up to budget packets to process */
565 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
566 unsigned int budget)
567 {
568 struct net_device *ndev = priv->netdev;
569 unsigned int processed = 0, to_process;
570 struct bcm_sysport_cb *cb;
571 struct sk_buff *skb;
572 unsigned int p_index;
573 u16 len, status;
574 struct bcm_rsb *rsb;
575
576 /* Determine how much we should process since last call */
577 p_index = rdma_readl(priv, RDMA_PROD_INDEX);
578 p_index &= RDMA_PROD_INDEX_MASK;
579
580 if (p_index < priv->rx_c_index)
581 to_process = (RDMA_CONS_INDEX_MASK + 1) -
582 priv->rx_c_index + p_index;
583 else
584 to_process = p_index - priv->rx_c_index;
585
586 netif_dbg(priv, rx_status, ndev,
587 "p_index=%d rx_c_index=%d to_process=%d\n",
588 p_index, priv->rx_c_index, to_process);
589
590 while ((processed < to_process) && (processed < budget)) {
591 cb = &priv->rx_cbs[priv->rx_read_ptr];
592 skb = bcm_sysport_rx_refill(priv, cb);
593
594
595 /* We do not have a backing SKB, so we do not a corresponding
596 * DMA mapping for this incoming packet since
597 * bcm_sysport_rx_refill always either has both skb and mapping
598 * or none.
599 */
600 if (unlikely(!skb)) {
601 netif_err(priv, rx_err, ndev, "out of memory!\n");
602 ndev->stats.rx_dropped++;
603 ndev->stats.rx_errors++;
604 goto next;
605 }
606
607 /* Extract the Receive Status Block prepended */
608 rsb = (struct bcm_rsb *)skb->data;
609 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
610 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
611 DESC_STATUS_MASK;
612
613 netif_dbg(priv, rx_status, ndev,
614 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
615 p_index, priv->rx_c_index, priv->rx_read_ptr,
616 len, status);
617
618 if (unlikely(len > RX_BUF_LENGTH)) {
619 netif_err(priv, rx_status, ndev, "oversized packet\n");
620 ndev->stats.rx_length_errors++;
621 ndev->stats.rx_errors++;
622 dev_kfree_skb_any(skb);
623 goto next;
624 }
625
626 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
627 netif_err(priv, rx_status, ndev, "fragmented packet!\n");
628 ndev->stats.rx_dropped++;
629 ndev->stats.rx_errors++;
630 dev_kfree_skb_any(skb);
631 goto next;
632 }
633
634 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
635 netif_err(priv, rx_err, ndev, "error packet\n");
636 if (status & RX_STATUS_OVFLOW)
637 ndev->stats.rx_over_errors++;
638 ndev->stats.rx_dropped++;
639 ndev->stats.rx_errors++;
640 dev_kfree_skb_any(skb);
641 goto next;
642 }
643
644 skb_put(skb, len);
645
646 /* Hardware validated our checksum */
647 if (likely(status & DESC_L4_CSUM))
648 skb->ip_summed = CHECKSUM_UNNECESSARY;
649
650 /* Hardware pre-pends packets with 2bytes before Ethernet
651 * header plus we have the Receive Status Block, strip off all
652 * of this from the SKB.
653 */
654 skb_pull(skb, sizeof(*rsb) + 2);
655 len -= (sizeof(*rsb) + 2);
656
657 /* UniMAC may forward CRC */
658 if (priv->crc_fwd) {
659 skb_trim(skb, len - ETH_FCS_LEN);
660 len -= ETH_FCS_LEN;
661 }
662
663 skb->protocol = eth_type_trans(skb, ndev);
664 ndev->stats.rx_packets++;
665 ndev->stats.rx_bytes += len;
666
667 napi_gro_receive(&priv->napi, skb);
668 next:
669 processed++;
670 priv->rx_read_ptr++;
671
672 if (priv->rx_read_ptr == priv->num_rx_bds)
673 priv->rx_read_ptr = 0;
674 }
675
676 return processed;
677 }
678
679 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv,
680 struct bcm_sysport_cb *cb,
681 unsigned int *bytes_compl,
682 unsigned int *pkts_compl)
683 {
684 struct device *kdev = &priv->pdev->dev;
685 struct net_device *ndev = priv->netdev;
686
687 if (cb->skb) {
688 ndev->stats.tx_bytes += cb->skb->len;
689 *bytes_compl += cb->skb->len;
690 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
691 dma_unmap_len(cb, dma_len),
692 DMA_TO_DEVICE);
693 ndev->stats.tx_packets++;
694 (*pkts_compl)++;
695 bcm_sysport_free_cb(cb);
696 /* SKB fragment */
697 } else if (dma_unmap_addr(cb, dma_addr)) {
698 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len);
699 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
700 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
701 dma_unmap_addr_set(cb, dma_addr, 0);
702 }
703 }
704
705 /* Reclaim queued SKBs for transmission completion, lockless version */
706 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
707 struct bcm_sysport_tx_ring *ring)
708 {
709 struct net_device *ndev = priv->netdev;
710 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs;
711 unsigned int pkts_compl = 0, bytes_compl = 0;
712 struct bcm_sysport_cb *cb;
713 struct netdev_queue *txq;
714 u32 hw_ind;
715
716 txq = netdev_get_tx_queue(ndev, ring->index);
717
718 /* Compute how many descriptors have been processed since last call */
719 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
720 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
721 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK);
722
723 last_c_index = ring->c_index;
724 num_tx_cbs = ring->size;
725
726 c_index &= (num_tx_cbs - 1);
727
728 if (c_index >= last_c_index)
729 last_tx_cn = c_index - last_c_index;
730 else
731 last_tx_cn = num_tx_cbs - last_c_index + c_index;
732
733 netif_dbg(priv, tx_done, ndev,
734 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n",
735 ring->index, c_index, last_tx_cn, last_c_index);
736
737 while (last_tx_cn-- > 0) {
738 cb = ring->cbs + last_c_index;
739 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl);
740
741 ring->desc_count++;
742 last_c_index++;
743 last_c_index &= (num_tx_cbs - 1);
744 }
745
746 ring->c_index = c_index;
747
748 if (netif_tx_queue_stopped(txq) && pkts_compl)
749 netif_tx_wake_queue(txq);
750
751 netif_dbg(priv, tx_done, ndev,
752 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
753 ring->index, ring->c_index, pkts_compl, bytes_compl);
754
755 return pkts_compl;
756 }
757
758 /* Locked version of the per-ring TX reclaim routine */
759 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
760 struct bcm_sysport_tx_ring *ring)
761 {
762 unsigned int released;
763 unsigned long flags;
764
765 spin_lock_irqsave(&ring->lock, flags);
766 released = __bcm_sysport_tx_reclaim(priv, ring);
767 spin_unlock_irqrestore(&ring->lock, flags);
768
769 return released;
770 }
771
772 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
773 {
774 struct bcm_sysport_tx_ring *ring =
775 container_of(napi, struct bcm_sysport_tx_ring, napi);
776 unsigned int work_done = 0;
777
778 work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
779
780 if (work_done == 0) {
781 napi_complete(napi);
782 /* re-enable TX interrupt */
783 intrl2_1_mask_clear(ring->priv, BIT(ring->index));
784
785 return 0;
786 }
787
788 return budget;
789 }
790
791 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
792 {
793 unsigned int q;
794
795 for (q = 0; q < priv->netdev->num_tx_queues; q++)
796 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
797 }
798
799 static int bcm_sysport_poll(struct napi_struct *napi, int budget)
800 {
801 struct bcm_sysport_priv *priv =
802 container_of(napi, struct bcm_sysport_priv, napi);
803 unsigned int work_done = 0;
804
805 work_done = bcm_sysport_desc_rx(priv, budget);
806
807 priv->rx_c_index += work_done;
808 priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
809 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
810
811 if (work_done < budget) {
812 napi_complete_done(napi, work_done);
813 /* re-enable RX interrupts */
814 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
815 }
816
817 return work_done;
818 }
819
820 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
821 {
822 u32 reg;
823
824 /* Stop monitoring MPD interrupt */
825 intrl2_0_mask_set(priv, INTRL2_0_MPD);
826
827 /* Clear the MagicPacket detection logic */
828 reg = umac_readl(priv, UMAC_MPD_CTRL);
829 reg &= ~MPD_EN;
830 umac_writel(priv, reg, UMAC_MPD_CTRL);
831
832 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
833 }
834
835 /* RX and misc interrupt routine */
836 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
837 {
838 struct net_device *dev = dev_id;
839 struct bcm_sysport_priv *priv = netdev_priv(dev);
840
841 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
842 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
843 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
844
845 if (unlikely(priv->irq0_stat == 0)) {
846 netdev_warn(priv->netdev, "spurious RX interrupt\n");
847 return IRQ_NONE;
848 }
849
850 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
851 if (likely(napi_schedule_prep(&priv->napi))) {
852 /* disable RX interrupts */
853 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
854 __napi_schedule_irqoff(&priv->napi);
855 }
856 }
857
858 /* TX ring is full, perform a full reclaim since we do not know
859 * which one would trigger this interrupt
860 */
861 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
862 bcm_sysport_tx_reclaim_all(priv);
863
864 if (priv->irq0_stat & INTRL2_0_MPD) {
865 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n");
866 bcm_sysport_resume_from_wol(priv);
867 }
868
869 return IRQ_HANDLED;
870 }
871
872 /* TX interrupt service routine */
873 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
874 {
875 struct net_device *dev = dev_id;
876 struct bcm_sysport_priv *priv = netdev_priv(dev);
877 struct bcm_sysport_tx_ring *txr;
878 unsigned int ring;
879
880 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
881 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
882 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
883
884 if (unlikely(priv->irq1_stat == 0)) {
885 netdev_warn(priv->netdev, "spurious TX interrupt\n");
886 return IRQ_NONE;
887 }
888
889 for (ring = 0; ring < dev->num_tx_queues; ring++) {
890 if (!(priv->irq1_stat & BIT(ring)))
891 continue;
892
893 txr = &priv->tx_rings[ring];
894
895 if (likely(napi_schedule_prep(&txr->napi))) {
896 intrl2_1_mask_set(priv, BIT(ring));
897 __napi_schedule_irqoff(&txr->napi);
898 }
899 }
900
901 return IRQ_HANDLED;
902 }
903
904 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
905 {
906 struct bcm_sysport_priv *priv = dev_id;
907
908 pm_wakeup_event(&priv->pdev->dev, 0);
909
910 return IRQ_HANDLED;
911 }
912
913 #ifdef CONFIG_NET_POLL_CONTROLLER
914 static void bcm_sysport_poll_controller(struct net_device *dev)
915 {
916 struct bcm_sysport_priv *priv = netdev_priv(dev);
917
918 disable_irq(priv->irq0);
919 bcm_sysport_rx_isr(priv->irq0, priv);
920 enable_irq(priv->irq0);
921
922 disable_irq(priv->irq1);
923 bcm_sysport_tx_isr(priv->irq1, priv);
924 enable_irq(priv->irq1);
925 }
926 #endif
927
928 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
929 struct net_device *dev)
930 {
931 struct sk_buff *nskb;
932 struct bcm_tsb *tsb;
933 u32 csum_info;
934 u8 ip_proto;
935 u16 csum_start;
936 u16 ip_ver;
937
938 /* Re-allocate SKB if needed */
939 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
940 nskb = skb_realloc_headroom(skb, sizeof(*tsb));
941 dev_kfree_skb(skb);
942 if (!nskb) {
943 dev->stats.tx_errors++;
944 dev->stats.tx_dropped++;
945 return NULL;
946 }
947 skb = nskb;
948 }
949
950 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb));
951 /* Zero-out TSB by default */
952 memset(tsb, 0, sizeof(*tsb));
953
954 if (skb->ip_summed == CHECKSUM_PARTIAL) {
955 ip_ver = htons(skb->protocol);
956 switch (ip_ver) {
957 case ETH_P_IP:
958 ip_proto = ip_hdr(skb)->protocol;
959 break;
960 case ETH_P_IPV6:
961 ip_proto = ipv6_hdr(skb)->nexthdr;
962 break;
963 default:
964 return skb;
965 }
966
967 /* Get the checksum offset and the L4 (transport) offset */
968 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
969 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
970 csum_info |= (csum_start << L4_PTR_SHIFT);
971
972 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
973 csum_info |= L4_LENGTH_VALID;
974 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
975 csum_info |= L4_UDP;
976 } else {
977 csum_info = 0;
978 }
979
980 tsb->l4_ptr_dest_map = csum_info;
981 }
982
983 return skb;
984 }
985
986 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
987 struct net_device *dev)
988 {
989 struct bcm_sysport_priv *priv = netdev_priv(dev);
990 struct device *kdev = &priv->pdev->dev;
991 struct bcm_sysport_tx_ring *ring;
992 struct bcm_sysport_cb *cb;
993 struct netdev_queue *txq;
994 struct dma_desc *desc;
995 unsigned int skb_len;
996 unsigned long flags;
997 dma_addr_t mapping;
998 u32 len_status;
999 u16 queue;
1000 int ret;
1001
1002 queue = skb_get_queue_mapping(skb);
1003 txq = netdev_get_tx_queue(dev, queue);
1004 ring = &priv->tx_rings[queue];
1005
1006 /* lock against tx reclaim in BH context and TX ring full interrupt */
1007 spin_lock_irqsave(&ring->lock, flags);
1008 if (unlikely(ring->desc_count == 0)) {
1009 netif_tx_stop_queue(txq);
1010 netdev_err(dev, "queue %d awake and ring full!\n", queue);
1011 ret = NETDEV_TX_BUSY;
1012 goto out;
1013 }
1014
1015 /* Insert TSB and checksum infos */
1016 if (priv->tsb_en) {
1017 skb = bcm_sysport_insert_tsb(skb, dev);
1018 if (!skb) {
1019 ret = NETDEV_TX_OK;
1020 goto out;
1021 }
1022 }
1023
1024 /* The Ethernet switch we are interfaced with needs packets to be at
1025 * least 64 bytes (including FCS) otherwise they will be discarded when
1026 * they enter the switch port logic. When Broadcom tags are enabled, we
1027 * need to make sure that packets are at least 68 bytes
1028 * (including FCS and tag) because the length verification is done after
1029 * the Broadcom tag is stripped off the ingress packet.
1030 */
1031 if (skb_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) {
1032 ret = NETDEV_TX_OK;
1033 goto out;
1034 }
1035
1036 skb_len = skb->len < ETH_ZLEN + ENET_BRCM_TAG_LEN ?
1037 ETH_ZLEN + ENET_BRCM_TAG_LEN : skb->len;
1038
1039 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1040 if (dma_mapping_error(kdev, mapping)) {
1041 priv->mib.tx_dma_failed++;
1042 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
1043 skb->data, skb_len);
1044 ret = NETDEV_TX_OK;
1045 goto out;
1046 }
1047
1048 /* Remember the SKB for future freeing */
1049 cb = &ring->cbs[ring->curr_desc];
1050 cb->skb = skb;
1051 dma_unmap_addr_set(cb, dma_addr, mapping);
1052 dma_unmap_len_set(cb, dma_len, skb_len);
1053
1054 /* Fetch a descriptor entry from our pool */
1055 desc = ring->desc_cpu;
1056
1057 desc->addr_lo = lower_32_bits(mapping);
1058 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
1059 len_status |= (skb_len << DESC_LEN_SHIFT);
1060 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
1061 DESC_STATUS_SHIFT;
1062 if (skb->ip_summed == CHECKSUM_PARTIAL)
1063 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
1064
1065 ring->curr_desc++;
1066 if (ring->curr_desc == ring->size)
1067 ring->curr_desc = 0;
1068 ring->desc_count--;
1069
1070 /* Ensure write completion of the descriptor status/length
1071 * in DRAM before the System Port WRITE_PORT register latches
1072 * the value
1073 */
1074 wmb();
1075 desc->addr_status_len = len_status;
1076 wmb();
1077
1078 /* Write this descriptor address to the RING write port */
1079 tdma_port_write_desc_addr(priv, desc, ring->index);
1080
1081 /* Check ring space and update SW control flow */
1082 if (ring->desc_count == 0)
1083 netif_tx_stop_queue(txq);
1084
1085 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
1086 ring->index, ring->desc_count, ring->curr_desc);
1087
1088 ret = NETDEV_TX_OK;
1089 out:
1090 spin_unlock_irqrestore(&ring->lock, flags);
1091 return ret;
1092 }
1093
1094 static void bcm_sysport_tx_timeout(struct net_device *dev)
1095 {
1096 netdev_warn(dev, "transmit timeout!\n");
1097
1098 netif_trans_update(dev);
1099 dev->stats.tx_errors++;
1100
1101 netif_tx_wake_all_queues(dev);
1102 }
1103
1104 /* phylib adjust link callback */
1105 static void bcm_sysport_adj_link(struct net_device *dev)
1106 {
1107 struct bcm_sysport_priv *priv = netdev_priv(dev);
1108 struct phy_device *phydev = dev->phydev;
1109 unsigned int changed = 0;
1110 u32 cmd_bits = 0, reg;
1111
1112 if (priv->old_link != phydev->link) {
1113 changed = 1;
1114 priv->old_link = phydev->link;
1115 }
1116
1117 if (priv->old_duplex != phydev->duplex) {
1118 changed = 1;
1119 priv->old_duplex = phydev->duplex;
1120 }
1121
1122 switch (phydev->speed) {
1123 case SPEED_2500:
1124 cmd_bits = CMD_SPEED_2500;
1125 break;
1126 case SPEED_1000:
1127 cmd_bits = CMD_SPEED_1000;
1128 break;
1129 case SPEED_100:
1130 cmd_bits = CMD_SPEED_100;
1131 break;
1132 case SPEED_10:
1133 cmd_bits = CMD_SPEED_10;
1134 break;
1135 default:
1136 break;
1137 }
1138 cmd_bits <<= CMD_SPEED_SHIFT;
1139
1140 if (phydev->duplex == DUPLEX_HALF)
1141 cmd_bits |= CMD_HD_EN;
1142
1143 if (priv->old_pause != phydev->pause) {
1144 changed = 1;
1145 priv->old_pause = phydev->pause;
1146 }
1147
1148 if (!phydev->pause)
1149 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1150
1151 if (!changed)
1152 return;
1153
1154 if (phydev->link) {
1155 reg = umac_readl(priv, UMAC_CMD);
1156 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
1157 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1158 CMD_TX_PAUSE_IGNORE);
1159 reg |= cmd_bits;
1160 umac_writel(priv, reg, UMAC_CMD);
1161 }
1162
1163 phy_print_status(phydev);
1164 }
1165
1166 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1167 unsigned int index)
1168 {
1169 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1170 struct device *kdev = &priv->pdev->dev;
1171 size_t size;
1172 void *p;
1173 u32 reg;
1174
1175 /* Simple descriptors partitioning for now */
1176 size = 256;
1177
1178 /* We just need one DMA descriptor which is DMA-able, since writing to
1179 * the port will allocate a new descriptor in its internal linked-list
1180 */
1181 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
1182 GFP_KERNEL);
1183 if (!p) {
1184 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
1185 return -ENOMEM;
1186 }
1187
1188 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
1189 if (!ring->cbs) {
1190 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1191 return -ENOMEM;
1192 }
1193
1194 /* Initialize SW view of the ring */
1195 spin_lock_init(&ring->lock);
1196 ring->priv = priv;
1197 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
1198 ring->index = index;
1199 ring->size = size;
1200 ring->alloc_size = ring->size;
1201 ring->desc_cpu = p;
1202 ring->desc_count = ring->size;
1203 ring->curr_desc = 0;
1204
1205 /* Initialize HW ring */
1206 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1207 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1208 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1209 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
1210 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index));
1211 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
1212
1213 /* Program the number of descriptors as MAX_THRESHOLD and half of
1214 * its size for the hysteresis trigger
1215 */
1216 tdma_writel(priv, ring->size |
1217 1 << RING_HYST_THRESH_SHIFT,
1218 TDMA_DESC_RING_MAX_HYST(index));
1219
1220 /* Enable the ring queue in the arbiter */
1221 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1222 reg |= (1 << index);
1223 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1224
1225 napi_enable(&ring->napi);
1226
1227 netif_dbg(priv, hw, priv->netdev,
1228 "TDMA cfg, size=%d, desc_cpu=%p\n",
1229 ring->size, ring->desc_cpu);
1230
1231 return 0;
1232 }
1233
1234 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
1235 unsigned int index)
1236 {
1237 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1238 struct device *kdev = &priv->pdev->dev;
1239 u32 reg;
1240
1241 /* Caller should stop the TDMA engine */
1242 reg = tdma_readl(priv, TDMA_STATUS);
1243 if (!(reg & TDMA_DISABLED))
1244 netdev_warn(priv->netdev, "TDMA not stopped!\n");
1245
1246 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1247 * fail, so by checking this pointer we know whether the TX ring was
1248 * fully initialized or not.
1249 */
1250 if (!ring->cbs)
1251 return;
1252
1253 napi_disable(&ring->napi);
1254 netif_napi_del(&ring->napi);
1255
1256 bcm_sysport_tx_reclaim(priv, ring);
1257
1258 kfree(ring->cbs);
1259 ring->cbs = NULL;
1260
1261 if (ring->desc_dma) {
1262 dma_free_coherent(kdev, sizeof(struct dma_desc),
1263 ring->desc_cpu, ring->desc_dma);
1264 ring->desc_dma = 0;
1265 }
1266 ring->size = 0;
1267 ring->alloc_size = 0;
1268
1269 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1270 }
1271
1272 /* RDMA helper */
1273 static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
1274 unsigned int enable)
1275 {
1276 unsigned int timeout = 1000;
1277 u32 reg;
1278
1279 reg = rdma_readl(priv, RDMA_CONTROL);
1280 if (enable)
1281 reg |= RDMA_EN;
1282 else
1283 reg &= ~RDMA_EN;
1284 rdma_writel(priv, reg, RDMA_CONTROL);
1285
1286 /* Poll for RMDA disabling completion */
1287 do {
1288 reg = rdma_readl(priv, RDMA_STATUS);
1289 if (!!(reg & RDMA_DISABLED) == !enable)
1290 return 0;
1291 usleep_range(1000, 2000);
1292 } while (timeout-- > 0);
1293
1294 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1295
1296 return -ETIMEDOUT;
1297 }
1298
1299 /* TDMA helper */
1300 static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
1301 unsigned int enable)
1302 {
1303 unsigned int timeout = 1000;
1304 u32 reg;
1305
1306 reg = tdma_readl(priv, TDMA_CONTROL);
1307 if (enable)
1308 reg |= TDMA_EN;
1309 else
1310 reg &= ~TDMA_EN;
1311 tdma_writel(priv, reg, TDMA_CONTROL);
1312
1313 /* Poll for TMDA disabling completion */
1314 do {
1315 reg = tdma_readl(priv, TDMA_STATUS);
1316 if (!!(reg & TDMA_DISABLED) == !enable)
1317 return 0;
1318
1319 usleep_range(1000, 2000);
1320 } while (timeout-- > 0);
1321
1322 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1323
1324 return -ETIMEDOUT;
1325 }
1326
1327 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1328 {
1329 struct bcm_sysport_cb *cb;
1330 u32 reg;
1331 int ret;
1332 int i;
1333
1334 /* Initialize SW view of the RX ring */
1335 priv->num_rx_bds = NUM_RX_DESC;
1336 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
1337 priv->rx_c_index = 0;
1338 priv->rx_read_ptr = 0;
1339 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1340 GFP_KERNEL);
1341 if (!priv->rx_cbs) {
1342 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1343 return -ENOMEM;
1344 }
1345
1346 for (i = 0; i < priv->num_rx_bds; i++) {
1347 cb = priv->rx_cbs + i;
1348 cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
1349 }
1350
1351 ret = bcm_sysport_alloc_rx_bufs(priv);
1352 if (ret) {
1353 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1354 return ret;
1355 }
1356
1357 /* Initialize HW, ensure RDMA is disabled */
1358 reg = rdma_readl(priv, RDMA_STATUS);
1359 if (!(reg & RDMA_DISABLED))
1360 rdma_enable_set(priv, 0);
1361
1362 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1363 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1364 rdma_writel(priv, 0, RDMA_PROD_INDEX);
1365 rdma_writel(priv, 0, RDMA_CONS_INDEX);
1366 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1367 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1368 /* Operate the queue in ring mode */
1369 rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1370 rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1371 rdma_writel(priv, 0, RDMA_END_ADDR_HI);
1372 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO);
1373
1374 rdma_writel(priv, 1, RDMA_MBDONE_INTR);
1375
1376 netif_dbg(priv, hw, priv->netdev,
1377 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1378 priv->num_rx_bds, priv->rx_bds);
1379
1380 return 0;
1381 }
1382
1383 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1384 {
1385 struct bcm_sysport_cb *cb;
1386 unsigned int i;
1387 u32 reg;
1388
1389 /* Caller should ensure RDMA is disabled */
1390 reg = rdma_readl(priv, RDMA_STATUS);
1391 if (!(reg & RDMA_DISABLED))
1392 netdev_warn(priv->netdev, "RDMA not stopped!\n");
1393
1394 for (i = 0; i < priv->num_rx_bds; i++) {
1395 cb = &priv->rx_cbs[i];
1396 if (dma_unmap_addr(cb, dma_addr))
1397 dma_unmap_single(&priv->pdev->dev,
1398 dma_unmap_addr(cb, dma_addr),
1399 RX_BUF_LENGTH, DMA_FROM_DEVICE);
1400 bcm_sysport_free_cb(cb);
1401 }
1402
1403 kfree(priv->rx_cbs);
1404 priv->rx_cbs = NULL;
1405
1406 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1407 }
1408
1409 static void bcm_sysport_set_rx_mode(struct net_device *dev)
1410 {
1411 struct bcm_sysport_priv *priv = netdev_priv(dev);
1412 u32 reg;
1413
1414 reg = umac_readl(priv, UMAC_CMD);
1415 if (dev->flags & IFF_PROMISC)
1416 reg |= CMD_PROMISC;
1417 else
1418 reg &= ~CMD_PROMISC;
1419 umac_writel(priv, reg, UMAC_CMD);
1420
1421 /* No support for ALLMULTI */
1422 if (dev->flags & IFF_ALLMULTI)
1423 return;
1424 }
1425
1426 static inline void umac_enable_set(struct bcm_sysport_priv *priv,
1427 u32 mask, unsigned int enable)
1428 {
1429 u32 reg;
1430
1431 reg = umac_readl(priv, UMAC_CMD);
1432 if (enable)
1433 reg |= mask;
1434 else
1435 reg &= ~mask;
1436 umac_writel(priv, reg, UMAC_CMD);
1437
1438 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1439 * to be processed (1 msec).
1440 */
1441 if (enable == 0)
1442 usleep_range(1000, 2000);
1443 }
1444
1445 static inline void umac_reset(struct bcm_sysport_priv *priv)
1446 {
1447 u32 reg;
1448
1449 reg = umac_readl(priv, UMAC_CMD);
1450 reg |= CMD_SW_RESET;
1451 umac_writel(priv, reg, UMAC_CMD);
1452 udelay(10);
1453 reg = umac_readl(priv, UMAC_CMD);
1454 reg &= ~CMD_SW_RESET;
1455 umac_writel(priv, reg, UMAC_CMD);
1456 }
1457
1458 static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
1459 unsigned char *addr)
1460 {
1461 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1462 (addr[2] << 8) | addr[3], UMAC_MAC0);
1463 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1464 }
1465
1466 static void topctrl_flush(struct bcm_sysport_priv *priv)
1467 {
1468 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1469 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1470 mdelay(1);
1471 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1472 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1473 }
1474
1475 static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1476 {
1477 struct bcm_sysport_priv *priv = netdev_priv(dev);
1478 struct sockaddr *addr = p;
1479
1480 if (!is_valid_ether_addr(addr->sa_data))
1481 return -EINVAL;
1482
1483 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1484
1485 /* interface is disabled, changes to MAC will be reflected on next
1486 * open call
1487 */
1488 if (!netif_running(dev))
1489 return 0;
1490
1491 umac_set_hw_addr(priv, dev->dev_addr);
1492
1493 return 0;
1494 }
1495
1496 static void bcm_sysport_netif_start(struct net_device *dev)
1497 {
1498 struct bcm_sysport_priv *priv = netdev_priv(dev);
1499
1500 /* Enable NAPI */
1501 napi_enable(&priv->napi);
1502
1503 /* Enable RX interrupt and TX ring full interrupt */
1504 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1505
1506 phy_start(dev->phydev);
1507
1508 /* Enable TX interrupts for the 32 TXQs */
1509 intrl2_1_mask_clear(priv, 0xffffffff);
1510
1511 /* Last call before we start the real business */
1512 netif_tx_start_all_queues(dev);
1513 }
1514
1515 static void rbuf_init(struct bcm_sysport_priv *priv)
1516 {
1517 u32 reg;
1518
1519 reg = rbuf_readl(priv, RBUF_CONTROL);
1520 reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
1521 rbuf_writel(priv, reg, RBUF_CONTROL);
1522 }
1523
1524 static int bcm_sysport_open(struct net_device *dev)
1525 {
1526 struct bcm_sysport_priv *priv = netdev_priv(dev);
1527 struct phy_device *phydev;
1528 unsigned int i;
1529 int ret;
1530
1531 /* Reset UniMAC */
1532 umac_reset(priv);
1533
1534 /* Flush TX and RX FIFOs at TOPCTRL level */
1535 topctrl_flush(priv);
1536
1537 /* Disable the UniMAC RX/TX */
1538 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
1539
1540 /* Enable RBUF 2bytes alignment and Receive Status Block */
1541 rbuf_init(priv);
1542
1543 /* Set maximum frame length */
1544 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1545
1546 /* Set MAC address */
1547 umac_set_hw_addr(priv, dev->dev_addr);
1548
1549 /* Read CRC forward */
1550 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
1551
1552 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1553 0, priv->phy_interface);
1554 if (!phydev) {
1555 netdev_err(dev, "could not attach to PHY\n");
1556 return -ENODEV;
1557 }
1558
1559 /* Reset house keeping link status */
1560 priv->old_duplex = -1;
1561 priv->old_link = -1;
1562 priv->old_pause = -1;
1563
1564 /* mask all interrupts and request them */
1565 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1566 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1567 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1568 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1569 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1570 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1571
1572 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
1573 if (ret) {
1574 netdev_err(dev, "failed to request RX interrupt\n");
1575 goto out_phy_disconnect;
1576 }
1577
1578 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev);
1579 if (ret) {
1580 netdev_err(dev, "failed to request TX interrupt\n");
1581 goto out_free_irq0;
1582 }
1583
1584 /* Initialize both hardware and software ring */
1585 for (i = 0; i < dev->num_tx_queues; i++) {
1586 ret = bcm_sysport_init_tx_ring(priv, i);
1587 if (ret) {
1588 netdev_err(dev, "failed to initialize TX ring %d\n",
1589 i);
1590 goto out_free_tx_ring;
1591 }
1592 }
1593
1594 /* Initialize linked-list */
1595 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1596
1597 /* Initialize RX ring */
1598 ret = bcm_sysport_init_rx_ring(priv);
1599 if (ret) {
1600 netdev_err(dev, "failed to initialize RX ring\n");
1601 goto out_free_rx_ring;
1602 }
1603
1604 /* Turn on RDMA */
1605 ret = rdma_enable_set(priv, 1);
1606 if (ret)
1607 goto out_free_rx_ring;
1608
1609 /* Turn on TDMA */
1610 ret = tdma_enable_set(priv, 1);
1611 if (ret)
1612 goto out_clear_rx_int;
1613
1614 /* Turn on UniMAC TX/RX */
1615 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
1616
1617 bcm_sysport_netif_start(dev);
1618
1619 return 0;
1620
1621 out_clear_rx_int:
1622 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1623 out_free_rx_ring:
1624 bcm_sysport_fini_rx_ring(priv);
1625 out_free_tx_ring:
1626 for (i = 0; i < dev->num_tx_queues; i++)
1627 bcm_sysport_fini_tx_ring(priv, i);
1628 free_irq(priv->irq1, dev);
1629 out_free_irq0:
1630 free_irq(priv->irq0, dev);
1631 out_phy_disconnect:
1632 phy_disconnect(phydev);
1633 return ret;
1634 }
1635
1636 static void bcm_sysport_netif_stop(struct net_device *dev)
1637 {
1638 struct bcm_sysport_priv *priv = netdev_priv(dev);
1639
1640 /* stop all software from updating hardware */
1641 netif_tx_stop_all_queues(dev);
1642 napi_disable(&priv->napi);
1643 phy_stop(dev->phydev);
1644
1645 /* mask all interrupts */
1646 intrl2_0_mask_set(priv, 0xffffffff);
1647 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1648 intrl2_1_mask_set(priv, 0xffffffff);
1649 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1650 }
1651
1652 static int bcm_sysport_stop(struct net_device *dev)
1653 {
1654 struct bcm_sysport_priv *priv = netdev_priv(dev);
1655 unsigned int i;
1656 int ret;
1657
1658 bcm_sysport_netif_stop(dev);
1659
1660 /* Disable UniMAC RX */
1661 umac_enable_set(priv, CMD_RX_EN, 0);
1662
1663 ret = tdma_enable_set(priv, 0);
1664 if (ret) {
1665 netdev_err(dev, "timeout disabling RDMA\n");
1666 return ret;
1667 }
1668
1669 /* Wait for a maximum packet size to be drained */
1670 usleep_range(2000, 3000);
1671
1672 ret = rdma_enable_set(priv, 0);
1673 if (ret) {
1674 netdev_err(dev, "timeout disabling TDMA\n");
1675 return ret;
1676 }
1677
1678 /* Disable UniMAC TX */
1679 umac_enable_set(priv, CMD_TX_EN, 0);
1680
1681 /* Free RX/TX rings SW structures */
1682 for (i = 0; i < dev->num_tx_queues; i++)
1683 bcm_sysport_fini_tx_ring(priv, i);
1684 bcm_sysport_fini_rx_ring(priv);
1685
1686 free_irq(priv->irq0, dev);
1687 free_irq(priv->irq1, dev);
1688
1689 /* Disconnect from PHY */
1690 phy_disconnect(dev->phydev);
1691
1692 return 0;
1693 }
1694
1695 static struct ethtool_ops bcm_sysport_ethtool_ops = {
1696 .get_drvinfo = bcm_sysport_get_drvinfo,
1697 .get_msglevel = bcm_sysport_get_msglvl,
1698 .set_msglevel = bcm_sysport_set_msglvl,
1699 .get_link = ethtool_op_get_link,
1700 .get_strings = bcm_sysport_get_strings,
1701 .get_ethtool_stats = bcm_sysport_get_stats,
1702 .get_sset_count = bcm_sysport_get_sset_count,
1703 .get_wol = bcm_sysport_get_wol,
1704 .set_wol = bcm_sysport_set_wol,
1705 .get_coalesce = bcm_sysport_get_coalesce,
1706 .set_coalesce = bcm_sysport_set_coalesce,
1707 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1708 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1709 };
1710
1711 static const struct net_device_ops bcm_sysport_netdev_ops = {
1712 .ndo_start_xmit = bcm_sysport_xmit,
1713 .ndo_tx_timeout = bcm_sysport_tx_timeout,
1714 .ndo_open = bcm_sysport_open,
1715 .ndo_stop = bcm_sysport_stop,
1716 .ndo_set_features = bcm_sysport_set_features,
1717 .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
1718 .ndo_set_mac_address = bcm_sysport_change_mac,
1719 #ifdef CONFIG_NET_POLL_CONTROLLER
1720 .ndo_poll_controller = bcm_sysport_poll_controller,
1721 #endif
1722 };
1723
1724 #define REV_FMT "v%2x.%02x"
1725
1726 static int bcm_sysport_probe(struct platform_device *pdev)
1727 {
1728 struct bcm_sysport_priv *priv;
1729 struct device_node *dn;
1730 struct net_device *dev;
1731 const void *macaddr;
1732 struct resource *r;
1733 u32 txq, rxq;
1734 int ret;
1735
1736 dn = pdev->dev.of_node;
1737 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1738
1739 /* Read the Transmit/Receive Queue properties */
1740 if (of_property_read_u32(dn, "systemport,num-txq", &txq))
1741 txq = TDMA_NUM_RINGS;
1742 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
1743 rxq = 1;
1744
1745 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
1746 if (!dev)
1747 return -ENOMEM;
1748
1749 /* Initialize private members */
1750 priv = netdev_priv(dev);
1751
1752 priv->irq0 = platform_get_irq(pdev, 0);
1753 priv->irq1 = platform_get_irq(pdev, 1);
1754 priv->wol_irq = platform_get_irq(pdev, 2);
1755 if (priv->irq0 <= 0 || priv->irq1 <= 0) {
1756 dev_err(&pdev->dev, "invalid interrupts\n");
1757 ret = -EINVAL;
1758 goto err;
1759 }
1760
1761 priv->base = devm_ioremap_resource(&pdev->dev, r);
1762 if (IS_ERR(priv->base)) {
1763 ret = PTR_ERR(priv->base);
1764 goto err;
1765 }
1766
1767 priv->netdev = dev;
1768 priv->pdev = pdev;
1769
1770 priv->phy_interface = of_get_phy_mode(dn);
1771 /* Default to GMII interface mode */
1772 if (priv->phy_interface < 0)
1773 priv->phy_interface = PHY_INTERFACE_MODE_GMII;
1774
1775 /* In the case of a fixed PHY, the DT node associated
1776 * to the PHY is the Ethernet MAC DT node.
1777 */
1778 if (of_phy_is_fixed_link(dn)) {
1779 ret = of_phy_register_fixed_link(dn);
1780 if (ret) {
1781 dev_err(&pdev->dev, "failed to register fixed PHY\n");
1782 goto err;
1783 }
1784
1785 priv->phy_dn = dn;
1786 }
1787
1788 /* Initialize netdevice members */
1789 macaddr = of_get_mac_address(dn);
1790 if (!macaddr || !is_valid_ether_addr(macaddr)) {
1791 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
1792 eth_hw_addr_random(dev);
1793 } else {
1794 ether_addr_copy(dev->dev_addr, macaddr);
1795 }
1796
1797 SET_NETDEV_DEV(dev, &pdev->dev);
1798 dev_set_drvdata(&pdev->dev, dev);
1799 dev->ethtool_ops = &bcm_sysport_ethtool_ops;
1800 dev->netdev_ops = &bcm_sysport_netdev_ops;
1801 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
1802
1803 /* HW supported features, none enabled by default */
1804 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
1805 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1806
1807 /* Request the WOL interrupt and advertise suspend if available */
1808 priv->wol_irq_disabled = 1;
1809 ret = devm_request_irq(&pdev->dev, priv->wol_irq,
1810 bcm_sysport_wol_isr, 0, dev->name, priv);
1811 if (!ret)
1812 device_set_wakeup_capable(&pdev->dev, 1);
1813
1814 /* Set the needed headroom once and for all */
1815 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
1816 dev->needed_headroom += sizeof(struct bcm_tsb);
1817
1818 /* libphy will adjust the link state accordingly */
1819 netif_carrier_off(dev);
1820
1821 ret = register_netdev(dev);
1822 if (ret) {
1823 dev_err(&pdev->dev, "failed to register net_device\n");
1824 goto err;
1825 }
1826
1827 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
1828 dev_info(&pdev->dev,
1829 "Broadcom SYSTEMPORT" REV_FMT
1830 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
1831 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
1832 priv->base, priv->irq0, priv->irq1, txq, rxq);
1833
1834 return 0;
1835 err:
1836 free_netdev(dev);
1837 return ret;
1838 }
1839
1840 static int bcm_sysport_remove(struct platform_device *pdev)
1841 {
1842 struct net_device *dev = dev_get_drvdata(&pdev->dev);
1843
1844 /* Not much to do, ndo_close has been called
1845 * and we use managed allocations
1846 */
1847 unregister_netdev(dev);
1848 free_netdev(dev);
1849 dev_set_drvdata(&pdev->dev, NULL);
1850
1851 return 0;
1852 }
1853
1854 #ifdef CONFIG_PM_SLEEP
1855 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
1856 {
1857 struct net_device *ndev = priv->netdev;
1858 unsigned int timeout = 1000;
1859 u32 reg;
1860
1861 /* Password has already been programmed */
1862 reg = umac_readl(priv, UMAC_MPD_CTRL);
1863 reg |= MPD_EN;
1864 reg &= ~PSW_EN;
1865 if (priv->wolopts & WAKE_MAGICSECURE)
1866 reg |= PSW_EN;
1867 umac_writel(priv, reg, UMAC_MPD_CTRL);
1868
1869 /* Make sure RBUF entered WoL mode as result */
1870 do {
1871 reg = rbuf_readl(priv, RBUF_STATUS);
1872 if (reg & RBUF_WOL_MODE)
1873 break;
1874
1875 udelay(10);
1876 } while (timeout-- > 0);
1877
1878 /* Do not leave the UniMAC RBUF matching only MPD packets */
1879 if (!timeout) {
1880 reg = umac_readl(priv, UMAC_MPD_CTRL);
1881 reg &= ~MPD_EN;
1882 umac_writel(priv, reg, UMAC_MPD_CTRL);
1883 netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
1884 return -ETIMEDOUT;
1885 }
1886
1887 /* UniMAC receive needs to be turned on */
1888 umac_enable_set(priv, CMD_RX_EN, 1);
1889
1890 /* Enable the interrupt wake-up source */
1891 intrl2_0_mask_clear(priv, INTRL2_0_MPD);
1892
1893 netif_dbg(priv, wol, ndev, "entered WOL mode\n");
1894
1895 return 0;
1896 }
1897
1898 static int bcm_sysport_suspend(struct device *d)
1899 {
1900 struct net_device *dev = dev_get_drvdata(d);
1901 struct bcm_sysport_priv *priv = netdev_priv(dev);
1902 unsigned int i;
1903 int ret = 0;
1904 u32 reg;
1905
1906 if (!netif_running(dev))
1907 return 0;
1908
1909 bcm_sysport_netif_stop(dev);
1910
1911 phy_suspend(dev->phydev);
1912
1913 netif_device_detach(dev);
1914
1915 /* Disable UniMAC RX */
1916 umac_enable_set(priv, CMD_RX_EN, 0);
1917
1918 ret = rdma_enable_set(priv, 0);
1919 if (ret) {
1920 netdev_err(dev, "RDMA timeout!\n");
1921 return ret;
1922 }
1923
1924 /* Disable RXCHK if enabled */
1925 if (priv->rx_chk_en) {
1926 reg = rxchk_readl(priv, RXCHK_CONTROL);
1927 reg &= ~RXCHK_EN;
1928 rxchk_writel(priv, reg, RXCHK_CONTROL);
1929 }
1930
1931 /* Flush RX pipe */
1932 if (!priv->wolopts)
1933 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1934
1935 ret = tdma_enable_set(priv, 0);
1936 if (ret) {
1937 netdev_err(dev, "TDMA timeout!\n");
1938 return ret;
1939 }
1940
1941 /* Wait for a packet boundary */
1942 usleep_range(2000, 3000);
1943
1944 umac_enable_set(priv, CMD_TX_EN, 0);
1945
1946 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1947
1948 /* Free RX/TX rings SW structures */
1949 for (i = 0; i < dev->num_tx_queues; i++)
1950 bcm_sysport_fini_tx_ring(priv, i);
1951 bcm_sysport_fini_rx_ring(priv);
1952
1953 /* Get prepared for Wake-on-LAN */
1954 if (device_may_wakeup(d) && priv->wolopts)
1955 ret = bcm_sysport_suspend_to_wol(priv);
1956
1957 return ret;
1958 }
1959
1960 static int bcm_sysport_resume(struct device *d)
1961 {
1962 struct net_device *dev = dev_get_drvdata(d);
1963 struct bcm_sysport_priv *priv = netdev_priv(dev);
1964 unsigned int i;
1965 u32 reg;
1966 int ret;
1967
1968 if (!netif_running(dev))
1969 return 0;
1970
1971 umac_reset(priv);
1972
1973 /* We may have been suspended and never received a WOL event that
1974 * would turn off MPD detection, take care of that now
1975 */
1976 bcm_sysport_resume_from_wol(priv);
1977
1978 /* Initialize both hardware and software ring */
1979 for (i = 0; i < dev->num_tx_queues; i++) {
1980 ret = bcm_sysport_init_tx_ring(priv, i);
1981 if (ret) {
1982 netdev_err(dev, "failed to initialize TX ring %d\n",
1983 i);
1984 goto out_free_tx_rings;
1985 }
1986 }
1987
1988 /* Initialize linked-list */
1989 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1990
1991 /* Initialize RX ring */
1992 ret = bcm_sysport_init_rx_ring(priv);
1993 if (ret) {
1994 netdev_err(dev, "failed to initialize RX ring\n");
1995 goto out_free_rx_ring;
1996 }
1997
1998 netif_device_attach(dev);
1999
2000 /* RX pipe enable */
2001 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
2002
2003 ret = rdma_enable_set(priv, 1);
2004 if (ret) {
2005 netdev_err(dev, "failed to enable RDMA\n");
2006 goto out_free_rx_ring;
2007 }
2008
2009 /* Enable rxhck */
2010 if (priv->rx_chk_en) {
2011 reg = rxchk_readl(priv, RXCHK_CONTROL);
2012 reg |= RXCHK_EN;
2013 rxchk_writel(priv, reg, RXCHK_CONTROL);
2014 }
2015
2016 rbuf_init(priv);
2017
2018 /* Set maximum frame length */
2019 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2020
2021 /* Set MAC address */
2022 umac_set_hw_addr(priv, dev->dev_addr);
2023
2024 umac_enable_set(priv, CMD_RX_EN, 1);
2025
2026 /* TX pipe enable */
2027 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2028
2029 umac_enable_set(priv, CMD_TX_EN, 1);
2030
2031 ret = tdma_enable_set(priv, 1);
2032 if (ret) {
2033 netdev_err(dev, "TDMA timeout!\n");
2034 goto out_free_rx_ring;
2035 }
2036
2037 phy_resume(dev->phydev);
2038
2039 bcm_sysport_netif_start(dev);
2040
2041 return 0;
2042
2043 out_free_rx_ring:
2044 bcm_sysport_fini_rx_ring(priv);
2045 out_free_tx_rings:
2046 for (i = 0; i < dev->num_tx_queues; i++)
2047 bcm_sysport_fini_tx_ring(priv, i);
2048 return ret;
2049 }
2050 #endif
2051
2052 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2053 bcm_sysport_suspend, bcm_sysport_resume);
2054
2055 static const struct of_device_id bcm_sysport_of_match[] = {
2056 { .compatible = "brcm,systemport-v1.00" },
2057 { .compatible = "brcm,systemport" },
2058 { /* sentinel */ }
2059 };
2060 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match);
2061
2062 static struct platform_driver bcm_sysport_driver = {
2063 .probe = bcm_sysport_probe,
2064 .remove = bcm_sysport_remove,
2065 .driver = {
2066 .name = "brcm-systemport",
2067 .of_match_table = bcm_sysport_of_match,
2068 .pm = &bcm_sysport_pm_ops,
2069 },
2070 };
2071 module_platform_driver(bcm_sysport_driver);
2072
2073 MODULE_AUTHOR("Broadcom Corporation");
2074 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2075 MODULE_ALIAS("platform:brcm-systemport");
2076 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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