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Merge remote-tracking branch 'vfio/next'
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bgmac.c
1 /*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <linux/bcma/bcma.h>
13 #include <linux/etherdevice.h>
14 #include <linux/bcm47xx_nvram.h>
15 #include "bgmac.h"
16
17 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
18 u32 value, int timeout)
19 {
20 u32 val;
21 int i;
22
23 for (i = 0; i < timeout / 10; i++) {
24 val = bgmac_read(bgmac, reg);
25 if ((val & mask) == value)
26 return true;
27 udelay(10);
28 }
29 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
30 return false;
31 }
32
33 /**************************************************
34 * DMA
35 **************************************************/
36
37 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
38 {
39 u32 val;
40 int i;
41
42 if (!ring->mmio_base)
43 return;
44
45 /* Suspend DMA TX ring first.
46 * bgmac_wait_value doesn't support waiting for any of few values, so
47 * implement whole loop here.
48 */
49 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
50 BGMAC_DMA_TX_SUSPEND);
51 for (i = 0; i < 10000 / 10; i++) {
52 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
53 val &= BGMAC_DMA_TX_STAT;
54 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
55 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
56 val == BGMAC_DMA_TX_STAT_STOPPED) {
57 i = 0;
58 break;
59 }
60 udelay(10);
61 }
62 if (i)
63 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
64 ring->mmio_base, val);
65
66 /* Remove SUSPEND bit */
67 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
68 if (!bgmac_wait_value(bgmac,
69 ring->mmio_base + BGMAC_DMA_TX_STATUS,
70 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
71 10000)) {
72 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
73 ring->mmio_base);
74 udelay(300);
75 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
76 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
77 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
78 ring->mmio_base);
79 }
80 }
81
82 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
83 struct bgmac_dma_ring *ring)
84 {
85 u32 ctl;
86
87 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
88 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
89 ctl &= ~BGMAC_DMA_TX_BL_MASK;
90 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
91
92 ctl &= ~BGMAC_DMA_TX_MR_MASK;
93 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
94
95 ctl &= ~BGMAC_DMA_TX_PC_MASK;
96 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
97
98 ctl &= ~BGMAC_DMA_TX_PT_MASK;
99 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
100 }
101 ctl |= BGMAC_DMA_TX_ENABLE;
102 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
103 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
104 }
105
106 static void
107 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
108 int i, int len, u32 ctl0)
109 {
110 struct bgmac_slot_info *slot;
111 struct bgmac_dma_desc *dma_desc;
112 u32 ctl1;
113
114 if (i == BGMAC_TX_RING_SLOTS - 1)
115 ctl0 |= BGMAC_DESC_CTL0_EOT;
116
117 ctl1 = len & BGMAC_DESC_CTL1_LEN;
118
119 slot = &ring->slots[i];
120 dma_desc = &ring->cpu_base[i];
121 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
122 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
123 dma_desc->ctl0 = cpu_to_le32(ctl0);
124 dma_desc->ctl1 = cpu_to_le32(ctl1);
125 }
126
127 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
128 struct bgmac_dma_ring *ring,
129 struct sk_buff *skb)
130 {
131 struct device *dma_dev = bgmac->dma_dev;
132 struct net_device *net_dev = bgmac->net_dev;
133 int index = ring->end % BGMAC_TX_RING_SLOTS;
134 struct bgmac_slot_info *slot = &ring->slots[index];
135 int nr_frags;
136 u32 flags;
137 int i;
138
139 if (skb->len > BGMAC_DESC_CTL1_LEN) {
140 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
141 goto err_drop;
142 }
143
144 if (skb->ip_summed == CHECKSUM_PARTIAL)
145 skb_checksum_help(skb);
146
147 nr_frags = skb_shinfo(skb)->nr_frags;
148
149 /* ring->end - ring->start will return the number of valid slots,
150 * even when ring->end overflows
151 */
152 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
153 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
154 netif_stop_queue(net_dev);
155 return NETDEV_TX_BUSY;
156 }
157
158 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
159 DMA_TO_DEVICE);
160 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
161 goto err_dma_head;
162
163 flags = BGMAC_DESC_CTL0_SOF;
164 if (!nr_frags)
165 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
166
167 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
168 flags = 0;
169
170 for (i = 0; i < nr_frags; i++) {
171 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
172 int len = skb_frag_size(frag);
173
174 index = (index + 1) % BGMAC_TX_RING_SLOTS;
175 slot = &ring->slots[index];
176 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
177 len, DMA_TO_DEVICE);
178 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
179 goto err_dma;
180
181 if (i == nr_frags - 1)
182 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
183
184 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
185 }
186
187 slot->skb = skb;
188 ring->end += nr_frags + 1;
189 netdev_sent_queue(net_dev, skb->len);
190
191 wmb();
192
193 /* Increase ring->end to point empty slot. We tell hardware the first
194 * slot it should *not* read.
195 */
196 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
197 ring->index_base +
198 (ring->end % BGMAC_TX_RING_SLOTS) *
199 sizeof(struct bgmac_dma_desc));
200
201 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
202 netif_stop_queue(net_dev);
203
204 return NETDEV_TX_OK;
205
206 err_dma:
207 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
208 DMA_TO_DEVICE);
209
210 while (i-- > 0) {
211 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
212 struct bgmac_slot_info *slot = &ring->slots[index];
213 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
214 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
215
216 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
217 }
218
219 err_dma_head:
220 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
221 ring->mmio_base);
222
223 err_drop:
224 dev_kfree_skb(skb);
225 net_dev->stats.tx_dropped++;
226 net_dev->stats.tx_errors++;
227 return NETDEV_TX_OK;
228 }
229
230 /* Free transmitted packets */
231 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
232 {
233 struct device *dma_dev = bgmac->dma_dev;
234 int empty_slot;
235 bool freed = false;
236 unsigned bytes_compl = 0, pkts_compl = 0;
237
238 /* The last slot that hardware didn't consume yet */
239 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
240 empty_slot &= BGMAC_DMA_TX_STATDPTR;
241 empty_slot -= ring->index_base;
242 empty_slot &= BGMAC_DMA_TX_STATDPTR;
243 empty_slot /= sizeof(struct bgmac_dma_desc);
244
245 while (ring->start != ring->end) {
246 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
247 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
248 u32 ctl0, ctl1;
249 int len;
250
251 if (slot_idx == empty_slot)
252 break;
253
254 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
255 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
256 len = ctl1 & BGMAC_DESC_CTL1_LEN;
257 if (ctl0 & BGMAC_DESC_CTL0_SOF)
258 /* Unmap no longer used buffer */
259 dma_unmap_single(dma_dev, slot->dma_addr, len,
260 DMA_TO_DEVICE);
261 else
262 dma_unmap_page(dma_dev, slot->dma_addr, len,
263 DMA_TO_DEVICE);
264
265 if (slot->skb) {
266 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
267 bgmac->net_dev->stats.tx_packets++;
268 bytes_compl += slot->skb->len;
269 pkts_compl++;
270
271 /* Free memory! :) */
272 dev_kfree_skb(slot->skb);
273 slot->skb = NULL;
274 }
275
276 slot->dma_addr = 0;
277 ring->start++;
278 freed = true;
279 }
280
281 if (!pkts_compl)
282 return;
283
284 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
285
286 if (netif_queue_stopped(bgmac->net_dev))
287 netif_wake_queue(bgmac->net_dev);
288 }
289
290 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
291 {
292 if (!ring->mmio_base)
293 return;
294
295 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
296 if (!bgmac_wait_value(bgmac,
297 ring->mmio_base + BGMAC_DMA_RX_STATUS,
298 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
299 10000))
300 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
301 ring->mmio_base);
302 }
303
304 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
305 struct bgmac_dma_ring *ring)
306 {
307 u32 ctl;
308
309 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
310 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
311 ctl &= ~BGMAC_DMA_RX_BL_MASK;
312 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
313
314 ctl &= ~BGMAC_DMA_RX_PC_MASK;
315 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
316
317 ctl &= ~BGMAC_DMA_RX_PT_MASK;
318 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
319 }
320 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
321 ctl |= BGMAC_DMA_RX_ENABLE;
322 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
323 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
324 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
325 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
326 }
327
328 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
329 struct bgmac_slot_info *slot)
330 {
331 struct device *dma_dev = bgmac->dma_dev;
332 dma_addr_t dma_addr;
333 struct bgmac_rx_header *rx;
334 void *buf;
335
336 /* Alloc skb */
337 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
338 if (!buf)
339 return -ENOMEM;
340
341 /* Poison - if everything goes fine, hardware will overwrite it */
342 rx = buf + BGMAC_RX_BUF_OFFSET;
343 rx->len = cpu_to_le16(0xdead);
344 rx->flags = cpu_to_le16(0xbeef);
345
346 /* Map skb for the DMA */
347 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
348 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
349 if (dma_mapping_error(dma_dev, dma_addr)) {
350 netdev_err(bgmac->net_dev, "DMA mapping error\n");
351 put_page(virt_to_head_page(buf));
352 return -ENOMEM;
353 }
354
355 /* Update the slot */
356 slot->buf = buf;
357 slot->dma_addr = dma_addr;
358
359 return 0;
360 }
361
362 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
363 struct bgmac_dma_ring *ring)
364 {
365 dma_wmb();
366
367 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
368 ring->index_base +
369 ring->end * sizeof(struct bgmac_dma_desc));
370 }
371
372 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
373 struct bgmac_dma_ring *ring, int desc_idx)
374 {
375 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
376 u32 ctl0 = 0, ctl1 = 0;
377
378 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
379 ctl0 |= BGMAC_DESC_CTL0_EOT;
380 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
381 /* Is there any BGMAC device that requires extension? */
382 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
383 * B43_DMA64_DCTL1_ADDREXT_MASK;
384 */
385
386 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
387 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
388 dma_desc->ctl0 = cpu_to_le32(ctl0);
389 dma_desc->ctl1 = cpu_to_le32(ctl1);
390
391 ring->end = desc_idx;
392 }
393
394 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
395 struct bgmac_slot_info *slot)
396 {
397 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
398
399 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
400 DMA_FROM_DEVICE);
401 rx->len = cpu_to_le16(0xdead);
402 rx->flags = cpu_to_le16(0xbeef);
403 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
404 DMA_FROM_DEVICE);
405 }
406
407 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
408 int weight)
409 {
410 u32 end_slot;
411 int handled = 0;
412
413 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
414 end_slot &= BGMAC_DMA_RX_STATDPTR;
415 end_slot -= ring->index_base;
416 end_slot &= BGMAC_DMA_RX_STATDPTR;
417 end_slot /= sizeof(struct bgmac_dma_desc);
418
419 while (ring->start != end_slot) {
420 struct device *dma_dev = bgmac->dma_dev;
421 struct bgmac_slot_info *slot = &ring->slots[ring->start];
422 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
423 struct sk_buff *skb;
424 void *buf = slot->buf;
425 dma_addr_t dma_addr = slot->dma_addr;
426 u16 len, flags;
427
428 do {
429 /* Prepare new skb as replacement */
430 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
431 bgmac_dma_rx_poison_buf(dma_dev, slot);
432 break;
433 }
434
435 /* Unmap buffer to make it accessible to the CPU */
436 dma_unmap_single(dma_dev, dma_addr,
437 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
438
439 /* Get info from the header */
440 len = le16_to_cpu(rx->len);
441 flags = le16_to_cpu(rx->flags);
442
443 /* Check for poison and drop or pass the packet */
444 if (len == 0xdead && flags == 0xbeef) {
445 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
446 ring->start);
447 put_page(virt_to_head_page(buf));
448 bgmac->net_dev->stats.rx_errors++;
449 break;
450 }
451
452 if (len > BGMAC_RX_ALLOC_SIZE) {
453 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
454 ring->start);
455 put_page(virt_to_head_page(buf));
456 bgmac->net_dev->stats.rx_length_errors++;
457 bgmac->net_dev->stats.rx_errors++;
458 break;
459 }
460
461 /* Omit CRC. */
462 len -= ETH_FCS_LEN;
463
464 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
465 if (unlikely(!skb)) {
466 netdev_err(bgmac->net_dev, "build_skb failed\n");
467 put_page(virt_to_head_page(buf));
468 bgmac->net_dev->stats.rx_errors++;
469 break;
470 }
471 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
472 BGMAC_RX_BUF_OFFSET + len);
473 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
474 BGMAC_RX_BUF_OFFSET);
475
476 skb_checksum_none_assert(skb);
477 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
478 bgmac->net_dev->stats.rx_bytes += len;
479 bgmac->net_dev->stats.rx_packets++;
480 napi_gro_receive(&bgmac->napi, skb);
481 handled++;
482 } while (0);
483
484 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
485
486 if (++ring->start >= BGMAC_RX_RING_SLOTS)
487 ring->start = 0;
488
489 if (handled >= weight) /* Should never be greater */
490 break;
491 }
492
493 bgmac_dma_rx_update_index(bgmac, ring);
494
495 return handled;
496 }
497
498 /* Does ring support unaligned addressing? */
499 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
500 struct bgmac_dma_ring *ring,
501 enum bgmac_dma_ring_type ring_type)
502 {
503 switch (ring_type) {
504 case BGMAC_DMA_RING_TX:
505 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
506 0xff0);
507 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
508 return true;
509 break;
510 case BGMAC_DMA_RING_RX:
511 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
512 0xff0);
513 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
514 return true;
515 break;
516 }
517 return false;
518 }
519
520 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
521 struct bgmac_dma_ring *ring)
522 {
523 struct device *dma_dev = bgmac->dma_dev;
524 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
525 struct bgmac_slot_info *slot;
526 int i;
527
528 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
529 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
530
531 slot = &ring->slots[i];
532 dev_kfree_skb(slot->skb);
533
534 if (!slot->dma_addr)
535 continue;
536
537 if (slot->skb)
538 dma_unmap_single(dma_dev, slot->dma_addr,
539 len, DMA_TO_DEVICE);
540 else
541 dma_unmap_page(dma_dev, slot->dma_addr,
542 len, DMA_TO_DEVICE);
543 }
544 }
545
546 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
547 struct bgmac_dma_ring *ring)
548 {
549 struct device *dma_dev = bgmac->dma_dev;
550 struct bgmac_slot_info *slot;
551 int i;
552
553 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
554 slot = &ring->slots[i];
555 if (!slot->dma_addr)
556 continue;
557
558 dma_unmap_single(dma_dev, slot->dma_addr,
559 BGMAC_RX_BUF_SIZE,
560 DMA_FROM_DEVICE);
561 put_page(virt_to_head_page(slot->buf));
562 slot->dma_addr = 0;
563 }
564 }
565
566 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
567 struct bgmac_dma_ring *ring,
568 int num_slots)
569 {
570 struct device *dma_dev = bgmac->dma_dev;
571 int size;
572
573 if (!ring->cpu_base)
574 return;
575
576 /* Free ring of descriptors */
577 size = num_slots * sizeof(struct bgmac_dma_desc);
578 dma_free_coherent(dma_dev, size, ring->cpu_base,
579 ring->dma_base);
580 }
581
582 static void bgmac_dma_cleanup(struct bgmac *bgmac)
583 {
584 int i;
585
586 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
587 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
588
589 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
590 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
591 }
592
593 static void bgmac_dma_free(struct bgmac *bgmac)
594 {
595 int i;
596
597 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
598 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
599 BGMAC_TX_RING_SLOTS);
600
601 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
602 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
603 BGMAC_RX_RING_SLOTS);
604 }
605
606 static int bgmac_dma_alloc(struct bgmac *bgmac)
607 {
608 struct device *dma_dev = bgmac->dma_dev;
609 struct bgmac_dma_ring *ring;
610 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
611 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
612 int size; /* ring size: different for Tx and Rx */
613 int err;
614 int i;
615
616 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
617 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
618
619 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
620 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
621 return -ENOTSUPP;
622 }
623
624 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
625 ring = &bgmac->tx_ring[i];
626 ring->mmio_base = ring_base[i];
627
628 /* Alloc ring of descriptors */
629 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
630 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
631 &ring->dma_base,
632 GFP_KERNEL);
633 if (!ring->cpu_base) {
634 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
635 ring->mmio_base);
636 goto err_dma_free;
637 }
638
639 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
640 BGMAC_DMA_RING_TX);
641 if (ring->unaligned)
642 ring->index_base = lower_32_bits(ring->dma_base);
643 else
644 ring->index_base = 0;
645
646 /* No need to alloc TX slots yet */
647 }
648
649 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
650 ring = &bgmac->rx_ring[i];
651 ring->mmio_base = ring_base[i];
652
653 /* Alloc ring of descriptors */
654 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
655 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
656 &ring->dma_base,
657 GFP_KERNEL);
658 if (!ring->cpu_base) {
659 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
660 ring->mmio_base);
661 err = -ENOMEM;
662 goto err_dma_free;
663 }
664
665 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
666 BGMAC_DMA_RING_RX);
667 if (ring->unaligned)
668 ring->index_base = lower_32_bits(ring->dma_base);
669 else
670 ring->index_base = 0;
671 }
672
673 return 0;
674
675 err_dma_free:
676 bgmac_dma_free(bgmac);
677 return -ENOMEM;
678 }
679
680 static int bgmac_dma_init(struct bgmac *bgmac)
681 {
682 struct bgmac_dma_ring *ring;
683 int i, err;
684
685 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
686 ring = &bgmac->tx_ring[i];
687
688 if (!ring->unaligned)
689 bgmac_dma_tx_enable(bgmac, ring);
690 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
691 lower_32_bits(ring->dma_base));
692 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
693 upper_32_bits(ring->dma_base));
694 if (ring->unaligned)
695 bgmac_dma_tx_enable(bgmac, ring);
696
697 ring->start = 0;
698 ring->end = 0; /* Points the slot that should *not* be read */
699 }
700
701 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
702 int j;
703
704 ring = &bgmac->rx_ring[i];
705
706 if (!ring->unaligned)
707 bgmac_dma_rx_enable(bgmac, ring);
708 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
709 lower_32_bits(ring->dma_base));
710 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
711 upper_32_bits(ring->dma_base));
712 if (ring->unaligned)
713 bgmac_dma_rx_enable(bgmac, ring);
714
715 ring->start = 0;
716 ring->end = 0;
717 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
718 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
719 if (err)
720 goto error;
721
722 bgmac_dma_rx_setup_desc(bgmac, ring, j);
723 }
724
725 bgmac_dma_rx_update_index(bgmac, ring);
726 }
727
728 return 0;
729
730 error:
731 bgmac_dma_cleanup(bgmac);
732 return err;
733 }
734
735
736 /**************************************************
737 * Chip ops
738 **************************************************/
739
740 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
741 * nothing to change? Try if after stabilizng driver.
742 */
743 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
744 bool force)
745 {
746 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
747 u32 new_val = (cmdcfg & mask) | set;
748 u32 cmdcfg_sr;
749
750 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
751 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
752 else
753 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
754
755 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
756 udelay(2);
757
758 if (new_val != cmdcfg || force)
759 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
760
761 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
762 udelay(2);
763 }
764
765 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
766 {
767 u32 tmp;
768
769 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
770 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
771 tmp = (addr[4] << 8) | addr[5];
772 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
773 }
774
775 static void bgmac_set_rx_mode(struct net_device *net_dev)
776 {
777 struct bgmac *bgmac = netdev_priv(net_dev);
778
779 if (net_dev->flags & IFF_PROMISC)
780 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
781 else
782 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
783 }
784
785 #if 0 /* We don't use that regs yet */
786 static void bgmac_chip_stats_update(struct bgmac *bgmac)
787 {
788 int i;
789
790 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
791 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
792 bgmac->mib_tx_regs[i] =
793 bgmac_read(bgmac,
794 BGMAC_TX_GOOD_OCTETS + (i * 4));
795 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
796 bgmac->mib_rx_regs[i] =
797 bgmac_read(bgmac,
798 BGMAC_RX_GOOD_OCTETS + (i * 4));
799 }
800
801 /* TODO: what else? how to handle BCM4706? Specs are needed */
802 }
803 #endif
804
805 static void bgmac_clear_mib(struct bgmac *bgmac)
806 {
807 int i;
808
809 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
810 return;
811
812 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
813 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
814 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
815 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
816 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
817 }
818
819 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
820 static void bgmac_mac_speed(struct bgmac *bgmac)
821 {
822 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
823 u32 set = 0;
824
825 switch (bgmac->mac_speed) {
826 case SPEED_10:
827 set |= BGMAC_CMDCFG_ES_10;
828 break;
829 case SPEED_100:
830 set |= BGMAC_CMDCFG_ES_100;
831 break;
832 case SPEED_1000:
833 set |= BGMAC_CMDCFG_ES_1000;
834 break;
835 case SPEED_2500:
836 set |= BGMAC_CMDCFG_ES_2500;
837 break;
838 default:
839 dev_err(bgmac->dev, "Unsupported speed: %d\n",
840 bgmac->mac_speed);
841 }
842
843 if (bgmac->mac_duplex == DUPLEX_HALF)
844 set |= BGMAC_CMDCFG_HD;
845
846 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
847 }
848
849 static void bgmac_miiconfig(struct bgmac *bgmac)
850 {
851 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
852 bgmac_idm_write(bgmac, BCMA_IOCTL,
853 bgmac_idm_read(bgmac, BCMA_IOCTL) | 0x40 |
854 BGMAC_BCMA_IOCTL_SW_CLKEN);
855 bgmac->mac_speed = SPEED_2500;
856 bgmac->mac_duplex = DUPLEX_FULL;
857 bgmac_mac_speed(bgmac);
858 } else {
859 u8 imode;
860
861 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
862 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
863 if (imode == 0 || imode == 1) {
864 bgmac->mac_speed = SPEED_100;
865 bgmac->mac_duplex = DUPLEX_FULL;
866 bgmac_mac_speed(bgmac);
867 }
868 }
869 }
870
871 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
872 static void bgmac_chip_reset(struct bgmac *bgmac)
873 {
874 u32 cmdcfg_sr;
875 u32 iost;
876 int i;
877
878 if (bgmac_clk_enabled(bgmac)) {
879 if (!bgmac->stats_grabbed) {
880 /* bgmac_chip_stats_update(bgmac); */
881 bgmac->stats_grabbed = true;
882 }
883
884 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
885 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
886
887 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
888 udelay(1);
889
890 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
891 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
892
893 /* TODO: Clear software multicast filter list */
894 }
895
896 iost = bgmac_idm_read(bgmac, BCMA_IOST);
897 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
898 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
899
900 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
901 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
902 u32 flags = 0;
903 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
904 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
905 if (!bgmac->has_robosw)
906 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
907 }
908 bgmac_clk_enable(bgmac, flags);
909 }
910
911 /* Request Misc PLL for corerev > 2 */
912 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
913 bgmac_set(bgmac, BCMA_CLKCTLST,
914 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
915 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
916 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
917 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
918 1000);
919 }
920
921 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
922 u8 et_swtype = 0;
923 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
924 BGMAC_CHIPCTL_1_IF_TYPE_MII;
925 char buf[4];
926
927 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
928 if (kstrtou8(buf, 0, &et_swtype))
929 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
930 buf);
931 et_swtype &= 0x0f;
932 et_swtype <<= 4;
933 sw_type = et_swtype;
934 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
935 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
936 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
937 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
938 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
939 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
940 }
941 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
942 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
943 sw_type);
944 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
945 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
946 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
947 u8 et_swtype = 0;
948 char buf[4];
949
950 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
951 if (kstrtou8(buf, 0, &et_swtype))
952 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
953 buf);
954 sw_type = (et_swtype & 0x0f) << 12;
955 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
956 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
957 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
958 }
959 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
960 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
961 sw_type);
962 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
963 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
964 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
965 }
966
967 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
968 bgmac_idm_write(bgmac, BCMA_IOCTL,
969 bgmac_idm_read(bgmac, BCMA_IOCTL) &
970 ~BGMAC_BCMA_IOCTL_SW_RESET);
971
972 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
973 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
974 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
975 * be keps until taking MAC out of the reset.
976 */
977 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
978 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
979 else
980 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
981
982 bgmac_cmdcfg_maskset(bgmac,
983 ~(BGMAC_CMDCFG_TE |
984 BGMAC_CMDCFG_RE |
985 BGMAC_CMDCFG_RPI |
986 BGMAC_CMDCFG_TAI |
987 BGMAC_CMDCFG_HD |
988 BGMAC_CMDCFG_ML |
989 BGMAC_CMDCFG_CFE |
990 BGMAC_CMDCFG_RL |
991 BGMAC_CMDCFG_RED |
992 BGMAC_CMDCFG_PE |
993 BGMAC_CMDCFG_TPI |
994 BGMAC_CMDCFG_PAD_EN |
995 BGMAC_CMDCFG_PF),
996 BGMAC_CMDCFG_PROM |
997 BGMAC_CMDCFG_NLC |
998 BGMAC_CMDCFG_CFE |
999 cmdcfg_sr,
1000 false);
1001 bgmac->mac_speed = SPEED_UNKNOWN;
1002 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1003
1004 bgmac_clear_mib(bgmac);
1005 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1006 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1007 BCMA_GMAC_CMN_PC_MTE);
1008 else
1009 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1010 bgmac_miiconfig(bgmac);
1011 if (bgmac->mii_bus)
1012 bgmac->mii_bus->reset(bgmac->mii_bus);
1013
1014 netdev_reset_queue(bgmac->net_dev);
1015 }
1016
1017 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1018 {
1019 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1020 }
1021
1022 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1023 {
1024 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1025 bgmac_read(bgmac, BGMAC_INT_MASK);
1026 }
1027
1028 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1029 static void bgmac_enable(struct bgmac *bgmac)
1030 {
1031 u32 cmdcfg_sr;
1032 u32 cmdcfg;
1033 u32 mode;
1034
1035 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1036 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1037 else
1038 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1039
1040 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1041 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1042 cmdcfg_sr, true);
1043 udelay(2);
1044 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1045 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1046
1047 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1048 BGMAC_DS_MM_SHIFT;
1049 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1050 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1051 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST && mode == 2)
1052 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1053 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1054
1055 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1056 BGMAC_FEAT_FLW_CTRL2)) {
1057 u32 fl_ctl;
1058
1059 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1060 fl_ctl = 0x2300e1;
1061 else
1062 fl_ctl = 0x03cb04cb;
1063
1064 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1065 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1066 }
1067
1068 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1069 u32 rxq_ctl;
1070 u16 bp_clk;
1071 u8 mdp;
1072
1073 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1074 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1075 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1076 mdp = (bp_clk * 128 / 1000) - 3;
1077 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1078 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1079 }
1080 }
1081
1082 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1083 static void bgmac_chip_init(struct bgmac *bgmac)
1084 {
1085 /* 1 interrupt per received frame */
1086 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1087
1088 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1089 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1090
1091 bgmac_set_rx_mode(bgmac->net_dev);
1092
1093 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1094
1095 if (bgmac->loopback)
1096 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1097 else
1098 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1099
1100 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1101
1102 bgmac_chip_intrs_on(bgmac);
1103
1104 bgmac_enable(bgmac);
1105 }
1106
1107 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1108 {
1109 struct bgmac *bgmac = netdev_priv(dev_id);
1110
1111 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1112 int_status &= bgmac->int_mask;
1113
1114 if (!int_status)
1115 return IRQ_NONE;
1116
1117 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1118 if (int_status)
1119 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1120
1121 /* Disable new interrupts until handling existing ones */
1122 bgmac_chip_intrs_off(bgmac);
1123
1124 napi_schedule(&bgmac->napi);
1125
1126 return IRQ_HANDLED;
1127 }
1128
1129 static int bgmac_poll(struct napi_struct *napi, int weight)
1130 {
1131 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1132 int handled = 0;
1133
1134 /* Ack */
1135 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1136
1137 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1138 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1139
1140 /* Poll again if more events arrived in the meantime */
1141 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1142 return weight;
1143
1144 if (handled < weight) {
1145 napi_complete(napi);
1146 bgmac_chip_intrs_on(bgmac);
1147 }
1148
1149 return handled;
1150 }
1151
1152 /**************************************************
1153 * net_device_ops
1154 **************************************************/
1155
1156 static int bgmac_open(struct net_device *net_dev)
1157 {
1158 struct bgmac *bgmac = netdev_priv(net_dev);
1159 int err = 0;
1160
1161 bgmac_chip_reset(bgmac);
1162
1163 err = bgmac_dma_init(bgmac);
1164 if (err)
1165 return err;
1166
1167 /* Specs say about reclaiming rings here, but we do that in DMA init */
1168 bgmac_chip_init(bgmac);
1169
1170 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1171 KBUILD_MODNAME, net_dev);
1172 if (err < 0) {
1173 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1174 bgmac_dma_cleanup(bgmac);
1175 return err;
1176 }
1177 napi_enable(&bgmac->napi);
1178
1179 phy_start(net_dev->phydev);
1180
1181 netif_start_queue(net_dev);
1182
1183 return 0;
1184 }
1185
1186 static int bgmac_stop(struct net_device *net_dev)
1187 {
1188 struct bgmac *bgmac = netdev_priv(net_dev);
1189
1190 netif_carrier_off(net_dev);
1191
1192 phy_stop(net_dev->phydev);
1193
1194 napi_disable(&bgmac->napi);
1195 bgmac_chip_intrs_off(bgmac);
1196 free_irq(bgmac->irq, net_dev);
1197
1198 bgmac_chip_reset(bgmac);
1199 bgmac_dma_cleanup(bgmac);
1200
1201 return 0;
1202 }
1203
1204 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1205 struct net_device *net_dev)
1206 {
1207 struct bgmac *bgmac = netdev_priv(net_dev);
1208 struct bgmac_dma_ring *ring;
1209
1210 /* No QOS support yet */
1211 ring = &bgmac->tx_ring[0];
1212 return bgmac_dma_tx_add(bgmac, ring, skb);
1213 }
1214
1215 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1216 {
1217 struct bgmac *bgmac = netdev_priv(net_dev);
1218 int ret;
1219
1220 ret = eth_prepare_mac_addr_change(net_dev, addr);
1221 if (ret < 0)
1222 return ret;
1223 bgmac_write_mac_address(bgmac, (u8 *)addr);
1224 eth_commit_mac_addr_change(net_dev, addr);
1225 return 0;
1226 }
1227
1228 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1229 {
1230 if (!netif_running(net_dev))
1231 return -EINVAL;
1232
1233 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1234 }
1235
1236 static const struct net_device_ops bgmac_netdev_ops = {
1237 .ndo_open = bgmac_open,
1238 .ndo_stop = bgmac_stop,
1239 .ndo_start_xmit = bgmac_start_xmit,
1240 .ndo_set_rx_mode = bgmac_set_rx_mode,
1241 .ndo_set_mac_address = bgmac_set_mac_address,
1242 .ndo_validate_addr = eth_validate_addr,
1243 .ndo_do_ioctl = bgmac_ioctl,
1244 };
1245
1246 /**************************************************
1247 * ethtool_ops
1248 **************************************************/
1249
1250 struct bgmac_stat {
1251 u8 size;
1252 u32 offset;
1253 const char *name;
1254 };
1255
1256 static struct bgmac_stat bgmac_get_strings_stats[] = {
1257 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1258 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1259 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1260 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1261 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1262 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1263 { 4, BGMAC_TX_LEN_64, "tx_64" },
1264 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1265 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1266 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1267 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1268 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1269 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1270 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1271 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1272 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1273 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1274 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1275 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1276 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1277 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1278 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1279 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1280 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1281 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1282 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1283 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1284 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1285 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1286 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1287 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1288 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1289 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1290 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1291 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1292 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1293 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1294 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1295 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1296 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1297 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1298 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1299 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1300 { 4, BGMAC_RX_LEN_64, "rx_64" },
1301 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1302 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1303 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1304 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1305 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1306 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1307 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1308 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1309 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1310 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1311 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1312 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1313 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1314 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1315 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1316 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1317 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1318 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1319 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1320 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1321 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1322 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1323 };
1324
1325 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1326
1327 static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1328 {
1329 switch (string_set) {
1330 case ETH_SS_STATS:
1331 return BGMAC_STATS_LEN;
1332 }
1333
1334 return -EOPNOTSUPP;
1335 }
1336
1337 static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1338 u8 *data)
1339 {
1340 int i;
1341
1342 if (stringset != ETH_SS_STATS)
1343 return;
1344
1345 for (i = 0; i < BGMAC_STATS_LEN; i++)
1346 strlcpy(data + i * ETH_GSTRING_LEN,
1347 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1348 }
1349
1350 static void bgmac_get_ethtool_stats(struct net_device *dev,
1351 struct ethtool_stats *ss, uint64_t *data)
1352 {
1353 struct bgmac *bgmac = netdev_priv(dev);
1354 const struct bgmac_stat *s;
1355 unsigned int i;
1356 u64 val;
1357
1358 if (!netif_running(dev))
1359 return;
1360
1361 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1362 s = &bgmac_get_strings_stats[i];
1363 val = 0;
1364 if (s->size == 8)
1365 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1366 val |= bgmac_read(bgmac, s->offset);
1367 data[i] = val;
1368 }
1369 }
1370
1371 static void bgmac_get_drvinfo(struct net_device *net_dev,
1372 struct ethtool_drvinfo *info)
1373 {
1374 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1375 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1376 }
1377
1378 static const struct ethtool_ops bgmac_ethtool_ops = {
1379 .get_strings = bgmac_get_strings,
1380 .get_sset_count = bgmac_get_sset_count,
1381 .get_ethtool_stats = bgmac_get_ethtool_stats,
1382 .get_drvinfo = bgmac_get_drvinfo,
1383 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1384 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1385 };
1386
1387 /**************************************************
1388 * MII
1389 **************************************************/
1390
1391 static void bgmac_adjust_link(struct net_device *net_dev)
1392 {
1393 struct bgmac *bgmac = netdev_priv(net_dev);
1394 struct phy_device *phy_dev = net_dev->phydev;
1395 bool update = false;
1396
1397 if (phy_dev->link) {
1398 if (phy_dev->speed != bgmac->mac_speed) {
1399 bgmac->mac_speed = phy_dev->speed;
1400 update = true;
1401 }
1402
1403 if (phy_dev->duplex != bgmac->mac_duplex) {
1404 bgmac->mac_duplex = phy_dev->duplex;
1405 update = true;
1406 }
1407 }
1408
1409 if (update) {
1410 bgmac_mac_speed(bgmac);
1411 phy_print_status(phy_dev);
1412 }
1413 }
1414
1415 static int bgmac_phy_connect_direct(struct bgmac *bgmac)
1416 {
1417 struct fixed_phy_status fphy_status = {
1418 .link = 1,
1419 .speed = SPEED_1000,
1420 .duplex = DUPLEX_FULL,
1421 };
1422 struct phy_device *phy_dev;
1423 int err;
1424
1425 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1426 if (!phy_dev || IS_ERR(phy_dev)) {
1427 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1428 return -ENODEV;
1429 }
1430
1431 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1432 PHY_INTERFACE_MODE_MII);
1433 if (err) {
1434 dev_err(bgmac->dev, "Connecting PHY failed\n");
1435 return err;
1436 }
1437
1438 return err;
1439 }
1440
1441 static int bgmac_phy_connect(struct bgmac *bgmac)
1442 {
1443 struct phy_device *phy_dev;
1444 char bus_id[MII_BUS_ID_SIZE + 3];
1445
1446 /* Connect to the PHY */
1447 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
1448 bgmac->phyaddr);
1449 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1450 PHY_INTERFACE_MODE_MII);
1451 if (IS_ERR(phy_dev)) {
1452 dev_err(bgmac->dev, "PHY connecton failed\n");
1453 return PTR_ERR(phy_dev);
1454 }
1455
1456 return 0;
1457 }
1458
1459 int bgmac_enet_probe(struct bgmac *info)
1460 {
1461 struct net_device *net_dev;
1462 struct bgmac *bgmac;
1463 int err;
1464
1465 /* Allocation and references */
1466 net_dev = alloc_etherdev(sizeof(*bgmac));
1467 if (!net_dev)
1468 return -ENOMEM;
1469
1470 net_dev->netdev_ops = &bgmac_netdev_ops;
1471 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1472 bgmac = netdev_priv(net_dev);
1473 memcpy(bgmac, info, sizeof(*bgmac));
1474 bgmac->net_dev = net_dev;
1475 net_dev->irq = bgmac->irq;
1476 SET_NETDEV_DEV(net_dev, bgmac->dev);
1477
1478 if (!is_valid_ether_addr(bgmac->mac_addr)) {
1479 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1480 bgmac->mac_addr);
1481 eth_random_addr(bgmac->mac_addr);
1482 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1483 bgmac->mac_addr);
1484 }
1485 ether_addr_copy(net_dev->dev_addr, bgmac->mac_addr);
1486
1487 /* This (reset &) enable is not preset in specs or reference driver but
1488 * Broadcom does it in arch PCI code when enabling fake PCI device.
1489 */
1490 bgmac_clk_enable(bgmac, 0);
1491
1492 /* This seems to be fixing IRQ by assigning OOB #6 to the core */
1493 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1494 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1495
1496 bgmac_chip_reset(bgmac);
1497
1498 err = bgmac_dma_alloc(bgmac);
1499 if (err) {
1500 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1501 goto err_netdev_free;
1502 }
1503
1504 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1505 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1506 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1507
1508 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1509
1510 if (!bgmac->mii_bus)
1511 err = bgmac_phy_connect_direct(bgmac);
1512 else
1513 err = bgmac_phy_connect(bgmac);
1514 if (err) {
1515 dev_err(bgmac->dev, "Cannot connect to phy\n");
1516 goto err_dma_free;
1517 }
1518
1519 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1520 net_dev->hw_features = net_dev->features;
1521 net_dev->vlan_features = net_dev->features;
1522
1523 err = register_netdev(bgmac->net_dev);
1524 if (err) {
1525 dev_err(bgmac->dev, "Cannot register net device\n");
1526 goto err_phy_disconnect;
1527 }
1528
1529 netif_carrier_off(net_dev);
1530
1531 return 0;
1532
1533 err_phy_disconnect:
1534 phy_disconnect(net_dev->phydev);
1535 err_dma_free:
1536 bgmac_dma_free(bgmac);
1537 err_netdev_free:
1538 free_netdev(net_dev);
1539
1540 return err;
1541 }
1542 EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1543
1544 void bgmac_enet_remove(struct bgmac *bgmac)
1545 {
1546 unregister_netdev(bgmac->net_dev);
1547 phy_disconnect(bgmac->net_dev->phydev);
1548 netif_napi_del(&bgmac->napi);
1549 bgmac_dma_free(bgmac);
1550 free_netdev(bgmac->net_dev);
1551 }
1552 EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1553
1554 MODULE_AUTHOR("Rafał Miłecki");
1555 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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