1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
63 #include "bnx2x_init.h"
64 #include "bnx2x_init_ops.h"
65 #include "bnx2x_cmn.h"
66 #include "bnx2x_vfpf.h"
67 #include "bnx2x_dcb.h"
69 #include <linux/firmware.h>
70 #include "bnx2x_fw_file_hdr.h"
72 #define FW_FILE_VERSION \
73 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
74 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
75 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
76 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
77 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
78 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
79 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
81 /* Time in jiffies before concluding the transmitter is hung */
82 #define TX_TIMEOUT (5*HZ)
84 static char version
[] =
85 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
86 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
88 MODULE_AUTHOR("Eliezer Tamir");
89 MODULE_DESCRIPTION("QLogic "
90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
93 MODULE_LICENSE("GPL");
94 MODULE_VERSION(DRV_MODULE_VERSION
);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
96 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
97 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
100 module_param_named(num_queues
, bnx2x_num_queues
, int, S_IRUGO
);
101 MODULE_PARM_DESC(num_queues
,
102 " Set number of queues (default is as a number of CPUs)");
104 static int disable_tpa
;
105 module_param(disable_tpa
, int, S_IRUGO
);
106 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
109 module_param(int_mode
, int, S_IRUGO
);
110 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
113 static int dropless_fc
;
114 module_param(dropless_fc
, int, S_IRUGO
);
115 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
117 static int mrrs
= -1;
118 module_param(mrrs
, int, S_IRUGO
);
119 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
122 module_param(debug
, int, S_IRUGO
);
123 MODULE_PARM_DESC(debug
, " Default debug msglevel");
125 static struct workqueue_struct
*bnx2x_wq
;
126 struct workqueue_struct
*bnx2x_iov_wq
;
128 struct bnx2x_mac_vals
{
139 enum bnx2x_board_type
{
163 /* indexed by board_type, above */
167 [BCM57710
] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
168 [BCM57711
] = { "QLogic BCM57711 10 Gigabit PCIe" },
169 [BCM57711E
] = { "QLogic BCM57711E 10 Gigabit PCIe" },
170 [BCM57712
] = { "QLogic BCM57712 10 Gigabit Ethernet" },
171 [BCM57712_MF
] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
172 [BCM57712_VF
] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
173 [BCM57800
] = { "QLogic BCM57800 10 Gigabit Ethernet" },
174 [BCM57800_MF
] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
175 [BCM57800_VF
] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
176 [BCM57810
] = { "QLogic BCM57810 10 Gigabit Ethernet" },
177 [BCM57810_MF
] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
178 [BCM57810_VF
] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
179 [BCM57840_4_10
] = { "QLogic BCM57840 10 Gigabit Ethernet" },
180 [BCM57840_2_20
] = { "QLogic BCM57840 20 Gigabit Ethernet" },
181 [BCM57840_MF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
182 [BCM57840_VF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
183 [BCM57811
] = { "QLogic BCM57811 10 Gigabit Ethernet" },
184 [BCM57811_MF
] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
185 [BCM57840_O
] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
186 [BCM57840_MFO
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
187 [BCM57811_VF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
190 #ifndef PCI_DEVICE_ID_NX2_57710
191 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
193 #ifndef PCI_DEVICE_ID_NX2_57711
194 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
196 #ifndef PCI_DEVICE_ID_NX2_57711E
197 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
199 #ifndef PCI_DEVICE_ID_NX2_57712
200 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
202 #ifndef PCI_DEVICE_ID_NX2_57712_MF
203 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
205 #ifndef PCI_DEVICE_ID_NX2_57712_VF
206 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
208 #ifndef PCI_DEVICE_ID_NX2_57800
209 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
211 #ifndef PCI_DEVICE_ID_NX2_57800_MF
212 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
214 #ifndef PCI_DEVICE_ID_NX2_57800_VF
215 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
217 #ifndef PCI_DEVICE_ID_NX2_57810
218 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
220 #ifndef PCI_DEVICE_ID_NX2_57810_MF
221 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
223 #ifndef PCI_DEVICE_ID_NX2_57840_O
224 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
226 #ifndef PCI_DEVICE_ID_NX2_57810_VF
227 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
229 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
230 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
232 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
233 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
235 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
236 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
238 #ifndef PCI_DEVICE_ID_NX2_57840_MF
239 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
241 #ifndef PCI_DEVICE_ID_NX2_57840_VF
242 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
244 #ifndef PCI_DEVICE_ID_NX2_57811
245 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
247 #ifndef PCI_DEVICE_ID_NX2_57811_MF
248 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
250 #ifndef PCI_DEVICE_ID_NX2_57811_VF
251 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
254 static const struct pci_device_id bnx2x_pci_tbl
[] = {
255 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
256 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
257 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
258 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
259 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
260 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_VF
), BCM57712_VF
},
261 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
262 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
263 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_VF
), BCM57800_VF
},
264 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
265 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
266 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_O
), BCM57840_O
},
267 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
268 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
269 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_2_20
), BCM57840_2_20
},
270 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_VF
), BCM57810_VF
},
271 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MFO
), BCM57840_MFO
},
272 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
273 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
274 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
275 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
276 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811
), BCM57811
},
277 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_MF
), BCM57811_MF
},
278 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_VF
), BCM57811_VF
},
282 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
284 /* Global resources for unloading a previously loaded device */
285 #define BNX2X_PREV_WAIT_NEEDED 1
286 static DEFINE_SEMAPHORE(bnx2x_prev_sem
);
287 static LIST_HEAD(bnx2x_prev_list
);
289 /* Forward declaration */
290 static struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
);
291 static u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
);
292 static int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
);
294 /****************************************************************************
295 * General service functions
296 ****************************************************************************/
298 static int bnx2x_hwtstamp_ioctl(struct bnx2x
*bp
, struct ifreq
*ifr
);
300 static void __storm_memset_dma_mapping(struct bnx2x
*bp
,
301 u32 addr
, dma_addr_t mapping
)
303 REG_WR(bp
, addr
, U64_LO(mapping
));
304 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
307 static void storm_memset_spq_addr(struct bnx2x
*bp
,
308 dma_addr_t mapping
, u16 abs_fid
)
310 u32 addr
= XSEM_REG_FAST_MEMORY
+
311 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
313 __storm_memset_dma_mapping(bp
, addr
, mapping
);
316 static void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
319 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
321 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
323 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
325 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
329 static void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
332 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
334 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
336 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
338 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
342 static void storm_memset_eq_data(struct bnx2x
*bp
,
343 struct event_ring_data
*eq_data
,
346 size_t size
= sizeof(struct event_ring_data
);
348 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
350 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
353 static void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
356 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
357 REG_WR16(bp
, addr
, eq_prod
);
361 * locking is done by mcp
363 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
365 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
366 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
367 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
368 PCICFG_VENDOR_ID_OFFSET
);
371 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
375 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
376 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
377 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
378 PCICFG_VENDOR_ID_OFFSET
);
383 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
384 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
385 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
386 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
387 #define DMAE_DP_DST_NONE "dst_addr [none]"
389 static void bnx2x_dp_dmae(struct bnx2x
*bp
,
390 struct dmae_command
*dmae
, int msglvl
)
392 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
395 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
396 case DMAE_CMD_DST_PCI
:
397 if (src_type
== DMAE_CMD_SRC_PCI
)
398 DP(msglvl
, "DMAE: opcode 0x%08x\n"
399 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
402 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
403 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
406 DP(msglvl
, "DMAE: opcode 0x%08x\n"
407 "src [%08x], len [%d*4], dst [%x:%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
410 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
411 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
414 case DMAE_CMD_DST_GRC
:
415 if (src_type
== DMAE_CMD_SRC_PCI
)
416 DP(msglvl
, "DMAE: opcode 0x%08x\n"
417 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
420 dmae
->len
, dmae
->dst_addr_lo
>> 2,
421 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
424 DP(msglvl
, "DMAE: opcode 0x%08x\n"
425 "src [%08x], len [%d*4], dst [%08x]\n"
426 "comp_addr [%x:%08x], comp_val 0x%08x\n",
427 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
428 dmae
->len
, dmae
->dst_addr_lo
>> 2,
429 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
433 if (src_type
== DMAE_CMD_SRC_PCI
)
434 DP(msglvl
, "DMAE: opcode 0x%08x\n"
435 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
436 "comp_addr [%x:%08x] comp_val 0x%08x\n",
437 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
438 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
441 DP(msglvl
, "DMAE: opcode 0x%08x\n"
442 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
443 "comp_addr [%x:%08x] comp_val 0x%08x\n",
444 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
445 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
450 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++)
451 DP(msglvl
, "DMAE RAW [%02d]: 0x%08x\n",
452 i
, *(((u32
*)dmae
) + i
));
455 /* copy command into DMAE command memory and set DMAE command go */
456 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
461 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
462 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
463 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
465 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
468 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
470 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
474 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
476 return opcode
& ~DMAE_CMD_SRC_RESET
;
479 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
480 bool with_comp
, u8 comp_type
)
484 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
485 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
487 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
489 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
490 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
491 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
492 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
495 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
497 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
500 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
504 void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
505 struct dmae_command
*dmae
,
506 u8 src_type
, u8 dst_type
)
508 memset(dmae
, 0, sizeof(struct dmae_command
));
511 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
512 true, DMAE_COMP_PCI
);
514 /* fill in the completion parameters */
515 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
516 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
517 dmae
->comp_val
= DMAE_COMP_VAL
;
520 /* issue a dmae command over the init-channel and wait for completion */
521 int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
, struct dmae_command
*dmae
,
524 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
527 bnx2x_dp_dmae(bp
, dmae
, BNX2X_MSG_DMAE
);
529 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
530 * as long as this code is called both from syscall context and
531 * from ndo_set_rx_mode() flow that may be called from BH.
534 spin_lock_bh(&bp
->dmae_lock
);
536 /* reset completion */
539 /* post the command on the channel used for initializations */
540 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
542 /* wait for completion */
544 while ((*comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
547 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
548 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
549 BNX2X_ERR("DMAE timeout!\n");
556 if (*comp
& DMAE_PCI_ERR_FLAG
) {
557 BNX2X_ERR("DMAE PCI error!\n");
563 spin_unlock_bh(&bp
->dmae_lock
);
568 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
572 struct dmae_command dmae
;
574 if (!bp
->dmae_ready
) {
575 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
578 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
580 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
584 /* set opcode and fixed command fields */
585 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
587 /* fill in addresses and len */
588 dmae
.src_addr_lo
= U64_LO(dma_addr
);
589 dmae
.src_addr_hi
= U64_HI(dma_addr
);
590 dmae
.dst_addr_lo
= dst_addr
>> 2;
591 dmae
.dst_addr_hi
= 0;
594 /* issue the command and wait for completion */
595 rc
= bnx2x_issue_dmae_with_comp(bp
, &dmae
, bnx2x_sp(bp
, wb_comp
));
597 BNX2X_ERR("DMAE returned failure %d\n", rc
);
598 #ifdef BNX2X_STOP_ON_ERROR
604 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
607 struct dmae_command dmae
;
609 if (!bp
->dmae_ready
) {
610 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
614 for (i
= 0; i
< len32
; i
++)
615 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
617 for (i
= 0; i
< len32
; i
++)
618 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
623 /* set opcode and fixed command fields */
624 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
626 /* fill in addresses and len */
627 dmae
.src_addr_lo
= src_addr
>> 2;
628 dmae
.src_addr_hi
= 0;
629 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
630 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
633 /* issue the command and wait for completion */
634 rc
= bnx2x_issue_dmae_with_comp(bp
, &dmae
, bnx2x_sp(bp
, wb_comp
));
636 BNX2X_ERR("DMAE returned failure %d\n", rc
);
637 #ifdef BNX2X_STOP_ON_ERROR
643 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
646 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
649 while (len
> dmae_wr_max
) {
650 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
651 addr
+ offset
, dmae_wr_max
);
652 offset
+= dmae_wr_max
* 4;
656 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
668 #define REGS_IN_ENTRY 4
670 static inline int bnx2x_get_assert_list_entry(struct bnx2x
*bp
,
676 return XSTORM_ASSERT_LIST_OFFSET(entry
);
678 return TSTORM_ASSERT_LIST_OFFSET(entry
);
680 return CSTORM_ASSERT_LIST_OFFSET(entry
);
682 return USTORM_ASSERT_LIST_OFFSET(entry
);
685 BNX2X_ERR("unknown storm\n");
690 static int bnx2x_mc_assert(struct bnx2x
*bp
)
695 u32 regs
[REGS_IN_ENTRY
];
696 u32 bar_storm_intmem
[STORMS_NUM
] = {
702 u32 storm_assert_list_index
[STORMS_NUM
] = {
703 XSTORM_ASSERT_LIST_INDEX_OFFSET
,
704 TSTORM_ASSERT_LIST_INDEX_OFFSET
,
705 CSTORM_ASSERT_LIST_INDEX_OFFSET
,
706 USTORM_ASSERT_LIST_INDEX_OFFSET
708 char *storms_string
[STORMS_NUM
] = {
715 for (storm
= XSTORM
; storm
< MAX_STORMS
; storm
++) {
716 last_idx
= REG_RD8(bp
, bar_storm_intmem
[storm
] +
717 storm_assert_list_index
[storm
]);
719 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
720 storms_string
[storm
], last_idx
);
722 /* print the asserts */
723 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
724 /* read a single assert entry */
725 for (j
= 0; j
< REGS_IN_ENTRY
; j
++)
726 regs
[j
] = REG_RD(bp
, bar_storm_intmem
[storm
] +
727 bnx2x_get_assert_list_entry(bp
,
732 /* log entry if it contains a valid assert */
733 if (regs
[0] != COMMON_ASM_INVALID_ASSERT_OPCODE
) {
734 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
735 storms_string
[storm
], i
, regs
[3],
736 regs
[2], regs
[1], regs
[0]);
744 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
745 CHIP_IS_E1(bp
) ? "everest1" :
746 CHIP_IS_E1H(bp
) ? "everest1h" :
747 CHIP_IS_E2(bp
) ? "everest2" : "everest3",
748 BCM_5710_FW_MAJOR_VERSION
,
749 BCM_5710_FW_MINOR_VERSION
,
750 BCM_5710_FW_REVISION_VERSION
);
755 #define MCPR_TRACE_BUFFER_SIZE (0x800)
756 #define SCRATCH_BUFFER_SIZE(bp) \
757 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
759 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
765 u32 trace_shmem_base
;
767 BNX2X_ERR("NO MCP - can not dump\n");
770 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
771 (bp
->common
.bc_ver
& 0xff0000) >> 16,
772 (bp
->common
.bc_ver
& 0xff00) >> 8,
773 (bp
->common
.bc_ver
& 0xff));
775 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
776 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
777 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl
, val
);
779 if (BP_PATH(bp
) == 0)
780 trace_shmem_base
= bp
->common
.shmem_base
;
782 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
785 if (trace_shmem_base
< MCPR_SCRATCH_BASE(bp
) + MCPR_TRACE_BUFFER_SIZE
||
786 trace_shmem_base
>= MCPR_SCRATCH_BASE(bp
) +
787 SCRATCH_BUFFER_SIZE(bp
)) {
788 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
793 addr
= trace_shmem_base
- MCPR_TRACE_BUFFER_SIZE
;
795 /* validate TRCB signature */
796 mark
= REG_RD(bp
, addr
);
797 if (mark
!= MFW_TRACE_SIGNATURE
) {
798 BNX2X_ERR("Trace buffer signature is missing.");
802 /* read cyclic buffer pointer */
804 mark
= REG_RD(bp
, addr
);
805 mark
= MCPR_SCRATCH_BASE(bp
) + ((mark
+ 0x3) & ~0x3) - 0x08000000;
806 if (mark
>= trace_shmem_base
|| mark
< addr
+ 4) {
807 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
810 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
814 /* dump buffer after the mark */
815 for (offset
= mark
; offset
< trace_shmem_base
; offset
+= 0x8*4) {
816 for (word
= 0; word
< 8; word
++)
817 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
819 pr_cont("%s", (char *)data
);
822 /* dump buffer before the mark */
823 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
824 for (word
= 0; word
< 8; word
++)
825 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
827 pr_cont("%s", (char *)data
);
829 printk("%s" "end of fw dump\n", lvl
);
832 static void bnx2x_fw_dump(struct bnx2x
*bp
)
834 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
837 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
839 int port
= BP_PORT(bp
);
840 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
841 u32 val
= REG_RD(bp
, addr
);
843 /* in E1 we must use only PCI configuration space to disable
844 * MSI/MSIX capability
845 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
847 if (CHIP_IS_E1(bp
)) {
848 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
849 * Use mask register to prevent from HC sending interrupts
850 * after we exit the function
852 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
854 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
855 HC_CONFIG_0_REG_INT_LINE_EN_0
|
856 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
858 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
859 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
860 HC_CONFIG_0_REG_INT_LINE_EN_0
|
861 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
864 "write %x to HC %d (addr 0x%x)\n",
867 /* flush all outstanding writes */
870 REG_WR(bp
, addr
, val
);
871 if (REG_RD(bp
, addr
) != val
)
872 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
875 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
877 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
879 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
880 IGU_PF_CONF_INT_LINE_EN
|
881 IGU_PF_CONF_ATTN_BIT_EN
);
883 DP(NETIF_MSG_IFDOWN
, "write %x to IGU\n", val
);
885 /* flush all outstanding writes */
888 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
889 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
890 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
893 static void bnx2x_int_disable(struct bnx2x
*bp
)
895 if (bp
->common
.int_block
== INT_BLOCK_HC
)
896 bnx2x_hc_int_disable(bp
);
898 bnx2x_igu_int_disable(bp
);
901 void bnx2x_panic_dump(struct bnx2x
*bp
, bool disable_int
)
905 struct hc_sp_status_block_data sp_sb_data
;
906 int func
= BP_FUNC(bp
);
907 #ifdef BNX2X_STOP_ON_ERROR
908 u16 start
= 0, end
= 0;
911 if (IS_PF(bp
) && disable_int
)
912 bnx2x_int_disable(bp
);
914 bp
->stats_state
= STATS_STATE_DISABLED
;
915 bp
->eth_stats
.unrecoverable_error
++;
916 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
918 BNX2X_ERR("begin crash dump -----------------\n");
923 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
924 int data_size
, cstorm_offset
;
926 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
927 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
928 bp
->spq_prod_idx
, bp
->stats_counter
);
929 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
930 def_sb
->atten_status_block
.attn_bits
,
931 def_sb
->atten_status_block
.attn_bits_ack
,
932 def_sb
->atten_status_block
.status_block_id
,
933 def_sb
->atten_status_block
.attn_bits_index
);
935 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
937 def_sb
->sp_sb
.index_values
[i
],
938 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
940 data_size
= sizeof(struct hc_sp_status_block_data
) /
942 cstorm_offset
= CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
);
943 for (i
= 0; i
< data_size
; i
++)
944 *((u32
*)&sp_sb_data
+ i
) =
945 REG_RD(bp
, BAR_CSTRORM_INTMEM
+ cstorm_offset
+
948 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
949 sp_sb_data
.igu_sb_id
,
950 sp_sb_data
.igu_seg_id
,
951 sp_sb_data
.p_func
.pf_id
,
952 sp_sb_data
.p_func
.vnic_id
,
953 sp_sb_data
.p_func
.vf_id
,
954 sp_sb_data
.p_func
.vf_valid
,
958 for_each_eth_queue(bp
, i
) {
959 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
961 struct hc_status_block_data_e2 sb_data_e2
;
962 struct hc_status_block_data_e1x sb_data_e1x
;
963 struct hc_status_block_sm
*hc_sm_p
=
965 sb_data_e1x
.common
.state_machine
:
966 sb_data_e2
.common
.state_machine
;
967 struct hc_index_data
*hc_index_p
=
969 sb_data_e1x
.index_data
:
970 sb_data_e2
.index_data
;
973 struct bnx2x_fp_txdata txdata
;
982 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
983 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
985 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
986 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
987 fp
->rx_sge_prod
, fp
->last_max_sge
,
988 le16_to_cpu(fp
->fp_hc_idx
));
991 for_each_cos_in_tx_queue(fp
, cos
)
993 if (!fp
->txdata_ptr
[cos
])
996 txdata
= *fp
->txdata_ptr
[cos
];
998 if (!txdata
.tx_cons_sb
)
1001 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1002 i
, txdata
.tx_pkt_prod
,
1003 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
1005 le16_to_cpu(*txdata
.tx_cons_sb
));
1008 loop
= CHIP_IS_E1x(bp
) ?
1009 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
1016 BNX2X_ERR(" run indexes (");
1017 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
1019 fp
->sb_running_index
[j
],
1020 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
1022 BNX2X_ERR(" indexes (");
1023 for (j
= 0; j
< loop
; j
++)
1025 fp
->sb_index_values
[j
],
1026 (j
== loop
- 1) ? ")" : " ");
1028 /* VF cannot access FW refelection for status block */
1033 data_size
= CHIP_IS_E1x(bp
) ?
1034 sizeof(struct hc_status_block_data_e1x
) :
1035 sizeof(struct hc_status_block_data_e2
);
1036 data_size
/= sizeof(u32
);
1037 sb_data_p
= CHIP_IS_E1x(bp
) ?
1038 (u32
*)&sb_data_e1x
:
1040 /* copy sb data in here */
1041 for (j
= 0; j
< data_size
; j
++)
1042 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
1043 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
1046 if (!CHIP_IS_E1x(bp
)) {
1047 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1048 sb_data_e2
.common
.p_func
.pf_id
,
1049 sb_data_e2
.common
.p_func
.vf_id
,
1050 sb_data_e2
.common
.p_func
.vf_valid
,
1051 sb_data_e2
.common
.p_func
.vnic_id
,
1052 sb_data_e2
.common
.same_igu_sb_1b
,
1053 sb_data_e2
.common
.state
);
1055 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1056 sb_data_e1x
.common
.p_func
.pf_id
,
1057 sb_data_e1x
.common
.p_func
.vf_id
,
1058 sb_data_e1x
.common
.p_func
.vf_valid
,
1059 sb_data_e1x
.common
.p_func
.vnic_id
,
1060 sb_data_e1x
.common
.same_igu_sb_1b
,
1061 sb_data_e1x
.common
.state
);
1065 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
1066 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1067 j
, hc_sm_p
[j
].__flags
,
1068 hc_sm_p
[j
].igu_sb_id
,
1069 hc_sm_p
[j
].igu_seg_id
,
1070 hc_sm_p
[j
].time_to_expire
,
1071 hc_sm_p
[j
].timer_value
);
1075 for (j
= 0; j
< loop
; j
++) {
1076 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j
,
1077 hc_index_p
[j
].flags
,
1078 hc_index_p
[j
].timeout
);
1082 #ifdef BNX2X_STOP_ON_ERROR
1085 BNX2X_ERR("eq cons %x prod %x\n", bp
->eq_cons
, bp
->eq_prod
);
1086 for (i
= 0; i
< NUM_EQ_DESC
; i
++) {
1087 u32
*data
= (u32
*)&bp
->eq_ring
[i
].message
.data
;
1089 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1090 i
, bp
->eq_ring
[i
].message
.opcode
,
1091 bp
->eq_ring
[i
].message
.error
);
1092 BNX2X_ERR("data: %x %x %x\n",
1093 data
[0], data
[1], data
[2]);
1099 for_each_valid_rx_queue(bp
, i
) {
1100 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1105 if (!fp
->rx_cons_sb
)
1108 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
1109 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
1110 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
1111 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
1112 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
1114 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1115 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
1118 start
= RX_SGE(fp
->rx_sge_prod
);
1119 end
= RX_SGE(fp
->last_max_sge
);
1120 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
1121 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
1122 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
1124 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1125 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
1128 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
1129 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
1130 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
1131 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
1133 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1134 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
1139 for_each_valid_tx_queue(bp
, i
) {
1140 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1145 for_each_cos_in_tx_queue(fp
, cos
) {
1146 struct bnx2x_fp_txdata
*txdata
= fp
->txdata_ptr
[cos
];
1148 if (!fp
->txdata_ptr
[cos
])
1151 if (!txdata
->tx_cons_sb
)
1154 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
1155 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
1156 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1157 struct sw_tx_bd
*sw_bd
=
1158 &txdata
->tx_buf_ring
[j
];
1160 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1161 i
, cos
, j
, sw_bd
->skb
,
1165 start
= TX_BD(txdata
->tx_bd_cons
- 10);
1166 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
1167 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1168 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
1170 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1171 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1172 tx_bd
[2], tx_bd
[3]);
1179 bnx2x_mc_assert(bp
);
1181 BNX2X_ERR("end crash dump -----------------\n");
1185 * FLR Support for E2
1187 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1190 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1191 #define FLR_WAIT_INTERVAL 50 /* usec */
1192 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1194 struct pbf_pN_buf_regs
{
1201 struct pbf_pN_cmd_regs
{
1207 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1208 struct pbf_pN_buf_regs
*regs
,
1211 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1212 u32 cur_cnt
= poll_count
;
1214 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1215 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1216 init_crd
= REG_RD(bp
, regs
->init_crd
);
1218 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1219 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1220 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1222 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1223 (init_crd
- crd_start
))) {
1225 udelay(FLR_WAIT_INTERVAL
);
1226 crd
= REG_RD(bp
, regs
->crd
);
1227 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1229 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1231 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1233 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1234 regs
->pN
, crd_freed
);
1238 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1239 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1242 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1243 struct pbf_pN_cmd_regs
*regs
,
1246 u32 occup
, to_free
, freed
, freed_start
;
1247 u32 cur_cnt
= poll_count
;
1249 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1250 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1252 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1253 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1255 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1257 udelay(FLR_WAIT_INTERVAL
);
1258 occup
= REG_RD(bp
, regs
->lines_occup
);
1259 freed
= REG_RD(bp
, regs
->lines_freed
);
1261 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1263 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1265 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1270 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1271 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1274 static u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1275 u32 expected
, u32 poll_count
)
1277 u32 cur_cnt
= poll_count
;
1280 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1281 udelay(FLR_WAIT_INTERVAL
);
1286 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1287 char *msg
, u32 poll_cnt
)
1289 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1291 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1297 /* Common routines with VF FLR cleanup */
1298 u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1300 /* adjust polling timeout */
1301 if (CHIP_REV_IS_EMUL(bp
))
1302 return FLR_POLL_CNT
* 2000;
1304 if (CHIP_REV_IS_FPGA(bp
))
1305 return FLR_POLL_CNT
* 120;
1307 return FLR_POLL_CNT
;
1310 void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1312 struct pbf_pN_cmd_regs cmd_regs
[] = {
1313 {0, (CHIP_IS_E3B0(bp
)) ?
1314 PBF_REG_TQ_OCCUPANCY_Q0
:
1315 PBF_REG_P0_TQ_OCCUPANCY
,
1316 (CHIP_IS_E3B0(bp
)) ?
1317 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1318 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1319 {1, (CHIP_IS_E3B0(bp
)) ?
1320 PBF_REG_TQ_OCCUPANCY_Q1
:
1321 PBF_REG_P1_TQ_OCCUPANCY
,
1322 (CHIP_IS_E3B0(bp
)) ?
1323 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1324 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1325 {4, (CHIP_IS_E3B0(bp
)) ?
1326 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1327 PBF_REG_P4_TQ_OCCUPANCY
,
1328 (CHIP_IS_E3B0(bp
)) ?
1329 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1330 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1333 struct pbf_pN_buf_regs buf_regs
[] = {
1334 {0, (CHIP_IS_E3B0(bp
)) ?
1335 PBF_REG_INIT_CRD_Q0
:
1336 PBF_REG_P0_INIT_CRD
,
1337 (CHIP_IS_E3B0(bp
)) ?
1340 (CHIP_IS_E3B0(bp
)) ?
1341 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1342 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1343 {1, (CHIP_IS_E3B0(bp
)) ?
1344 PBF_REG_INIT_CRD_Q1
:
1345 PBF_REG_P1_INIT_CRD
,
1346 (CHIP_IS_E3B0(bp
)) ?
1349 (CHIP_IS_E3B0(bp
)) ?
1350 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1351 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1352 {4, (CHIP_IS_E3B0(bp
)) ?
1353 PBF_REG_INIT_CRD_LB_Q
:
1354 PBF_REG_P4_INIT_CRD
,
1355 (CHIP_IS_E3B0(bp
)) ?
1356 PBF_REG_CREDIT_LB_Q
:
1358 (CHIP_IS_E3B0(bp
)) ?
1359 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1360 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1365 /* Verify the command queues are flushed P0, P1, P4 */
1366 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1367 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1369 /* Verify the transmission buffers are flushed P0, P1, P4 */
1370 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1371 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1374 #define OP_GEN_PARAM(param) \
1375 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1377 #define OP_GEN_TYPE(type) \
1378 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1380 #define OP_GEN_AGG_VECT(index) \
1381 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1383 int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
, u32 poll_cnt
)
1385 u32 op_gen_command
= 0;
1386 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1387 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1390 if (REG_RD(bp
, comp_addr
)) {
1391 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1395 op_gen_command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1396 op_gen_command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1397 op_gen_command
|= OP_GEN_AGG_VECT(clnup_func
);
1398 op_gen_command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1400 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1401 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen_command
);
1403 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1404 BNX2X_ERR("FW final cleanup did not succeed\n");
1405 DP(BNX2X_MSG_SP
, "At timeout completion address contained %x\n",
1406 (REG_RD(bp
, comp_addr
)));
1410 /* Zero completion for next FLR */
1411 REG_WR(bp
, comp_addr
, 0);
1416 u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1420 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
1421 return status
& PCI_EXP_DEVSTA_TRPND
;
1424 /* PF FLR specific routines
1426 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1428 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1429 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1430 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1431 "CFC PF usage counter timed out",
1435 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1436 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1437 DORQ_REG_PF_USAGE_CNT
,
1438 "DQ PF usage counter timed out",
1442 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1443 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1444 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1445 "QM PF usage counter timed out",
1449 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1450 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1451 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1452 "Timers VNIC usage counter timed out",
1455 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1456 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1457 "Timers NUM_SCANS usage counter timed out",
1461 /* Wait DMAE PF usage counter to zero */
1462 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1463 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1464 "DMAE command register timed out",
1471 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1475 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1476 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1478 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1479 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1481 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1482 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1484 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1485 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1487 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1488 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1490 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1491 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1493 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1494 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1496 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1497 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1501 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1503 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1505 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1507 /* Re-enable PF target read access */
1508 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1510 /* Poll HW usage counters */
1511 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1512 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1515 /* Zero the igu 'trailing edge' and 'leading edge' */
1517 /* Send the FW cleanup command */
1518 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1523 /* Verify TX hw is flushed */
1524 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1526 /* Wait 100ms (not adjusted according to platform) */
1529 /* Verify no pending pci transactions */
1530 if (bnx2x_is_pcie_pending(bp
->pdev
))
1531 BNX2X_ERR("PCIE Transactions still pending\n");
1534 bnx2x_hw_enable_status(bp
);
1537 * Master enable - Due to WB DMAE writes performed before this
1538 * register is re-initialized as part of the regular function init
1540 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1545 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1547 int port
= BP_PORT(bp
);
1548 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1549 u32 val
= REG_RD(bp
, addr
);
1550 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1551 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1552 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1555 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1556 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1557 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1558 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1560 val
|= HC_CONFIG_0_REG_SINGLE_ISR_EN_0
;
1562 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1563 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1564 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1565 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1567 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1568 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1569 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1570 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1572 if (!CHIP_IS_E1(bp
)) {
1574 "write %x to HC %d (addr 0x%x)\n", val
, port
, addr
);
1576 REG_WR(bp
, addr
, val
);
1578 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1583 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1586 "write %x to HC %d (addr 0x%x) mode %s\n", val
, port
, addr
,
1587 (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1589 REG_WR(bp
, addr
, val
);
1591 * Ensure that HC_CONFIG is written before leading/trailing edge config
1596 if (!CHIP_IS_E1(bp
)) {
1597 /* init leading/trailing edge */
1599 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1601 /* enable nig and gpio3 attention */
1606 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1607 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1610 /* Make sure that interrupts are indeed enabled from here on */
1614 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1617 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1618 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1619 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1621 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1624 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1625 IGU_PF_CONF_SINGLE_ISR_EN
);
1626 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1627 IGU_PF_CONF_ATTN_BIT_EN
);
1630 val
|= IGU_PF_CONF_SINGLE_ISR_EN
;
1632 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1633 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1634 IGU_PF_CONF_ATTN_BIT_EN
|
1635 IGU_PF_CONF_SINGLE_ISR_EN
);
1637 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1638 val
|= (IGU_PF_CONF_INT_LINE_EN
|
1639 IGU_PF_CONF_ATTN_BIT_EN
|
1640 IGU_PF_CONF_SINGLE_ISR_EN
);
1643 /* Clean previous status - need to configure igu prior to ack*/
1644 if ((!msix
) || single_msix
) {
1645 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1649 val
|= IGU_PF_CONF_FUNC_EN
;
1651 DP(NETIF_MSG_IFUP
, "write 0x%x to IGU mode %s\n",
1652 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1654 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1656 if (val
& IGU_PF_CONF_INT_LINE_EN
)
1657 pci_intx(bp
->pdev
, true);
1661 /* init leading/trailing edge */
1663 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1665 /* enable nig and gpio3 attention */
1670 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1671 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1673 /* Make sure that interrupts are indeed enabled from here on */
1677 void bnx2x_int_enable(struct bnx2x
*bp
)
1679 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1680 bnx2x_hc_int_enable(bp
);
1682 bnx2x_igu_int_enable(bp
);
1685 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1687 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1691 /* prevent the HW from sending interrupts */
1692 bnx2x_int_disable(bp
);
1694 /* make sure all ISRs are done */
1696 synchronize_irq(bp
->msix_table
[0].vector
);
1698 if (CNIC_SUPPORT(bp
))
1700 for_each_eth_queue(bp
, i
)
1701 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1703 synchronize_irq(bp
->pdev
->irq
);
1705 /* make sure sp_task is not running */
1706 cancel_delayed_work(&bp
->sp_task
);
1707 cancel_delayed_work(&bp
->period_task
);
1708 flush_workqueue(bnx2x_wq
);
1714 * General service functions
1717 /* Return true if succeeded to acquire the lock */
1718 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1721 u32 resource_bit
= (1 << resource
);
1722 int func
= BP_FUNC(bp
);
1723 u32 hw_lock_control_reg
;
1725 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1726 "Trying to take a lock on resource %d\n", resource
);
1728 /* Validating that the resource is within range */
1729 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1730 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1731 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1732 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1737 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1739 hw_lock_control_reg
=
1740 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1742 /* Try to acquire the lock */
1743 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1744 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1745 if (lock_status
& resource_bit
)
1748 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1749 "Failed to get a lock on resource %d\n", resource
);
1754 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1756 * @bp: driver handle
1758 * Returns the recovery leader resource id according to the engine this function
1759 * belongs to. Currently only only 2 engines is supported.
1761 static int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1764 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1766 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1770 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1772 * @bp: driver handle
1774 * Tries to acquire a leader lock for current engine.
1776 static bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1778 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1781 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1783 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1784 static int bnx2x_schedule_sp_task(struct bnx2x
*bp
)
1786 /* Set the interrupt occurred bit for the sp-task to recognize it
1787 * must ack the interrupt and transition according to the IGU
1790 atomic_set(&bp
->interrupt_occurred
, 1);
1792 /* The sp_task must execute only after this bit
1793 * is set, otherwise we will get out of sync and miss all
1794 * further interrupts. Hence, the barrier.
1798 /* schedule sp_task to workqueue */
1799 return queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1802 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1804 struct bnx2x
*bp
= fp
->bp
;
1805 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1806 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1807 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1808 struct bnx2x_queue_sp_obj
*q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
1811 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1812 fp
->index
, cid
, command
, bp
->state
,
1813 rr_cqe
->ramrod_cqe
.ramrod_type
);
1815 /* If cid is within VF range, replace the slowpath object with the
1816 * one corresponding to this VF
1818 if (cid
>= BNX2X_FIRST_VF_CID
&&
1819 cid
< BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)
1820 bnx2x_iov_set_queue_sp_obj(bp
, cid
, &q_obj
);
1823 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1824 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1825 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1828 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1829 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1830 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1833 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1834 DP(BNX2X_MSG_SP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1835 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1838 case (RAMROD_CMD_ID_ETH_HALT
):
1839 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1840 drv_cmd
= BNX2X_Q_CMD_HALT
;
1843 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1844 DP(BNX2X_MSG_SP
, "got MULTI[%d] terminate ramrod\n", cid
);
1845 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1848 case (RAMROD_CMD_ID_ETH_EMPTY
):
1849 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1850 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1853 case (RAMROD_CMD_ID_ETH_TPA_UPDATE
):
1854 DP(BNX2X_MSG_SP
, "got tpa update ramrod CID=%d\n", cid
);
1855 drv_cmd
= BNX2X_Q_CMD_UPDATE_TPA
;
1859 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1860 command
, fp
->index
);
1864 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1865 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1866 /* q_obj->complete_cmd() failure means that this was
1867 * an unexpected completion.
1869 * In this case we don't want to increase the bp->spq_left
1870 * because apparently we haven't sent this command the first
1873 #ifdef BNX2X_STOP_ON_ERROR
1879 smp_mb__before_atomic();
1880 atomic_inc(&bp
->cq_spq_left
);
1881 /* push the change in bp->spq_left and towards the memory */
1882 smp_mb__after_atomic();
1884 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1886 if ((drv_cmd
== BNX2X_Q_CMD_UPDATE
) && (IS_FCOE_FP(fp
)) &&
1887 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
))) {
1888 /* if Q update ramrod is completed for last Q in AFEX vif set
1889 * flow, then ACK MCP at the end
1891 * mark pending ACK to MCP bit.
1892 * prevent case that both bits are cleared.
1893 * At the end of load/unload driver checks that
1894 * sp_state is cleared, and this order prevents
1897 smp_mb__before_atomic();
1898 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
, &bp
->sp_state
);
1900 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
1901 smp_mb__after_atomic();
1903 /* schedule the sp task as mcp ack is required */
1904 bnx2x_schedule_sp_task(bp
);
1910 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1912 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1913 u16 status
= bnx2x_ack_int(bp
);
1918 /* Return here if interrupt is shared and it's not for us */
1919 if (unlikely(status
== 0)) {
1920 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1923 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1925 #ifdef BNX2X_STOP_ON_ERROR
1926 if (unlikely(bp
->panic
))
1930 for_each_eth_queue(bp
, i
) {
1931 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1933 mask
= 0x2 << (fp
->index
+ CNIC_SUPPORT(bp
));
1934 if (status
& mask
) {
1935 /* Handle Rx or Tx according to SB id */
1936 for_each_cos_in_tx_queue(fp
, cos
)
1937 prefetch(fp
->txdata_ptr
[cos
]->tx_cons_sb
);
1938 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1939 napi_schedule_irqoff(&bnx2x_fp(bp
, fp
->index
, napi
));
1944 if (CNIC_SUPPORT(bp
)) {
1946 if (status
& (mask
| 0x1)) {
1947 struct cnic_ops
*c_ops
= NULL
;
1950 c_ops
= rcu_dereference(bp
->cnic_ops
);
1951 if (c_ops
&& (bp
->cnic_eth_dev
.drv_state
&
1952 CNIC_DRV_STATE_HANDLES_IRQ
))
1953 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1960 if (unlikely(status
& 0x1)) {
1962 /* schedule sp task to perform default status block work, ack
1963 * attentions and enable interrupts.
1965 bnx2x_schedule_sp_task(bp
);
1972 if (unlikely(status
))
1973 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1982 * General service functions
1985 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1988 u32 resource_bit
= (1 << resource
);
1989 int func
= BP_FUNC(bp
);
1990 u32 hw_lock_control_reg
;
1993 /* Validating that the resource is within range */
1994 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1995 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1996 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
2001 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
2003 hw_lock_control_reg
=
2004 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
2007 /* Validating that the resource is not already taken */
2008 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2009 if (lock_status
& resource_bit
) {
2010 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2011 lock_status
, resource_bit
);
2015 /* Try for 5 second every 5ms */
2016 for (cnt
= 0; cnt
< 1000; cnt
++) {
2017 /* Try to acquire the lock */
2018 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
2019 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2020 if (lock_status
& resource_bit
)
2023 usleep_range(5000, 10000);
2025 BNX2X_ERR("Timeout\n");
2029 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
2031 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
2034 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
2037 u32 resource_bit
= (1 << resource
);
2038 int func
= BP_FUNC(bp
);
2039 u32 hw_lock_control_reg
;
2041 /* Validating that the resource is within range */
2042 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
2043 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2044 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
2049 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
2051 hw_lock_control_reg
=
2052 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
2055 /* Validating that the resource is currently taken */
2056 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2057 if (!(lock_status
& resource_bit
)) {
2058 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2059 lock_status
, resource_bit
);
2063 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
2067 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
2069 /* The GPIO should be swapped if swap register is set and active */
2070 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2071 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2072 int gpio_shift
= gpio_num
+
2073 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2074 u32 gpio_mask
= (1 << gpio_shift
);
2078 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2079 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2083 /* read GPIO value */
2084 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2086 /* get the requested pin value */
2087 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
2095 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2097 /* The GPIO should be swapped if swap register is set and active */
2098 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2099 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2100 int gpio_shift
= gpio_num
+
2101 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2102 u32 gpio_mask
= (1 << gpio_shift
);
2105 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2106 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2110 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2111 /* read GPIO and mask except the float bits */
2112 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
2115 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2117 "Set GPIO %d (shift %d) -> output low\n",
2118 gpio_num
, gpio_shift
);
2119 /* clear FLOAT and set CLR */
2120 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2121 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
2124 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2126 "Set GPIO %d (shift %d) -> output high\n",
2127 gpio_num
, gpio_shift
);
2128 /* clear FLOAT and set SET */
2129 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2130 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
2133 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2135 "Set GPIO %d (shift %d) -> input\n",
2136 gpio_num
, gpio_shift
);
2138 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2145 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2146 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2151 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
2156 /* Any port swapping should be handled by caller. */
2158 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2159 /* read GPIO and mask except the float bits */
2160 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2161 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2162 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2163 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2166 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2167 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2169 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2172 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2173 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2175 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2178 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2179 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2181 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2185 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2191 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2193 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2198 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2200 /* The GPIO should be swapped if swap register is set and active */
2201 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2202 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2203 int gpio_shift
= gpio_num
+
2204 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2205 u32 gpio_mask
= (1 << gpio_shift
);
2208 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2209 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2213 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2215 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2218 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2220 "Clear GPIO INT %d (shift %d) -> output low\n",
2221 gpio_num
, gpio_shift
);
2222 /* clear SET and set CLR */
2223 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2224 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2227 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2229 "Set GPIO INT %d (shift %d) -> output high\n",
2230 gpio_num
, gpio_shift
);
2231 /* clear CLR and set SET */
2232 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2233 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2240 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2241 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2246 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio
, u32 mode
)
2250 /* Only 2 SPIOs are configurable */
2251 if ((spio
!= MISC_SPIO_SPIO4
) && (spio
!= MISC_SPIO_SPIO5
)) {
2252 BNX2X_ERR("Invalid SPIO 0x%x\n", spio
);
2256 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2257 /* read SPIO and mask except the float bits */
2258 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_SPIO_FLOAT
);
2261 case MISC_SPIO_OUTPUT_LOW
:
2262 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output low\n", spio
);
2263 /* clear FLOAT and set CLR */
2264 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2265 spio_reg
|= (spio
<< MISC_SPIO_CLR_POS
);
2268 case MISC_SPIO_OUTPUT_HIGH
:
2269 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output high\n", spio
);
2270 /* clear FLOAT and set SET */
2271 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2272 spio_reg
|= (spio
<< MISC_SPIO_SET_POS
);
2275 case MISC_SPIO_INPUT_HI_Z
:
2276 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> input\n", spio
);
2278 spio_reg
|= (spio
<< MISC_SPIO_FLOAT_POS
);
2285 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2286 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2291 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2293 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2295 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2297 switch (bp
->link_vars
.ieee_fc
&
2298 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2299 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2300 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2304 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2305 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2313 static void bnx2x_set_requested_fc(struct bnx2x
*bp
)
2315 /* Initialize link parameters structure variables
2316 * It is recommended to turn off RX FC for jumbo frames
2317 * for better performance
2319 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2320 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2322 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2325 static void bnx2x_init_dropless_fc(struct bnx2x
*bp
)
2327 u32 pause_enabled
= 0;
2329 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
&& bp
->link_vars
.link_up
) {
2330 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2333 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2334 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp
)),
2338 DP(NETIF_MSG_IFUP
| NETIF_MSG_LINK
, "dropless_fc is %s\n",
2339 pause_enabled
? "enabled" : "disabled");
2342 int bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2344 int rc
, cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2345 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2347 if (!BP_NOMCP(bp
)) {
2348 bnx2x_set_requested_fc(bp
);
2349 bnx2x_acquire_phy_lock(bp
);
2351 if (load_mode
== LOAD_DIAG
) {
2352 struct link_params
*lp
= &bp
->link_params
;
2353 lp
->loopback_mode
= LOOPBACK_XGXS
;
2354 /* Prefer doing PHY loopback at highest speed */
2355 if (lp
->req_line_speed
[cfx_idx
] < SPEED_20000
) {
2356 if (lp
->speed_cap_mask
[cfx_idx
] &
2357 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)
2358 lp
->req_line_speed
[cfx_idx
] =
2360 else if (lp
->speed_cap_mask
[cfx_idx
] &
2361 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2362 lp
->req_line_speed
[cfx_idx
] =
2365 lp
->req_line_speed
[cfx_idx
] =
2370 if (load_mode
== LOAD_LOOPBACK_EXT
) {
2371 struct link_params
*lp
= &bp
->link_params
;
2372 lp
->loopback_mode
= LOOPBACK_EXT
;
2375 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2377 bnx2x_release_phy_lock(bp
);
2379 bnx2x_init_dropless_fc(bp
);
2381 bnx2x_calc_fc_adv(bp
);
2383 if (bp
->link_vars
.link_up
) {
2384 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2385 bnx2x_link_report(bp
);
2387 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2388 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2391 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2395 void bnx2x_link_set(struct bnx2x
*bp
)
2397 if (!BP_NOMCP(bp
)) {
2398 bnx2x_acquire_phy_lock(bp
);
2399 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2400 bnx2x_release_phy_lock(bp
);
2402 bnx2x_init_dropless_fc(bp
);
2404 bnx2x_calc_fc_adv(bp
);
2406 BNX2X_ERR("Bootcode is missing - can not set link\n");
2409 static void bnx2x__link_reset(struct bnx2x
*bp
)
2411 if (!BP_NOMCP(bp
)) {
2412 bnx2x_acquire_phy_lock(bp
);
2413 bnx2x_lfa_reset(&bp
->link_params
, &bp
->link_vars
);
2414 bnx2x_release_phy_lock(bp
);
2416 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2419 void bnx2x_force_link_reset(struct bnx2x
*bp
)
2421 bnx2x_acquire_phy_lock(bp
);
2422 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2423 bnx2x_release_phy_lock(bp
);
2426 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2430 if (!BP_NOMCP(bp
)) {
2431 bnx2x_acquire_phy_lock(bp
);
2432 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2434 bnx2x_release_phy_lock(bp
);
2436 BNX2X_ERR("Bootcode is missing - can not test link\n");
2441 /* Calculates the sum of vn_min_rates.
2442 It's needed for further normalizing of the min_rates.
2444 sum of vn_min_rates.
2446 0 - if all the min_rates are 0.
2447 In the later case fairness algorithm should be deactivated.
2448 If not all min_rates are zero then those that are zeroes will be set to 1.
2450 static void bnx2x_calc_vn_min(struct bnx2x
*bp
,
2451 struct cmng_init_input
*input
)
2456 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2457 u32 vn_cfg
= bp
->mf_config
[vn
];
2458 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2459 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2461 /* Skip hidden vns */
2462 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2464 /* If min rate is zero - set it to 1 */
2465 else if (!vn_min_rate
)
2466 vn_min_rate
= DEF_MIN_RATE
;
2470 input
->vnic_min_rate
[vn
] = vn_min_rate
;
2473 /* if ETS or all min rates are zeros - disable fairness */
2474 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2475 input
->flags
.cmng_enables
&=
2476 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2477 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2478 } else if (all_zero
) {
2479 input
->flags
.cmng_enables
&=
2480 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2482 "All MIN values are zeroes fairness will be disabled\n");
2484 input
->flags
.cmng_enables
|=
2485 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2488 static void bnx2x_calc_vn_max(struct bnx2x
*bp
, int vn
,
2489 struct cmng_init_input
*input
)
2492 u32 vn_cfg
= bp
->mf_config
[vn
];
2494 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2497 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2499 if (IS_MF_PERCENT_BW(bp
)) {
2500 /* maxCfg in percents of linkspeed */
2501 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2502 } else /* SD modes */
2503 /* maxCfg is absolute in 100Mb units */
2504 vn_max_rate
= maxCfg
* 100;
2507 DP(NETIF_MSG_IFUP
, "vn %d: vn_max_rate %d\n", vn
, vn_max_rate
);
2509 input
->vnic_max_rate
[vn
] = vn_max_rate
;
2512 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2514 if (CHIP_REV_IS_SLOW(bp
))
2515 return CMNG_FNS_NONE
;
2517 return CMNG_FNS_MINMAX
;
2519 return CMNG_FNS_NONE
;
2522 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2524 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2527 return; /* what should be the default value in this case */
2529 /* For 2 port configuration the absolute function number formula
2531 * abs_func = 2 * vn + BP_PORT + BP_PATH
2533 * and there are 4 functions per port
2535 * For 4 port configuration it is
2536 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2538 * and there are 2 functions per port
2540 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2541 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2543 if (func
>= E1H_FUNC_MAX
)
2547 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2549 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
2550 DP(NETIF_MSG_IFUP
, "mf_cfg function disabled\n");
2551 bp
->flags
|= MF_FUNC_DIS
;
2553 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
2554 bp
->flags
&= ~MF_FUNC_DIS
;
2558 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2560 struct cmng_init_input input
;
2561 memset(&input
, 0, sizeof(struct cmng_init_input
));
2563 input
.port_rate
= bp
->link_vars
.line_speed
;
2565 if (cmng_type
== CMNG_FNS_MINMAX
&& input
.port_rate
) {
2568 /* read mf conf from shmem */
2570 bnx2x_read_mf_cfg(bp
);
2572 /* vn_weight_sum and enable fairness if not 0 */
2573 bnx2x_calc_vn_min(bp
, &input
);
2575 /* calculate and set min-max rate for each vn */
2577 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2578 bnx2x_calc_vn_max(bp
, vn
, &input
);
2580 /* always enable rate shaping and fairness */
2581 input
.flags
.cmng_enables
|=
2582 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2584 bnx2x_init_cmng(&input
, &bp
->cmng
);
2588 /* rate shaping and fairness are disabled */
2590 "rate shaping and fairness are disabled\n");
2593 static void storm_memset_cmng(struct bnx2x
*bp
,
2594 struct cmng_init
*cmng
,
2598 size_t size
= sizeof(struct cmng_struct_per_port
);
2600 u32 addr
= BAR_XSTRORM_INTMEM
+
2601 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
);
2603 __storm_memset_struct(bp
, addr
, size
, (u32
*)&cmng
->port
);
2605 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2606 int func
= func_by_vn(bp
, vn
);
2608 addr
= BAR_XSTRORM_INTMEM
+
2609 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
);
2610 size
= sizeof(struct rate_shaping_vars_per_vn
);
2611 __storm_memset_struct(bp
, addr
, size
,
2612 (u32
*)&cmng
->vnic
.vnic_max_rate
[vn
]);
2614 addr
= BAR_XSTRORM_INTMEM
+
2615 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
);
2616 size
= sizeof(struct fairness_vars_per_vn
);
2617 __storm_memset_struct(bp
, addr
, size
,
2618 (u32
*)&cmng
->vnic
.vnic_min_rate
[vn
]);
2622 /* init cmng mode in HW according to local configuration */
2623 void bnx2x_set_local_cmng(struct bnx2x
*bp
)
2625 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2627 if (cmng_fns
!= CMNG_FNS_NONE
) {
2628 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2629 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2631 /* rate shaping and fairness are disabled */
2633 "single function mode without fairness\n");
2637 /* This function is called upon link interrupt */
2638 static void bnx2x_link_attn(struct bnx2x
*bp
)
2640 /* Make sure that we are synced with the current statistics */
2641 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2643 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2645 bnx2x_init_dropless_fc(bp
);
2647 if (bp
->link_vars
.link_up
) {
2649 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2650 struct host_port_stats
*pstats
;
2652 pstats
= bnx2x_sp(bp
, port_stats
);
2653 /* reset old mac stats */
2654 memset(&(pstats
->mac_stx
[0]), 0,
2655 sizeof(struct mac_stx
));
2657 if (bp
->state
== BNX2X_STATE_OPEN
)
2658 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2661 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
)
2662 bnx2x_set_local_cmng(bp
);
2664 __bnx2x_link_report(bp
);
2667 bnx2x_link_sync_notify(bp
);
2670 void bnx2x__link_status_update(struct bnx2x
*bp
)
2672 if (bp
->state
!= BNX2X_STATE_OPEN
)
2675 /* read updated dcb configuration */
2677 bnx2x_dcbx_pmf_update(bp
);
2678 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2679 if (bp
->link_vars
.link_up
)
2680 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2682 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2683 /* indicate link status */
2684 bnx2x_link_report(bp
);
2687 bp
->port
.supported
[0] |= (SUPPORTED_10baseT_Half
|
2688 SUPPORTED_10baseT_Full
|
2689 SUPPORTED_100baseT_Half
|
2690 SUPPORTED_100baseT_Full
|
2691 SUPPORTED_1000baseT_Full
|
2692 SUPPORTED_2500baseX_Full
|
2693 SUPPORTED_10000baseT_Full
|
2698 SUPPORTED_Asym_Pause
);
2699 bp
->port
.advertising
[0] = bp
->port
.supported
[0];
2701 bp
->link_params
.bp
= bp
;
2702 bp
->link_params
.port
= BP_PORT(bp
);
2703 bp
->link_params
.req_duplex
[0] = DUPLEX_FULL
;
2704 bp
->link_params
.req_flow_ctrl
[0] = BNX2X_FLOW_CTRL_NONE
;
2705 bp
->link_params
.req_line_speed
[0] = SPEED_10000
;
2706 bp
->link_params
.speed_cap_mask
[0] = 0x7f0000;
2707 bp
->link_params
.switch_cfg
= SWITCH_CFG_10G
;
2708 bp
->link_vars
.mac_type
= MAC_TYPE_BMAC
;
2709 bp
->link_vars
.line_speed
= SPEED_10000
;
2710 bp
->link_vars
.link_status
=
2711 (LINK_STATUS_LINK_UP
|
2712 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
);
2713 bp
->link_vars
.link_up
= 1;
2714 bp
->link_vars
.duplex
= DUPLEX_FULL
;
2715 bp
->link_vars
.flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
2716 __bnx2x_link_report(bp
);
2718 bnx2x_sample_bulletin(bp
);
2720 /* if bulletin board did not have an update for link status
2721 * __bnx2x_link_report will report current status
2722 * but it will NOT duplicate report in case of already reported
2723 * during sampling bulletin board.
2725 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2729 static int bnx2x_afex_func_update(struct bnx2x
*bp
, u16 vifid
,
2730 u16 vlan_val
, u8 allowed_prio
)
2732 struct bnx2x_func_state_params func_params
= {NULL
};
2733 struct bnx2x_func_afex_update_params
*f_update_params
=
2734 &func_params
.params
.afex_update
;
2736 func_params
.f_obj
= &bp
->func_obj
;
2737 func_params
.cmd
= BNX2X_F_CMD_AFEX_UPDATE
;
2739 /* no need to wait for RAMROD completion, so don't
2740 * set RAMROD_COMP_WAIT flag
2743 f_update_params
->vif_id
= vifid
;
2744 f_update_params
->afex_default_vlan
= vlan_val
;
2745 f_update_params
->allowed_priorities
= allowed_prio
;
2747 /* if ramrod can not be sent, response to MCP immediately */
2748 if (bnx2x_func_state_change(bp
, &func_params
) < 0)
2749 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
2754 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x
*bp
, u8 cmd_type
,
2755 u16 vif_index
, u8 func_bit_map
)
2757 struct bnx2x_func_state_params func_params
= {NULL
};
2758 struct bnx2x_func_afex_viflists_params
*update_params
=
2759 &func_params
.params
.afex_viflists
;
2763 /* validate only LIST_SET and LIST_GET are received from switch */
2764 if ((cmd_type
!= VIF_LIST_RULE_GET
) && (cmd_type
!= VIF_LIST_RULE_SET
))
2765 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2768 func_params
.f_obj
= &bp
->func_obj
;
2769 func_params
.cmd
= BNX2X_F_CMD_AFEX_VIFLISTS
;
2771 /* set parameters according to cmd_type */
2772 update_params
->afex_vif_list_command
= cmd_type
;
2773 update_params
->vif_list_index
= vif_index
;
2774 update_params
->func_bit_map
=
2775 (cmd_type
== VIF_LIST_RULE_GET
) ? 0 : func_bit_map
;
2776 update_params
->func_to_clear
= 0;
2778 (cmd_type
== VIF_LIST_RULE_GET
) ?
2779 DRV_MSG_CODE_AFEX_LISTGET_ACK
:
2780 DRV_MSG_CODE_AFEX_LISTSET_ACK
;
2782 /* if ramrod can not be sent, respond to MCP immediately for
2783 * SET and GET requests (other are not triggered from MCP)
2785 rc
= bnx2x_func_state_change(bp
, &func_params
);
2787 bnx2x_fw_command(bp
, drv_msg_code
, 0);
2792 static void bnx2x_handle_afex_cmd(struct bnx2x
*bp
, u32 cmd
)
2794 struct afex_stats afex_stats
;
2795 u32 func
= BP_ABS_FUNC(bp
);
2802 u32 addr_to_write
, vifid
, addrs
, stats_type
, i
;
2804 if (cmd
& DRV_STATUS_AFEX_LISTGET_REQ
) {
2805 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2807 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid
);
2808 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_GET
, vifid
, 0);
2811 if (cmd
& DRV_STATUS_AFEX_LISTSET_REQ
) {
2812 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2813 addrs
= SHMEM2_RD(bp
, afex_param2_to_driver
[BP_FW_MB_IDX(bp
)]);
2815 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2817 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_SET
, vifid
,
2821 if (cmd
& DRV_STATUS_AFEX_STATSGET_REQ
) {
2822 addr_to_write
= SHMEM2_RD(bp
,
2823 afex_scratchpad_addr_to_write
[BP_FW_MB_IDX(bp
)]);
2824 stats_type
= SHMEM2_RD(bp
,
2825 afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2828 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2831 bnx2x_afex_collect_stats(bp
, (void *)&afex_stats
, stats_type
);
2833 /* write response to scratchpad, for MCP */
2834 for (i
= 0; i
< (sizeof(struct afex_stats
)/sizeof(u32
)); i
++)
2835 REG_WR(bp
, addr_to_write
+ i
*sizeof(u32
),
2836 *(((u32
*)(&afex_stats
))+i
));
2838 /* send ack message to MCP */
2839 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_STATSGET_ACK
, 0);
2842 if (cmd
& DRV_STATUS_AFEX_VIFSET_REQ
) {
2843 mf_config
= MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2844 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2846 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2849 /* if VIF_SET is "enabled" */
2850 if (!(mf_config
& FUNC_MF_CFG_FUNC_DISABLED
)) {
2851 /* set rate limit directly to internal RAM */
2852 struct cmng_init_input cmng_input
;
2853 struct rate_shaping_vars_per_vn m_rs_vn
;
2854 size_t size
= sizeof(struct rate_shaping_vars_per_vn
);
2855 u32 addr
= BAR_XSTRORM_INTMEM
+
2856 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp
));
2858 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2860 bnx2x_calc_vn_max(bp
, BP_VN(bp
), &cmng_input
);
2861 m_rs_vn
.vn_counter
.rate
=
2862 cmng_input
.vnic_max_rate
[BP_VN(bp
)];
2863 m_rs_vn
.vn_counter
.quota
=
2864 (m_rs_vn
.vn_counter
.rate
*
2865 RS_PERIODIC_TIMEOUT_USEC
) / 8;
2867 __storm_memset_struct(bp
, addr
, size
, (u32
*)&m_rs_vn
);
2869 /* read relevant values from mf_cfg struct in shmem */
2871 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2872 FUNC_MF_CFG_E1HOV_TAG_MASK
) >>
2873 FUNC_MF_CFG_E1HOV_TAG_SHIFT
;
2875 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2876 FUNC_MF_CFG_AFEX_VLAN_MASK
) >>
2877 FUNC_MF_CFG_AFEX_VLAN_SHIFT
;
2878 vlan_prio
= (mf_config
&
2879 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK
) >>
2880 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT
;
2881 vlan_val
|= (vlan_prio
<< VLAN_PRIO_SHIFT
);
2884 func_mf_config
[func
].afex_config
) &
2885 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK
) >>
2886 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT
;
2889 func_mf_config
[func
].afex_config
) &
2890 FUNC_MF_CFG_AFEX_COS_FILTER_MASK
) >>
2891 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT
;
2893 /* send ramrod to FW, return in case of failure */
2894 if (bnx2x_afex_func_update(bp
, vif_id
, vlan_val
,
2898 bp
->afex_def_vlan_tag
= vlan_val
;
2899 bp
->afex_vlan_mode
= vlan_mode
;
2901 /* notify link down because BP->flags is disabled */
2902 bnx2x_link_report(bp
);
2904 /* send INVALID VIF ramrod to FW */
2905 bnx2x_afex_func_update(bp
, 0xFFFF, 0, 0);
2907 /* Reset the default afex VLAN */
2908 bp
->afex_def_vlan_tag
= -1;
2913 static void bnx2x_handle_update_svid_cmd(struct bnx2x
*bp
)
2915 struct bnx2x_func_switch_update_params
*switch_update_params
;
2916 struct bnx2x_func_state_params func_params
;
2918 memset(&func_params
, 0, sizeof(struct bnx2x_func_state_params
));
2919 switch_update_params
= &func_params
.params
.switch_update
;
2920 func_params
.f_obj
= &bp
->func_obj
;
2921 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
2923 if (IS_MF_UFP(bp
) || IS_MF_BD(bp
)) {
2924 int func
= BP_ABS_FUNC(bp
);
2927 /* Re-learn the S-tag from shmem */
2928 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2929 FUNC_MF_CFG_E1HOV_TAG_MASK
;
2930 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
2933 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2937 /* Configure new S-tag in LLH */
2938 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ BP_PORT(bp
) * 8,
2941 /* Send Ramrod to update FW of change */
2942 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG
,
2943 &switch_update_params
->changes
);
2944 switch_update_params
->vlan
= bp
->mf_ov
;
2946 if (bnx2x_func_state_change(bp
, &func_params
) < 0) {
2947 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2951 DP(BNX2X_MSG_MCP
, "Configured S-tag %02x\n",
2958 bnx2x_fw_command(bp
, DRV_MSG_CODE_OEM_UPDATE_SVID_OK
, 0);
2961 bnx2x_fw_command(bp
, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE
, 0);
2964 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2966 int port
= BP_PORT(bp
);
2970 DP(BNX2X_MSG_MCP
, "pmf %d\n", bp
->port
.pmf
);
2973 * We need the mb() to ensure the ordering between the writing to
2974 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2978 /* queue a periodic task */
2979 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2981 bnx2x_dcbx_pmf_update(bp
);
2983 /* enable nig attention */
2984 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2985 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2986 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2987 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2988 } else if (!CHIP_IS_E1x(bp
)) {
2989 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2990 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2993 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
3001 * General service functions
3004 /* send the MCP a request, block until there is a reply */
3005 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
3007 int mb_idx
= BP_FW_MB_IDX(bp
);
3011 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
3013 mutex_lock(&bp
->fw_mb_mutex
);
3015 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
3016 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
3018 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
3019 (command
| seq
), param
);
3022 /* let the FW do it's magic ... */
3025 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
3027 /* Give the FW up to 5 second (500*10ms) */
3028 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
3030 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3031 cnt
*delay
, rc
, seq
);
3033 /* is this a reply to our command? */
3034 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
3035 rc
&= FW_MSG_CODE_MASK
;
3038 BNX2X_ERR("FW failed to respond!\n");
3042 mutex_unlock(&bp
->fw_mb_mutex
);
3047 static void storm_memset_func_cfg(struct bnx2x
*bp
,
3048 struct tstorm_eth_function_common_config
*tcfg
,
3051 size_t size
= sizeof(struct tstorm_eth_function_common_config
);
3053 u32 addr
= BAR_TSTRORM_INTMEM
+
3054 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid
);
3056 __storm_memset_struct(bp
, addr
, size
, (u32
*)tcfg
);
3059 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
3061 if (CHIP_IS_E1x(bp
)) {
3062 struct tstorm_eth_function_common_config tcfg
= {0};
3064 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
3067 /* Enable the function in the FW */
3068 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
3069 storm_memset_func_en(bp
, p
->func_id
, 1);
3072 if (p
->spq_active
) {
3073 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
3074 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
3075 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
3080 * bnx2x_get_common_flags - Return common flags
3084 * @zero_stats TRUE if statistics zeroing is needed
3086 * Return the flags that are common for the Tx-only and not normal connections.
3088 static unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
3089 struct bnx2x_fastpath
*fp
,
3092 unsigned long flags
= 0;
3094 /* PF driver will always initialize the Queue to an ACTIVE state */
3095 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
3097 /* tx only connections collect statistics (on the same index as the
3098 * parent connection). The statistics are zeroed when the parent
3099 * connection is initialized.
3102 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
3104 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
3106 if (bp
->flags
& TX_SWITCHING
)
3107 __set_bit(BNX2X_Q_FLG_TX_SWITCH
, &flags
);
3109 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT
, &flags
);
3110 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
, &flags
);
3112 #ifdef BNX2X_STOP_ON_ERROR
3113 __set_bit(BNX2X_Q_FLG_TX_SEC
, &flags
);
3119 static unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
3120 struct bnx2x_fastpath
*fp
,
3123 unsigned long flags
= 0;
3125 /* calculate other queue flags */
3127 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
3129 if (IS_FCOE_FP(fp
)) {
3130 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
3131 /* For FCoE - force usage of default priority (for afex) */
3132 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI
, &flags
);
3135 if (fp
->mode
!= TPA_MODE_DISABLED
) {
3136 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
3137 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
3138 if (fp
->mode
== TPA_MODE_GRO
)
3139 __set_bit(BNX2X_Q_FLG_TPA_GRO
, &flags
);
3143 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
3144 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
3147 /* Always set HW VLAN stripping */
3148 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
3150 /* configure silent vlan removal */
3152 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM
, &flags
);
3154 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
3157 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
3158 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
3161 gen_init
->stat_id
= bnx2x_stats_id(fp
);
3162 gen_init
->spcl_id
= fp
->cl_id
;
3164 /* Always use mini-jumbo MTU for FCoE L2 ring */
3166 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
3168 gen_init
->mtu
= bp
->dev
->mtu
;
3170 gen_init
->cos
= cos
;
3172 gen_init
->fp_hsi
= ETH_FP_HSI_VERSION
;
3175 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
3176 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
3177 struct bnx2x_rxq_setup_params
*rxq_init
)
3181 u16 tpa_agg_size
= 0;
3183 if (fp
->mode
!= TPA_MODE_DISABLED
) {
3184 pause
->sge_th_lo
= SGE_TH_LO(bp
);
3185 pause
->sge_th_hi
= SGE_TH_HI(bp
);
3187 /* validate SGE ring has enough to cross high threshold */
3188 WARN_ON(bp
->dropless_fc
&&
3189 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
3190 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
3192 tpa_agg_size
= TPA_AGG_SIZE
;
3193 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
3195 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
3196 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
3197 sge_sz
= (u16
)min_t(u32
, SGE_PAGES
, 0xffff);
3200 /* pause - not for e1 */
3201 if (!CHIP_IS_E1(bp
)) {
3202 pause
->bd_th_lo
= BD_TH_LO(bp
);
3203 pause
->bd_th_hi
= BD_TH_HI(bp
);
3205 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
3206 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
3208 * validate that rings have enough entries to cross
3211 WARN_ON(bp
->dropless_fc
&&
3212 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
3214 WARN_ON(bp
->dropless_fc
&&
3215 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
3216 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
3222 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
3223 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
3224 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
3225 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
3227 /* This should be a maximum number of data bytes that may be
3228 * placed on the BD (not including paddings).
3230 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
3231 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
3233 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
3234 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
3235 rxq_init
->sge_buf_sz
= sge_sz
;
3236 rxq_init
->max_sges_pkt
= max_sge
;
3237 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
3238 rxq_init
->mcast_engine_id
= BP_FUNC(bp
);
3240 /* Maximum number or simultaneous TPA aggregation for this Queue.
3242 * For PF Clients it should be the maximum available number.
3243 * VF driver(s) may want to define it to a smaller value.
3245 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
3247 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
3248 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
3251 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
3253 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
3254 /* configure silent vlan removal
3255 * if multi function mode is afex, then mask default vlan
3257 if (IS_MF_AFEX(bp
)) {
3258 rxq_init
->silent_removal_value
= bp
->afex_def_vlan_tag
;
3259 rxq_init
->silent_removal_mask
= VLAN_VID_MASK
;
3263 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
3264 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
3267 txq_init
->dscr_map
= fp
->txdata_ptr
[cos
]->tx_desc_mapping
;
3268 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
3269 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
3270 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
3273 * set the tss leading client id for TX classification ==
3274 * leading RSS client id
3276 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
3278 if (IS_FCOE_FP(fp
)) {
3279 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
3280 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
3284 static void bnx2x_pf_init(struct bnx2x
*bp
)
3286 struct bnx2x_func_init_params func_init
= {0};
3287 struct event_ring_data eq_data
= { {0} };
3289 if (!CHIP_IS_E1x(bp
)) {
3290 /* reset IGU PF statistics: MSIX + ATTN */
3292 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3293 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3294 (CHIP_MODE_IS_4_PORT(bp
) ?
3295 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3297 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3298 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3299 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
3300 (CHIP_MODE_IS_4_PORT(bp
) ?
3301 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3304 func_init
.spq_active
= true;
3305 func_init
.pf_id
= BP_FUNC(bp
);
3306 func_init
.func_id
= BP_FUNC(bp
);
3307 func_init
.spq_map
= bp
->spq_mapping
;
3308 func_init
.spq_prod
= bp
->spq_prod_idx
;
3310 bnx2x_func_init(bp
, &func_init
);
3312 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
3315 * Congestion management values depend on the link rate
3316 * There is no active link so initial link rate is set to 10 Gbps.
3317 * When the link comes up The congestion management values are
3318 * re-calculated according to the actual link rate.
3320 bp
->link_vars
.line_speed
= SPEED_10000
;
3321 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
3323 /* Only the PMF sets the HW */
3325 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3327 /* init Event Queue - PCI bus guarantees correct endianity*/
3328 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
3329 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
3330 eq_data
.producer
= bp
->eq_prod
;
3331 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
3332 eq_data
.sb_id
= DEF_SB_ID
;
3333 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
3336 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
3338 int port
= BP_PORT(bp
);
3340 bnx2x_tx_disable(bp
);
3342 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
3345 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
3347 int port
= BP_PORT(bp
);
3349 if (!(IS_MF_UFP(bp
) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)))
3350 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
* 8, 1);
3352 /* Tx queue should be only re-enabled */
3353 netif_tx_wake_all_queues(bp
->dev
);
3356 * Should not call netif_carrier_on since it will be called if the link
3357 * is up when checking for link state
3361 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3363 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
3365 struct eth_stats_info
*ether_stat
=
3366 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
3367 struct bnx2x_vlan_mac_obj
*mac_obj
=
3368 &bp
->sp_objs
->mac_obj
;
3371 strlcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
3372 ETH_STAT_INFO_VERSION_LEN
);
3374 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3375 * mac_local field in ether_stat struct. The base address is offset by 2
3376 * bytes to account for the field being 8 bytes but a mac address is
3377 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3378 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3379 * allocated by the ether_stat struct, so the macs will land in their
3382 for (i
= 0; i
< DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
; i
++)
3383 memset(ether_stat
->mac_local
+ i
, 0,
3384 sizeof(ether_stat
->mac_local
[0]));
3385 mac_obj
->get_n_elements(bp
, &bp
->sp_objs
[0].mac_obj
,
3386 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
3387 ether_stat
->mac_local
+ MAC_PAD
, MAC_PAD
,
3389 ether_stat
->mtu_size
= bp
->dev
->mtu
;
3390 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
3391 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
3392 if (bp
->dev
->features
& NETIF_F_TSO
)
3393 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
3394 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
3396 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
3398 ether_stat
->txq_size
= bp
->tx_ring_size
;
3399 ether_stat
->rxq_size
= bp
->rx_ring_size
;
3401 #ifdef CONFIG_BNX2X_SRIOV
3402 ether_stat
->vf_cnt
= IS_SRIOV(bp
) ? bp
->vfdb
->sriov
.nr_virtfn
: 0;
3406 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
3408 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3409 struct fcoe_stats_info
*fcoe_stat
=
3410 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
3412 if (!CNIC_LOADED(bp
))
3415 memcpy(fcoe_stat
->mac_local
+ MAC_PAD
, bp
->fip_mac
, ETH_ALEN
);
3417 fcoe_stat
->qos_priority
=
3418 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
3420 /* insert FCoE stats from ramrod response */
3422 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
3423 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3424 tstorm_queue_statistics
;
3426 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
3427 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3428 xstorm_queue_statistics
;
3430 struct fcoe_statistics_params
*fw_fcoe_stat
=
3431 &bp
->fw_stats_data
->fcoe
;
3433 ADD_64_LE(fcoe_stat
->rx_bytes_hi
, LE32_0
,
3434 fcoe_stat
->rx_bytes_lo
,
3435 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
3437 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3438 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
3439 fcoe_stat
->rx_bytes_lo
,
3440 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
3442 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3443 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
3444 fcoe_stat
->rx_bytes_lo
,
3445 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
3447 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3448 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
3449 fcoe_stat
->rx_bytes_lo
,
3450 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
3452 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3453 fcoe_stat
->rx_frames_lo
,
3454 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
3456 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3457 fcoe_stat
->rx_frames_lo
,
3458 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
3460 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3461 fcoe_stat
->rx_frames_lo
,
3462 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
3464 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3465 fcoe_stat
->rx_frames_lo
,
3466 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
3468 ADD_64_LE(fcoe_stat
->tx_bytes_hi
, LE32_0
,
3469 fcoe_stat
->tx_bytes_lo
,
3470 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
3472 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3473 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
3474 fcoe_stat
->tx_bytes_lo
,
3475 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
3477 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3478 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3479 fcoe_stat
->tx_bytes_lo
,
3480 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3482 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3483 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3484 fcoe_stat
->tx_bytes_lo
,
3485 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3487 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3488 fcoe_stat
->tx_frames_lo
,
3489 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3491 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3492 fcoe_stat
->tx_frames_lo
,
3493 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3495 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3496 fcoe_stat
->tx_frames_lo
,
3497 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3499 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3500 fcoe_stat
->tx_frames_lo
,
3501 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3504 /* ask L5 driver to add data to the struct */
3505 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3508 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3510 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3511 struct iscsi_stats_info
*iscsi_stat
=
3512 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3514 if (!CNIC_LOADED(bp
))
3517 memcpy(iscsi_stat
->mac_local
+ MAC_PAD
, bp
->cnic_eth_dev
.iscsi_mac
,
3520 iscsi_stat
->qos_priority
=
3521 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3523 /* ask L5 driver to add data to the struct */
3524 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3527 /* called due to MCP event (on pmf):
3528 * reread new bandwidth configuration
3530 * notify others function about the change
3532 static void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3534 if (bp
->link_vars
.link_up
) {
3535 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3536 bnx2x_link_sync_notify(bp
);
3538 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3541 static void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3543 bnx2x_config_mf_bw(bp
);
3544 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3547 static void bnx2x_handle_eee_event(struct bnx2x
*bp
)
3549 DP(BNX2X_MSG_MCP
, "EEE - LLDP event\n");
3550 bnx2x_fw_command(bp
, DRV_MSG_CODE_EEE_RESULTS_ACK
, 0);
3553 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3554 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3556 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3558 enum drv_info_opcode op_code
;
3559 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3560 bool release
= false;
3563 /* if drv_info version supported by MFW doesn't match - send NACK */
3564 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3565 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3569 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3570 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3572 /* Must prevent other flows from accessing drv_info_to_mcp */
3573 mutex_lock(&bp
->drv_info_mutex
);
3575 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3576 sizeof(union drv_info_to_mcp
));
3579 case ETH_STATS_OPCODE
:
3580 bnx2x_drv_info_ether_stat(bp
);
3582 case FCOE_STATS_OPCODE
:
3583 bnx2x_drv_info_fcoe_stat(bp
);
3585 case ISCSI_STATS_OPCODE
:
3586 bnx2x_drv_info_iscsi_stat(bp
);
3589 /* if op code isn't supported - send NACK */
3590 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3594 /* if we got drv_info attn from MFW then these fields are defined in
3597 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3598 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3599 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3600 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3602 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3604 /* Since possible management wants both this and get_driver_version
3605 * need to wait until management notifies us it finished utilizing
3608 if (!SHMEM2_HAS(bp
, mfw_drv_indication
)) {
3609 DP(BNX2X_MSG_MCP
, "Management does not support indication\n");
3610 } else if (!bp
->drv_info_mng_owner
) {
3611 u32 bit
= MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp
) >> 1));
3613 for (wait
= 0; wait
< BNX2X_UPDATE_DRV_INFO_IND_COUNT
; wait
++) {
3614 u32 indication
= SHMEM2_RD(bp
, mfw_drv_indication
);
3616 /* Management is done; need to clear indication */
3617 if (indication
& bit
) {
3618 SHMEM2_WR(bp
, mfw_drv_indication
,
3624 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH
);
3628 DP(BNX2X_MSG_MCP
, "Management did not release indication\n");
3629 bp
->drv_info_mng_owner
= true;
3633 mutex_unlock(&bp
->drv_info_mutex
);
3636 static u32
bnx2x_update_mng_version_utility(u8
*version
, bool bnx2x_format
)
3642 i
= sscanf(version
, "1.%c%hhd.%hhd.%hhd",
3643 &vals
[0], &vals
[1], &vals
[2], &vals
[3]);
3647 i
= sscanf(version
, "%hhd.%hhd.%hhd.%hhd",
3648 &vals
[0], &vals
[1], &vals
[2], &vals
[3]);
3654 return (vals
[0] << 24) | (vals
[1] << 16) | (vals
[2] << 8) | vals
[3];
3657 void bnx2x_update_mng_version(struct bnx2x
*bp
)
3659 u32 iscsiver
= DRV_VER_NOT_LOADED
;
3660 u32 fcoever
= DRV_VER_NOT_LOADED
;
3661 u32 ethver
= DRV_VER_NOT_LOADED
;
3662 int idx
= BP_FW_MB_IDX(bp
);
3665 if (!SHMEM2_HAS(bp
, func_os_drv_ver
))
3668 mutex_lock(&bp
->drv_info_mutex
);
3669 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3670 if (bp
->drv_info_mng_owner
)
3673 if (bp
->state
!= BNX2X_STATE_OPEN
)
3676 /* Parse ethernet driver version */
3677 ethver
= bnx2x_update_mng_version_utility(DRV_MODULE_VERSION
, true);
3678 if (!CNIC_LOADED(bp
))
3681 /* Try getting storage driver version via cnic */
3682 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3683 sizeof(union drv_info_to_mcp
));
3684 bnx2x_drv_info_iscsi_stat(bp
);
3685 version
= bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
.version
;
3686 iscsiver
= bnx2x_update_mng_version_utility(version
, false);
3688 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3689 sizeof(union drv_info_to_mcp
));
3690 bnx2x_drv_info_fcoe_stat(bp
);
3691 version
= bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
.version
;
3692 fcoever
= bnx2x_update_mng_version_utility(version
, false);
3695 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_ETHERNET
], ethver
);
3696 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_ISCSI
], iscsiver
);
3697 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_FCOE
], fcoever
);
3699 mutex_unlock(&bp
->drv_info_mutex
);
3701 DP(BNX2X_MSG_MCP
, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3702 ethver
, iscsiver
, fcoever
);
3705 void bnx2x_update_mfw_dump(struct bnx2x
*bp
)
3710 if (!SHMEM2_HAS(bp
, drv_info
))
3713 /* Update Driver load time, possibly broken in y2038 */
3714 SHMEM2_WR(bp
, drv_info
.epoc
, (u32
)ktime_get_real_seconds());
3716 drv_ver
= bnx2x_update_mng_version_utility(DRV_MODULE_VERSION
, true);
3717 SHMEM2_WR(bp
, drv_info
.drv_ver
, drv_ver
);
3719 SHMEM2_WR(bp
, drv_info
.fw_ver
, REG_RD(bp
, XSEM_REG_PRAM
));
3721 /* Check & notify On-Chip dump. */
3722 valid_dump
= SHMEM2_RD(bp
, drv_info
.valid_dump
);
3724 if (valid_dump
& FIRST_DUMP_VALID
)
3725 DP(NETIF_MSG_IFUP
, "A valid On-Chip MFW dump found on 1st partition\n");
3727 if (valid_dump
& SECOND_DUMP_VALID
)
3728 DP(NETIF_MSG_IFUP
, "A valid On-Chip MFW dump found on 2nd partition\n");
3731 static void bnx2x_oem_event(struct bnx2x
*bp
, u32 event
)
3733 u32 cmd_ok
, cmd_fail
;
3736 if (event
& DRV_STATUS_DCC_EVENT_MASK
&&
3737 event
& DRV_STATUS_OEM_EVENT_MASK
) {
3738 BNX2X_ERR("Received simultaneous events %08x\n", event
);
3742 if (event
& DRV_STATUS_DCC_EVENT_MASK
) {
3743 cmd_fail
= DRV_MSG_CODE_DCC_FAILURE
;
3744 cmd_ok
= DRV_MSG_CODE_DCC_OK
;
3745 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3746 cmd_fail
= DRV_MSG_CODE_OEM_FAILURE
;
3747 cmd_ok
= DRV_MSG_CODE_OEM_OK
;
3750 DP(BNX2X_MSG_MCP
, "oem_event 0x%x\n", event
);
3752 if (event
& (DRV_STATUS_DCC_DISABLE_ENABLE_PF
|
3753 DRV_STATUS_OEM_DISABLE_ENABLE_PF
)) {
3754 /* This is the only place besides the function initialization
3755 * where the bp->flags can change so it is done without any
3758 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3759 DP(BNX2X_MSG_MCP
, "mf_cfg function disabled\n");
3760 bp
->flags
|= MF_FUNC_DIS
;
3762 bnx2x_e1h_disable(bp
);
3764 DP(BNX2X_MSG_MCP
, "mf_cfg function enabled\n");
3765 bp
->flags
&= ~MF_FUNC_DIS
;
3767 bnx2x_e1h_enable(bp
);
3769 event
&= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF
|
3770 DRV_STATUS_OEM_DISABLE_ENABLE_PF
);
3773 if (event
& (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
|
3774 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
)) {
3775 bnx2x_config_mf_bw(bp
);
3776 event
&= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
|
3777 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
);
3780 /* Report results to MCP */
3782 bnx2x_fw_command(bp
, cmd_fail
, 0);
3784 bnx2x_fw_command(bp
, cmd_ok
, 0);
3787 /* must be called under the spq lock */
3788 static struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3790 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3792 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3793 bp
->spq_prod_bd
= bp
->spq
;
3794 bp
->spq_prod_idx
= 0;
3795 DP(BNX2X_MSG_SP
, "end of spq\n");
3803 /* must be called under the spq lock */
3804 static void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3806 int func
= BP_FUNC(bp
);
3809 * Make sure that BD data is updated before writing the producer:
3810 * BD data is written to the memory, the producer is read from the
3811 * memory, thus we need a full memory barrier to ensure the ordering.
3815 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3821 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3823 * @cmd: command to check
3824 * @cmd_type: command type
3826 static bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3828 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3829 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3830 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3831 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3832 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3833 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3834 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3841 * bnx2x_sp_post - place a single command on an SP ring
3843 * @bp: driver handle
3844 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3845 * @cid: SW CID the command is related to
3846 * @data_hi: command private data address (high 32 bits)
3847 * @data_lo: command private data address (low 32 bits)
3848 * @cmd_type: command type (e.g. NONE, ETH)
3850 * SP data is handled as if it's always an address pair, thus data fields are
3851 * not swapped to little endian in upper functions. Instead this function swaps
3852 * data as if it's two u32 fields.
3854 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3855 u32 data_hi
, u32 data_lo
, int cmd_type
)
3857 struct eth_spe
*spe
;
3859 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3861 #ifdef BNX2X_STOP_ON_ERROR
3862 if (unlikely(bp
->panic
)) {
3863 BNX2X_ERR("Can't post SP when there is panic\n");
3868 spin_lock_bh(&bp
->spq_lock
);
3871 if (!atomic_read(&bp
->eq_spq_left
)) {
3872 BNX2X_ERR("BUG! EQ ring full!\n");
3873 spin_unlock_bh(&bp
->spq_lock
);
3877 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3878 BNX2X_ERR("BUG! SPQ ring full!\n");
3879 spin_unlock_bh(&bp
->spq_lock
);
3884 spe
= bnx2x_sp_get_next(bp
);
3886 /* CID needs port number to be encoded int it */
3887 spe
->hdr
.conn_and_cmd_data
=
3888 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3891 /* In some cases, type may already contain the func-id
3892 * mainly in SRIOV related use cases, so we add it here only
3893 * if it's not already set.
3895 if (!(cmd_type
& SPE_HDR_FUNCTION_ID
)) {
3896 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) &
3898 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3899 SPE_HDR_FUNCTION_ID
);
3904 spe
->hdr
.type
= cpu_to_le16(type
);
3906 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3907 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3910 * It's ok if the actual decrement is issued towards the memory
3911 * somewhere between the spin_lock and spin_unlock. Thus no
3912 * more explicit memory barrier is needed.
3915 atomic_dec(&bp
->eq_spq_left
);
3917 atomic_dec(&bp
->cq_spq_left
);
3920 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3921 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3922 (u32
)(U64_LO(bp
->spq_mapping
) +
3923 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3924 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3925 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3927 bnx2x_sp_prod_update(bp
);
3928 spin_unlock_bh(&bp
->spq_lock
);
3932 /* acquire split MCP access lock register */
3933 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3939 for (j
= 0; j
< 1000; j
++) {
3940 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, MCPR_ACCESS_LOCK_LOCK
);
3941 val
= REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
);
3942 if (val
& MCPR_ACCESS_LOCK_LOCK
)
3945 usleep_range(5000, 10000);
3947 if (!(val
& MCPR_ACCESS_LOCK_LOCK
)) {
3948 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3955 /* release split MCP access lock register */
3956 static void bnx2x_release_alr(struct bnx2x
*bp
)
3958 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, 0);
3961 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3962 #define BNX2X_DEF_SB_IDX 0x0002
3964 static u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3966 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3969 barrier(); /* status block is written to by the chip */
3970 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3971 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3972 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3975 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3976 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3977 rc
|= BNX2X_DEF_SB_IDX
;
3980 /* Do not reorder: indices reading should complete before handling */
3986 * slow path service functions
3989 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3991 int port
= BP_PORT(bp
);
3992 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3993 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3994 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3995 NIG_REG_MASK_INTERRUPT_PORT0
;
4000 if (bp
->attn_state
& asserted
)
4001 BNX2X_ERR("IGU ERROR\n");
4003 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4004 aeu_mask
= REG_RD(bp
, aeu_addr
);
4006 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
4007 aeu_mask
, asserted
);
4008 aeu_mask
&= ~(asserted
& 0x3ff);
4009 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4011 REG_WR(bp
, aeu_addr
, aeu_mask
);
4012 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4014 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4015 bp
->attn_state
|= asserted
;
4016 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4018 if (asserted
& ATTN_HARD_WIRED_MASK
) {
4019 if (asserted
& ATTN_NIG_FOR_FUNC
) {
4021 bnx2x_acquire_phy_lock(bp
);
4023 /* save nig interrupt mask */
4024 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
4026 /* If nig_mask is not set, no need to call the update
4030 REG_WR(bp
, nig_int_mask_addr
, 0);
4032 bnx2x_link_attn(bp
);
4035 /* handle unicore attn? */
4037 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
4038 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
4040 if (asserted
& GPIO_2_FUNC
)
4041 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
4043 if (asserted
& GPIO_3_FUNC
)
4044 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
4046 if (asserted
& GPIO_4_FUNC
)
4047 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
4050 if (asserted
& ATTN_GENERAL_ATTN_1
) {
4051 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
4052 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
4054 if (asserted
& ATTN_GENERAL_ATTN_2
) {
4055 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
4056 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
4058 if (asserted
& ATTN_GENERAL_ATTN_3
) {
4059 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
4060 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
4063 if (asserted
& ATTN_GENERAL_ATTN_4
) {
4064 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
4065 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
4067 if (asserted
& ATTN_GENERAL_ATTN_5
) {
4068 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
4069 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
4071 if (asserted
& ATTN_GENERAL_ATTN_6
) {
4072 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
4073 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
4077 } /* if hardwired */
4079 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4080 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4081 COMMAND_REG_ATTN_BITS_SET
);
4083 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
4085 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
4086 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4087 REG_WR(bp
, reg_addr
, asserted
);
4089 /* now set back the mask */
4090 if (asserted
& ATTN_NIG_FOR_FUNC
) {
4091 /* Verify that IGU ack through BAR was written before restoring
4092 * NIG mask. This loop should exit after 2-3 iterations max.
4094 if (bp
->common
.int_block
!= INT_BLOCK_HC
) {
4095 u32 cnt
= 0, igu_acked
;
4097 igu_acked
= REG_RD(bp
,
4098 IGU_REG_ATTENTION_ACK_BITS
);
4099 } while (((igu_acked
& ATTN_NIG_FOR_FUNC
) == 0) &&
4100 (++cnt
< MAX_IGU_ATTN_ACK_TO
));
4103 "Failed to verify IGU ack on time\n");
4106 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
4107 bnx2x_release_phy_lock(bp
);
4111 static void bnx2x_fan_failure(struct bnx2x
*bp
)
4113 int port
= BP_PORT(bp
);
4115 /* mark the failure */
4118 dev_info
.port_hw_config
[port
].external_phy_config
);
4120 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
4121 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
4122 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
4125 /* log the failure */
4126 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4127 "Please contact OEM Support for assistance\n");
4129 /* Schedule device reset (unload)
4130 * This is due to some boards consuming sufficient power when driver is
4131 * up to overheat if fan fails.
4133 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_FAN_FAILURE
, 0);
4136 static void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
4138 int port
= BP_PORT(bp
);
4142 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
4143 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
4145 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
4147 val
= REG_RD(bp
, reg_offset
);
4148 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
4149 REG_WR(bp
, reg_offset
, val
);
4151 BNX2X_ERR("SPIO5 hw attention\n");
4153 /* Fan failure attention */
4154 bnx2x_hw_reset_phy(&bp
->link_params
);
4155 bnx2x_fan_failure(bp
);
4158 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
4159 bnx2x_acquire_phy_lock(bp
);
4160 bnx2x_handle_module_detect_int(&bp
->link_params
);
4161 bnx2x_release_phy_lock(bp
);
4164 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
4166 val
= REG_RD(bp
, reg_offset
);
4167 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
4168 REG_WR(bp
, reg_offset
, val
);
4170 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4171 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
4176 static void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
4180 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
4182 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
4183 BNX2X_ERR("DB hw attention 0x%x\n", val
);
4184 /* DORQ discard attention */
4186 BNX2X_ERR("FATAL error from DORQ\n");
4189 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
4191 int port
= BP_PORT(bp
);
4194 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
4195 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
4197 val
= REG_RD(bp
, reg_offset
);
4198 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
4199 REG_WR(bp
, reg_offset
, val
);
4201 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4202 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
4207 static void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
4211 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
4213 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
4214 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
4215 /* CFC error attention */
4217 BNX2X_ERR("FATAL error from CFC\n");
4220 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
4221 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
4222 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
4223 /* RQ_USDMDP_FIFO_OVERFLOW */
4225 BNX2X_ERR("FATAL error from PXP\n");
4227 if (!CHIP_IS_E1x(bp
)) {
4228 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
4229 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
4233 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
4235 int port
= BP_PORT(bp
);
4238 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
4239 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
4241 val
= REG_RD(bp
, reg_offset
);
4242 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
4243 REG_WR(bp
, reg_offset
, val
);
4245 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4246 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
4251 static void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
4255 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
4257 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
4258 int func
= BP_FUNC(bp
);
4260 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
4261 bnx2x_read_mf_cfg(bp
);
4262 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
4263 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
4265 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
4267 if (val
& (DRV_STATUS_DCC_EVENT_MASK
|
4268 DRV_STATUS_OEM_EVENT_MASK
))
4270 (val
& (DRV_STATUS_DCC_EVENT_MASK
|
4271 DRV_STATUS_OEM_EVENT_MASK
)));
4273 if (val
& DRV_STATUS_SET_MF_BW
)
4274 bnx2x_set_mf_bw(bp
);
4276 if (val
& DRV_STATUS_DRV_INFO_REQ
)
4277 bnx2x_handle_drv_info_req(bp
);
4279 if (val
& DRV_STATUS_VF_DISABLED
)
4280 bnx2x_schedule_iov_task(bp
,
4281 BNX2X_IOV_HANDLE_FLR
);
4283 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
4284 bnx2x_pmf_update(bp
);
4287 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
4288 bp
->dcbx_enabled
> 0)
4289 /* start dcbx state machine */
4290 bnx2x_dcbx_set_params(bp
,
4291 BNX2X_DCBX_STATE_NEG_RECEIVED
);
4292 if (val
& DRV_STATUS_AFEX_EVENT_MASK
)
4293 bnx2x_handle_afex_cmd(bp
,
4294 val
& DRV_STATUS_AFEX_EVENT_MASK
);
4295 if (val
& DRV_STATUS_EEE_NEGOTIATION_RESULTS
)
4296 bnx2x_handle_eee_event(bp
);
4298 if (val
& DRV_STATUS_OEM_UPDATE_SVID
)
4299 bnx2x_handle_update_svid_cmd(bp
);
4301 if (bp
->link_vars
.periodic_flags
&
4302 PERIODIC_FLAGS_LINK_EVENT
) {
4303 /* sync with link */
4304 bnx2x_acquire_phy_lock(bp
);
4305 bp
->link_vars
.periodic_flags
&=
4306 ~PERIODIC_FLAGS_LINK_EVENT
;
4307 bnx2x_release_phy_lock(bp
);
4309 bnx2x_link_sync_notify(bp
);
4310 bnx2x_link_report(bp
);
4312 /* Always call it here: bnx2x_link_report() will
4313 * prevent the link indication duplication.
4315 bnx2x__link_status_update(bp
);
4316 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
4318 BNX2X_ERR("MC assert!\n");
4319 bnx2x_mc_assert(bp
);
4320 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
4321 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
4322 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
4323 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
4326 } else if (attn
& BNX2X_MCP_ASSERT
) {
4328 BNX2X_ERR("MCP assert!\n");
4329 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
4333 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
4336 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
4337 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
4338 if (attn
& BNX2X_GRC_TIMEOUT
) {
4339 val
= CHIP_IS_E1(bp
) ? 0 :
4340 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
4341 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
4343 if (attn
& BNX2X_GRC_RSV
) {
4344 val
= CHIP_IS_E1(bp
) ? 0 :
4345 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
4346 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
4348 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
4354 * 0-7 - Engine0 load counter.
4355 * 8-15 - Engine1 load counter.
4356 * 16 - Engine0 RESET_IN_PROGRESS bit.
4357 * 17 - Engine1 RESET_IN_PROGRESS bit.
4358 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4360 * 19 - Engine1 ONE_IS_LOADED.
4361 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4362 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4363 * just the one belonging to its engine).
4366 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4368 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4369 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4370 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4371 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4372 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4373 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4374 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4377 * Set the GLOBAL_RESET bit.
4379 * Should be run under rtnl lock
4381 void bnx2x_set_reset_global(struct bnx2x
*bp
)
4384 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4385 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4386 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
4387 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4391 * Clear the GLOBAL_RESET bit.
4393 * Should be run under rtnl lock
4395 static void bnx2x_clear_reset_global(struct bnx2x
*bp
)
4398 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4399 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4400 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
4401 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4405 * Checks the GLOBAL_RESET bit.
4407 * should be run under rtnl lock
4409 static bool bnx2x_reset_is_global(struct bnx2x
*bp
)
4411 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4413 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
4414 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
4418 * Clear RESET_IN_PROGRESS bit for the current engine.
4420 * Should be run under rtnl lock
4422 static void bnx2x_set_reset_done(struct bnx2x
*bp
)
4425 u32 bit
= BP_PATH(bp
) ?
4426 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4427 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4428 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4432 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4434 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4438 * Set RESET_IN_PROGRESS for the current engine.
4440 * should be run under rtnl lock
4442 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
4445 u32 bit
= BP_PATH(bp
) ?
4446 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4447 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4448 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4452 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4453 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4457 * Checks the RESET_IN_PROGRESS bit for the given engine.
4458 * should be run under rtnl lock
4460 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
4462 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4464 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4466 /* return false if bit is set */
4467 return (val
& bit
) ? false : true;
4471 * set pf load for the current pf.
4473 * should be run under rtnl lock
4475 void bnx2x_set_pf_load(struct bnx2x
*bp
)
4478 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4479 BNX2X_PATH0_LOAD_CNT_MASK
;
4480 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4481 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4483 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4484 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4486 DP(NETIF_MSG_IFUP
, "Old GEN_REG_VAL=0x%08x\n", val
);
4488 /* get the current counter value */
4489 val1
= (val
& mask
) >> shift
;
4491 /* set bit of that PF */
4492 val1
|= (1 << bp
->pf_num
);
4494 /* clear the old value */
4497 /* set the new one */
4498 val
|= ((val1
<< shift
) & mask
);
4500 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4501 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4505 * bnx2x_clear_pf_load - clear pf load mark
4507 * @bp: driver handle
4509 * Should be run under rtnl lock.
4510 * Decrements the load counter for the current engine. Returns
4511 * whether other functions are still loaded
4513 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
4516 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4517 BNX2X_PATH0_LOAD_CNT_MASK
;
4518 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4519 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4521 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4522 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4523 DP(NETIF_MSG_IFDOWN
, "Old GEN_REG_VAL=0x%08x\n", val
);
4525 /* get the current counter value */
4526 val1
= (val
& mask
) >> shift
;
4528 /* clear bit of that PF */
4529 val1
&= ~(1 << bp
->pf_num
);
4531 /* clear the old value */
4534 /* set the new one */
4535 val
|= ((val1
<< shift
) & mask
);
4537 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4538 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4543 * Read the load status for the current engine.
4545 * should be run under rtnl lock
4547 static bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
4549 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
4550 BNX2X_PATH0_LOAD_CNT_MASK
);
4551 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4552 BNX2X_PATH0_LOAD_CNT_SHIFT
);
4553 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4555 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "GLOB_REG=0x%08x\n", val
);
4557 val
= (val
& mask
) >> shift
;
4559 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "load mask for engine %d = 0x%x\n",
4565 static void _print_parity(struct bnx2x
*bp
, u32 reg
)
4567 pr_cont(" [0x%08x] ", REG_RD(bp
, reg
));
4570 static void _print_next_block(int idx
, const char *blk
)
4572 pr_cont("%s%s", idx
? ", " : "", blk
);
4575 static bool bnx2x_check_blocks_with_parity0(struct bnx2x
*bp
, u32 sig
,
4576 int *par_num
, bool print
)
4584 for (i
= 0; sig
; i
++) {
4585 cur_bit
= (0x1UL
<< i
);
4586 if (sig
& cur_bit
) {
4587 res
|= true; /* Each bit is real error! */
4591 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
4592 _print_next_block((*par_num
)++, "BRB");
4594 BRB1_REG_BRB1_PRTY_STS
);
4596 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
4597 _print_next_block((*par_num
)++,
4599 _print_parity(bp
, PRS_REG_PRS_PRTY_STS
);
4601 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
4602 _print_next_block((*par_num
)++, "TSDM");
4604 TSDM_REG_TSDM_PRTY_STS
);
4606 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
4607 _print_next_block((*par_num
)++,
4609 _print_parity(bp
, SRC_REG_SRC_PRTY_STS
);
4611 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
4612 _print_next_block((*par_num
)++, "TCM");
4613 _print_parity(bp
, TCM_REG_TCM_PRTY_STS
);
4615 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
4616 _print_next_block((*par_num
)++,
4619 TSEM_REG_TSEM_PRTY_STS_0
);
4621 TSEM_REG_TSEM_PRTY_STS_1
);
4623 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
4624 _print_next_block((*par_num
)++, "XPB");
4625 _print_parity(bp
, GRCBASE_XPB
+
4626 PB_REG_PB_PRTY_STS
);
4639 static bool bnx2x_check_blocks_with_parity1(struct bnx2x
*bp
, u32 sig
,
4640 int *par_num
, bool *global
,
4649 for (i
= 0; sig
; i
++) {
4650 cur_bit
= (0x1UL
<< i
);
4651 if (sig
& cur_bit
) {
4652 res
|= true; /* Each bit is real error! */
4654 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
4656 _print_next_block((*par_num
)++, "PBF");
4657 _print_parity(bp
, PBF_REG_PBF_PRTY_STS
);
4660 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
4662 _print_next_block((*par_num
)++, "QM");
4663 _print_parity(bp
, QM_REG_QM_PRTY_STS
);
4666 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
4668 _print_next_block((*par_num
)++, "TM");
4669 _print_parity(bp
, TM_REG_TM_PRTY_STS
);
4672 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
4674 _print_next_block((*par_num
)++, "XSDM");
4676 XSDM_REG_XSDM_PRTY_STS
);
4679 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
4681 _print_next_block((*par_num
)++, "XCM");
4682 _print_parity(bp
, XCM_REG_XCM_PRTY_STS
);
4685 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
4687 _print_next_block((*par_num
)++,
4690 XSEM_REG_XSEM_PRTY_STS_0
);
4692 XSEM_REG_XSEM_PRTY_STS_1
);
4695 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
4697 _print_next_block((*par_num
)++,
4700 DORQ_REG_DORQ_PRTY_STS
);
4703 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
4705 _print_next_block((*par_num
)++, "NIG");
4706 if (CHIP_IS_E1x(bp
)) {
4708 NIG_REG_NIG_PRTY_STS
);
4711 NIG_REG_NIG_PRTY_STS_0
);
4713 NIG_REG_NIG_PRTY_STS_1
);
4717 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4719 _print_next_block((*par_num
)++,
4723 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4725 _print_next_block((*par_num
)++,
4727 _print_parity(bp
, DBG_REG_DBG_PRTY_STS
);
4730 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4732 _print_next_block((*par_num
)++, "USDM");
4734 USDM_REG_USDM_PRTY_STS
);
4737 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4739 _print_next_block((*par_num
)++, "UCM");
4740 _print_parity(bp
, UCM_REG_UCM_PRTY_STS
);
4743 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4745 _print_next_block((*par_num
)++,
4748 USEM_REG_USEM_PRTY_STS_0
);
4750 USEM_REG_USEM_PRTY_STS_1
);
4753 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4755 _print_next_block((*par_num
)++, "UPB");
4756 _print_parity(bp
, GRCBASE_UPB
+
4757 PB_REG_PB_PRTY_STS
);
4760 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4762 _print_next_block((*par_num
)++, "CSDM");
4764 CSDM_REG_CSDM_PRTY_STS
);
4767 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4769 _print_next_block((*par_num
)++, "CCM");
4770 _print_parity(bp
, CCM_REG_CCM_PRTY_STS
);
4783 static bool bnx2x_check_blocks_with_parity2(struct bnx2x
*bp
, u32 sig
,
4784 int *par_num
, bool print
)
4792 for (i
= 0; sig
; i
++) {
4793 cur_bit
= (0x1UL
<< i
);
4794 if (sig
& cur_bit
) {
4795 res
= true; /* Each bit is real error! */
4798 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4799 _print_next_block((*par_num
)++,
4802 CSEM_REG_CSEM_PRTY_STS_0
);
4804 CSEM_REG_CSEM_PRTY_STS_1
);
4806 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4807 _print_next_block((*par_num
)++, "PXP");
4808 _print_parity(bp
, PXP_REG_PXP_PRTY_STS
);
4810 PXP2_REG_PXP2_PRTY_STS_0
);
4812 PXP2_REG_PXP2_PRTY_STS_1
);
4814 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4815 _print_next_block((*par_num
)++,
4816 "PXPPCICLOCKCLIENT");
4818 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4819 _print_next_block((*par_num
)++, "CFC");
4821 CFC_REG_CFC_PRTY_STS
);
4823 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4824 _print_next_block((*par_num
)++, "CDU");
4825 _print_parity(bp
, CDU_REG_CDU_PRTY_STS
);
4827 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4828 _print_next_block((*par_num
)++, "DMAE");
4830 DMAE_REG_DMAE_PRTY_STS
);
4832 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4833 _print_next_block((*par_num
)++, "IGU");
4834 if (CHIP_IS_E1x(bp
))
4836 HC_REG_HC_PRTY_STS
);
4839 IGU_REG_IGU_PRTY_STS
);
4841 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4842 _print_next_block((*par_num
)++, "MISC");
4844 MISC_REG_MISC_PRTY_STS
);
4857 static bool bnx2x_check_blocks_with_parity3(struct bnx2x
*bp
, u32 sig
,
4858 int *par_num
, bool *global
,
4865 for (i
= 0; sig
; i
++) {
4866 cur_bit
= (0x1UL
<< i
);
4867 if (sig
& cur_bit
) {
4869 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4871 _print_next_block((*par_num
)++,
4876 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4878 _print_next_block((*par_num
)++,
4883 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4885 _print_next_block((*par_num
)++,
4890 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4892 /* clear latched SCPAD PATIRY from MCP */
4893 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
,
4906 static bool bnx2x_check_blocks_with_parity4(struct bnx2x
*bp
, u32 sig
,
4907 int *par_num
, bool print
)
4915 for (i
= 0; sig
; i
++) {
4916 cur_bit
= (0x1UL
<< i
);
4917 if (sig
& cur_bit
) {
4918 res
= true; /* Each bit is real error! */
4921 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4922 _print_next_block((*par_num
)++,
4925 PGLUE_B_REG_PGLUE_B_PRTY_STS
);
4927 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4928 _print_next_block((*par_num
)++, "ATC");
4930 ATC_REG_ATC_PRTY_STS
);
4942 static bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4947 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4948 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4949 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4950 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4951 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4954 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention:\n"
4955 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4956 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4957 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4958 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4959 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4960 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4962 if (((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4963 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4964 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4965 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) ||
4966 (sig
[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD
)) {
4968 "Parity errors detected in blocks: ");
4973 res
|= bnx2x_check_blocks_with_parity0(bp
,
4974 sig
[0] & HW_PRTY_ASSERT_SET_0
, &par_num
, print
);
4975 res
|= bnx2x_check_blocks_with_parity1(bp
,
4976 sig
[1] & HW_PRTY_ASSERT_SET_1
, &par_num
, global
, print
);
4977 res
|= bnx2x_check_blocks_with_parity2(bp
,
4978 sig
[2] & HW_PRTY_ASSERT_SET_2
, &par_num
, print
);
4979 res
|= bnx2x_check_blocks_with_parity3(bp
,
4980 sig
[3] & HW_PRTY_ASSERT_SET_3
, &par_num
, global
, print
);
4981 res
|= bnx2x_check_blocks_with_parity4(bp
,
4982 sig
[4] & HW_PRTY_ASSERT_SET_4
, &par_num
, print
);
4992 * bnx2x_chk_parity_attn - checks for parity attentions.
4994 * @bp: driver handle
4995 * @global: true if there was a global attention
4996 * @print: show parity attention in syslog
4998 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
5000 struct attn_route attn
= { {0} };
5001 int port
= BP_PORT(bp
);
5003 attn
.sig
[0] = REG_RD(bp
,
5004 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
5006 attn
.sig
[1] = REG_RD(bp
,
5007 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
5009 attn
.sig
[2] = REG_RD(bp
,
5010 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
5012 attn
.sig
[3] = REG_RD(bp
,
5013 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
5015 /* Since MCP attentions can't be disabled inside the block, we need to
5016 * read AEU registers to see whether they're currently disabled
5018 attn
.sig
[3] &= ((REG_RD(bp
,
5019 !port
? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5020 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0
) &
5021 MISC_AEU_ENABLE_MCP_PRTY_BITS
) |
5022 ~MISC_AEU_ENABLE_MCP_PRTY_BITS
);
5024 if (!CHIP_IS_E1x(bp
))
5025 attn
.sig
[4] = REG_RD(bp
,
5026 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
5029 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
5032 static void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
5035 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
5037 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
5038 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
5039 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
5040 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5041 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
5042 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5043 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
5044 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5045 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
5046 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5048 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
5049 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5051 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
5052 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5053 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
5054 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5055 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
5056 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5057 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
5058 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5060 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
5061 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
5062 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
5063 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
5064 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5065 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
5066 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5067 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
5068 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5069 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
5070 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5071 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
5072 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5073 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
5074 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5077 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
5078 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
5079 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5080 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
5081 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
5085 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
5087 struct attn_route attn
, *group_mask
;
5088 int port
= BP_PORT(bp
);
5093 bool global
= false;
5095 /* need to take HW lock because MCP or other port might also
5096 try to handle this event */
5097 bnx2x_acquire_alr(bp
);
5099 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
5100 #ifndef BNX2X_STOP_ON_ERROR
5101 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
5102 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
5103 /* Disable HW interrupts */
5104 bnx2x_int_disable(bp
);
5105 /* In case of parity errors don't handle attentions so that
5106 * other function would "see" parity errors.
5111 bnx2x_release_alr(bp
);
5115 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
5116 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
5117 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
5118 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
5119 if (!CHIP_IS_E1x(bp
))
5121 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
5125 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
5126 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
5128 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5129 if (deasserted
& (1 << index
)) {
5130 group_mask
= &bp
->attn_group
[index
];
5132 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x %08x\n",
5134 group_mask
->sig
[0], group_mask
->sig
[1],
5135 group_mask
->sig
[2], group_mask
->sig
[3],
5136 group_mask
->sig
[4]);
5138 bnx2x_attn_int_deasserted4(bp
,
5139 attn
.sig
[4] & group_mask
->sig
[4]);
5140 bnx2x_attn_int_deasserted3(bp
,
5141 attn
.sig
[3] & group_mask
->sig
[3]);
5142 bnx2x_attn_int_deasserted1(bp
,
5143 attn
.sig
[1] & group_mask
->sig
[1]);
5144 bnx2x_attn_int_deasserted2(bp
,
5145 attn
.sig
[2] & group_mask
->sig
[2]);
5146 bnx2x_attn_int_deasserted0(bp
,
5147 attn
.sig
[0] & group_mask
->sig
[0]);
5151 bnx2x_release_alr(bp
);
5153 if (bp
->common
.int_block
== INT_BLOCK_HC
)
5154 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
5155 COMMAND_REG_ATTN_BITS_CLR
);
5157 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
5160 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
5161 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
5162 REG_WR(bp
, reg_addr
, val
);
5164 if (~bp
->attn_state
& deasserted
)
5165 BNX2X_ERR("IGU ERROR\n");
5167 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
5168 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
5170 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
5171 aeu_mask
= REG_RD(bp
, reg_addr
);
5173 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
5174 aeu_mask
, deasserted
);
5175 aeu_mask
|= (deasserted
& 0x3ff);
5176 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
5178 REG_WR(bp
, reg_addr
, aeu_mask
);
5179 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
5181 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
5182 bp
->attn_state
&= ~deasserted
;
5183 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
5186 static void bnx2x_attn_int(struct bnx2x
*bp
)
5188 /* read local copy of bits */
5189 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
5191 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
5193 u32 attn_state
= bp
->attn_state
;
5195 /* look for changed bits */
5196 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
5197 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
5200 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5201 attn_bits
, attn_ack
, asserted
, deasserted
);
5203 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
5204 BNX2X_ERR("BAD attention state\n");
5206 /* handle bits that were raised */
5208 bnx2x_attn_int_asserted(bp
, asserted
);
5211 bnx2x_attn_int_deasserted(bp
, deasserted
);
5214 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
5215 u16 index
, u8 op
, u8 update
)
5217 u32 igu_addr
= bp
->igu_base_addr
;
5218 igu_addr
+= (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
5219 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
5223 static void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
5225 /* No memory barriers */
5226 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
5227 mmiowb(); /* keep prod updates ordered */
5230 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
5231 union event_ring_elem
*elem
)
5233 u8 err
= elem
->message
.error
;
5235 if (!bp
->cnic_eth_dev
.starting_cid
||
5236 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
5237 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
5240 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
5242 if (unlikely(err
)) {
5244 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5246 bnx2x_panic_dump(bp
, false);
5248 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
5252 static void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
5254 struct bnx2x_mcast_ramrod_params rparam
;
5257 memset(&rparam
, 0, sizeof(rparam
));
5259 rparam
.mcast_obj
= &bp
->mcast_obj
;
5261 netif_addr_lock_bh(bp
->dev
);
5263 /* Clear pending state for the last command */
5264 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
5266 /* If there are pending mcast commands - send them */
5267 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
5268 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
5270 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5274 netif_addr_unlock_bh(bp
->dev
);
5277 static void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
5278 union event_ring_elem
*elem
)
5280 unsigned long ramrod_flags
= 0;
5282 u32 echo
= le32_to_cpu(elem
->message
.data
.eth_event
.echo
);
5283 u32 cid
= echo
& BNX2X_SWCID_MASK
;
5284 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
5286 /* Always push next commands out, don't wait here */
5287 __set_bit(RAMROD_CONT
, &ramrod_flags
);
5289 switch (echo
>> BNX2X_SWCID_SHIFT
) {
5290 case BNX2X_FILTER_MAC_PENDING
:
5291 DP(BNX2X_MSG_SP
, "Got SETUP_MAC completions\n");
5292 if (CNIC_LOADED(bp
) && (cid
== BNX2X_ISCSI_ETH_CID(bp
)))
5293 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
5295 vlan_mac_obj
= &bp
->sp_objs
[cid
].mac_obj
;
5298 case BNX2X_FILTER_VLAN_PENDING
:
5299 DP(BNX2X_MSG_SP
, "Got SETUP_VLAN completions\n");
5300 vlan_mac_obj
= &bp
->sp_objs
[cid
].vlan_obj
;
5302 case BNX2X_FILTER_MCAST_PENDING
:
5303 DP(BNX2X_MSG_SP
, "Got SETUP_MCAST completions\n");
5304 /* This is only relevant for 57710 where multicast MACs are
5305 * configured as unicast MACs using the same ramrod.
5307 bnx2x_handle_mcast_eqe(bp
);
5310 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo
);
5314 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
5317 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
5319 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
5322 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
5324 static void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
5326 netif_addr_lock_bh(bp
->dev
);
5328 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5330 /* Send rx_mode command again if was requested */
5331 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
5332 bnx2x_set_storm_rx_mode(bp
);
5333 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
5335 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
5336 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
5338 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
5340 netif_addr_unlock_bh(bp
->dev
);
5343 static void bnx2x_after_afex_vif_lists(struct bnx2x
*bp
,
5344 union event_ring_elem
*elem
)
5346 if (elem
->message
.data
.vif_list_event
.echo
== VIF_LIST_RULE_GET
) {
5348 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5349 elem
->message
.data
.vif_list_event
.func_bit_map
);
5350 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTGET_ACK
,
5351 elem
->message
.data
.vif_list_event
.func_bit_map
);
5352 } else if (elem
->message
.data
.vif_list_event
.echo
==
5353 VIF_LIST_RULE_SET
) {
5354 DP(BNX2X_MSG_SP
, "afex: ramrod completed VIF LIST_SET\n");
5355 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTSET_ACK
, 0);
5359 /* called with rtnl_lock */
5360 static void bnx2x_after_function_update(struct bnx2x
*bp
)
5363 struct bnx2x_fastpath
*fp
;
5364 struct bnx2x_queue_state_params queue_params
= {NULL
};
5365 struct bnx2x_queue_update_params
*q_update_params
=
5366 &queue_params
.params
.update
;
5368 /* Send Q update command with afex vlan removal values for all Qs */
5369 queue_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
5371 /* set silent vlan removal values according to vlan mode */
5372 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
,
5373 &q_update_params
->update_flags
);
5374 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM
,
5375 &q_update_params
->update_flags
);
5376 __set_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
5378 /* in access mode mark mask and value are 0 to strip all vlans */
5379 if (bp
->afex_vlan_mode
== FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE
) {
5380 q_update_params
->silent_removal_value
= 0;
5381 q_update_params
->silent_removal_mask
= 0;
5383 q_update_params
->silent_removal_value
=
5384 (bp
->afex_def_vlan_tag
& VLAN_VID_MASK
);
5385 q_update_params
->silent_removal_mask
= VLAN_VID_MASK
;
5388 for_each_eth_queue(bp
, q
) {
5389 /* Set the appropriate Queue object */
5391 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
5393 /* send the ramrod */
5394 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
5396 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5400 if (!NO_FCOE(bp
) && CNIC_ENABLED(bp
)) {
5401 fp
= &bp
->fp
[FCOE_IDX(bp
)];
5402 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
5404 /* clear pending completion bit */
5405 __clear_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
5407 /* mark latest Q bit */
5408 smp_mb__before_atomic();
5409 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
5410 smp_mb__after_atomic();
5412 /* send Q update ramrod for FCoE Q */
5413 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
5415 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5418 /* If no FCoE ring - ACK MCP now */
5419 bnx2x_link_report(bp
);
5420 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5424 static struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
5425 struct bnx2x
*bp
, u32 cid
)
5427 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
5429 if (CNIC_LOADED(bp
) && (cid
== BNX2X_FCOE_ETH_CID(bp
)))
5430 return &bnx2x_fcoe_sp_obj(bp
, q_obj
);
5432 return &bp
->sp_objs
[CID_TO_FP(cid
, bp
)].q_obj
;
5435 static void bnx2x_eq_int(struct bnx2x
*bp
)
5437 u16 hw_cons
, sw_cons
, sw_prod
;
5438 union event_ring_elem
*elem
;
5442 int rc
, spqe_cnt
= 0;
5443 struct bnx2x_queue_sp_obj
*q_obj
;
5444 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
5445 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
5447 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
5449 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5450 * when we get the next-page we need to adjust so the loop
5451 * condition below will be met. The next element is the size of a
5452 * regular element and hence incrementing by 1
5454 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
5457 /* This function may never run in parallel with itself for a
5458 * specific bp, thus there is no need in "paired" read memory
5461 sw_cons
= bp
->eq_cons
;
5462 sw_prod
= bp
->eq_prod
;
5464 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5465 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
5467 for (; sw_cons
!= hw_cons
;
5468 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
5470 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
5472 rc
= bnx2x_iov_eq_sp_event(bp
, elem
);
5474 DP(BNX2X_MSG_IOV
, "bnx2x_iov_eq_sp_event returned %d\n",
5479 opcode
= elem
->message
.opcode
;
5481 /* handle eq element */
5483 case EVENT_RING_OPCODE_VF_PF_CHANNEL
:
5484 bnx2x_vf_mbx_schedule(bp
,
5485 &elem
->message
.data
.vf_pf_event
);
5488 case EVENT_RING_OPCODE_STAT_QUERY
:
5489 DP_AND((BNX2X_MSG_SP
| BNX2X_MSG_STATS
),
5490 "got statistics comp event %d\n",
5492 /* nothing to do with stats comp */
5495 case EVENT_RING_OPCODE_CFC_DEL
:
5496 /* handle according to cid range */
5498 * we may want to verify here that the bp state is
5502 /* elem CID originates from FW; actually LE */
5503 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
5506 "got delete ramrod for MULTI[%d]\n", cid
);
5508 if (CNIC_LOADED(bp
) &&
5509 !bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
5512 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
5514 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
5519 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
5520 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got STOP TRAFFIC\n");
5521 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
5522 if (f_obj
->complete_cmd(bp
, f_obj
,
5523 BNX2X_F_CMD_TX_STOP
))
5527 case EVENT_RING_OPCODE_START_TRAFFIC
:
5528 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got START TRAFFIC\n");
5529 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
5530 if (f_obj
->complete_cmd(bp
, f_obj
,
5531 BNX2X_F_CMD_TX_START
))
5535 case EVENT_RING_OPCODE_FUNCTION_UPDATE
:
5536 echo
= elem
->message
.data
.function_update_event
.echo
;
5537 if (echo
== SWITCH_UPDATE
) {
5538 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5539 "got FUNC_SWITCH_UPDATE ramrod\n");
5540 if (f_obj
->complete_cmd(
5541 bp
, f_obj
, BNX2X_F_CMD_SWITCH_UPDATE
))
5545 int cmd
= BNX2X_SP_RTNL_AFEX_F_UPDATE
;
5547 DP(BNX2X_MSG_SP
| BNX2X_MSG_MCP
,
5548 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5549 f_obj
->complete_cmd(bp
, f_obj
,
5550 BNX2X_F_CMD_AFEX_UPDATE
);
5552 /* We will perform the Queues update from
5553 * sp_rtnl task as all Queue SP operations
5554 * should run under rtnl_lock.
5556 bnx2x_schedule_sp_rtnl(bp
, cmd
, 0);
5561 case EVENT_RING_OPCODE_AFEX_VIF_LISTS
:
5562 f_obj
->complete_cmd(bp
, f_obj
,
5563 BNX2X_F_CMD_AFEX_VIFLISTS
);
5564 bnx2x_after_afex_vif_lists(bp
, elem
);
5566 case EVENT_RING_OPCODE_FUNCTION_START
:
5567 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5568 "got FUNC_START ramrod\n");
5569 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
5574 case EVENT_RING_OPCODE_FUNCTION_STOP
:
5575 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5576 "got FUNC_STOP ramrod\n");
5577 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
5582 case EVENT_RING_OPCODE_SET_TIMESYNC
:
5583 DP(BNX2X_MSG_SP
| BNX2X_MSG_PTP
,
5584 "got set_timesync ramrod completion\n");
5585 if (f_obj
->complete_cmd(bp
, f_obj
,
5586 BNX2X_F_CMD_SET_TIMESYNC
))
5591 switch (opcode
| bp
->state
) {
5592 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5594 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5595 BNX2X_STATE_OPENING_WAIT4_PORT
):
5596 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5597 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5598 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
5599 SW_CID(elem
->message
.data
.eth_event
.echo
));
5600 rss_raw
->clear_pending(rss_raw
);
5603 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
5604 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
5605 case (EVENT_RING_OPCODE_SET_MAC
|
5606 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5607 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5609 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5611 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5612 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5613 DP(BNX2X_MSG_SP
, "got (un)set vlan/mac ramrod\n");
5614 bnx2x_handle_classification_eqe(bp
, elem
);
5617 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5619 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5621 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5622 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5623 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
5624 bnx2x_handle_mcast_eqe(bp
);
5627 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5629 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5631 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5632 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5633 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
5634 bnx2x_handle_rx_mode_eqe(bp
);
5637 /* unknown event log error and continue */
5638 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5639 elem
->message
.opcode
, bp
->state
);
5645 smp_mb__before_atomic();
5646 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
5648 bp
->eq_cons
= sw_cons
;
5649 bp
->eq_prod
= sw_prod
;
5650 /* Make sure that above mem writes were issued towards the memory */
5653 /* update producer */
5654 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
5657 static void bnx2x_sp_task(struct work_struct
*work
)
5659 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
5661 DP(BNX2X_MSG_SP
, "sp task invoked\n");
5663 /* make sure the atomic interrupt_occurred has been written */
5665 if (atomic_read(&bp
->interrupt_occurred
)) {
5667 /* what work needs to be performed? */
5668 u16 status
= bnx2x_update_dsb_idx(bp
);
5670 DP(BNX2X_MSG_SP
, "status %x\n", status
);
5671 DP(BNX2X_MSG_SP
, "setting interrupt_occurred to 0\n");
5672 atomic_set(&bp
->interrupt_occurred
, 0);
5675 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
5677 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
5680 /* SP events: STAT_QUERY and others */
5681 if (status
& BNX2X_DEF_SB_IDX
) {
5682 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
5684 if (FCOE_INIT(bp
) &&
5685 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
5686 /* Prevent local bottom-halves from running as
5687 * we are going to change the local NAPI list.
5690 napi_schedule(&bnx2x_fcoe(bp
, napi
));
5694 /* Handle EQ completions */
5696 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
5697 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
5699 status
&= ~BNX2X_DEF_SB_IDX
;
5702 /* if status is non zero then perhaps something went wrong */
5703 if (unlikely(status
))
5705 "got an unknown interrupt! (status 0x%x)\n", status
);
5707 /* ack status block only if something was actually handled */
5708 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
5709 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
5712 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5713 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
,
5715 bnx2x_link_report(bp
);
5716 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5720 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
5722 struct net_device
*dev
= dev_instance
;
5723 struct bnx2x
*bp
= netdev_priv(dev
);
5725 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
5726 IGU_INT_DISABLE
, 0);
5728 #ifdef BNX2X_STOP_ON_ERROR
5729 if (unlikely(bp
->panic
))
5733 if (CNIC_LOADED(bp
)) {
5734 struct cnic_ops
*c_ops
;
5737 c_ops
= rcu_dereference(bp
->cnic_ops
);
5739 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
5743 /* schedule sp task to perform default status block work, ack
5744 * attentions and enable interrupts.
5746 bnx2x_schedule_sp_task(bp
);
5751 /* end of slow path */
5753 void bnx2x_drv_pulse(struct bnx2x
*bp
)
5755 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
5756 bp
->fw_drv_pulse_wr_seq
);
5759 static void bnx2x_timer(unsigned long data
)
5761 struct bnx2x
*bp
= (struct bnx2x
*) data
;
5763 if (!netif_running(bp
->dev
))
5768 int mb_idx
= BP_FW_MB_IDX(bp
);
5772 ++bp
->fw_drv_pulse_wr_seq
;
5773 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
5774 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
5775 bnx2x_drv_pulse(bp
);
5777 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
5778 MCP_PULSE_SEQ_MASK
);
5779 /* The delta between driver pulse and mcp response
5780 * should not get too big. If the MFW is more than 5 pulses
5781 * behind, we should worry about it enough to generate an error
5784 if (((drv_pulse
- mcp_pulse
) & MCP_PULSE_SEQ_MASK
) > 5)
5785 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5786 drv_pulse
, mcp_pulse
);
5789 if (bp
->state
== BNX2X_STATE_OPEN
)
5790 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
5792 /* sample pf vf bulletin board for new posts from pf */
5794 bnx2x_timer_sriov(bp
);
5796 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5799 /* end of Statistics */
5804 * nic init service functions
5807 static void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
5810 if (!(len
%4) && !(addr
%4))
5811 for (i
= 0; i
< len
; i
+= 4)
5812 REG_WR(bp
, addr
+ i
, fill
);
5814 for (i
= 0; i
< len
; i
++)
5815 REG_WR8(bp
, addr
+ i
, fill
);
5818 /* helper: writes FP SP data to FW - data_size in dwords */
5819 static void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
5825 for (index
= 0; index
< data_size
; index
++)
5826 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5827 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
5829 *(sb_data_p
+ index
));
5832 static void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
5836 struct hc_status_block_data_e2 sb_data_e2
;
5837 struct hc_status_block_data_e1x sb_data_e1x
;
5839 /* disable the function first */
5840 if (!CHIP_IS_E1x(bp
)) {
5841 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5842 sb_data_e2
.common
.state
= SB_DISABLED
;
5843 sb_data_e2
.common
.p_func
.vf_valid
= false;
5844 sb_data_p
= (u32
*)&sb_data_e2
;
5845 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5847 memset(&sb_data_e1x
, 0,
5848 sizeof(struct hc_status_block_data_e1x
));
5849 sb_data_e1x
.common
.state
= SB_DISABLED
;
5850 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5851 sb_data_p
= (u32
*)&sb_data_e1x
;
5852 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5854 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5856 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5857 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
5858 CSTORM_STATUS_BLOCK_SIZE
);
5859 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5860 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
5861 CSTORM_SYNC_BLOCK_SIZE
);
5864 /* helper: writes SP SB data to FW */
5865 static void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
5866 struct hc_sp_status_block_data
*sp_sb_data
)
5868 int func
= BP_FUNC(bp
);
5870 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
5871 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5872 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
5874 *((u32
*)sp_sb_data
+ i
));
5877 static void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
5879 int func
= BP_FUNC(bp
);
5880 struct hc_sp_status_block_data sp_sb_data
;
5881 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5883 sp_sb_data
.state
= SB_DISABLED
;
5884 sp_sb_data
.p_func
.vf_valid
= false;
5886 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5888 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5889 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
5890 CSTORM_SP_STATUS_BLOCK_SIZE
);
5891 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5892 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
5893 CSTORM_SP_SYNC_BLOCK_SIZE
);
5896 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
5897 int igu_sb_id
, int igu_seg_id
)
5899 hc_sm
->igu_sb_id
= igu_sb_id
;
5900 hc_sm
->igu_seg_id
= igu_seg_id
;
5901 hc_sm
->timer_value
= 0xFF;
5902 hc_sm
->time_to_expire
= 0xFFFFFFFF;
5905 /* allocates state machine ids. */
5906 static void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
5908 /* zero out state machine indices */
5910 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5913 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5914 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5915 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5916 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5920 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
5921 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5924 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
5925 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5926 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
5927 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5928 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
5929 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5930 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
5931 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5934 void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5935 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5939 struct hc_status_block_data_e2 sb_data_e2
;
5940 struct hc_status_block_data_e1x sb_data_e1x
;
5941 struct hc_status_block_sm
*hc_sm_p
;
5945 if (CHIP_INT_MODE_IS_BC(bp
))
5946 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5948 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5950 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5952 if (!CHIP_IS_E1x(bp
)) {
5953 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5954 sb_data_e2
.common
.state
= SB_ENABLED
;
5955 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5956 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5957 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5958 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5959 sb_data_e2
.common
.same_igu_sb_1b
= true;
5960 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5961 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5962 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5963 sb_data_p
= (u32
*)&sb_data_e2
;
5964 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5965 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5967 memset(&sb_data_e1x
, 0,
5968 sizeof(struct hc_status_block_data_e1x
));
5969 sb_data_e1x
.common
.state
= SB_ENABLED
;
5970 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5971 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5972 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5973 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5974 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5975 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5976 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5977 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5978 sb_data_p
= (u32
*)&sb_data_e1x
;
5979 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5980 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5983 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5984 igu_sb_id
, igu_seg_id
);
5985 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5986 igu_sb_id
, igu_seg_id
);
5988 DP(NETIF_MSG_IFUP
, "Init FW SB %d\n", fw_sb_id
);
5990 /* write indices to HW - PCI guarantees endianity of regpairs */
5991 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5994 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
5995 u16 tx_usec
, u16 rx_usec
)
5997 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
5999 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6000 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
6002 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6003 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
6005 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6006 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
6010 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
6012 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
6013 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
6014 int igu_sp_sb_index
;
6016 int port
= BP_PORT(bp
);
6017 int func
= BP_FUNC(bp
);
6018 int reg_offset
, reg_offset_en5
;
6021 struct hc_sp_status_block_data sp_sb_data
;
6022 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
6024 if (CHIP_INT_MODE_IS_BC(bp
)) {
6025 igu_sp_sb_index
= DEF_SB_IGU_ID
;
6026 igu_seg_id
= HC_SEG_ACCESS_DEF
;
6028 igu_sp_sb_index
= bp
->igu_dsb_id
;
6029 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
6033 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
6034 atten_status_block
);
6035 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
6039 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
6040 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
6041 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
6042 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
6043 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
6045 /* take care of sig[0]..sig[4] */
6046 for (sindex
= 0; sindex
< 4; sindex
++)
6047 bp
->attn_group
[index
].sig
[sindex
] =
6048 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
6050 if (!CHIP_IS_E1x(bp
))
6052 * enable5 is separate from the rest of the registers,
6053 * and therefore the address skip is 4
6054 * and not 16 between the different groups
6056 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
6057 reg_offset_en5
+ 0x4*index
);
6059 bp
->attn_group
[index
].sig
[4] = 0;
6062 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6063 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
6064 HC_REG_ATTN_MSG0_ADDR_L
);
6066 REG_WR(bp
, reg_offset
, U64_LO(section
));
6067 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
6068 } else if (!CHIP_IS_E1x(bp
)) {
6069 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
6070 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
6073 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
6076 bnx2x_zero_sp_sb(bp
);
6078 /* PCI guarantees endianity of regpairs */
6079 sp_sb_data
.state
= SB_ENABLED
;
6080 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
6081 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
6082 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
6083 sp_sb_data
.igu_seg_id
= igu_seg_id
;
6084 sp_sb_data
.p_func
.pf_id
= func
;
6085 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
6086 sp_sb_data
.p_func
.vf_id
= 0xff;
6088 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
6090 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
6093 void bnx2x_update_coalesce(struct bnx2x
*bp
)
6097 for_each_eth_queue(bp
, i
)
6098 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
6099 bp
->tx_ticks
, bp
->rx_ticks
);
6102 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
6104 spin_lock_init(&bp
->spq_lock
);
6105 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
6107 bp
->spq_prod_idx
= 0;
6108 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
6109 bp
->spq_prod_bd
= bp
->spq
;
6110 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
6113 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
6116 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
6117 union event_ring_elem
*elem
=
6118 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
6120 elem
->next_page
.addr
.hi
=
6121 cpu_to_le32(U64_HI(bp
->eq_mapping
+
6122 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
6123 elem
->next_page
.addr
.lo
=
6124 cpu_to_le32(U64_LO(bp
->eq_mapping
+
6125 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
6128 bp
->eq_prod
= NUM_EQ_DESC
;
6129 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
6130 /* we want a warning message before it gets wrought... */
6131 atomic_set(&bp
->eq_spq_left
,
6132 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
6135 /* called with netif_addr_lock_bh() */
6136 static int bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
6137 unsigned long rx_mode_flags
,
6138 unsigned long rx_accept_flags
,
6139 unsigned long tx_accept_flags
,
6140 unsigned long ramrod_flags
)
6142 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
6145 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
6147 /* Prepare ramrod parameters */
6148 ramrod_param
.cid
= 0;
6149 ramrod_param
.cl_id
= cl_id
;
6150 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
6151 ramrod_param
.func_id
= BP_FUNC(bp
);
6153 ramrod_param
.pstate
= &bp
->sp_state
;
6154 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
6156 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
6157 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
6159 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
6161 ramrod_param
.ramrod_flags
= ramrod_flags
;
6162 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
6164 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
6165 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
6167 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
6169 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
6176 static int bnx2x_fill_accept_flags(struct bnx2x
*bp
, u32 rx_mode
,
6177 unsigned long *rx_accept_flags
,
6178 unsigned long *tx_accept_flags
)
6180 /* Clear the flags first */
6181 *rx_accept_flags
= 0;
6182 *tx_accept_flags
= 0;
6185 case BNX2X_RX_MODE_NONE
:
6187 * 'drop all' supersedes any accept flags that may have been
6188 * passed to the function.
6191 case BNX2X_RX_MODE_NORMAL
:
6192 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6193 __set_bit(BNX2X_ACCEPT_MULTICAST
, rx_accept_flags
);
6194 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6196 /* internal switching mode */
6197 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6198 __set_bit(BNX2X_ACCEPT_MULTICAST
, tx_accept_flags
);
6199 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6201 if (bp
->accept_any_vlan
) {
6202 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6203 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6207 case BNX2X_RX_MODE_ALLMULTI
:
6208 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6209 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
6210 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6212 /* internal switching mode */
6213 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6214 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
6215 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6217 if (bp
->accept_any_vlan
) {
6218 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6219 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6223 case BNX2X_RX_MODE_PROMISC
:
6224 /* According to definition of SI mode, iface in promisc mode
6225 * should receive matched and unmatched (in resolution of port)
6228 __set_bit(BNX2X_ACCEPT_UNMATCHED
, rx_accept_flags
);
6229 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6230 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
6231 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6233 /* internal switching mode */
6234 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
6235 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6238 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, tx_accept_flags
);
6240 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6242 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6243 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6247 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode
);
6254 /* called with netif_addr_lock_bh() */
6255 static int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
6257 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
6258 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
6262 /* Configure rx_mode of FCoE Queue */
6263 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
6265 rc
= bnx2x_fill_accept_flags(bp
, bp
->rx_mode
, &rx_accept_flags
,
6270 __set_bit(RAMROD_RX
, &ramrod_flags
);
6271 __set_bit(RAMROD_TX
, &ramrod_flags
);
6273 return bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
,
6274 rx_accept_flags
, tx_accept_flags
,
6278 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
6282 /* Zero this manually as its initialization is
6283 currently missing in the initTool */
6284 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
6285 REG_WR(bp
, BAR_USTRORM_INTMEM
+
6286 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
6287 if (!CHIP_IS_E1x(bp
)) {
6288 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
6289 CHIP_INT_MODE_IS_BC(bp
) ?
6290 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
6294 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
6296 switch (load_code
) {
6297 case FW_MSG_CODE_DRV_LOAD_COMMON
:
6298 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
6299 bnx2x_init_internal_common(bp
);
6302 case FW_MSG_CODE_DRV_LOAD_PORT
:
6306 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
6307 /* internal memory per function is
6308 initialized inside bnx2x_pf_init */
6312 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
6317 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
6319 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
6322 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
6324 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
6327 static u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
6329 if (CHIP_IS_E1x(fp
->bp
))
6330 return BP_L_ID(fp
->bp
) + fp
->index
;
6331 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6332 return bnx2x_fp_igu_sb_id(fp
);
6335 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
6337 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
6339 unsigned long q_type
= 0;
6340 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
6341 fp
->rx_queue
= fp_idx
;
6343 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
6344 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
6345 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
6346 /* qZone id equals to FW (per path) client id */
6347 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
6350 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
6352 /* Setup SB indices */
6353 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
6355 /* Configure Queue State object */
6356 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
6357 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
6359 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
6362 for_each_cos_in_tx_queue(fp
, cos
) {
6363 bnx2x_init_txdata(bp
, fp
->txdata_ptr
[cos
],
6364 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
, bp
),
6365 FP_COS_TO_TXQ(fp
, cos
, bp
),
6366 BNX2X_TX_SB_INDEX_BASE
+ cos
, fp
);
6367 cids
[cos
] = fp
->txdata_ptr
[cos
]->cid
;
6370 /* nothing more for vf to do here */
6374 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
6375 fp
->fw_sb_id
, fp
->igu_sb_id
);
6376 bnx2x_update_fpsb_idx(fp
);
6377 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
, cids
,
6378 fp
->max_cos
, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
6379 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
6382 * Configure classification DBs: Always enable Tx switching
6384 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
6387 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6388 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
6392 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata
*txdata
)
6396 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
6397 struct eth_tx_next_bd
*tx_next_bd
=
6398 &txdata
->tx_desc_ring
[TX_DESC_CNT
* i
- 1].next_bd
;
6400 tx_next_bd
->addr_hi
=
6401 cpu_to_le32(U64_HI(txdata
->tx_desc_mapping
+
6402 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
6403 tx_next_bd
->addr_lo
=
6404 cpu_to_le32(U64_LO(txdata
->tx_desc_mapping
+
6405 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
6408 *txdata
->tx_cons_sb
= cpu_to_le16(0);
6410 SET_FLAG(txdata
->tx_db
.data
.header
.header
, DOORBELL_HDR_DB_TYPE
, 1);
6411 txdata
->tx_db
.data
.zero_fill1
= 0;
6412 txdata
->tx_db
.data
.prod
= 0;
6414 txdata
->tx_pkt_prod
= 0;
6415 txdata
->tx_pkt_cons
= 0;
6416 txdata
->tx_bd_prod
= 0;
6417 txdata
->tx_bd_cons
= 0;
6421 static void bnx2x_init_tx_rings_cnic(struct bnx2x
*bp
)
6425 for_each_tx_queue_cnic(bp
, i
)
6426 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[0]);
6429 static void bnx2x_init_tx_rings(struct bnx2x
*bp
)
6434 for_each_eth_queue(bp
, i
)
6435 for_each_cos_in_tx_queue(&bp
->fp
[i
], cos
)
6436 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[cos
]);
6439 static void bnx2x_init_fcoe_fp(struct bnx2x
*bp
)
6441 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
6442 unsigned long q_type
= 0;
6444 bnx2x_fcoe(bp
, rx_queue
) = BNX2X_NUM_ETH_QUEUES(bp
);
6445 bnx2x_fcoe(bp
, cl_id
) = bnx2x_cnic_eth_cl_id(bp
,
6446 BNX2X_FCOE_ETH_CL_ID_IDX
);
6447 bnx2x_fcoe(bp
, cid
) = BNX2X_FCOE_ETH_CID(bp
);
6448 bnx2x_fcoe(bp
, fw_sb_id
) = DEF_SB_ID
;
6449 bnx2x_fcoe(bp
, igu_sb_id
) = bp
->igu_dsb_id
;
6450 bnx2x_fcoe(bp
, rx_cons_sb
) = BNX2X_FCOE_L2_RX_INDEX
;
6451 bnx2x_init_txdata(bp
, bnx2x_fcoe(bp
, txdata_ptr
[0]),
6452 fp
->cid
, FCOE_TXQ_IDX(bp
), BNX2X_FCOE_L2_TX_INDEX
,
6455 DP(NETIF_MSG_IFUP
, "created fcoe tx data (fp index %d)\n", fp
->index
);
6457 /* qZone id equals to FW (per path) client id */
6458 bnx2x_fcoe(bp
, cl_qzone_id
) = bnx2x_fp_qzone_id(fp
);
6460 bnx2x_fcoe(bp
, ustorm_rx_prods_offset
) =
6461 bnx2x_rx_ustorm_prods_offset(fp
);
6463 /* Configure Queue State object */
6464 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
6465 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
6467 /* No multi-CoS for FCoE L2 client */
6468 BUG_ON(fp
->max_cos
!= 1);
6470 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
,
6471 &fp
->cid
, 1, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
6472 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
6475 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6476 fp
->index
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
6480 void bnx2x_nic_init_cnic(struct bnx2x
*bp
)
6483 bnx2x_init_fcoe_fp(bp
);
6485 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
6486 BNX2X_VF_ID_INVALID
, false,
6487 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
6489 /* ensure status block indices were read */
6491 bnx2x_init_rx_rings_cnic(bp
);
6492 bnx2x_init_tx_rings_cnic(bp
);
6499 void bnx2x_pre_irq_nic_init(struct bnx2x
*bp
)
6503 /* Setup NIC internals and enable interrupts */
6504 for_each_eth_queue(bp
, i
)
6505 bnx2x_init_eth_fp(bp
, i
);
6507 /* ensure status block indices were read */
6509 bnx2x_init_rx_rings(bp
);
6510 bnx2x_init_tx_rings(bp
);
6513 /* Initialize MOD_ABS interrupts */
6514 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
6515 bp
->common
.shmem_base
,
6516 bp
->common
.shmem2_base
, BP_PORT(bp
));
6518 /* initialize the default status block and sp ring */
6519 bnx2x_init_def_sb(bp
);
6520 bnx2x_update_dsb_idx(bp
);
6521 bnx2x_init_sp_ring(bp
);
6523 bnx2x_memset_stats(bp
);
6527 void bnx2x_post_irq_nic_init(struct bnx2x
*bp
, u32 load_code
)
6529 bnx2x_init_eq_ring(bp
);
6530 bnx2x_init_internal(bp
, load_code
);
6532 bnx2x_stats_init(bp
);
6534 /* flush all before enabling interrupts */
6538 bnx2x_int_enable(bp
);
6540 /* Check for SPIO5 */
6541 bnx2x_attn_int_deasserted0(bp
,
6542 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
6543 AEU_INPUTS_ATTN_BITS_SPIO5
);
6546 /* gzip service functions */
6547 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
6549 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
6550 &bp
->gunzip_mapping
, GFP_KERNEL
);
6551 if (bp
->gunzip_buf
== NULL
)
6554 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
6555 if (bp
->strm
== NULL
)
6558 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
6559 if (bp
->strm
->workspace
== NULL
)
6569 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6570 bp
->gunzip_mapping
);
6571 bp
->gunzip_buf
= NULL
;
6574 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6578 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
6581 vfree(bp
->strm
->workspace
);
6586 if (bp
->gunzip_buf
) {
6587 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6588 bp
->gunzip_mapping
);
6589 bp
->gunzip_buf
= NULL
;
6593 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
6597 /* check gzip header */
6598 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
6599 BNX2X_ERR("Bad gzip header\n");
6607 if (zbuf
[3] & FNAME
)
6608 while ((zbuf
[n
++] != 0) && (n
< len
));
6610 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
6611 bp
->strm
->avail_in
= len
- n
;
6612 bp
->strm
->next_out
= bp
->gunzip_buf
;
6613 bp
->strm
->avail_out
= FW_BUF_SIZE
;
6615 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
6619 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
6620 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
6621 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
6624 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
6625 if (bp
->gunzip_outlen
& 0x3)
6627 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6629 bp
->gunzip_outlen
>>= 2;
6631 zlib_inflateEnd(bp
->strm
);
6633 if (rc
== Z_STREAM_END
)
6639 /* nic load/unload */
6642 * General service functions
6645 /* send a NIG loopback debug packet */
6646 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
6650 /* Ethernet source and destination addresses */
6651 wb_write
[0] = 0x55555555;
6652 wb_write
[1] = 0x55555555;
6653 wb_write
[2] = 0x20; /* SOP */
6654 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6656 /* NON-IP protocol */
6657 wb_write
[0] = 0x09000000;
6658 wb_write
[1] = 0x55555555;
6659 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
6660 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6663 /* some of the internal memories
6664 * are not directly readable from the driver
6665 * to test them we send debug packets
6667 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
6673 if (CHIP_REV_IS_FPGA(bp
))
6675 else if (CHIP_REV_IS_EMUL(bp
))
6680 /* Disable inputs of parser neighbor blocks */
6681 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6682 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6683 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6684 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6686 /* Write 0 to parser credits for CFC search request */
6687 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6689 /* send Ethernet packet */
6692 /* TODO do i reset NIG statistic? */
6693 /* Wait until NIG register shows 1 packet of size 0x10 */
6694 count
= 1000 * factor
;
6697 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6698 val
= *bnx2x_sp(bp
, wb_data
[0]);
6702 usleep_range(10000, 20000);
6706 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6710 /* Wait until PRS register shows 1 packet */
6711 count
= 1000 * factor
;
6713 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6717 usleep_range(10000, 20000);
6721 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6725 /* Reset and init BRB, PRS */
6726 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6728 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6730 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6731 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6733 DP(NETIF_MSG_HW
, "part2\n");
6735 /* Disable inputs of parser neighbor blocks */
6736 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6737 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6738 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6739 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6741 /* Write 0 to parser credits for CFC search request */
6742 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6744 /* send 10 Ethernet packets */
6745 for (i
= 0; i
< 10; i
++)
6748 /* Wait until NIG register shows 10 + 1
6749 packets of size 11*0x10 = 0xb0 */
6750 count
= 1000 * factor
;
6753 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6754 val
= *bnx2x_sp(bp
, wb_data
[0]);
6758 usleep_range(10000, 20000);
6762 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6766 /* Wait until PRS register shows 2 packets */
6767 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6769 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6771 /* Write 1 to parser credits for CFC search request */
6772 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
6774 /* Wait until PRS register shows 3 packets */
6775 msleep(10 * factor
);
6776 /* Wait until NIG register shows 1 packet of size 0x10 */
6777 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6779 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6781 /* clear NIG EOP FIFO */
6782 for (i
= 0; i
< 11; i
++)
6783 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
6784 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
6786 BNX2X_ERR("clear of NIG failed\n");
6790 /* Reset and init BRB, PRS, NIG */
6791 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6793 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6795 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6796 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6797 if (!CNIC_SUPPORT(bp
))
6799 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6801 /* Enable inputs of parser neighbor blocks */
6802 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
6803 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
6804 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
6805 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
6807 DP(NETIF_MSG_HW
, "done\n");
6812 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
6816 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6817 if (!CHIP_IS_E1x(bp
))
6818 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
6820 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
6821 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6822 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6824 * mask read length error interrupts in brb for parser
6825 * (parsing unit and 'checksum and crc' unit)
6826 * these errors are legal (PU reads fixed length and CAC can cause
6827 * read length error on truncated packets)
6829 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
6830 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
6831 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
6832 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
6833 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
6834 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
6835 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6836 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6837 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
6838 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
6839 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
6840 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6841 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6842 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
6843 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
6844 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
6845 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
6846 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6847 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6849 val
= PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
|
6850 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
|
6851 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
;
6852 if (!CHIP_IS_E1x(bp
))
6853 val
|= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
|
6854 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
;
6855 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, val
);
6857 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
6858 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
6859 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
6860 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6862 if (!CHIP_IS_E1x(bp
))
6863 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6864 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
6866 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
6867 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
6868 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6869 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
6872 static void bnx2x_reset_common(struct bnx2x
*bp
)
6877 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6880 if (CHIP_IS_E3(bp
)) {
6881 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6882 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6885 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
6888 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
6891 spin_lock_init(&bp
->dmae_lock
);
6894 static void bnx2x_init_pxp(struct bnx2x
*bp
)
6897 int r_order
, w_order
;
6899 pcie_capability_read_word(bp
->pdev
, PCI_EXP_DEVCTL
, &devctl
);
6900 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
6901 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6903 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
6905 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
6909 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
6912 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
6922 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
6923 SHARED_HW_CFG_FAN_FAILURE_MASK
;
6925 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
6929 * The fan failure mechanism is usually related to the PHY type since
6930 * the power consumption of the board is affected by the PHY. Currently,
6931 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6933 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
6934 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
6936 bnx2x_fan_failure_det_req(
6938 bp
->common
.shmem_base
,
6939 bp
->common
.shmem2_base
,
6943 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
6945 if (is_required
== 0)
6948 /* Fan failure is indicated by SPIO 5 */
6949 bnx2x_set_spio(bp
, MISC_SPIO_SPIO5
, MISC_SPIO_INPUT_HI_Z
);
6951 /* set to active low mode */
6952 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
6953 val
|= (MISC_SPIO_SPIO5
<< MISC_SPIO_INT_OLD_SET_POS
);
6954 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
6956 /* enable interrupt to signal the IGU */
6957 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6958 val
|= MISC_SPIO_SPIO5
;
6959 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
6962 void bnx2x_pf_disable(struct bnx2x
*bp
)
6964 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
6965 val
&= ~IGU_PF_CONF_FUNC_EN
;
6967 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
6968 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
6969 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
6972 static void bnx2x__common_init_phy(struct bnx2x
*bp
)
6974 u32 shmem_base
[2], shmem2_base
[2];
6975 /* Avoid common init in case MFW supports LFA */
6976 if (SHMEM2_RD(bp
, size
) >
6977 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
6979 shmem_base
[0] = bp
->common
.shmem_base
;
6980 shmem2_base
[0] = bp
->common
.shmem2_base
;
6981 if (!CHIP_IS_E1x(bp
)) {
6983 SHMEM2_RD(bp
, other_shmem_base_addr
);
6985 SHMEM2_RD(bp
, other_shmem2_base_addr
);
6987 bnx2x_acquire_phy_lock(bp
);
6988 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
6989 bp
->common
.chip_id
);
6990 bnx2x_release_phy_lock(bp
);
6993 static void bnx2x_config_endianity(struct bnx2x
*bp
, u32 val
)
6995 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, val
);
6996 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, val
);
6997 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, val
);
6998 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, val
);
6999 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, val
);
7001 /* make sure this value is 0 */
7002 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
7004 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, val
);
7005 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, val
);
7006 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, val
);
7007 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, val
);
7010 static void bnx2x_set_endianity(struct bnx2x
*bp
)
7013 bnx2x_config_endianity(bp
, 1);
7015 bnx2x_config_endianity(bp
, 0);
7019 static void bnx2x_reset_endianity(struct bnx2x
*bp
)
7021 bnx2x_config_endianity(bp
, 0);
7025 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7027 * @bp: driver handle
7029 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
7033 DP(NETIF_MSG_HW
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
7036 * take the RESET lock to protect undi_unload flow from accessing
7037 * registers while we're resetting the chip
7039 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
7041 bnx2x_reset_common(bp
);
7042 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
7045 if (CHIP_IS_E3(bp
)) {
7046 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
7047 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
7049 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
7051 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
7053 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
7055 if (!CHIP_IS_E1x(bp
)) {
7059 * 4-port mode or 2-port mode we need to turn of master-enable
7060 * for everyone, after that, turn it back on for self.
7061 * so, we disregard multi-function or not, and always disable
7062 * for all functions on the given path, this means 0,2,4,6 for
7063 * path 0 and 1,3,5,7 for path 1
7065 for (abs_func_id
= BP_PATH(bp
);
7066 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
7067 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
7069 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
7074 bnx2x_pretend_func(bp
, abs_func_id
);
7075 /* clear pf enable */
7076 bnx2x_pf_disable(bp
);
7077 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
7081 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
7082 if (CHIP_IS_E1(bp
)) {
7083 /* enable HW interrupt from PXP on USDM overflow
7084 bit 16 on INT_MASK_0 */
7085 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
7088 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
7090 bnx2x_set_endianity(bp
);
7091 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
7093 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
7094 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
7096 /* let the HW do it's magic ... */
7098 /* finish PXP init */
7099 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
7101 BNX2X_ERR("PXP2 CFG failed\n");
7104 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
7106 BNX2X_ERR("PXP2 RD_INIT failed\n");
7110 /* Timers bug workaround E2 only. We need to set the entire ILT to
7111 * have entries with value "0" and valid bit on.
7112 * This needs to be done by the first PF that is loaded in a path
7113 * (i.e. common phase)
7115 if (!CHIP_IS_E1x(bp
)) {
7116 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7117 * (i.e. vnic3) to start even if it is marked as "scan-off".
7118 * This occurs when a different function (func2,3) is being marked
7119 * as "scan-off". Real-life scenario for example: if a driver is being
7120 * load-unloaded while func6,7 are down. This will cause the timer to access
7121 * the ilt, translate to a logical address and send a request to read/write.
7122 * Since the ilt for the function that is down is not valid, this will cause
7123 * a translation error which is unrecoverable.
7124 * The Workaround is intended to make sure that when this happens nothing fatal
7125 * will occur. The workaround:
7126 * 1. First PF driver which loads on a path will:
7127 * a. After taking the chip out of reset, by using pretend,
7128 * it will write "0" to the following registers of
7130 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7131 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7132 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7133 * And for itself it will write '1' to
7134 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7135 * dmae-operations (writing to pram for example.)
7136 * note: can be done for only function 6,7 but cleaner this
7138 * b. Write zero+valid to the entire ILT.
7139 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7140 * VNIC3 (of that port). The range allocated will be the
7141 * entire ILT. This is needed to prevent ILT range error.
7142 * 2. Any PF driver load flow:
7143 * a. ILT update with the physical addresses of the allocated
7145 * b. Wait 20msec. - note that this timeout is needed to make
7146 * sure there are no requests in one of the PXP internal
7147 * queues with "old" ILT addresses.
7148 * c. PF enable in the PGLC.
7149 * d. Clear the was_error of the PF in the PGLC. (could have
7150 * occurred while driver was down)
7151 * e. PF enable in the CFC (WEAK + STRONG)
7152 * f. Timers scan enable
7153 * 3. PF driver unload flow:
7154 * a. Clear the Timers scan_en.
7155 * b. Polling for scan_on=0 for that PF.
7156 * c. Clear the PF enable bit in the PXP.
7157 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7158 * e. Write zero+valid to all ILT entries (The valid bit must
7160 * f. If this is VNIC 3 of a port then also init
7161 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7162 * to the last entry in the ILT.
7165 * Currently the PF error in the PGLC is non recoverable.
7166 * In the future the there will be a recovery routine for this error.
7167 * Currently attention is masked.
7168 * Having an MCP lock on the load/unload process does not guarantee that
7169 * there is no Timer disable during Func6/7 enable. This is because the
7170 * Timers scan is currently being cleared by the MCP on FLR.
7171 * Step 2.d can be done only for PF6/7 and the driver can also check if
7172 * there is error before clearing it. But the flow above is simpler and
7174 * All ILT entries are written by zero+valid and not just PF6/7
7175 * ILT entries since in the future the ILT entries allocation for
7176 * PF-s might be dynamic.
7178 struct ilt_client_info ilt_cli
;
7179 struct bnx2x_ilt ilt
;
7180 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
7181 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
7183 /* initialize dummy TM client */
7185 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
7186 ilt_cli
.client_num
= ILT_CLIENT_TM
;
7188 /* Step 1: set zeroes to all ilt page entries with valid bit on
7189 * Step 2: set the timers first/last ilt entry to point
7190 * to the entire range to prevent ILT range error for 3rd/4th
7191 * vnic (this code assumes existence of the vnic)
7193 * both steps performed by call to bnx2x_ilt_client_init_op()
7194 * with dummy TM client
7196 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7197 * and his brother are split registers
7199 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
7200 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
7201 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
7203 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
7204 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
7205 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
7208 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
7209 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
7211 if (!CHIP_IS_E1x(bp
)) {
7212 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
7213 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
7214 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
7216 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
7218 /* let the HW do it's magic ... */
7221 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
7222 } while (factor
-- && (val
!= 1));
7225 BNX2X_ERR("ATC_INIT failed\n");
7230 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
7232 bnx2x_iov_init_dmae(bp
);
7234 /* clean the DMAE memory */
7236 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
7238 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
7240 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
7242 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
7244 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
7246 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
7247 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
7248 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
7249 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
7251 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
7253 /* QM queues pointers table */
7254 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
7256 /* soft reset pulse */
7257 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
7258 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
7260 if (CNIC_SUPPORT(bp
))
7261 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
7263 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
7265 if (!CHIP_REV_IS_SLOW(bp
))
7266 /* enable hw interrupt from doorbell Q */
7267 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
7269 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
7271 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
7272 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
7274 if (!CHIP_IS_E1(bp
))
7275 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
7277 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
)) {
7278 if (IS_MF_AFEX(bp
)) {
7279 /* configure that VNTag and VLAN headers must be
7280 * received in afex mode
7282 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
, 0xE);
7283 REG_WR(bp
, PRS_REG_MUST_HAVE_HDRS
, 0xA);
7284 REG_WR(bp
, PRS_REG_HDRS_AFTER_TAG_0
, 0x6);
7285 REG_WR(bp
, PRS_REG_TAG_ETHERTYPE_0
, 0x8926);
7286 REG_WR(bp
, PRS_REG_TAG_LEN_0
, 0x4);
7288 /* Bit-map indicating which L2 hdrs may appear
7289 * after the basic Ethernet header
7291 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
7292 bp
->path_has_ovlan
? 7 : 6);
7296 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
7297 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
7298 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
7299 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
7301 if (!CHIP_IS_E1x(bp
)) {
7302 /* reset VFC memories */
7303 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
7304 VFC_MEMORIES_RST_REG_CAM_RST
|
7305 VFC_MEMORIES_RST_REG_RAM_RST
);
7306 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
7307 VFC_MEMORIES_RST_REG_CAM_RST
|
7308 VFC_MEMORIES_RST_REG_RAM_RST
);
7313 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
7314 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
7315 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
7316 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
7319 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
7321 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
7324 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
7325 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
7326 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
7328 if (!CHIP_IS_E1x(bp
)) {
7329 if (IS_MF_AFEX(bp
)) {
7330 /* configure that VNTag and VLAN headers must be
7333 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
, 0xE);
7334 REG_WR(bp
, PBF_REG_MUST_HAVE_HDRS
, 0xA);
7335 REG_WR(bp
, PBF_REG_HDRS_AFTER_TAG_0
, 0x6);
7336 REG_WR(bp
, PBF_REG_TAG_ETHERTYPE_0
, 0x8926);
7337 REG_WR(bp
, PBF_REG_TAG_LEN_0
, 0x4);
7339 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
7340 bp
->path_has_ovlan
? 7 : 6);
7344 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
7346 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
7348 if (CNIC_SUPPORT(bp
)) {
7349 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
7350 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
7351 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
7352 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
7353 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
7354 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
7355 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
7356 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
7357 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
7358 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
7360 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
7362 if (sizeof(union cdu_context
) != 1024)
7363 /* we currently assume that a context is 1024 bytes */
7364 dev_alert(&bp
->pdev
->dev
,
7365 "please adjust the size of cdu_context(%ld)\n",
7366 (long)sizeof(union cdu_context
));
7368 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
7369 val
= (4 << 24) + (0 << 12) + 1024;
7370 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
7372 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
7373 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
7374 /* enable context validation interrupt from CFC */
7375 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
7377 /* set the thresholds to prevent CFC/CDU race */
7378 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
7380 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
7382 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
7383 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
7385 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
7386 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
7388 /* Reset PCIE errors for debug */
7389 REG_WR(bp
, 0x2814, 0xffffffff);
7390 REG_WR(bp
, 0x3820, 0xffffffff);
7392 if (!CHIP_IS_E1x(bp
)) {
7393 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
7394 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
7395 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
7396 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
7397 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
7398 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
7399 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
7400 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
7401 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
7402 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
7403 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
7406 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
7407 if (!CHIP_IS_E1(bp
)) {
7408 /* in E3 this done in per-port section */
7409 if (!CHIP_IS_E3(bp
))
7410 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7412 if (CHIP_IS_E1H(bp
))
7413 /* not applicable for E2 (and above ...) */
7414 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
7416 if (CHIP_REV_IS_SLOW(bp
))
7419 /* finish CFC init */
7420 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
7422 BNX2X_ERR("CFC LL_INIT failed\n");
7425 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
7427 BNX2X_ERR("CFC AC_INIT failed\n");
7430 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
7432 BNX2X_ERR("CFC CAM_INIT failed\n");
7435 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
7437 if (CHIP_IS_E1(bp
)) {
7438 /* read NIG statistic
7439 to see if this is our first up since powerup */
7440 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
7441 val
= *bnx2x_sp(bp
, wb_data
[0]);
7443 /* do internal memory self test */
7444 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
7445 BNX2X_ERR("internal mem self test failed\n");
7450 bnx2x_setup_fan_failure_detection(bp
);
7452 /* clear PXP2 attentions */
7453 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
7455 bnx2x_enable_blocks_attention(bp
);
7456 bnx2x_enable_blocks_parity(bp
);
7458 if (!BP_NOMCP(bp
)) {
7459 if (CHIP_IS_E1x(bp
))
7460 bnx2x__common_init_phy(bp
);
7462 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7464 if (SHMEM2_HAS(bp
, netproc_fw_ver
))
7465 SHMEM2_WR(bp
, netproc_fw_ver
, REG_RD(bp
, XSEM_REG_PRAM
));
7471 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7473 * @bp: driver handle
7475 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
7477 int rc
= bnx2x_init_hw_common(bp
);
7482 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7484 bnx2x__common_init_phy(bp
);
7489 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
7491 int port
= BP_PORT(bp
);
7492 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
7496 DP(NETIF_MSG_HW
, "starting port init port %d\n", port
);
7498 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7500 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
7501 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7502 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7504 /* Timers bug workaround: disables the pf_master bit in pglue at
7505 * common phase, we need to enable it here before any dmae access are
7506 * attempted. Therefore we manually added the enable-master to the
7507 * port phase (it also happens in the function phase)
7509 if (!CHIP_IS_E1x(bp
))
7510 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
7512 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
7513 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
7514 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
7515 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
7517 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
7518 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
7519 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
7520 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
7522 /* QM cid (connection) count */
7523 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
7525 if (CNIC_SUPPORT(bp
)) {
7526 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
7527 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
7528 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
7531 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
7533 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
7535 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
7538 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
7539 else if (bp
->dev
->mtu
> 4096) {
7540 if (bp
->flags
& ONE_PORT_FLAG
)
7544 /* (24*1024 + val*4)/256 */
7545 low
= 96 + (val
/64) +
7546 ((val
% 64) ? 1 : 0);
7549 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
7550 high
= low
+ 56; /* 14*1024/256 */
7551 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
7552 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
7555 if (CHIP_MODE_IS_4_PORT(bp
))
7556 REG_WR(bp
, (BP_PORT(bp
) ?
7557 BRB1_REG_MAC_GUARANTIED_1
:
7558 BRB1_REG_MAC_GUARANTIED_0
), 40);
7560 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7561 if (CHIP_IS_E3B0(bp
)) {
7562 if (IS_MF_AFEX(bp
)) {
7563 /* configure headers for AFEX mode */
7564 REG_WR(bp
, BP_PORT(bp
) ?
7565 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7566 PRS_REG_HDRS_AFTER_BASIC_PORT_0
, 0xE);
7567 REG_WR(bp
, BP_PORT(bp
) ?
7568 PRS_REG_HDRS_AFTER_TAG_0_PORT_1
:
7569 PRS_REG_HDRS_AFTER_TAG_0_PORT_0
, 0x6);
7570 REG_WR(bp
, BP_PORT(bp
) ?
7571 PRS_REG_MUST_HAVE_HDRS_PORT_1
:
7572 PRS_REG_MUST_HAVE_HDRS_PORT_0
, 0xA);
7574 /* Ovlan exists only if we are in multi-function +
7575 * switch-dependent mode, in switch-independent there
7576 * is no ovlan headers
7578 REG_WR(bp
, BP_PORT(bp
) ?
7579 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7580 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
7581 (bp
->path_has_ovlan
? 7 : 6));
7585 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7586 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7587 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7588 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7590 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7591 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7592 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7593 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7595 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7596 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7598 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7600 if (CHIP_IS_E1x(bp
)) {
7601 /* configure PBF to work without PAUSE mtu 9000 */
7602 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
7604 /* update threshold */
7605 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
7606 /* update init credit */
7607 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
7610 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
7612 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
7615 if (CNIC_SUPPORT(bp
))
7616 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7618 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7619 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7621 if (CHIP_IS_E1(bp
)) {
7622 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7623 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7625 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7627 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7629 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7630 /* init aeu_mask_attn_func_0/1:
7631 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7632 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7633 * bits 4-7 are used for "per vn group attention" */
7634 val
= IS_MF(bp
) ? 0xF7 : 0x7;
7635 /* Enable DCBX attention for all but E1 */
7636 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
7637 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
7639 /* SCPAD_PARITY should NOT trigger close the gates */
7640 reg
= port
? MISC_REG_AEU_ENABLE4_NIG_1
: MISC_REG_AEU_ENABLE4_NIG_0
;
7643 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
);
7645 reg
= port
? MISC_REG_AEU_ENABLE4_PXP_1
: MISC_REG_AEU_ENABLE4_PXP_0
;
7648 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
);
7650 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7652 if (!CHIP_IS_E1x(bp
)) {
7653 /* Bit-map indicating which L2 hdrs may appear after the
7654 * basic Ethernet header
7657 REG_WR(bp
, BP_PORT(bp
) ?
7658 NIG_REG_P1_HDRS_AFTER_BASIC
:
7659 NIG_REG_P0_HDRS_AFTER_BASIC
, 0xE);
7661 REG_WR(bp
, BP_PORT(bp
) ?
7662 NIG_REG_P1_HDRS_AFTER_BASIC
:
7663 NIG_REG_P0_HDRS_AFTER_BASIC
,
7664 IS_MF_SD(bp
) ? 7 : 6);
7667 REG_WR(bp
, BP_PORT(bp
) ?
7668 NIG_REG_LLH1_MF_MODE
:
7669 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7671 if (!CHIP_IS_E3(bp
))
7672 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
7674 if (!CHIP_IS_E1(bp
)) {
7675 /* 0x2 disable mf_ov, 0x1 enable */
7676 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
7677 (IS_MF_SD(bp
) ? 0x1 : 0x2));
7679 if (!CHIP_IS_E1x(bp
)) {
7681 switch (bp
->mf_mode
) {
7682 case MULTI_FUNCTION_SD
:
7685 case MULTI_FUNCTION_SI
:
7686 case MULTI_FUNCTION_AFEX
:
7691 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
7692 NIG_REG_LLH0_CLS_TYPE
), val
);
7695 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
7696 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
7697 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
7701 /* If SPIO5 is set to generate interrupts, enable it for this port */
7702 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
7703 if (val
& MISC_SPIO_SPIO5
) {
7704 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
7705 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
7706 val
= REG_RD(bp
, reg_addr
);
7707 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
7708 REG_WR(bp
, reg_addr
, val
);
7714 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
7720 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
7722 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
7724 wb_write
[0] = ONCHIP_ADDR1(addr
);
7725 wb_write
[1] = ONCHIP_ADDR2(addr
);
7726 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
7729 void bnx2x_igu_clear_sb_gen(struct bnx2x
*bp
, u8 func
, u8 idu_sb_id
, bool is_pf
)
7731 u32 data
, ctl
, cnt
= 100;
7732 u32 igu_addr_data
= IGU_REG_COMMAND_REG_32LSB_DATA
;
7733 u32 igu_addr_ctl
= IGU_REG_COMMAND_REG_CTRL
;
7734 u32 igu_addr_ack
= IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
+ (idu_sb_id
/32)*4;
7735 u32 sb_bit
= 1 << (idu_sb_id
%32);
7736 u32 func_encode
= func
| (is_pf
? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT
;
7737 u32 addr_encode
= IGU_CMD_E2_PROD_UPD_BASE
+ idu_sb_id
;
7739 /* Not supported in BC mode */
7740 if (CHIP_INT_MODE_IS_BC(bp
))
7743 data
= (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7744 << IGU_REGULAR_CLEANUP_TYPE_SHIFT
) |
7745 IGU_REGULAR_CLEANUP_SET
|
7746 IGU_REGULAR_BCLEANUP
;
7748 ctl
= addr_encode
<< IGU_CTRL_REG_ADDRESS_SHIFT
|
7749 func_encode
<< IGU_CTRL_REG_FID_SHIFT
|
7750 IGU_CTRL_CMD_TYPE_WR
<< IGU_CTRL_REG_TYPE_SHIFT
;
7752 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7753 data
, igu_addr_data
);
7754 REG_WR(bp
, igu_addr_data
, data
);
7757 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7759 REG_WR(bp
, igu_addr_ctl
, ctl
);
7763 /* wait for clean up to finish */
7764 while (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
) && --cnt
)
7767 if (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
)) {
7769 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7770 idu_sb_id
, idu_sb_id
/32, idu_sb_id
%32, cnt
);
7774 static void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
7776 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
7779 static void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
7781 u32 i
, base
= FUNC_ILT_BASE(func
);
7782 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
7783 bnx2x_ilt_wr(bp
, i
, 0);
7786 static void bnx2x_init_searcher(struct bnx2x
*bp
)
7788 int port
= BP_PORT(bp
);
7789 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
7790 /* T1 hash bits value determines the T1 number of entries */
7791 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
7794 static inline int bnx2x_func_switch_update(struct bnx2x
*bp
, int suspend
)
7797 struct bnx2x_func_state_params func_params
= {NULL
};
7798 struct bnx2x_func_switch_update_params
*switch_update_params
=
7799 &func_params
.params
.switch_update
;
7801 /* Prepare parameters for function state transitions */
7802 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7803 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
7805 func_params
.f_obj
= &bp
->func_obj
;
7806 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
7808 /* Function parameters */
7809 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG
,
7810 &switch_update_params
->changes
);
7812 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND
,
7813 &switch_update_params
->changes
);
7815 rc
= bnx2x_func_state_change(bp
, &func_params
);
7820 static int bnx2x_reset_nic_mode(struct bnx2x
*bp
)
7822 int rc
, i
, port
= BP_PORT(bp
);
7823 int vlan_en
= 0, mac_en
[NUM_MACS
];
7825 /* Close input from network */
7826 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7827 bnx2x_set_rx_filter(&bp
->link_params
, 0);
7829 vlan_en
= REG_RD(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7830 NIG_REG_LLH0_FUNC_EN
);
7831 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7832 NIG_REG_LLH0_FUNC_EN
, 0);
7833 for (i
= 0; i
< NUM_MACS
; i
++) {
7834 mac_en
[i
] = REG_RD(bp
, port
?
7835 (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7837 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+
7839 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7841 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
), 0);
7845 /* Close BMC to host */
7846 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7847 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 0);
7849 /* Suspend Tx switching to the PF. Completion of this ramrod
7850 * further guarantees that all the packets of that PF / child
7851 * VFs in BRB were processed by the Parser, so it is safe to
7852 * change the NIC_MODE register.
7854 rc
= bnx2x_func_switch_update(bp
, 1);
7856 BNX2X_ERR("Can't suspend tx-switching!\n");
7860 /* Change NIC_MODE register */
7861 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7863 /* Open input from network */
7864 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7865 bnx2x_set_rx_filter(&bp
->link_params
, 1);
7867 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7868 NIG_REG_LLH0_FUNC_EN
, vlan_en
);
7869 for (i
= 0; i
< NUM_MACS
; i
++) {
7870 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7872 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
),
7877 /* Enable BMC to host */
7878 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7879 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 1);
7881 /* Resume Tx switching to the PF */
7882 rc
= bnx2x_func_switch_update(bp
, 0);
7884 BNX2X_ERR("Can't resume tx-switching!\n");
7888 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7892 int bnx2x_init_hw_func_cnic(struct bnx2x
*bp
)
7896 bnx2x_ilt_init_op_cnic(bp
, INITOP_SET
);
7898 if (CONFIGURE_NIC_MODE(bp
)) {
7899 /* Configure searcher as part of function hw init */
7900 bnx2x_init_searcher(bp
);
7902 /* Reset NIC mode */
7903 rc
= bnx2x_reset_nic_mode(bp
);
7905 BNX2X_ERR("Can't change NIC mode!\n");
7912 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7913 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7914 * the addresses of the transaction, resulting in was-error bit set in the pci
7915 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7916 * to clear the interrupt which detected this from the pglueb and the was done
7919 static void bnx2x_clean_pglue_errors(struct bnx2x
*bp
)
7921 if (!CHIP_IS_E1x(bp
))
7922 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
,
7923 1 << BP_ABS_FUNC(bp
));
7926 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
7928 int port
= BP_PORT(bp
);
7929 int func
= BP_FUNC(bp
);
7930 int init_phase
= PHASE_PF0
+ func
;
7931 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7934 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
7935 int i
, main_mem_width
, rc
;
7937 DP(NETIF_MSG_HW
, "starting func init func %d\n", func
);
7939 /* FLR cleanup - hmmm */
7940 if (!CHIP_IS_E1x(bp
)) {
7941 rc
= bnx2x_pf_flr_clnup(bp
);
7948 /* set MSI reconfigure capability */
7949 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7950 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
7951 val
= REG_RD(bp
, addr
);
7952 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
7953 REG_WR(bp
, addr
, val
);
7956 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7957 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7960 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7963 cdu_ilt_start
+= BNX2X_FIRST_VF_CID
/ILT_PAGE_CIDS
;
7964 cdu_ilt_start
= bnx2x_iov_init_ilt(bp
, cdu_ilt_start
);
7966 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7967 * those of the VFs, so start line should be reset
7969 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7970 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
7971 ilt
->lines
[cdu_ilt_start
+ i
].page
= bp
->context
[i
].vcxt
;
7972 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
7973 bp
->context
[i
].cxt_mapping
;
7974 ilt
->lines
[cdu_ilt_start
+ i
].size
= bp
->context
[i
].size
;
7977 bnx2x_ilt_init_op(bp
, INITOP_SET
);
7979 if (!CONFIGURE_NIC_MODE(bp
)) {
7980 bnx2x_init_searcher(bp
);
7981 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7982 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7985 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
7986 DP(NETIF_MSG_IFUP
, "NIC MODE configured\n");
7989 if (!CHIP_IS_E1x(bp
)) {
7990 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
7992 /* Turn on a single ISR mode in IGU if driver is going to use
7995 if (!(bp
->flags
& USING_MSIX_FLAG
))
7996 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
7998 * Timers workaround bug: function init part.
7999 * Need to wait 20msec after initializing ILT,
8000 * needed to make sure there are no requests in
8001 * one of the PXP internal queues with "old" ILT addresses
8005 * Master enable - Due to WB DMAE writes performed before this
8006 * register is re-initialized as part of the regular function
8009 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
8010 /* Enable the function in IGU */
8011 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
8016 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
8018 bnx2x_clean_pglue_errors(bp
);
8020 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
8021 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
8022 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
8023 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
8024 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
8025 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
8026 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
8027 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
8028 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
8029 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
8030 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
8031 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
8032 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
8034 if (!CHIP_IS_E1x(bp
))
8035 REG_WR(bp
, QM_REG_PF_EN
, 1);
8037 if (!CHIP_IS_E1x(bp
)) {
8038 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8039 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8040 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8041 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8043 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
8045 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
8046 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
8047 REG_WR(bp
, DORQ_REG_MODE_ACT
, 1); /* no dpm */
8049 bnx2x_iov_init_dq(bp
);
8051 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
8052 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
8053 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
8054 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
8055 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
8056 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
8057 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
8058 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
8059 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
8060 if (!CHIP_IS_E1x(bp
))
8061 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
8063 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
8065 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
8067 if (!CHIP_IS_E1x(bp
))
8068 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
8071 if (!(IS_MF_UFP(bp
) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
))) {
8072 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
* 8, 1);
8073 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
* 8,
8078 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
8080 /* HC init per function */
8081 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8082 if (CHIP_IS_E1H(bp
)) {
8083 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
8085 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8086 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8088 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
8091 int num_segs
, sb_idx
, prod_offset
;
8093 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
8095 if (!CHIP_IS_E1x(bp
)) {
8096 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8097 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8100 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
8102 if (!CHIP_IS_E1x(bp
)) {
8106 * E2 mode: address 0-135 match to the mapping memory;
8107 * 136 - PF0 default prod; 137 - PF1 default prod;
8108 * 138 - PF2 default prod; 139 - PF3 default prod;
8109 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8110 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8113 * E1.5 mode - In backward compatible mode;
8114 * for non default SB; each even line in the memory
8115 * holds the U producer and each odd line hold
8116 * the C producer. The first 128 producers are for
8117 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8118 * producers are for the DSB for each PF.
8119 * Each PF has five segments: (the order inside each
8120 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8121 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8122 * 144-147 attn prods;
8124 /* non-default-status-blocks */
8125 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
8126 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
8127 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
8128 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
8131 for (i
= 0; i
< num_segs
; i
++) {
8132 addr
= IGU_REG_PROD_CONS_MEMORY
+
8133 (prod_offset
+ i
) * 4;
8134 REG_WR(bp
, addr
, 0);
8136 /* send consumer update with value 0 */
8137 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
8138 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8139 bnx2x_igu_clear_sb(bp
,
8140 bp
->igu_base_sb
+ sb_idx
);
8143 /* default-status-blocks */
8144 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
8145 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
8147 if (CHIP_MODE_IS_4_PORT(bp
))
8148 dsb_idx
= BP_FUNC(bp
);
8150 dsb_idx
= BP_VN(bp
);
8152 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
8153 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
8154 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
8157 * igu prods come in chunks of E1HVN_MAX (4) -
8158 * does not matters what is the current chip mode
8160 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
8162 addr
= IGU_REG_PROD_CONS_MEMORY
+
8163 (prod_offset
+ i
)*4;
8164 REG_WR(bp
, addr
, 0);
8166 /* send consumer update with 0 */
8167 if (CHIP_INT_MODE_IS_BC(bp
)) {
8168 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8169 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8170 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8171 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
8172 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8173 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
8174 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8175 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
8176 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8177 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
8179 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8180 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8181 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8182 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
8184 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
8186 /* !!! These should become driver const once
8187 rf-tool supports split-68 const */
8188 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
8189 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
8190 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
8191 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
8192 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
8193 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
8197 /* Reset PCIE errors for debug */
8198 REG_WR(bp
, 0x2114, 0xffffffff);
8199 REG_WR(bp
, 0x2120, 0xffffffff);
8201 if (CHIP_IS_E1x(bp
)) {
8202 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
8203 main_mem_base
= HC_REG_MAIN_MEMORY
+
8204 BP_PORT(bp
) * (main_mem_size
* 4);
8205 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
8208 val
= REG_RD(bp
, main_mem_prty_clr
);
8211 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8214 /* Clear "false" parity errors in MSI-X table */
8215 for (i
= main_mem_base
;
8216 i
< main_mem_base
+ main_mem_size
* 4;
8217 i
+= main_mem_width
) {
8218 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
8219 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
8220 i
, main_mem_width
/ 4);
8222 /* Clear HC parity attention */
8223 REG_RD(bp
, main_mem_prty_clr
);
8226 #ifdef BNX2X_STOP_ON_ERROR
8227 /* Enable STORMs SP logging */
8228 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
8229 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8230 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
8231 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8232 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8233 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8234 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
8235 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8238 bnx2x_phy_probe(&bp
->link_params
);
8243 void bnx2x_free_mem_cnic(struct bnx2x
*bp
)
8245 bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_FREE
);
8247 if (!CHIP_IS_E1x(bp
))
8248 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
8249 sizeof(struct host_hc_status_block_e2
));
8251 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
8252 sizeof(struct host_hc_status_block_e1x
));
8254 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
8257 void bnx2x_free_mem(struct bnx2x
*bp
)
8261 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
8262 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
8267 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
8268 sizeof(struct host_sp_status_block
));
8270 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
8271 sizeof(struct bnx2x_slowpath
));
8273 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++)
8274 BNX2X_PCI_FREE(bp
->context
[i
].vcxt
, bp
->context
[i
].cxt_mapping
,
8275 bp
->context
[i
].size
);
8276 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
8278 BNX2X_FREE(bp
->ilt
->lines
);
8280 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
8282 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
8283 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
8285 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
8287 bnx2x_iov_free_mem(bp
);
8290 int bnx2x_alloc_mem_cnic(struct bnx2x
*bp
)
8292 if (!CHIP_IS_E1x(bp
)) {
8293 /* size = the status block + ramrod buffers */
8294 bp
->cnic_sb
.e2_sb
= BNX2X_PCI_ALLOC(&bp
->cnic_sb_mapping
,
8295 sizeof(struct host_hc_status_block_e2
));
8296 if (!bp
->cnic_sb
.e2_sb
)
8299 bp
->cnic_sb
.e1x_sb
= BNX2X_PCI_ALLOC(&bp
->cnic_sb_mapping
,
8300 sizeof(struct host_hc_status_block_e1x
));
8301 if (!bp
->cnic_sb
.e1x_sb
)
8305 if (CONFIGURE_NIC_MODE(bp
) && !bp
->t2
) {
8306 /* allocate searcher T2 table, as it wasn't allocated before */
8307 bp
->t2
= BNX2X_PCI_ALLOC(&bp
->t2_mapping
, SRC_T2_SZ
);
8312 /* write address to which L5 should insert its values */
8313 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
=
8314 &bp
->slowpath
->drv_info_to_mcp
;
8316 if (bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_ALLOC
))
8322 bnx2x_free_mem_cnic(bp
);
8323 BNX2X_ERR("Can't allocate memory\n");
8327 int bnx2x_alloc_mem(struct bnx2x
*bp
)
8329 int i
, allocated
, context_size
;
8331 if (!CONFIGURE_NIC_MODE(bp
) && !bp
->t2
) {
8332 /* allocate searcher T2 table */
8333 bp
->t2
= BNX2X_PCI_ALLOC(&bp
->t2_mapping
, SRC_T2_SZ
);
8338 bp
->def_status_blk
= BNX2X_PCI_ALLOC(&bp
->def_status_blk_mapping
,
8339 sizeof(struct host_sp_status_block
));
8340 if (!bp
->def_status_blk
)
8343 bp
->slowpath
= BNX2X_PCI_ALLOC(&bp
->slowpath_mapping
,
8344 sizeof(struct bnx2x_slowpath
));
8348 /* Allocate memory for CDU context:
8349 * This memory is allocated separately and not in the generic ILT
8350 * functions because CDU differs in few aspects:
8351 * 1. There are multiple entities allocating memory for context -
8352 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8353 * its own ILT lines.
8354 * 2. Since CDU page-size is not a single 4KB page (which is the case
8355 * for the other ILT clients), to be efficient we want to support
8356 * allocation of sub-page-size in the last entry.
8357 * 3. Context pointers are used by the driver to pass to FW / update
8358 * the context (for the other ILT clients the pointers are used just to
8359 * free the memory during unload).
8361 context_size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
8363 for (i
= 0, allocated
= 0; allocated
< context_size
; i
++) {
8364 bp
->context
[i
].size
= min(CDU_ILT_PAGE_SZ
,
8365 (context_size
- allocated
));
8366 bp
->context
[i
].vcxt
= BNX2X_PCI_ALLOC(&bp
->context
[i
].cxt_mapping
,
8367 bp
->context
[i
].size
);
8368 if (!bp
->context
[i
].vcxt
)
8370 allocated
+= bp
->context
[i
].size
;
8372 bp
->ilt
->lines
= kcalloc(ILT_MAX_LINES
, sizeof(struct ilt_line
),
8374 if (!bp
->ilt
->lines
)
8377 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
8380 if (bnx2x_iov_alloc_mem(bp
))
8383 /* Slow path ring */
8384 bp
->spq
= BNX2X_PCI_ALLOC(&bp
->spq_mapping
, BCM_PAGE_SIZE
);
8389 bp
->eq_ring
= BNX2X_PCI_ALLOC(&bp
->eq_mapping
,
8390 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
8398 BNX2X_ERR("Can't allocate memory\n");
8403 * Init service functions
8406 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
8407 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
8408 int mac_type
, unsigned long *ramrod_flags
)
8411 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
8413 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
8415 /* Fill general parameters */
8416 ramrod_param
.vlan_mac_obj
= obj
;
8417 ramrod_param
.ramrod_flags
= *ramrod_flags
;
8419 /* Fill a user request section if needed */
8420 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
8421 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
8423 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
8425 /* Set the command: ADD or DEL */
8427 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
8429 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
8432 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
8434 if (rc
== -EEXIST
) {
8435 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
8436 /* do not treat adding same MAC as error */
8439 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
8444 int bnx2x_set_vlan_one(struct bnx2x
*bp
, u16 vlan
,
8445 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
8446 unsigned long *ramrod_flags
)
8449 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
8451 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
8453 /* Fill general parameters */
8454 ramrod_param
.vlan_mac_obj
= obj
;
8455 ramrod_param
.ramrod_flags
= *ramrod_flags
;
8457 /* Fill a user request section if needed */
8458 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
8459 ramrod_param
.user_req
.u
.vlan
.vlan
= vlan
;
8460 /* Set the command: ADD or DEL */
8462 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
8464 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
8467 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
8469 if (rc
== -EEXIST
) {
8470 /* Do not treat adding same vlan as error. */
8471 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
8473 } else if (rc
< 0) {
8474 BNX2X_ERR("%s VLAN failed\n", (set
? "Set" : "Del"));
8480 int bnx2x_del_all_macs(struct bnx2x
*bp
,
8481 struct bnx2x_vlan_mac_obj
*mac_obj
,
8482 int mac_type
, bool wait_for_comp
)
8485 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
8487 /* Wait for completion of requested */
8489 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
8491 /* Set the mac type of addresses we want to clear */
8492 __set_bit(mac_type
, &vlan_mac_flags
);
8494 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
8496 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
8501 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
8504 unsigned long ramrod_flags
= 0;
8506 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
8507 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
8508 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
,
8509 &bp
->sp_objs
->mac_obj
, set
,
8510 BNX2X_ETH_MAC
, &ramrod_flags
);
8512 return bnx2x_vfpf_config_mac(bp
, bp
->dev
->dev_addr
,
8513 bp
->fp
->index
, set
);
8517 int bnx2x_setup_leading(struct bnx2x
*bp
)
8520 return bnx2x_setup_queue(bp
, &bp
->fp
[0], true);
8522 return bnx2x_vfpf_setup_q(bp
, &bp
->fp
[0], true);
8526 * bnx2x_set_int_mode - configure interrupt mode
8528 * @bp: driver handle
8530 * In case of MSI-X it will also try to enable MSI-X.
8532 int bnx2x_set_int_mode(struct bnx2x
*bp
)
8536 if (IS_VF(bp
) && int_mode
!= BNX2X_INT_MODE_MSIX
) {
8537 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8542 case BNX2X_INT_MODE_MSIX
:
8543 /* attempt to enable msix */
8544 rc
= bnx2x_enable_msix(bp
);
8550 /* vfs use only msix */
8551 if (rc
&& IS_VF(bp
))
8554 /* failed to enable multiple MSI-X */
8555 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8557 1 + bp
->num_cnic_queues
);
8559 /* falling through... */
8560 case BNX2X_INT_MODE_MSI
:
8561 bnx2x_enable_msi(bp
);
8563 /* falling through... */
8564 case BNX2X_INT_MODE_INTX
:
8565 bp
->num_ethernet_queues
= 1;
8566 bp
->num_queues
= bp
->num_ethernet_queues
+ bp
->num_cnic_queues
;
8567 BNX2X_DEV_INFO("set number of queues to 1\n");
8570 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8576 /* must be called prior to any HW initializations */
8577 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
8580 return (BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)/ILT_PAGE_CIDS
;
8581 return L2_ILT_LINES(bp
);
8584 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
8586 struct ilt_client_info
*ilt_client
;
8587 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
8590 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
8591 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
8594 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
8595 ilt_client
->client_num
= ILT_CLIENT_CDU
;
8596 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
8597 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
8598 ilt_client
->start
= line
;
8599 line
+= bnx2x_cid_ilt_lines(bp
);
8601 if (CNIC_SUPPORT(bp
))
8602 line
+= CNIC_ILT_LINES
;
8603 ilt_client
->end
= line
- 1;
8605 DP(NETIF_MSG_IFUP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8608 ilt_client
->page_size
,
8610 ilog2(ilt_client
->page_size
>> 12));
8613 if (QM_INIT(bp
->qm_cid_count
)) {
8614 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
8615 ilt_client
->client_num
= ILT_CLIENT_QM
;
8616 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
8617 ilt_client
->flags
= 0;
8618 ilt_client
->start
= line
;
8620 /* 4 bytes for each cid */
8621 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
8624 ilt_client
->end
= line
- 1;
8627 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8630 ilt_client
->page_size
,
8632 ilog2(ilt_client
->page_size
>> 12));
8635 if (CNIC_SUPPORT(bp
)) {
8637 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
8638 ilt_client
->client_num
= ILT_CLIENT_SRC
;
8639 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
8640 ilt_client
->flags
= 0;
8641 ilt_client
->start
= line
;
8642 line
+= SRC_ILT_LINES
;
8643 ilt_client
->end
= line
- 1;
8646 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8649 ilt_client
->page_size
,
8651 ilog2(ilt_client
->page_size
>> 12));
8654 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
8655 ilt_client
->client_num
= ILT_CLIENT_TM
;
8656 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
8657 ilt_client
->flags
= 0;
8658 ilt_client
->start
= line
;
8659 line
+= TM_ILT_LINES
;
8660 ilt_client
->end
= line
- 1;
8663 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8666 ilt_client
->page_size
,
8668 ilog2(ilt_client
->page_size
>> 12));
8671 BUG_ON(line
> ILT_MAX_LINES
);
8675 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8677 * @bp: driver handle
8678 * @fp: pointer to fastpath
8679 * @init_params: pointer to parameters structure
8681 * parameters configured:
8682 * - HC configuration
8683 * - Queue's CDU context
8685 static void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
8686 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
8689 int cxt_index
, cxt_offset
;
8691 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8692 if (!IS_FCOE_FP(fp
)) {
8693 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
8694 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
8696 /* If HC is supported, enable host coalescing in the transition
8699 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
8700 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
8703 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
8704 (1000000 / bp
->rx_ticks
) : 0;
8705 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
8706 (1000000 / bp
->tx_ticks
) : 0;
8709 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
8713 * CQ index among the SB indices: FCoE clients uses the default
8714 * SB, therefore it's different.
8716 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
8717 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
8720 /* set maximum number of COSs supported by this queue */
8721 init_params
->max_cos
= fp
->max_cos
;
8723 DP(NETIF_MSG_IFUP
, "fp: %d setting queue params max cos to: %d\n",
8724 fp
->index
, init_params
->max_cos
);
8726 /* set the context pointers queue object */
8727 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++) {
8728 cxt_index
= fp
->txdata_ptr
[cos
]->cid
/ ILT_PAGE_CIDS
;
8729 cxt_offset
= fp
->txdata_ptr
[cos
]->cid
- (cxt_index
*
8731 init_params
->cxts
[cos
] =
8732 &bp
->context
[cxt_index
].vcxt
[cxt_offset
].eth
;
8736 static int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8737 struct bnx2x_queue_state_params
*q_params
,
8738 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
8739 int tx_index
, bool leading
)
8741 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
8743 /* Set the command */
8744 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
8746 /* Set tx-only QUEUE flags: don't zero statistics */
8747 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
8749 /* choose the index of the cid to send the slow path on */
8750 tx_only_params
->cid_index
= tx_index
;
8752 /* Set general TX_ONLY_SETUP parameters */
8753 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
8755 /* Set Tx TX_ONLY_SETUP parameters */
8756 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
8759 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8760 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
8761 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
8762 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
8764 /* send the ramrod */
8765 return bnx2x_queue_state_change(bp
, q_params
);
8769 * bnx2x_setup_queue - setup queue
8771 * @bp: driver handle
8772 * @fp: pointer to fastpath
8773 * @leading: is leading
8775 * This function performs 2 steps in a Queue state machine
8776 * actually: 1) RESET->INIT 2) INIT->SETUP
8779 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8782 struct bnx2x_queue_state_params q_params
= {NULL
};
8783 struct bnx2x_queue_setup_params
*setup_params
=
8784 &q_params
.params
.setup
;
8785 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
8786 &q_params
.params
.tx_only
;
8790 DP(NETIF_MSG_IFUP
, "setting up queue %d\n", fp
->index
);
8792 /* reset IGU state skip FCoE L2 queue */
8793 if (!IS_FCOE_FP(fp
))
8794 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
8797 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8798 /* We want to wait for completion in this context */
8799 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8801 /* Prepare the INIT parameters */
8802 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
8804 /* Set the command */
8805 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
8807 /* Change the state to INIT */
8808 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8810 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
8814 DP(NETIF_MSG_IFUP
, "init complete\n");
8816 /* Now move the Queue to the SETUP state... */
8817 memset(setup_params
, 0, sizeof(*setup_params
));
8819 /* Set QUEUE flags */
8820 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
8822 /* Set general SETUP parameters */
8823 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
8824 FIRST_TX_COS_INDEX
);
8826 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
8827 &setup_params
->rxq_params
);
8829 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
8830 FIRST_TX_COS_INDEX
);
8832 /* Set the command */
8833 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
8836 bp
->fcoe_init
= true;
8838 /* Change the state to SETUP */
8839 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8841 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
8845 /* loop through the relevant tx-only indices */
8846 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8847 tx_index
< fp
->max_cos
;
8850 /* prepare and send tx-only ramrod*/
8851 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
8852 tx_only_params
, tx_index
, leading
);
8854 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8855 fp
->index
, tx_index
);
8863 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
8865 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
8866 struct bnx2x_fp_txdata
*txdata
;
8867 struct bnx2x_queue_state_params q_params
= {NULL
};
8870 DP(NETIF_MSG_IFDOWN
, "stopping queue %d cid %d\n", index
, fp
->cid
);
8872 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8873 /* We want to wait for completion in this context */
8874 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8876 /* close tx-only connections */
8877 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8878 tx_index
< fp
->max_cos
;
8881 /* ascertain this is a normal queue*/
8882 txdata
= fp
->txdata_ptr
[tx_index
];
8884 DP(NETIF_MSG_IFDOWN
, "stopping tx-only queue %d\n",
8887 /* send halt terminate on tx-only connection */
8888 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8889 memset(&q_params
.params
.terminate
, 0,
8890 sizeof(q_params
.params
.terminate
));
8891 q_params
.params
.terminate
.cid_index
= tx_index
;
8893 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8897 /* send halt terminate on tx-only connection */
8898 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8899 memset(&q_params
.params
.cfc_del
, 0,
8900 sizeof(q_params
.params
.cfc_del
));
8901 q_params
.params
.cfc_del
.cid_index
= tx_index
;
8902 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8906 /* Stop the primary connection: */
8907 /* ...halt the connection */
8908 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
8909 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8913 /* ...terminate the connection */
8914 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8915 memset(&q_params
.params
.terminate
, 0,
8916 sizeof(q_params
.params
.terminate
));
8917 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
8918 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8921 /* ...delete cfc entry */
8922 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8923 memset(&q_params
.params
.cfc_del
, 0,
8924 sizeof(q_params
.params
.cfc_del
));
8925 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
8926 return bnx2x_queue_state_change(bp
, &q_params
);
8929 static void bnx2x_reset_func(struct bnx2x
*bp
)
8931 int port
= BP_PORT(bp
);
8932 int func
= BP_FUNC(bp
);
8935 /* Disable the function in the FW */
8936 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
8937 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
8938 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
8939 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
8942 for_each_eth_queue(bp
, i
) {
8943 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8944 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8945 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
8949 if (CNIC_LOADED(bp
))
8951 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8952 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8953 (bnx2x_cnic_fw_sb_id(bp
)), SB_DISABLED
);
8956 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8957 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
8960 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
8961 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
8965 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8966 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8967 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8969 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8970 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8973 if (CNIC_LOADED(bp
)) {
8974 /* Disable Timer scan */
8975 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
8977 * Wait for at least 10ms and up to 2 second for the timers
8980 for (i
= 0; i
< 200; i
++) {
8981 usleep_range(10000, 20000);
8982 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
8987 bnx2x_clear_func_ilt(bp
, func
);
8989 /* Timers workaround bug for E2: if this is vnic-3,
8990 * we need to set the entire ilt range for this timers.
8992 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
8993 struct ilt_client_info ilt_cli
;
8994 /* use dummy TM client */
8995 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
8997 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
8998 ilt_cli
.client_num
= ILT_CLIENT_TM
;
9000 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
9003 /* this assumes that reset_port() called before reset_func()*/
9004 if (!CHIP_IS_E1x(bp
))
9005 bnx2x_pf_disable(bp
);
9010 static void bnx2x_reset_port(struct bnx2x
*bp
)
9012 int port
= BP_PORT(bp
);
9015 /* Reset physical Link */
9016 bnx2x__link_reset(bp
);
9018 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
9020 /* Do not rcv packets to BRB */
9021 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
9022 /* Do not direct rcv packets that are not for MCP to the BRB */
9023 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
9024 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
9027 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
9030 /* Check for BRB port occupancy */
9031 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
9033 DP(NETIF_MSG_IFDOWN
,
9034 "BRB1 is not empty %d blocks are occupied\n", val
);
9036 /* TODO: Close Doorbell port? */
9039 static int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
9041 struct bnx2x_func_state_params func_params
= {NULL
};
9043 /* Prepare parameters for function state transitions */
9044 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
9046 func_params
.f_obj
= &bp
->func_obj
;
9047 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
9049 func_params
.params
.hw_init
.load_phase
= load_code
;
9051 return bnx2x_func_state_change(bp
, &func_params
);
9054 static int bnx2x_func_stop(struct bnx2x
*bp
)
9056 struct bnx2x_func_state_params func_params
= {NULL
};
9059 /* Prepare parameters for function state transitions */
9060 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
9061 func_params
.f_obj
= &bp
->func_obj
;
9062 func_params
.cmd
= BNX2X_F_CMD_STOP
;
9065 * Try to stop the function the 'good way'. If fails (in case
9066 * of a parity error during bnx2x_chip_cleanup()) and we are
9067 * not in a debug mode, perform a state transaction in order to
9068 * enable further HW_RESET transaction.
9070 rc
= bnx2x_func_state_change(bp
, &func_params
);
9072 #ifdef BNX2X_STOP_ON_ERROR
9075 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9076 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
9077 return bnx2x_func_state_change(bp
, &func_params
);
9085 * bnx2x_send_unload_req - request unload mode from the MCP.
9087 * @bp: driver handle
9088 * @unload_mode: requested function's unload mode
9090 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9092 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
9095 int port
= BP_PORT(bp
);
9097 /* Select the UNLOAD request mode */
9098 if (unload_mode
== UNLOAD_NORMAL
)
9099 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
9101 else if (bp
->flags
& NO_WOL_FLAG
)
9102 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
9105 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
9106 u8
*mac_addr
= bp
->dev
->dev_addr
;
9107 struct pci_dev
*pdev
= bp
->pdev
;
9111 /* The mac address is written to entries 1-4 to
9112 * preserve entry 0 which is used by the PMF
9114 u8 entry
= (BP_VN(bp
) + 1)*8;
9116 val
= (mac_addr
[0] << 8) | mac_addr
[1];
9117 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
9119 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
9120 (mac_addr
[4] << 8) | mac_addr
[5];
9121 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
9123 /* Enable the PME and clear the status */
9124 pci_read_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
9125 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
9126 pci_write_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, pmc
);
9128 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
9131 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
9133 /* Send the request to the MCP */
9135 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
9137 int path
= BP_PATH(bp
);
9139 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] %d, %d, %d\n",
9140 path
, bnx2x_load_count
[path
][0], bnx2x_load_count
[path
][1],
9141 bnx2x_load_count
[path
][2]);
9142 bnx2x_load_count
[path
][0]--;
9143 bnx2x_load_count
[path
][1 + port
]--;
9144 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] %d, %d, %d\n",
9145 path
, bnx2x_load_count
[path
][0], bnx2x_load_count
[path
][1],
9146 bnx2x_load_count
[path
][2]);
9147 if (bnx2x_load_count
[path
][0] == 0)
9148 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
9149 else if (bnx2x_load_count
[path
][1 + port
] == 0)
9150 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
9152 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
9159 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9161 * @bp: driver handle
9162 * @keep_link: true iff link should be kept up
9164 void bnx2x_send_unload_done(struct bnx2x
*bp
, bool keep_link
)
9166 u32 reset_param
= keep_link
? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
: 0;
9168 /* Report UNLOAD_DONE to MCP */
9170 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, reset_param
);
9173 static int bnx2x_func_wait_started(struct bnx2x
*bp
)
9176 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
9182 * (assumption: No Attention from MCP at this stage)
9183 * PMF probably in the middle of TX disable/enable transaction
9184 * 1. Sync IRS for default SB
9185 * 2. Sync SP queue - this guarantees us that attention handling started
9186 * 3. Wait, that TX disable/enable transaction completes
9188 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9189 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9190 * received completion for the transaction the state is TX_STOPPED.
9191 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9195 /* make sure default SB ISR is done */
9197 synchronize_irq(bp
->msix_table
[0].vector
);
9199 synchronize_irq(bp
->pdev
->irq
);
9201 flush_workqueue(bnx2x_wq
);
9202 flush_workqueue(bnx2x_iov_wq
);
9204 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
9205 BNX2X_F_STATE_STARTED
&& tout
--)
9208 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
9209 BNX2X_F_STATE_STARTED
) {
9210 #ifdef BNX2X_STOP_ON_ERROR
9211 BNX2X_ERR("Wrong function state\n");
9215 * Failed to complete the transaction in a "good way"
9216 * Force both transactions with CLR bit
9218 struct bnx2x_func_state_params func_params
= {NULL
};
9220 DP(NETIF_MSG_IFDOWN
,
9221 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9223 func_params
.f_obj
= &bp
->func_obj
;
9224 __set_bit(RAMROD_DRV_CLR_ONLY
,
9225 &func_params
.ramrod_flags
);
9227 /* STARTED-->TX_ST0PPED */
9228 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
9229 bnx2x_func_state_change(bp
, &func_params
);
9231 /* TX_ST0PPED-->STARTED */
9232 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
9233 return bnx2x_func_state_change(bp
, &func_params
);
9240 static void bnx2x_disable_ptp(struct bnx2x
*bp
)
9242 int port
= BP_PORT(bp
);
9244 /* Disable sending PTP packets to host */
9245 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
9246 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x0);
9248 /* Reset PTP event detection rules */
9249 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
9250 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7FF);
9251 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
9252 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFF);
9253 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
9254 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x7FF);
9255 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
9256 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3FFF);
9258 /* Disable the PTP feature */
9259 REG_WR(bp
, port
? NIG_REG_P1_PTP_EN
:
9260 NIG_REG_P0_PTP_EN
, 0x0);
9263 /* Called during unload, to stop PTP-related stuff */
9264 static void bnx2x_stop_ptp(struct bnx2x
*bp
)
9266 /* Cancel PTP work queue. Should be done after the Tx queues are
9267 * drained to prevent additional scheduling.
9269 cancel_work_sync(&bp
->ptp_task
);
9271 if (bp
->ptp_tx_skb
) {
9272 dev_kfree_skb_any(bp
->ptp_tx_skb
);
9273 bp
->ptp_tx_skb
= NULL
;
9276 /* Disable PTP in HW */
9277 bnx2x_disable_ptp(bp
);
9279 DP(BNX2X_MSG_PTP
, "PTP stop ended successfully\n");
9282 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
, bool keep_link
)
9284 int port
= BP_PORT(bp
);
9287 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
9290 /* Wait until tx fastpath tasks complete */
9291 for_each_tx_queue(bp
, i
) {
9292 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
9294 for_each_cos_in_tx_queue(fp
, cos
)
9295 rc
= bnx2x_clean_tx_queue(bp
, fp
->txdata_ptr
[cos
]);
9296 #ifdef BNX2X_STOP_ON_ERROR
9302 /* Give HW time to discard old tx messages */
9303 usleep_range(1000, 2000);
9305 /* Clean all ETH MACs */
9306 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_ETH_MAC
,
9309 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
9311 /* Clean up UC list */
9312 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
9315 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9319 if (!CHIP_IS_E1(bp
))
9320 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
9322 /* Set "drop all" (stop Rx).
9323 * We need to take a netif_addr_lock() here in order to prevent
9324 * a race between the completion code and this code.
9326 netif_addr_lock_bh(bp
->dev
);
9327 /* Schedule the rx_mode command */
9328 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
9329 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
9331 bnx2x_set_storm_rx_mode(bp
);
9333 /* Cleanup multicast configuration */
9334 rparam
.mcast_obj
= &bp
->mcast_obj
;
9335 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
9337 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
9339 netif_addr_unlock_bh(bp
->dev
);
9341 bnx2x_iov_chip_cleanup(bp
);
9344 * Send the UNLOAD_REQUEST to the MCP. This will return if
9345 * this function should perform FUNC, PORT or COMMON HW
9348 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
9351 * (assumption: No Attention from MCP at this stage)
9352 * PMF probably in the middle of TX disable/enable transaction
9354 rc
= bnx2x_func_wait_started(bp
);
9356 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9357 #ifdef BNX2X_STOP_ON_ERROR
9362 /* Close multi and leading connections
9363 * Completions for ramrods are collected in a synchronous way
9365 for_each_eth_queue(bp
, i
)
9366 if (bnx2x_stop_queue(bp
, i
))
9367 #ifdef BNX2X_STOP_ON_ERROR
9373 if (CNIC_LOADED(bp
)) {
9374 for_each_cnic_queue(bp
, i
)
9375 if (bnx2x_stop_queue(bp
, i
))
9376 #ifdef BNX2X_STOP_ON_ERROR
9383 /* If SP settings didn't get completed so far - something
9384 * very wrong has happen.
9386 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
9387 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9389 #ifndef BNX2X_STOP_ON_ERROR
9392 rc
= bnx2x_func_stop(bp
);
9394 BNX2X_ERR("Function stop failed!\n");
9395 #ifdef BNX2X_STOP_ON_ERROR
9400 /* stop_ptp should be after the Tx queues are drained to prevent
9401 * scheduling to the cancelled PTP work queue. It should also be after
9402 * function stop ramrod is sent, since as part of this ramrod FW access
9405 if (bp
->flags
& PTP_SUPPORTED
)
9408 /* Disable HW interrupts, NAPI */
9409 bnx2x_netif_stop(bp
, 1);
9410 /* Delete all NAPI objects */
9411 bnx2x_del_all_napi(bp
);
9412 if (CNIC_LOADED(bp
))
9413 bnx2x_del_all_napi_cnic(bp
);
9418 /* Reset the chip */
9419 rc
= bnx2x_reset_hw(bp
, reset_code
);
9421 BNX2X_ERR("HW_RESET failed\n");
9423 /* Report UNLOAD_DONE to MCP */
9424 bnx2x_send_unload_done(bp
, keep_link
);
9427 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
9431 DP(NETIF_MSG_IFDOWN
, "Disabling \"close the gates\"\n");
9433 if (CHIP_IS_E1(bp
)) {
9434 int port
= BP_PORT(bp
);
9435 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
9436 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
9438 val
= REG_RD(bp
, addr
);
9440 REG_WR(bp
, addr
, val
);
9442 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
9443 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
9444 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
9445 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
9449 /* Close gates #2, #3 and #4: */
9450 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
9454 /* Gates #2 and #4a are closed/opened for "not E1" only */
9455 if (!CHIP_IS_E1(bp
)) {
9457 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
9459 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
9463 if (CHIP_IS_E1x(bp
)) {
9464 /* Prevent interrupts from HC on both ports */
9465 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
9466 REG_WR(bp
, HC_REG_CONFIG_1
,
9467 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
9468 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
9470 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
9471 REG_WR(bp
, HC_REG_CONFIG_0
,
9472 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
9473 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
9475 /* Prevent incoming interrupts in IGU */
9476 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
9478 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
9480 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
9481 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
9484 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "%s gates #2, #3 and #4\n",
9485 close
? "closing" : "opening");
9489 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9491 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
9493 /* Do some magic... */
9494 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
9495 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
9496 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
9500 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9502 * @bp: driver handle
9503 * @magic_val: old value of the `magic' bit.
9505 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
9507 /* Restore the `magic' bit value... */
9508 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
9509 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
9510 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
9514 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9516 * @bp: driver handle
9517 * @magic_val: old value of 'magic' bit.
9519 * Takes care of CLP configurations.
9521 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
9524 u32 validity_offset
;
9526 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "Starting\n");
9528 /* Set `magic' bit in order to save MF config */
9529 if (!CHIP_IS_E1(bp
))
9530 bnx2x_clp_reset_prep(bp
, magic_val
);
9532 /* Get shmem offset */
9533 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
9535 offsetof(struct shmem_region
, validity_map
[BP_PORT(bp
)]);
9537 /* Clear validity map flags */
9539 REG_WR(bp
, shmem
+ validity_offset
, 0);
9542 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9543 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9546 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9548 * @bp: driver handle
9550 static void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
9552 /* special handling for emulation and FPGA,
9553 wait 10 times longer */
9554 if (CHIP_REV_IS_SLOW(bp
))
9555 msleep(MCP_ONE_TIMEOUT
*10);
9557 msleep(MCP_ONE_TIMEOUT
);
9561 * initializes bp->common.shmem_base and waits for validity signature to appear
9563 static int bnx2x_init_shmem(struct bnx2x
*bp
)
9569 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
9570 if (bp
->common
.shmem_base
) {
9571 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
9572 if (val
& SHR_MEM_VALIDITY_MB
)
9576 bnx2x_mcp_wait_one(bp
);
9578 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
9580 BNX2X_ERR("BAD MCP validity signature\n");
9585 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
9587 int rc
= bnx2x_init_shmem(bp
);
9589 /* Restore the `magic' bit value */
9590 if (!CHIP_IS_E1(bp
))
9591 bnx2x_clp_reset_done(bp
, magic_val
);
9596 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
9598 if (!CHIP_IS_E1(bp
)) {
9599 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
9600 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
9606 * Reset the whole chip except for:
9608 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9611 * - MISC (including AEU)
9615 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
9617 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
9618 u32 global_bits2
, stay_reset2
;
9621 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9622 * (per chip) blocks.
9625 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
9626 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
9628 /* Don't reset the following blocks.
9629 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9630 * reset, as in 4 port device they might still be owned
9631 * by the MCP (there is only one leader per path).
9634 MISC_REGISTERS_RESET_REG_1_RST_HC
|
9635 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
9636 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
9639 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
9640 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
9641 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
9642 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
9643 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
9644 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
9645 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
9646 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
9647 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
9648 MISC_REGISTERS_RESET_REG_2_PGLC
|
9649 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
9650 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
9651 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
9652 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
9653 MISC_REGISTERS_RESET_REG_2_UMAC0
|
9654 MISC_REGISTERS_RESET_REG_2_UMAC1
;
9657 * Keep the following blocks in reset:
9658 * - all xxMACs are handled by the bnx2x_link code.
9661 MISC_REGISTERS_RESET_REG_2_XMAC
|
9662 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
9664 /* Full reset masks according to the chip */
9665 reset_mask1
= 0xffffffff;
9668 reset_mask2
= 0xffff;
9669 else if (CHIP_IS_E1H(bp
))
9670 reset_mask2
= 0x1ffff;
9671 else if (CHIP_IS_E2(bp
))
9672 reset_mask2
= 0xfffff;
9673 else /* CHIP_IS_E3 */
9674 reset_mask2
= 0x3ffffff;
9676 /* Don't reset global blocks unless we need to */
9678 reset_mask2
&= ~global_bits2
;
9681 * In case of attention in the QM, we need to reset PXP
9682 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9683 * because otherwise QM reset would release 'close the gates' shortly
9684 * before resetting the PXP, then the PSWRQ would send a write
9685 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9686 * read the payload data from PSWWR, but PSWWR would not
9687 * respond. The write queue in PGLUE would stuck, dmae commands
9688 * would not return. Therefore it's important to reset the second
9689 * reset register (containing the
9690 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9691 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9694 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
9695 reset_mask2
& (~not_reset_mask2
));
9697 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
9698 reset_mask1
& (~not_reset_mask1
));
9703 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
9704 reset_mask2
& (~stay_reset2
));
9709 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
9714 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9715 * It should get cleared in no more than 1s.
9717 * @bp: driver handle
9719 * It should get cleared in no more than 1s. Returns 0 if
9720 * pending writes bit gets cleared.
9722 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
9728 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
9733 usleep_range(1000, 2000);
9734 } while (cnt
-- > 0);
9737 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9745 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
9749 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
9752 /* Empty the Tetris buffer, wait for 1s */
9754 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
9755 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
9756 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
9757 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
9758 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
9760 tags_63_32
= REG_RD(bp
, PGLUE_B_REG_TAGS_63_32
);
9762 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
9763 ((port_is_idle_0
& 0x1) == 0x1) &&
9764 ((port_is_idle_1
& 0x1) == 0x1) &&
9765 (pgl_exp_rom2
== 0xffffffff) &&
9766 (!CHIP_IS_E3(bp
) || (tags_63_32
== 0xffffffff)))
9768 usleep_range(1000, 2000);
9769 } while (cnt
-- > 0);
9772 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9773 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9774 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
9781 /* Close gates #2, #3 and #4 */
9782 bnx2x_set_234_gates(bp
, true);
9784 /* Poll for IGU VQs for 57712 and newer chips */
9785 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
9788 /* TBD: Indicate that "process kill" is in progress to MCP */
9790 /* Clear "unprepared" bit */
9791 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
9794 /* Make sure all is written to the chip before the reset */
9797 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9798 * PSWHST, GRC and PSWRD Tetris buffer.
9800 usleep_range(1000, 2000);
9802 /* Prepare to chip reset: */
9805 bnx2x_reset_mcp_prep(bp
, &val
);
9811 /* reset the chip */
9812 bnx2x_process_kill_chip_reset(bp
, global
);
9815 /* clear errors in PGB */
9816 if (!CHIP_IS_E1x(bp
))
9817 REG_WR(bp
, PGLUE_B_REG_LATCHED_ERRORS_CLR
, 0x7f);
9819 /* Recover after reset: */
9821 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
9824 /* TBD: Add resetting the NO_MCP mode DB here */
9826 /* Open the gates #2, #3 and #4 */
9827 bnx2x_set_234_gates(bp
, false);
9829 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9830 * reset state, re-enable attentions. */
9835 static int bnx2x_leader_reset(struct bnx2x
*bp
)
9838 bool global
= bnx2x_reset_is_global(bp
);
9841 /* if not going to reset MCP - load "fake" driver to reset HW while
9842 * driver is owner of the HW
9844 if (!global
&& !BP_NOMCP(bp
)) {
9845 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
,
9846 DRV_MSG_CODE_LOAD_REQ_WITH_LFA
);
9848 BNX2X_ERR("MCP response failure, aborting\n");
9850 goto exit_leader_reset
;
9852 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
9853 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
9854 BNX2X_ERR("MCP unexpected resp, aborting\n");
9856 goto exit_leader_reset2
;
9858 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
9860 BNX2X_ERR("MCP response failure, aborting\n");
9862 goto exit_leader_reset2
;
9866 /* Try to recover after the failure */
9867 if (bnx2x_process_kill(bp
, global
)) {
9868 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9871 goto exit_leader_reset2
;
9875 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9878 bnx2x_set_reset_done(bp
);
9880 bnx2x_clear_reset_global(bp
);
9883 /* unload "fake driver" if it was loaded */
9884 if (!global
&& !BP_NOMCP(bp
)) {
9885 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
9886 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
9890 bnx2x_release_leader_lock(bp
);
9895 static void bnx2x_recovery_failed(struct bnx2x
*bp
)
9897 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
9899 /* Disconnect this device */
9900 netif_device_detach(bp
->dev
);
9903 * Block ifup for all function on this engine until "process kill"
9906 bnx2x_set_reset_in_progress(bp
);
9908 /* Shut down the power */
9909 bnx2x_set_power_state(bp
, PCI_D3hot
);
9911 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
9917 * Assumption: runs under rtnl lock. This together with the fact
9918 * that it's called only from bnx2x_sp_rtnl() ensure that it
9919 * will never be called when netif_running(bp->dev) is false.
9921 static void bnx2x_parity_recover(struct bnx2x
*bp
)
9923 bool global
= false;
9924 u32 error_recovered
, error_unrecovered
;
9927 DP(NETIF_MSG_HW
, "Handling parity\n");
9929 switch (bp
->recovery_state
) {
9930 case BNX2X_RECOVERY_INIT
:
9931 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
9932 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
9933 WARN_ON(!is_parity
);
9935 /* Try to get a LEADER_LOCK HW lock */
9936 if (bnx2x_trylock_leader_lock(bp
)) {
9937 bnx2x_set_reset_in_progress(bp
);
9939 * Check if there is a global attention and if
9940 * there was a global attention, set the global
9945 bnx2x_set_reset_global(bp
);
9950 /* Stop the driver */
9951 /* If interface has been removed - break */
9952 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
, false))
9955 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
9957 /* Ensure "is_leader", MCP command sequence and
9958 * "recovery_state" update values are seen on other
9964 case BNX2X_RECOVERY_WAIT
:
9965 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
9966 if (bp
->is_leader
) {
9967 int other_engine
= BP_PATH(bp
) ? 0 : 1;
9968 bool other_load_status
=
9969 bnx2x_get_load_status(bp
, other_engine
);
9971 bnx2x_get_load_status(bp
, BP_PATH(bp
));
9972 global
= bnx2x_reset_is_global(bp
);
9975 * In case of a parity in a global block, let
9976 * the first leader that performs a
9977 * leader_reset() reset the global blocks in
9978 * order to clear global attentions. Otherwise
9979 * the gates will remain closed for that
9983 (global
&& other_load_status
)) {
9984 /* Wait until all other functions get
9987 schedule_delayed_work(&bp
->sp_rtnl_task
,
9991 /* If all other functions got down -
9992 * try to bring the chip back to
9993 * normal. In any case it's an exit
9994 * point for a leader.
9996 if (bnx2x_leader_reset(bp
)) {
9997 bnx2x_recovery_failed(bp
);
10001 /* If we are here, means that the
10002 * leader has succeeded and doesn't
10003 * want to be a leader any more. Try
10004 * to continue as a none-leader.
10008 } else { /* non-leader */
10009 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
10010 /* Try to get a LEADER_LOCK HW lock as
10011 * long as a former leader may have
10012 * been unloaded by the user or
10013 * released a leadership by another
10016 if (bnx2x_trylock_leader_lock(bp
)) {
10017 /* I'm a leader now! Restart a
10024 schedule_delayed_work(&bp
->sp_rtnl_task
,
10030 * If there was a global attention, wait
10031 * for it to be cleared.
10033 if (bnx2x_reset_is_global(bp
)) {
10034 schedule_delayed_work(
10041 bp
->eth_stats
.recoverable_error
;
10042 error_unrecovered
=
10043 bp
->eth_stats
.unrecoverable_error
;
10044 bp
->recovery_state
=
10045 BNX2X_RECOVERY_NIC_LOADING
;
10046 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
10047 error_unrecovered
++;
10048 netdev_err(bp
->dev
,
10049 "Recovery failed. Power cycle needed\n");
10050 /* Disconnect this device */
10051 netif_device_detach(bp
->dev
);
10052 /* Shut down the power */
10053 bnx2x_set_power_state(
10057 bp
->recovery_state
=
10058 BNX2X_RECOVERY_DONE
;
10062 bp
->eth_stats
.recoverable_error
=
10064 bp
->eth_stats
.unrecoverable_error
=
10076 static int bnx2x_udp_port_update(struct bnx2x
*bp
)
10078 struct bnx2x_func_switch_update_params
*switch_update_params
;
10079 struct bnx2x_func_state_params func_params
= {NULL
};
10080 struct bnx2x_udp_tunnel
*udp_tunnel
;
10081 u16 vxlan_port
= 0, geneve_port
= 0;
10084 switch_update_params
= &func_params
.params
.switch_update
;
10086 /* Prepare parameters for function state transitions */
10087 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
10088 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
10090 func_params
.f_obj
= &bp
->func_obj
;
10091 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
10093 /* Function parameters */
10094 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG
,
10095 &switch_update_params
->changes
);
10097 if (bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
].count
) {
10098 udp_tunnel
= &bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
];
10099 geneve_port
= udp_tunnel
->dst_port
;
10100 switch_update_params
->geneve_dst_port
= geneve_port
;
10103 if (bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
].count
) {
10104 udp_tunnel
= &bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
];
10105 vxlan_port
= udp_tunnel
->dst_port
;
10106 switch_update_params
->vxlan_dst_port
= vxlan_port
;
10109 /* Re-enable inner-rss for the offloaded UDP tunnels */
10110 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS
,
10111 &switch_update_params
->changes
);
10113 rc
= bnx2x_func_state_change(bp
, &func_params
);
10115 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10116 vxlan_port
, geneve_port
, rc
);
10119 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10120 vxlan_port
, geneve_port
);
10125 static void __bnx2x_add_udp_port(struct bnx2x
*bp
, u16 port
,
10126 enum bnx2x_udp_port_type type
)
10128 struct bnx2x_udp_tunnel
*udp_port
= &bp
->udp_tunnel_ports
[type
];
10130 if (!netif_running(bp
->dev
) || !IS_PF(bp
))
10133 if (udp_port
->count
&& udp_port
->dst_port
== port
) {
10138 if (udp_port
->count
) {
10140 "UDP tunnel [%d] - destination port limit reached\n",
10145 udp_port
->dst_port
= port
;
10146 udp_port
->count
= 1;
10147 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_CHANGE_UDP_PORT
, 0);
10150 static void __bnx2x_del_udp_port(struct bnx2x
*bp
, u16 port
,
10151 enum bnx2x_udp_port_type type
)
10153 struct bnx2x_udp_tunnel
*udp_port
= &bp
->udp_tunnel_ports
[type
];
10158 if (!udp_port
->count
|| udp_port
->dst_port
!= port
) {
10159 DP(BNX2X_MSG_SP
, "Invalid UDP tunnel [%d] port\n",
10164 /* Remove reference, and make certain it's no longer in use */
10166 if (udp_port
->count
)
10168 udp_port
->dst_port
= 0;
10170 if (netif_running(bp
->dev
))
10171 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_CHANGE_UDP_PORT
, 0);
10173 DP(BNX2X_MSG_SP
, "Deleted UDP tunnel [%d] port %d\n",
10177 static void bnx2x_udp_tunnel_add(struct net_device
*netdev
,
10178 struct udp_tunnel_info
*ti
)
10180 struct bnx2x
*bp
= netdev_priv(netdev
);
10181 u16 t_port
= ntohs(ti
->port
);
10183 switch (ti
->type
) {
10184 case UDP_TUNNEL_TYPE_VXLAN
:
10185 __bnx2x_add_udp_port(bp
, t_port
, BNX2X_UDP_PORT_VXLAN
);
10187 case UDP_TUNNEL_TYPE_GENEVE
:
10188 __bnx2x_add_udp_port(bp
, t_port
, BNX2X_UDP_PORT_GENEVE
);
10195 static void bnx2x_udp_tunnel_del(struct net_device
*netdev
,
10196 struct udp_tunnel_info
*ti
)
10198 struct bnx2x
*bp
= netdev_priv(netdev
);
10199 u16 t_port
= ntohs(ti
->port
);
10201 switch (ti
->type
) {
10202 case UDP_TUNNEL_TYPE_VXLAN
:
10203 __bnx2x_del_udp_port(bp
, t_port
, BNX2X_UDP_PORT_VXLAN
);
10205 case UDP_TUNNEL_TYPE_GENEVE
:
10206 __bnx2x_del_udp_port(bp
, t_port
, BNX2X_UDP_PORT_GENEVE
);
10213 static int bnx2x_close(struct net_device
*dev
);
10215 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10216 * scheduled on a general queue in order to prevent a dead lock.
10218 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
10220 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
10224 if (!netif_running(bp
->dev
)) {
10229 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
10230 #ifdef BNX2X_STOP_ON_ERROR
10231 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10232 "you will need to reboot when done\n");
10233 goto sp_rtnl_not_reset
;
10236 * Clear all pending SP commands as we are going to reset the
10239 bp
->sp_rtnl_state
= 0;
10242 bnx2x_parity_recover(bp
);
10248 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
10249 #ifdef BNX2X_STOP_ON_ERROR
10250 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10251 "you will need to reboot when done\n");
10252 goto sp_rtnl_not_reset
;
10256 * Clear all pending SP commands as we are going to reset the
10259 bp
->sp_rtnl_state
= 0;
10262 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
10263 bnx2x_nic_load(bp
, LOAD_NORMAL
);
10268 #ifdef BNX2X_STOP_ON_ERROR
10271 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
10272 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
10273 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
, &bp
->sp_rtnl_state
))
10274 bnx2x_after_function_update(bp
);
10276 * in case of fan failure we need to reset id if the "stop on error"
10277 * debug flag is set, since we trying to prevent permanent overheating
10280 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
10281 DP(NETIF_MSG_HW
, "fan failure detected. Unloading driver\n");
10282 netif_device_detach(bp
->dev
);
10283 bnx2x_close(bp
->dev
);
10288 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST
, &bp
->sp_rtnl_state
)) {
10290 "sending set mcast vf pf channel message from rtnl sp-task\n");
10291 bnx2x_vfpf_set_mcast(bp
->dev
);
10293 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN
,
10294 &bp
->sp_rtnl_state
)){
10295 if (!test_bit(__LINK_STATE_NOCARRIER
, &bp
->dev
->state
)) {
10296 bnx2x_tx_disable(bp
);
10297 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10301 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE
, &bp
->sp_rtnl_state
)) {
10302 DP(BNX2X_MSG_SP
, "Handling Rx Mode setting\n");
10303 bnx2x_set_rx_mode_inner(bp
);
10306 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN
,
10307 &bp
->sp_rtnl_state
))
10308 bnx2x_pf_set_vfs_vlan(bp
);
10310 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP
, &bp
->sp_rtnl_state
)) {
10311 bnx2x_dcbx_stop_hw_tx(bp
);
10312 bnx2x_dcbx_resume_hw_tx(bp
);
10315 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION
,
10316 &bp
->sp_rtnl_state
))
10317 bnx2x_update_mng_version(bp
);
10319 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT
,
10320 &bp
->sp_rtnl_state
)) {
10321 if (bnx2x_udp_port_update(bp
)) {
10322 /* On error, forget configuration */
10323 memset(bp
->udp_tunnel_ports
, 0,
10324 sizeof(struct bnx2x_udp_tunnel
) *
10325 BNX2X_UDP_PORT_MAX
);
10327 /* Since we don't store additional port information,
10328 * if no ports are configured for any feature ask for
10329 * information about currently configured ports.
10331 if (!bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
].count
&&
10332 !bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
].count
)
10333 udp_tunnel_get_rx_info(bp
->dev
);
10337 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10338 * can be called from other contexts as well)
10342 /* enable SR-IOV if applicable */
10343 if (IS_SRIOV(bp
) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV
,
10344 &bp
->sp_rtnl_state
)) {
10345 bnx2x_disable_sriov(bp
);
10346 bnx2x_enable_sriov(bp
);
10350 static void bnx2x_period_task(struct work_struct
*work
)
10352 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
10354 if (!netif_running(bp
->dev
))
10355 goto period_task_exit
;
10357 if (CHIP_REV_IS_SLOW(bp
)) {
10358 BNX2X_ERR("period task called on emulation, ignoring\n");
10359 goto period_task_exit
;
10362 bnx2x_acquire_phy_lock(bp
);
10364 * The barrier is needed to ensure the ordering between the writing to
10365 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10366 * the reading here.
10369 if (bp
->port
.pmf
) {
10370 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
10372 /* Re-queue task in 1 sec */
10373 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
10376 bnx2x_release_phy_lock(bp
);
10382 * Init service functions
10385 static u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
10387 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
10388 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
10389 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
10392 static bool bnx2x_prev_unload_close_umac(struct bnx2x
*bp
,
10393 u8 port
, u32 reset_reg
,
10394 struct bnx2x_mac_vals
*vals
)
10396 u32 mask
= MISC_REGISTERS_RESET_REG_2_UMAC0
<< port
;
10399 if (!(mask
& reset_reg
))
10402 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port
);
10403 base_addr
= port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
10404 vals
->umac_addr
[port
] = base_addr
+ UMAC_REG_COMMAND_CONFIG
;
10405 vals
->umac_val
[port
] = REG_RD(bp
, vals
->umac_addr
[port
]);
10406 REG_WR(bp
, vals
->umac_addr
[port
], 0);
10411 static void bnx2x_prev_unload_close_mac(struct bnx2x
*bp
,
10412 struct bnx2x_mac_vals
*vals
)
10414 u32 val
, base_addr
, offset
, mask
, reset_reg
;
10415 bool mac_stopped
= false;
10416 u8 port
= BP_PORT(bp
);
10418 /* reset addresses as they also mark which values were changed */
10419 memset(vals
, 0, sizeof(*vals
));
10421 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_2
);
10423 if (!CHIP_IS_E3(bp
)) {
10424 val
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
10425 mask
= MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
;
10426 if ((mask
& reset_reg
) && val
) {
10428 BNX2X_DEV_INFO("Disable bmac Rx\n");
10429 base_addr
= BP_PORT(bp
) ? NIG_REG_INGRESS_BMAC1_MEM
10430 : NIG_REG_INGRESS_BMAC0_MEM
;
10431 offset
= CHIP_IS_E2(bp
) ? BIGMAC2_REGISTER_BMAC_CONTROL
10432 : BIGMAC_REGISTER_BMAC_CONTROL
;
10435 * use rd/wr since we cannot use dmae. This is safe
10436 * since MCP won't access the bus due to the request
10437 * to unload, and no function on the path can be
10438 * loaded at this time.
10440 wb_data
[0] = REG_RD(bp
, base_addr
+ offset
);
10441 wb_data
[1] = REG_RD(bp
, base_addr
+ offset
+ 0x4);
10442 vals
->bmac_addr
= base_addr
+ offset
;
10443 vals
->bmac_val
[0] = wb_data
[0];
10444 vals
->bmac_val
[1] = wb_data
[1];
10445 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
10446 REG_WR(bp
, vals
->bmac_addr
, wb_data
[0]);
10447 REG_WR(bp
, vals
->bmac_addr
+ 0x4, wb_data
[1]);
10449 BNX2X_DEV_INFO("Disable emac Rx\n");
10450 vals
->emac_addr
= NIG_REG_NIG_EMAC0_EN
+ BP_PORT(bp
)*4;
10451 vals
->emac_val
= REG_RD(bp
, vals
->emac_addr
);
10452 REG_WR(bp
, vals
->emac_addr
, 0);
10453 mac_stopped
= true;
10455 if (reset_reg
& MISC_REGISTERS_RESET_REG_2_XMAC
) {
10456 BNX2X_DEV_INFO("Disable xmac Rx\n");
10457 base_addr
= BP_PORT(bp
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
10458 val
= REG_RD(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
);
10459 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
10461 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
10463 vals
->xmac_addr
= base_addr
+ XMAC_REG_CTRL
;
10464 vals
->xmac_val
= REG_RD(bp
, vals
->xmac_addr
);
10465 REG_WR(bp
, vals
->xmac_addr
, 0);
10466 mac_stopped
= true;
10469 mac_stopped
|= bnx2x_prev_unload_close_umac(bp
, 0,
10471 mac_stopped
|= bnx2x_prev_unload_close_umac(bp
, 1,
10479 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10480 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10481 0x1848 + ((f) << 4))
10482 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10483 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10484 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10486 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10487 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10488 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10490 static bool bnx2x_prev_is_after_undi(struct bnx2x
*bp
)
10492 /* UNDI marks its presence in DORQ -
10493 * it initializes CID offset for normal bell to 0x7
10495 if (!(REG_RD(bp
, MISC_REG_RESET_REG_1
) &
10496 MISC_REGISTERS_RESET_REG_1_RST_DORQ
))
10499 if (REG_RD(bp
, DORQ_REG_NORM_CID_OFST
) == 0x7) {
10500 BNX2X_DEV_INFO("UNDI previously loaded\n");
10507 static void bnx2x_prev_unload_undi_inc(struct bnx2x
*bp
, u8 inc
)
10512 if (BP_FUNC(bp
) < 2)
10513 addr
= BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp
));
10515 addr
= BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp
) - 2);
10517 tmp_reg
= REG_RD(bp
, addr
);
10518 rcq
= BNX2X_PREV_UNDI_RCQ(tmp_reg
) + inc
;
10519 bd
= BNX2X_PREV_UNDI_BD(tmp_reg
) + inc
;
10521 tmp_reg
= BNX2X_PREV_UNDI_PROD(rcq
, bd
);
10522 REG_WR(bp
, addr
, tmp_reg
);
10524 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10525 BP_PORT(bp
), BP_FUNC(bp
), addr
, bd
, rcq
);
10528 static int bnx2x_prev_mcp_done(struct bnx2x
*bp
)
10530 u32 rc
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
,
10531 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
);
10533 BNX2X_ERR("MCP response failure, aborting\n");
10540 static struct bnx2x_prev_path_list
*
10541 bnx2x_prev_path_get_entry(struct bnx2x
*bp
)
10543 struct bnx2x_prev_path_list
*tmp_list
;
10545 list_for_each_entry(tmp_list
, &bnx2x_prev_list
, list
)
10546 if (PCI_SLOT(bp
->pdev
->devfn
) == tmp_list
->slot
&&
10547 bp
->pdev
->bus
->number
== tmp_list
->bus
&&
10548 BP_PATH(bp
) == tmp_list
->path
)
10554 static int bnx2x_prev_path_mark_eeh(struct bnx2x
*bp
)
10556 struct bnx2x_prev_path_list
*tmp_list
;
10559 rc
= down_interruptible(&bnx2x_prev_sem
);
10561 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10565 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10570 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10574 up(&bnx2x_prev_sem
);
10579 static bool bnx2x_prev_is_path_marked(struct bnx2x
*bp
)
10581 struct bnx2x_prev_path_list
*tmp_list
;
10584 if (down_trylock(&bnx2x_prev_sem
))
10587 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10589 if (tmp_list
->aer
) {
10590 DP(NETIF_MSG_HW
, "Path %d was marked by AER\n",
10594 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10599 up(&bnx2x_prev_sem
);
10604 bool bnx2x_port_after_undi(struct bnx2x
*bp
)
10606 struct bnx2x_prev_path_list
*entry
;
10609 down(&bnx2x_prev_sem
);
10611 entry
= bnx2x_prev_path_get_entry(bp
);
10612 val
= !!(entry
&& (entry
->undi
& (1 << BP_PORT(bp
))));
10614 up(&bnx2x_prev_sem
);
10619 static int bnx2x_prev_mark_path(struct bnx2x
*bp
, bool after_undi
)
10621 struct bnx2x_prev_path_list
*tmp_list
;
10624 rc
= down_interruptible(&bnx2x_prev_sem
);
10626 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10630 /* Check whether the entry for this path already exists */
10631 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10633 if (!tmp_list
->aer
) {
10634 BNX2X_ERR("Re-Marking the path.\n");
10636 DP(NETIF_MSG_HW
, "Removing AER indication from path %d\n",
10640 up(&bnx2x_prev_sem
);
10643 up(&bnx2x_prev_sem
);
10645 /* Create an entry for this path and add it */
10646 tmp_list
= kmalloc(sizeof(struct bnx2x_prev_path_list
), GFP_KERNEL
);
10648 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10652 tmp_list
->bus
= bp
->pdev
->bus
->number
;
10653 tmp_list
->slot
= PCI_SLOT(bp
->pdev
->devfn
);
10654 tmp_list
->path
= BP_PATH(bp
);
10656 tmp_list
->undi
= after_undi
? (1 << BP_PORT(bp
)) : 0;
10658 rc
= down_interruptible(&bnx2x_prev_sem
);
10660 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10663 DP(NETIF_MSG_HW
, "Marked path [%d] - finished previous unload\n",
10665 list_add(&tmp_list
->list
, &bnx2x_prev_list
);
10666 up(&bnx2x_prev_sem
);
10672 static int bnx2x_do_flr(struct bnx2x
*bp
)
10674 struct pci_dev
*dev
= bp
->pdev
;
10676 if (CHIP_IS_E1x(bp
)) {
10677 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10681 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10682 if (bp
->common
.bc_ver
< REQ_BC_VER_4_INITIATE_FLR
) {
10683 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10684 bp
->common
.bc_ver
);
10688 if (!pci_wait_for_pending_transaction(dev
))
10689 dev_err(&dev
->dev
, "transaction is not cleared; proceeding with reset anyway\n");
10691 BNX2X_DEV_INFO("Initiating FLR\n");
10692 bnx2x_fw_command(bp
, DRV_MSG_CODE_INITIATE_FLR
, 0);
10697 static int bnx2x_prev_unload_uncommon(struct bnx2x
*bp
)
10701 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10703 /* Test if previous unload process was already finished for this path */
10704 if (bnx2x_prev_is_path_marked(bp
))
10705 return bnx2x_prev_mcp_done(bp
);
10707 BNX2X_DEV_INFO("Path is unmarked\n");
10709 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10710 if (bnx2x_prev_is_after_undi(bp
))
10713 /* If function has FLR capabilities, and existing FW version matches
10714 * the one required, then FLR will be sufficient to clean any residue
10715 * left by previous driver
10717 rc
= bnx2x_compare_fw_ver(bp
, FW_MSG_CODE_DRV_LOAD_FUNCTION
, false);
10720 /* fw version is good */
10721 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10722 rc
= bnx2x_do_flr(bp
);
10726 /* FLR was performed */
10727 BNX2X_DEV_INFO("FLR successful\n");
10731 BNX2X_DEV_INFO("Could not FLR\n");
10734 /* Close the MCP request, return failure*/
10735 rc
= bnx2x_prev_mcp_done(bp
);
10737 rc
= BNX2X_PREV_WAIT_NEEDED
;
10742 static int bnx2x_prev_unload_common(struct bnx2x
*bp
)
10744 u32 reset_reg
, tmp_reg
= 0, rc
;
10745 bool prev_undi
= false;
10746 struct bnx2x_mac_vals mac_vals
;
10748 /* It is possible a previous function received 'common' answer,
10749 * but hasn't loaded yet, therefore creating a scenario of
10750 * multiple functions receiving 'common' on the same path.
10752 BNX2X_DEV_INFO("Common unload Flow\n");
10754 memset(&mac_vals
, 0, sizeof(mac_vals
));
10756 if (bnx2x_prev_is_path_marked(bp
))
10757 return bnx2x_prev_mcp_done(bp
);
10759 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_1
);
10761 /* Reset should be performed after BRB is emptied */
10762 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_BRB1
) {
10763 u32 timer_count
= 1000;
10765 /* Close the MAC Rx to prevent BRB from filling up */
10766 bnx2x_prev_unload_close_mac(bp
, &mac_vals
);
10768 /* close LLH filters for both ports towards the BRB */
10769 bnx2x_set_rx_filter(&bp
->link_params
, 0);
10770 bp
->link_params
.port
^= 1;
10771 bnx2x_set_rx_filter(&bp
->link_params
, 0);
10772 bp
->link_params
.port
^= 1;
10774 /* Check if the UNDI driver was previously loaded */
10775 if (bnx2x_prev_is_after_undi(bp
)) {
10777 /* clear the UNDI indication */
10778 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
10779 /* clear possible idle check errors */
10780 REG_RD(bp
, NIG_REG_NIG_INT_STS_CLR_0
);
10782 if (!CHIP_IS_E1x(bp
))
10783 /* block FW from writing to host */
10784 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
10786 /* wait until BRB is empty */
10787 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
10788 while (timer_count
) {
10789 u32 prev_brb
= tmp_reg
;
10791 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
10795 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg
);
10797 /* reset timer as long as BRB actually gets emptied */
10798 if (prev_brb
> tmp_reg
)
10799 timer_count
= 1000;
10803 /* If UNDI resides in memory, manually increment it */
10805 bnx2x_prev_unload_undi_inc(bp
, 1);
10811 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10814 /* No packets are in the pipeline, path is ready for reset */
10815 bnx2x_reset_common(bp
);
10817 if (mac_vals
.xmac_addr
)
10818 REG_WR(bp
, mac_vals
.xmac_addr
, mac_vals
.xmac_val
);
10819 if (mac_vals
.umac_addr
[0])
10820 REG_WR(bp
, mac_vals
.umac_addr
[0], mac_vals
.umac_val
[0]);
10821 if (mac_vals
.umac_addr
[1])
10822 REG_WR(bp
, mac_vals
.umac_addr
[1], mac_vals
.umac_val
[1]);
10823 if (mac_vals
.emac_addr
)
10824 REG_WR(bp
, mac_vals
.emac_addr
, mac_vals
.emac_val
);
10825 if (mac_vals
.bmac_addr
) {
10826 REG_WR(bp
, mac_vals
.bmac_addr
, mac_vals
.bmac_val
[0]);
10827 REG_WR(bp
, mac_vals
.bmac_addr
+ 4, mac_vals
.bmac_val
[1]);
10830 rc
= bnx2x_prev_mark_path(bp
, prev_undi
);
10832 bnx2x_prev_mcp_done(bp
);
10836 return bnx2x_prev_mcp_done(bp
);
10839 static int bnx2x_prev_unload(struct bnx2x
*bp
)
10841 int time_counter
= 10;
10842 u32 rc
, fw
, hw_lock_reg
, hw_lock_val
;
10843 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10845 /* clear hw from errors which may have resulted from an interrupted
10846 * dmae transaction.
10848 bnx2x_clean_pglue_errors(bp
);
10850 /* Release previously held locks */
10851 hw_lock_reg
= (BP_FUNC(bp
) <= 5) ?
10852 (MISC_REG_DRIVER_CONTROL_1
+ BP_FUNC(bp
) * 8) :
10853 (MISC_REG_DRIVER_CONTROL_7
+ (BP_FUNC(bp
) - 6) * 8);
10855 hw_lock_val
= REG_RD(bp
, hw_lock_reg
);
10857 if (hw_lock_val
& HW_LOCK_RESOURCE_NVRAM
) {
10858 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10859 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
10860 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< BP_PORT(bp
)));
10863 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10864 REG_WR(bp
, hw_lock_reg
, 0xffffffff);
10866 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10868 if (MCPR_ACCESS_LOCK_LOCK
& REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
)) {
10869 BNX2X_DEV_INFO("Release previously held alr\n");
10870 bnx2x_release_alr(bp
);
10875 /* Lock MCP using an unload request */
10876 fw
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
, 0);
10878 BNX2X_ERR("MCP response failure, aborting\n");
10883 rc
= down_interruptible(&bnx2x_prev_sem
);
10885 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10888 /* If Path is marked by EEH, ignore unload status */
10889 aer
= !!(bnx2x_prev_path_get_entry(bp
) &&
10890 bnx2x_prev_path_get_entry(bp
)->aer
);
10891 up(&bnx2x_prev_sem
);
10894 if (fw
== FW_MSG_CODE_DRV_UNLOAD_COMMON
|| aer
) {
10895 rc
= bnx2x_prev_unload_common(bp
);
10899 /* non-common reply from MCP might require looping */
10900 rc
= bnx2x_prev_unload_uncommon(bp
);
10901 if (rc
!= BNX2X_PREV_WAIT_NEEDED
)
10905 } while (--time_counter
);
10907 if (!time_counter
|| rc
) {
10908 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10909 rc
= -EPROBE_DEFER
;
10912 /* Mark function if its port was used to boot from SAN */
10913 if (bnx2x_port_after_undi(bp
))
10914 bp
->link_params
.feature_config_flags
|=
10915 FEATURE_CONFIG_BOOT_FROM_SAN
;
10917 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc
);
10922 static void bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
10924 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
10927 /* Get the chip revision id and number. */
10928 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10929 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
10930 id
= ((val
& 0xffff) << 16);
10931 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
10932 id
|= ((val
& 0xf) << 12);
10934 /* Metal is read from PCI regs, but we can't access >=0x400 from
10935 * the configuration space (so we need to reg_rd)
10937 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCI_ID_VAL3
);
10938 id
|= (((val
>> 24) & 0xf) << 4);
10939 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
10941 bp
->common
.chip_id
= id
;
10943 /* force 57811 according to MISC register */
10944 if (REG_RD(bp
, MISC_REG_CHIP_TYPE
) & MISC_REG_CHIP_TYPE_57811_MASK
) {
10945 if (CHIP_IS_57810(bp
))
10946 bp
->common
.chip_id
= (CHIP_NUM_57811
<< 16) |
10947 (bp
->common
.chip_id
& 0x0000FFFF);
10948 else if (CHIP_IS_57810_MF(bp
))
10949 bp
->common
.chip_id
= (CHIP_NUM_57811_MF
<< 16) |
10950 (bp
->common
.chip_id
& 0x0000FFFF);
10951 bp
->common
.chip_id
|= 0x1;
10954 /* Set doorbell size */
10955 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
10957 if (!CHIP_IS_E1x(bp
)) {
10958 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
10959 if ((val
& 1) == 0)
10960 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
10962 val
= (val
>> 1) & 1;
10963 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
10965 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
10968 if (CHIP_MODE_IS_4_PORT(bp
))
10969 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
10971 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
10973 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
10974 bp
->pfid
= bp
->pf_num
; /* 0..7 */
10977 BNX2X_DEV_INFO("pf_id: %x", bp
->pfid
);
10979 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
10980 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
10982 val
= (REG_RD(bp
, 0x2874) & 0x55);
10983 if ((bp
->common
.chip_id
& 0x1) ||
10984 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
10985 bp
->flags
|= ONE_PORT_FLAG
;
10986 BNX2X_DEV_INFO("single port device\n");
10989 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
10990 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
10991 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
10992 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10993 bp
->common
.flash_size
, bp
->common
.flash_size
);
10995 bnx2x_init_shmem(bp
);
10997 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
10998 MISC_REG_GENERIC_CR_1
:
10999 MISC_REG_GENERIC_CR_0
));
11001 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
11002 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
11003 if (SHMEM2_RD(bp
, size
) >
11004 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
11005 bp
->link_params
.lfa_base
=
11006 REG_RD(bp
, bp
->common
.shmem2_base
+
11007 (u32
)offsetof(struct shmem2_region
,
11008 lfa_host_addr
[BP_PORT(bp
)]));
11010 bp
->link_params
.lfa_base
= 0;
11011 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11012 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
11014 if (!bp
->common
.shmem_base
) {
11015 BNX2X_DEV_INFO("MCP not active\n");
11016 bp
->flags
|= NO_MCP_FLAG
;
11020 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
11021 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
11023 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
11024 SHARED_HW_CFG_LED_MODE_MASK
) >>
11025 SHARED_HW_CFG_LED_MODE_SHIFT
);
11027 bp
->link_params
.feature_config_flags
= 0;
11028 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
11029 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
11030 bp
->link_params
.feature_config_flags
|=
11031 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
11033 bp
->link_params
.feature_config_flags
&=
11034 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
11036 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
11037 bp
->common
.bc_ver
= val
;
11038 BNX2X_DEV_INFO("bc_ver %X\n", val
);
11039 if (val
< BNX2X_BC_VER
) {
11040 /* for now only warn
11041 * later we might need to enforce this */
11042 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11043 BNX2X_BC_VER
, val
);
11045 bp
->link_params
.feature_config_flags
|=
11046 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
11047 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
11049 bp
->link_params
.feature_config_flags
|=
11050 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
11051 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
11052 bp
->link_params
.feature_config_flags
|=
11053 (val
>= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED
) ?
11054 FEATURE_CONFIG_BC_SUPPORTS_AFEX
: 0;
11055 bp
->link_params
.feature_config_flags
|=
11056 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
11057 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
11059 bp
->link_params
.feature_config_flags
|=
11060 (val
>= REQ_BC_VER_4_MT_SUPPORTED
) ?
11061 FEATURE_CONFIG_MT_SUPPORT
: 0;
11063 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
11064 BC_SUPPORTS_PFC_STATS
: 0;
11066 bp
->flags
|= (val
>= REQ_BC_VER_4_FCOE_FEATURES
) ?
11067 BC_SUPPORTS_FCOE_FEATURES
: 0;
11069 bp
->flags
|= (val
>= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF
) ?
11070 BC_SUPPORTS_DCBX_MSG_NON_PMF
: 0;
11072 bp
->flags
|= (val
>= REQ_BC_VER_4_RMMOD_CMD
) ?
11073 BC_SUPPORTS_RMMOD_CMD
: 0;
11075 boot_mode
= SHMEM_RD(bp
,
11076 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
11077 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
11078 switch (boot_mode
) {
11079 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
11080 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
11082 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
11083 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
11085 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
11086 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
11088 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
11089 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
11093 pci_read_config_word(bp
->pdev
, bp
->pdev
->pm_cap
+ PCI_PM_PMC
, &pmc
);
11094 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
11096 BNX2X_DEV_INFO("%sWoL capable\n",
11097 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
11099 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
11100 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
11101 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
11102 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
11104 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
11105 val
, val2
, val3
, val4
);
11108 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11109 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11111 static int bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
11113 int pfid
= BP_FUNC(bp
);
11116 u8 fid
, igu_sb_cnt
= 0;
11118 bp
->igu_base_sb
= 0xff;
11119 if (CHIP_INT_MODE_IS_BC(bp
)) {
11120 int vn
= BP_VN(bp
);
11121 igu_sb_cnt
= bp
->igu_sb_cnt
;
11122 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
11125 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
11126 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
11131 /* IGU in normal mode - read CAM */
11132 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
11134 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
11135 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
11137 fid
= IGU_FID(val
);
11138 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
11139 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
11141 if (IGU_VEC(val
) == 0)
11142 /* default status block */
11143 bp
->igu_dsb_id
= igu_sb_id
;
11145 if (bp
->igu_base_sb
== 0xff)
11146 bp
->igu_base_sb
= igu_sb_id
;
11152 #ifdef CONFIG_PCI_MSI
11153 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11154 * optional that number of CAM entries will not be equal to the value
11155 * advertised in PCI.
11156 * Driver should use the minimal value of both as the actual status
11159 bp
->igu_sb_cnt
= min_t(int, bp
->igu_sb_cnt
, igu_sb_cnt
);
11162 if (igu_sb_cnt
== 0) {
11163 BNX2X_ERR("CAM configuration error\n");
11170 static void bnx2x_link_settings_supported(struct bnx2x
*bp
, u32 switch_cfg
)
11172 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
11174 /* Aggregation of supported attributes of all external phys */
11175 bp
->port
.supported
[0] = 0;
11176 bp
->port
.supported
[1] = 0;
11177 switch (bp
->link_params
.num_phys
) {
11179 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
11183 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
11187 if (bp
->link_params
.multi_phy_config
&
11188 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
11189 bp
->port
.supported
[1] =
11190 bp
->link_params
.phy
[EXT_PHY1
].supported
;
11191 bp
->port
.supported
[0] =
11192 bp
->link_params
.phy
[EXT_PHY2
].supported
;
11194 bp
->port
.supported
[0] =
11195 bp
->link_params
.phy
[EXT_PHY1
].supported
;
11196 bp
->port
.supported
[1] =
11197 bp
->link_params
.phy
[EXT_PHY2
].supported
;
11203 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
11204 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11206 dev_info
.port_hw_config
[port
].external_phy_config
),
11208 dev_info
.port_hw_config
[port
].external_phy_config2
));
11212 if (CHIP_IS_E3(bp
))
11213 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
11215 switch (switch_cfg
) {
11216 case SWITCH_CFG_1G
:
11217 bp
->port
.phy_addr
= REG_RD(
11218 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
11220 case SWITCH_CFG_10G
:
11221 bp
->port
.phy_addr
= REG_RD(
11222 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
11225 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11226 bp
->port
.link_config
[0]);
11230 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
11231 /* mask what we support according to speed_cap_mask per configuration */
11232 for (idx
= 0; idx
< cfg_size
; idx
++) {
11233 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11234 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
11235 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
11237 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11238 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
11239 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
11241 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11242 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
11243 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
11245 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11246 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
11247 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
11249 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11250 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
11251 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
11252 SUPPORTED_1000baseT_Full
);
11254 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11255 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
11256 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
11258 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11259 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
11260 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
11262 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11263 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
))
11264 bp
->port
.supported
[idx
] &= ~SUPPORTED_20000baseKR2_Full
;
11267 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
11268 bp
->port
.supported
[1]);
11271 static void bnx2x_link_settings_requested(struct bnx2x
*bp
)
11273 u32 link_config
, idx
, cfg_size
= 0;
11274 bp
->port
.advertising
[0] = 0;
11275 bp
->port
.advertising
[1] = 0;
11276 switch (bp
->link_params
.num_phys
) {
11285 for (idx
= 0; idx
< cfg_size
; idx
++) {
11286 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
11287 link_config
= bp
->port
.link_config
[idx
];
11288 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
11289 case PORT_FEATURE_LINK_SPEED_AUTO
:
11290 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
11291 bp
->link_params
.req_line_speed
[idx
] =
11293 bp
->port
.advertising
[idx
] |=
11294 bp
->port
.supported
[idx
];
11295 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
11296 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
11297 bp
->port
.advertising
[idx
] |=
11298 (SUPPORTED_100baseT_Half
|
11299 SUPPORTED_100baseT_Full
);
11301 /* force 10G, no AN */
11302 bp
->link_params
.req_line_speed
[idx
] =
11304 bp
->port
.advertising
[idx
] |=
11305 (ADVERTISED_10000baseT_Full
|
11311 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
11312 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
11313 bp
->link_params
.req_line_speed
[idx
] =
11315 bp
->port
.advertising
[idx
] |=
11316 (ADVERTISED_10baseT_Full
|
11319 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11321 bp
->link_params
.speed_cap_mask
[idx
]);
11326 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
11327 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
11328 bp
->link_params
.req_line_speed
[idx
] =
11330 bp
->link_params
.req_duplex
[idx
] =
11332 bp
->port
.advertising
[idx
] |=
11333 (ADVERTISED_10baseT_Half
|
11336 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11338 bp
->link_params
.speed_cap_mask
[idx
]);
11343 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
11344 if (bp
->port
.supported
[idx
] &
11345 SUPPORTED_100baseT_Full
) {
11346 bp
->link_params
.req_line_speed
[idx
] =
11348 bp
->port
.advertising
[idx
] |=
11349 (ADVERTISED_100baseT_Full
|
11352 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11354 bp
->link_params
.speed_cap_mask
[idx
]);
11359 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
11360 if (bp
->port
.supported
[idx
] &
11361 SUPPORTED_100baseT_Half
) {
11362 bp
->link_params
.req_line_speed
[idx
] =
11364 bp
->link_params
.req_duplex
[idx
] =
11366 bp
->port
.advertising
[idx
] |=
11367 (ADVERTISED_100baseT_Half
|
11370 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11372 bp
->link_params
.speed_cap_mask
[idx
]);
11377 case PORT_FEATURE_LINK_SPEED_1G
:
11378 if (bp
->port
.supported
[idx
] &
11379 SUPPORTED_1000baseT_Full
) {
11380 bp
->link_params
.req_line_speed
[idx
] =
11382 bp
->port
.advertising
[idx
] |=
11383 (ADVERTISED_1000baseT_Full
|
11385 } else if (bp
->port
.supported
[idx
] &
11386 SUPPORTED_1000baseKX_Full
) {
11387 bp
->link_params
.req_line_speed
[idx
] =
11389 bp
->port
.advertising
[idx
] |=
11390 ADVERTISED_1000baseKX_Full
;
11392 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11394 bp
->link_params
.speed_cap_mask
[idx
]);
11399 case PORT_FEATURE_LINK_SPEED_2_5G
:
11400 if (bp
->port
.supported
[idx
] &
11401 SUPPORTED_2500baseX_Full
) {
11402 bp
->link_params
.req_line_speed
[idx
] =
11404 bp
->port
.advertising
[idx
] |=
11405 (ADVERTISED_2500baseX_Full
|
11408 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11410 bp
->link_params
.speed_cap_mask
[idx
]);
11415 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
11416 if (bp
->port
.supported
[idx
] &
11417 SUPPORTED_10000baseT_Full
) {
11418 bp
->link_params
.req_line_speed
[idx
] =
11420 bp
->port
.advertising
[idx
] |=
11421 (ADVERTISED_10000baseT_Full
|
11423 } else if (bp
->port
.supported
[idx
] &
11424 SUPPORTED_10000baseKR_Full
) {
11425 bp
->link_params
.req_line_speed
[idx
] =
11427 bp
->port
.advertising
[idx
] |=
11428 (ADVERTISED_10000baseKR_Full
|
11431 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11433 bp
->link_params
.speed_cap_mask
[idx
]);
11437 case PORT_FEATURE_LINK_SPEED_20G
:
11438 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
11442 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11444 bp
->link_params
.req_line_speed
[idx
] =
11446 bp
->port
.advertising
[idx
] =
11447 bp
->port
.supported
[idx
];
11451 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
11452 PORT_FEATURE_FLOW_CONTROL_MASK
);
11453 if (bp
->link_params
.req_flow_ctrl
[idx
] ==
11454 BNX2X_FLOW_CTRL_AUTO
) {
11455 if (!(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
))
11456 bp
->link_params
.req_flow_ctrl
[idx
] =
11457 BNX2X_FLOW_CTRL_NONE
;
11459 bnx2x_set_requested_fc(bp
);
11462 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11463 bp
->link_params
.req_line_speed
[idx
],
11464 bp
->link_params
.req_duplex
[idx
],
11465 bp
->link_params
.req_flow_ctrl
[idx
],
11466 bp
->port
.advertising
[idx
]);
11470 static void bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
11472 __be16 mac_hi_be
= cpu_to_be16(mac_hi
);
11473 __be32 mac_lo_be
= cpu_to_be32(mac_lo
);
11474 memcpy(mac_buf
, &mac_hi_be
, sizeof(mac_hi_be
));
11475 memcpy(mac_buf
+ sizeof(mac_hi_be
), &mac_lo_be
, sizeof(mac_lo_be
));
11478 static void bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
11480 int port
= BP_PORT(bp
);
11482 u32 ext_phy_type
, ext_phy_config
, eee_mode
;
11484 bp
->link_params
.bp
= bp
;
11485 bp
->link_params
.port
= port
;
11487 bp
->link_params
.lane_config
=
11488 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
11490 bp
->link_params
.speed_cap_mask
[0] =
11492 dev_info
.port_hw_config
[port
].speed_capability_mask
) &
11493 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
11494 bp
->link_params
.speed_cap_mask
[1] =
11496 dev_info
.port_hw_config
[port
].speed_capability_mask2
) &
11497 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
11498 bp
->port
.link_config
[0] =
11499 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
11501 bp
->port
.link_config
[1] =
11502 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
11504 bp
->link_params
.multi_phy_config
=
11505 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
11506 /* If the device is capable of WoL, set the default state according
11509 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
11510 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
11511 (config
& PORT_FEATURE_WOL_ENABLED
));
11513 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
11514 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE
&& !IS_MF(bp
))
11515 bp
->flags
|= NO_ISCSI_FLAG
;
11516 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
11517 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI
&& !(IS_MF(bp
)))
11518 bp
->flags
|= NO_FCOE_FLAG
;
11520 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11521 bp
->link_params
.lane_config
,
11522 bp
->link_params
.speed_cap_mask
[0],
11523 bp
->port
.link_config
[0]);
11525 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
11526 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
11527 bnx2x_phy_probe(&bp
->link_params
);
11528 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
11530 bnx2x_link_settings_requested(bp
);
11533 * If connected directly, work with the internal PHY, otherwise, work
11534 * with the external PHY
11538 dev_info
.port_hw_config
[port
].external_phy_config
);
11539 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
11540 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
11541 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
11543 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
11544 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
11546 XGXS_EXT_PHY_ADDR(ext_phy_config
);
11548 /* Configure link feature according to nvram value */
11549 eee_mode
= (((SHMEM_RD(bp
, dev_info
.
11550 port_feature_config
[port
].eee_power_mode
)) &
11551 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
11552 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
11553 if (eee_mode
!= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
) {
11554 bp
->link_params
.eee_mode
= EEE_MODE_ADV_LPI
|
11555 EEE_MODE_ENABLE_LPI
|
11556 EEE_MODE_OUTPUT_TIME
;
11558 bp
->link_params
.eee_mode
= 0;
11562 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
11564 u32 no_flags
= NO_ISCSI_FLAG
;
11565 int port
= BP_PORT(bp
);
11566 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
11567 drv_lic_key
[port
].max_iscsi_conn
);
11569 if (!CNIC_SUPPORT(bp
)) {
11570 bp
->flags
|= no_flags
;
11574 /* Get the number of maximum allowed iSCSI connections */
11575 bp
->cnic_eth_dev
.max_iscsi_conn
=
11576 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
11577 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
11579 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11580 bp
->cnic_eth_dev
.max_iscsi_conn
);
11583 * If maximum allowed number of connections is zero -
11584 * disable the feature.
11586 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
11587 bp
->flags
|= no_flags
;
11590 static void bnx2x_get_ext_wwn_info(struct bnx2x
*bp
, int func
)
11593 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
11594 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_upper
);
11595 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
11596 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_lower
);
11599 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
11600 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_upper
);
11601 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
11602 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_lower
);
11605 static int bnx2x_shared_fcoe_funcs(struct bnx2x
*bp
)
11612 /* iterate over absolute function ids for this path: */
11613 for (fid
= BP_PATH(bp
); fid
< E2_FUNC_MAX
* 2; fid
+= 2) {
11614 if (IS_MF_SD(bp
)) {
11615 u32 cfg
= MF_CFG_RD(bp
,
11616 func_mf_config
[fid
].config
);
11618 if (!(cfg
& FUNC_MF_CFG_FUNC_HIDE
) &&
11619 ((cfg
& FUNC_MF_CFG_PROTOCOL_MASK
) ==
11620 FUNC_MF_CFG_PROTOCOL_FCOE
))
11623 u32 cfg
= MF_CFG_RD(bp
,
11624 func_ext_config
[fid
].
11627 if ((cfg
& MACP_FUNC_CFG_FLAGS_ENABLED
) &&
11628 (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
))
11633 int port
, port_cnt
= CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1;
11635 for (port
= 0; port
< port_cnt
; port
++) {
11636 u32 lic
= SHMEM_RD(bp
,
11637 drv_lic_key
[port
].max_fcoe_conn
) ^
11638 FW_ENCODE_32BIT_PATTERN
;
11647 static void bnx2x_get_fcoe_info(struct bnx2x
*bp
)
11649 int port
= BP_PORT(bp
);
11650 int func
= BP_ABS_FUNC(bp
);
11651 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
11652 drv_lic_key
[port
].max_fcoe_conn
);
11653 u8 num_fcoe_func
= bnx2x_shared_fcoe_funcs(bp
);
11655 if (!CNIC_SUPPORT(bp
)) {
11656 bp
->flags
|= NO_FCOE_FLAG
;
11660 /* Get the number of maximum allowed FCoE connections */
11661 bp
->cnic_eth_dev
.max_fcoe_conn
=
11662 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
11663 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
11665 /* Calculate the number of maximum allowed FCoE tasks */
11666 bp
->cnic_eth_dev
.max_fcoe_exchanges
= MAX_NUM_FCOE_TASKS_PER_ENGINE
;
11668 /* check if FCoE resources must be shared between different functions */
11670 bp
->cnic_eth_dev
.max_fcoe_exchanges
/= num_fcoe_func
;
11672 /* Read the WWN: */
11675 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
11677 dev_info
.port_hw_config
[port
].
11678 fcoe_wwn_port_name_upper
);
11679 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
11681 dev_info
.port_hw_config
[port
].
11682 fcoe_wwn_port_name_lower
);
11685 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
11687 dev_info
.port_hw_config
[port
].
11688 fcoe_wwn_node_name_upper
);
11689 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
11691 dev_info
.port_hw_config
[port
].
11692 fcoe_wwn_node_name_lower
);
11693 } else if (!IS_MF_SD(bp
)) {
11694 /* Read the WWN info only if the FCoE feature is enabled for
11697 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp
))
11698 bnx2x_get_ext_wwn_info(bp
, func
);
11700 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
) && !CHIP_IS_E1x(bp
))
11701 bnx2x_get_ext_wwn_info(bp
, func
);
11704 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
11707 * If maximum allowed number of connections is zero -
11708 * disable the feature.
11710 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
11711 bp
->flags
|= NO_FCOE_FLAG
;
11714 static void bnx2x_get_cnic_info(struct bnx2x
*bp
)
11717 * iSCSI may be dynamically disabled but reading
11718 * info here we will decrease memory usage by driver
11719 * if the feature is disabled for good
11721 bnx2x_get_iscsi_info(bp
);
11722 bnx2x_get_fcoe_info(bp
);
11725 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x
*bp
)
11728 int func
= BP_ABS_FUNC(bp
);
11729 int port
= BP_PORT(bp
);
11730 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
11731 u8
*fip_mac
= bp
->fip_mac
;
11734 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11735 * FCoE MAC then the appropriate feature should be disabled.
11736 * In non SD mode features configuration comes from struct
11739 if (!IS_MF_SD(bp
)) {
11740 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
11741 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
11742 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
11743 iscsi_mac_addr_upper
);
11744 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
11745 iscsi_mac_addr_lower
);
11746 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
11748 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
11750 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11753 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
11754 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
11755 fcoe_mac_addr_upper
);
11756 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
11757 fcoe_mac_addr_lower
);
11758 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
11760 ("Read FCoE L2 MAC: %pM\n", fip_mac
);
11762 bp
->flags
|= NO_FCOE_FLAG
;
11765 bp
->mf_ext_config
= cfg
;
11767 } else { /* SD MODE */
11768 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp
)) {
11769 /* use primary mac as iscsi mac */
11770 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
11772 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11774 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
11775 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)) {
11776 /* use primary mac as fip mac */
11777 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
11778 BNX2X_DEV_INFO("SD FCoE MODE\n");
11780 ("Read FIP MAC: %pM\n", fip_mac
);
11784 /* If this is a storage-only interface, use SAN mac as
11785 * primary MAC. Notice that for SD this is already the case,
11786 * as the SAN mac was copied from the primary MAC.
11788 if (IS_MF_FCOE_AFEX(bp
))
11789 memcpy(bp
->dev
->dev_addr
, fip_mac
, ETH_ALEN
);
11791 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11793 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11795 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
11797 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11798 fcoe_fip_mac_upper
);
11799 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11800 fcoe_fip_mac_lower
);
11801 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
11804 /* Disable iSCSI OOO if MAC configuration is invalid. */
11805 if (!is_valid_ether_addr(iscsi_mac
)) {
11806 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11807 eth_zero_addr(iscsi_mac
);
11810 /* Disable FCoE if MAC configuration is invalid. */
11811 if (!is_valid_ether_addr(fip_mac
)) {
11812 bp
->flags
|= NO_FCOE_FLAG
;
11813 eth_zero_addr(bp
->fip_mac
);
11817 static void bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
11820 int func
= BP_ABS_FUNC(bp
);
11821 int port
= BP_PORT(bp
);
11823 /* Zero primary MAC configuration */
11824 eth_zero_addr(bp
->dev
->dev_addr
);
11826 if (BP_NOMCP(bp
)) {
11827 BNX2X_ERROR("warning: random MAC workaround active\n");
11828 eth_hw_addr_random(bp
->dev
);
11829 } else if (IS_MF(bp
)) {
11830 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11831 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
11832 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
11833 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
11834 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11836 if (CNIC_SUPPORT(bp
))
11837 bnx2x_get_cnic_mac_hwinfo(bp
);
11839 /* in SF read MACs from port configuration */
11840 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11841 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11842 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11844 if (CNIC_SUPPORT(bp
))
11845 bnx2x_get_cnic_mac_hwinfo(bp
);
11848 if (!BP_NOMCP(bp
)) {
11849 /* Read physical port identifier from shmem */
11850 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11851 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11852 bnx2x_set_mac_buf(bp
->phys_port_id
, val
, val2
);
11853 bp
->flags
|= HAS_PHYS_PORT_ID
;
11856 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
11858 if (!is_valid_ether_addr(bp
->dev
->dev_addr
))
11859 dev_err(&bp
->pdev
->dev
,
11860 "bad Ethernet MAC address configuration: %pM\n"
11861 "change it manually before bringing up the appropriate network interface\n",
11862 bp
->dev
->dev_addr
);
11865 static bool bnx2x_get_dropless_info(struct bnx2x
*bp
)
11873 if (IS_MF(bp
) && !CHIP_IS_E1x(bp
)) {
11874 /* Take function: tmp = func */
11875 tmp
= BP_ABS_FUNC(bp
);
11876 cfg
= MF_CFG_RD(bp
, func_ext_config
[tmp
].func_cfg
);
11877 cfg
= !!(cfg
& MACP_FUNC_CFG_PAUSE_ON_HOST_RING
);
11879 /* Take port: tmp = port */
11882 dev_info
.port_hw_config
[tmp
].generic_features
);
11883 cfg
= !!(cfg
& PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED
);
11888 static void validate_set_si_mode(struct bnx2x
*bp
)
11890 u8 func
= BP_ABS_FUNC(bp
);
11893 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11895 /* check for legal mac (upper bytes) */
11896 if (val
!= 0xffff) {
11897 bp
->mf_mode
= MULTI_FUNCTION_SI
;
11898 bp
->mf_config
[BP_VN(bp
)] =
11899 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
11901 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11904 static int bnx2x_get_hwinfo(struct bnx2x
*bp
)
11906 int /*abs*/func
= BP_ABS_FUNC(bp
);
11908 u32 val
= 0, val2
= 0;
11911 /* Validate that chip access is feasible */
11912 if (REG_RD(bp
, MISC_REG_CHIP_NUM
) == 0xffffffff) {
11913 dev_err(&bp
->pdev
->dev
,
11914 "Chip read returns all Fs. Preventing probe from continuing\n");
11918 bnx2x_get_common_hwinfo(bp
);
11921 * initialize IGU parameters
11923 if (CHIP_IS_E1x(bp
)) {
11924 bp
->common
.int_block
= INT_BLOCK_HC
;
11926 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
11927 bp
->igu_base_sb
= 0;
11929 bp
->common
.int_block
= INT_BLOCK_IGU
;
11931 /* do not allow device reset during IGU info processing */
11932 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11934 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
11936 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11939 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11941 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
11942 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
11943 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
11945 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11947 usleep_range(1000, 2000);
11950 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11951 dev_err(&bp
->pdev
->dev
,
11952 "FORCING Normal Mode failed!!!\n");
11953 bnx2x_release_hw_lock(bp
,
11954 HW_LOCK_RESOURCE_RESET
);
11959 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11960 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11961 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
11963 BNX2X_DEV_INFO("IGU Normal Mode\n");
11965 rc
= bnx2x_get_igu_cam_info(bp
);
11966 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11972 * set base FW non-default (fast path) status block id, this value is
11973 * used to initialize the fw_sb_id saved on the fp/queue structure to
11974 * determine the id used by the FW.
11976 if (CHIP_IS_E1x(bp
))
11977 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
11979 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11980 * the same queue are indicated on the same IGU SB). So we prefer
11981 * FW and IGU SBs to be the same value.
11983 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
11985 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11986 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
11987 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
11990 * Initialize MF configuration
11995 bp
->mf_sub_mode
= 0;
11997 mfw_vn
= BP_FW_MB_IDX(bp
);
11999 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
12000 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12001 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
12002 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
12004 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
12005 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
12007 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
12008 offsetof(struct shmem_region
, func_mb
) +
12009 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
12011 * get mf configuration:
12012 * 1. Existence of MF configuration
12013 * 2. MAC address must be legal (check only upper bytes)
12014 * for Switch-Independent mode;
12015 * OVLAN must be legal for Switch-Dependent mode
12016 * 3. SF_MODE configures specific MF mode
12018 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
12019 /* get mf configuration */
12021 dev_info
.shared_feature_config
.config
);
12022 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
12025 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
12026 validate_set_si_mode(bp
);
12028 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE
:
12029 if ((!CHIP_IS_E1x(bp
)) &&
12030 (MF_CFG_RD(bp
, func_mf_config
[func
].
12031 mac_upper
) != 0xffff) &&
12033 afex_driver_support
))) {
12034 bp
->mf_mode
= MULTI_FUNCTION_AFEX
;
12035 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
12036 func_mf_config
[func
].config
);
12038 BNX2X_DEV_INFO("can not configure afex mode\n");
12041 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
12042 /* get OV configuration */
12043 val
= MF_CFG_RD(bp
,
12044 func_mf_config
[FUNC_0
].e1hov_tag
);
12045 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
12047 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
12048 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12049 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
12050 func_mf_config
[func
].config
);
12052 BNX2X_DEV_INFO("illegal OV for SD\n");
12054 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE
:
12055 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12056 bp
->mf_sub_mode
= SUB_MF_MODE_BD
;
12057 bp
->mf_config
[vn
] =
12059 func_mf_config
[func
].config
);
12061 if (SHMEM2_HAS(bp
, mtu_size
)) {
12062 int mtu_idx
= BP_FW_MB_IDX(bp
);
12066 mtu
= SHMEM2_RD(bp
, mtu_size
[mtu_idx
]);
12067 mtu_size
= (u16
)mtu
;
12068 DP(NETIF_MSG_IFUP
, "Read MTU size %04x [%08x]\n",
12071 /* if valid: update device mtu */
12072 if (((mtu_size
+ ETH_HLEN
) >=
12073 ETH_MIN_PACKET_SIZE
) &&
12075 ETH_MAX_JUMBO_PACKET_SIZE
))
12076 bp
->dev
->mtu
= mtu_size
;
12079 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE
:
12080 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12081 bp
->mf_sub_mode
= SUB_MF_MODE_UFP
;
12082 bp
->mf_config
[vn
] =
12084 func_mf_config
[func
].config
);
12086 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF
:
12087 bp
->mf_config
[vn
] = 0;
12089 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE
:
12090 val2
= SHMEM_RD(bp
,
12091 dev_info
.shared_hw_config
.config_3
);
12092 val2
&= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK
;
12094 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5
:
12095 validate_set_si_mode(bp
);
12097 SUB_MF_MODE_NPAR1_DOT_5
;
12100 /* Unknown configuration */
12101 bp
->mf_config
[vn
] = 0;
12102 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12107 /* Unknown configuration: reset mf_config */
12108 bp
->mf_config
[vn
] = 0;
12109 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val
);
12113 BNX2X_DEV_INFO("%s function mode\n",
12114 IS_MF(bp
) ? "multi" : "single");
12116 switch (bp
->mf_mode
) {
12117 case MULTI_FUNCTION_SD
:
12118 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
12119 FUNC_MF_CFG_E1HOV_TAG_MASK
;
12120 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
12122 bp
->path_has_ovlan
= true;
12124 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12125 func
, bp
->mf_ov
, bp
->mf_ov
);
12126 } else if ((bp
->mf_sub_mode
== SUB_MF_MODE_UFP
) ||
12127 (bp
->mf_sub_mode
== SUB_MF_MODE_BD
)) {
12128 dev_err(&bp
->pdev
->dev
,
12129 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12131 bp
->path_has_ovlan
= true;
12133 dev_err(&bp
->pdev
->dev
,
12134 "No valid MF OV for func %d, aborting\n",
12139 case MULTI_FUNCTION_AFEX
:
12140 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func
);
12142 case MULTI_FUNCTION_SI
:
12143 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12148 dev_err(&bp
->pdev
->dev
,
12149 "VN %d is in a single function mode, aborting\n",
12156 /* check if other port on the path needs ovlan:
12157 * Since MF configuration is shared between ports
12158 * Possible mixed modes are only
12159 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12161 if (CHIP_MODE_IS_4_PORT(bp
) &&
12162 !bp
->path_has_ovlan
&&
12164 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
12165 u8 other_port
= !BP_PORT(bp
);
12166 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
12167 val
= MF_CFG_RD(bp
,
12168 func_mf_config
[other_func
].e1hov_tag
);
12169 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
12170 bp
->path_has_ovlan
= true;
12174 /* adjust igu_sb_cnt to MF for E1H */
12175 if (CHIP_IS_E1H(bp
) && IS_MF(bp
))
12176 bp
->igu_sb_cnt
= min_t(u8
, bp
->igu_sb_cnt
, E1H_MAX_MF_SB_COUNT
);
12179 bnx2x_get_port_hwinfo(bp
);
12181 /* Get MAC addresses */
12182 bnx2x_get_mac_hwinfo(bp
);
12184 bnx2x_get_cnic_info(bp
);
12189 static void bnx2x_read_fwinfo(struct bnx2x
*bp
)
12191 int cnt
, i
, block_end
, rodi
;
12192 char vpd_start
[BNX2X_VPD_LEN
+1];
12193 char str_id_reg
[VENDOR_ID_LEN
+1];
12194 char str_id_cap
[VENDOR_ID_LEN
+1];
12196 char *vpd_extended_data
= NULL
;
12199 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
12200 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
12202 if (cnt
< BNX2X_VPD_LEN
)
12203 goto out_not_found
;
12205 /* VPD RO tag should be first tag after identifier string, hence
12206 * we should be able to find it in first BNX2X_VPD_LEN chars
12208 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
12209 PCI_VPD_LRDT_RO_DATA
);
12211 goto out_not_found
;
12213 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
12214 pci_vpd_lrdt_size(&vpd_start
[i
]);
12216 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12218 if (block_end
> BNX2X_VPD_LEN
) {
12219 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
12220 if (vpd_extended_data
== NULL
)
12221 goto out_not_found
;
12223 /* read rest of vpd image into vpd_extended_data */
12224 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
12225 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
12226 block_end
- BNX2X_VPD_LEN
,
12227 vpd_extended_data
+ BNX2X_VPD_LEN
);
12228 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
12229 goto out_not_found
;
12230 vpd_data
= vpd_extended_data
;
12232 vpd_data
= vpd_start
;
12234 /* now vpd_data holds full vpd content in both cases */
12236 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
12237 PCI_VPD_RO_KEYWORD_MFR_ID
);
12239 goto out_not_found
;
12241 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
12243 if (len
!= VENDOR_ID_LEN
)
12244 goto out_not_found
;
12246 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12248 /* vendor specific info */
12249 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
12250 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
12251 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
12252 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
12254 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
12255 PCI_VPD_RO_KEYWORD_VENDOR0
);
12257 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
12259 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12261 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
12262 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
12263 bp
->fw_ver
[len
] = ' ';
12266 kfree(vpd_extended_data
);
12270 kfree(vpd_extended_data
);
12274 static void bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
12278 if (CHIP_REV_IS_FPGA(bp
))
12279 SET_FLAGS(flags
, MODE_FPGA
);
12280 else if (CHIP_REV_IS_EMUL(bp
))
12281 SET_FLAGS(flags
, MODE_EMUL
);
12283 SET_FLAGS(flags
, MODE_ASIC
);
12285 if (CHIP_MODE_IS_4_PORT(bp
))
12286 SET_FLAGS(flags
, MODE_PORT4
);
12288 SET_FLAGS(flags
, MODE_PORT2
);
12290 if (CHIP_IS_E2(bp
))
12291 SET_FLAGS(flags
, MODE_E2
);
12292 else if (CHIP_IS_E3(bp
)) {
12293 SET_FLAGS(flags
, MODE_E3
);
12294 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
12295 SET_FLAGS(flags
, MODE_E3_A0
);
12296 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12297 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
12301 SET_FLAGS(flags
, MODE_MF
);
12302 switch (bp
->mf_mode
) {
12303 case MULTI_FUNCTION_SD
:
12304 SET_FLAGS(flags
, MODE_MF_SD
);
12306 case MULTI_FUNCTION_SI
:
12307 SET_FLAGS(flags
, MODE_MF_SI
);
12309 case MULTI_FUNCTION_AFEX
:
12310 SET_FLAGS(flags
, MODE_MF_AFEX
);
12314 SET_FLAGS(flags
, MODE_SF
);
12316 #if defined(__LITTLE_ENDIAN)
12317 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
12318 #else /*(__BIG_ENDIAN)*/
12319 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
12321 INIT_MODE_FLAGS(bp
) = flags
;
12324 static int bnx2x_init_bp(struct bnx2x
*bp
)
12329 mutex_init(&bp
->port
.phy_mutex
);
12330 mutex_init(&bp
->fw_mb_mutex
);
12331 mutex_init(&bp
->drv_info_mutex
);
12332 sema_init(&bp
->stats_lock
, 1);
12333 bp
->drv_info_mng_owner
= false;
12334 INIT_LIST_HEAD(&bp
->vlan_reg
);
12336 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
12337 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
12338 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
12339 INIT_DELAYED_WORK(&bp
->iov_task
, bnx2x_iov_task
);
12341 rc
= bnx2x_get_hwinfo(bp
);
12345 eth_zero_addr(bp
->dev
->dev_addr
);
12348 bnx2x_set_modes_bitmap(bp
);
12350 rc
= bnx2x_alloc_mem_bp(bp
);
12354 bnx2x_read_fwinfo(bp
);
12356 func
= BP_FUNC(bp
);
12358 /* need to reset chip if undi was active */
12359 if (IS_PF(bp
) && !BP_NOMCP(bp
)) {
12362 SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
12363 DRV_MSG_SEQ_NUMBER_MASK
;
12364 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
12366 rc
= bnx2x_prev_unload(bp
);
12368 bnx2x_free_mem_bp(bp
);
12373 if (CHIP_REV_IS_FPGA(bp
))
12374 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
12376 if (BP_NOMCP(bp
) && (func
== 0))
12377 dev_err(&bp
->pdev
->dev
, "MCP disabled, must load devices in order!\n");
12379 bp
->disable_tpa
= disable_tpa
;
12380 bp
->disable_tpa
|= !!IS_MF_STORAGE_ONLY(bp
);
12381 /* Reduce memory usage in kdump environment by disabling TPA */
12382 bp
->disable_tpa
|= is_kdump_kernel();
12384 /* Set TPA flags */
12385 if (bp
->disable_tpa
) {
12386 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
12387 bp
->dev
->features
&= ~NETIF_F_LRO
;
12390 if (CHIP_IS_E1(bp
))
12391 bp
->dropless_fc
= 0;
12393 bp
->dropless_fc
= dropless_fc
| bnx2x_get_dropless_info(bp
);
12397 bp
->tx_ring_size
= IS_MF_STORAGE_ONLY(bp
) ? 0 : MAX_TX_AVAIL
;
12399 bp
->rx_ring_size
= MAX_RX_AVAIL
;
12401 /* make sure that the numbers are in the right granularity */
12402 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
12403 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
12405 bp
->current_interval
= CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
;
12407 init_timer(&bp
->timer
);
12408 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
12409 bp
->timer
.data
= (unsigned long) bp
;
12410 bp
->timer
.function
= bnx2x_timer
;
12412 if (SHMEM2_HAS(bp
, dcbx_lldp_params_offset
) &&
12413 SHMEM2_HAS(bp
, dcbx_lldp_dcbx_stat_offset
) &&
12414 SHMEM2_HAS(bp
, dcbx_en
) &&
12415 SHMEM2_RD(bp
, dcbx_lldp_params_offset
) &&
12416 SHMEM2_RD(bp
, dcbx_lldp_dcbx_stat_offset
) &&
12417 SHMEM2_RD(bp
, dcbx_en
[BP_PORT(bp
)])) {
12418 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
12419 bnx2x_dcbx_init_params(bp
);
12421 bnx2x_dcbx_set_state(bp
, false, BNX2X_DCBX_ENABLED_OFF
);
12424 if (CHIP_IS_E1x(bp
))
12425 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
12427 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
12429 /* multiple tx priority */
12432 else if (CHIP_IS_E1x(bp
))
12433 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
12434 else if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
12435 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
12436 else if (CHIP_IS_E3B0(bp
))
12437 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
12439 BNX2X_ERR("unknown chip %x revision %x\n",
12440 CHIP_NUM(bp
), CHIP_REV(bp
));
12441 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp
->max_cos
);
12443 /* We need at least one default status block for slow-path events,
12444 * second status block for the L2 queue, and a third status block for
12445 * CNIC if supported.
12448 bp
->min_msix_vec_cnt
= 1;
12449 else if (CNIC_SUPPORT(bp
))
12450 bp
->min_msix_vec_cnt
= 3;
12451 else /* PF w/o cnic */
12452 bp
->min_msix_vec_cnt
= 2;
12453 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp
->min_msix_vec_cnt
);
12455 bp
->dump_preset_idx
= 1;
12457 if (CHIP_IS_E3B0(bp
))
12458 bp
->flags
|= PTP_SUPPORTED
;
12463 /****************************************************************************
12464 * General service functions
12465 ****************************************************************************/
12468 * net_device service functions
12471 /* called with rtnl_lock */
12472 static int bnx2x_open(struct net_device
*dev
)
12474 struct bnx2x
*bp
= netdev_priv(dev
);
12477 bp
->stats_init
= true;
12479 netif_carrier_off(dev
);
12481 bnx2x_set_power_state(bp
, PCI_D0
);
12483 /* If parity had happen during the unload, then attentions
12484 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12485 * want the first function loaded on the current engine to
12486 * complete the recovery.
12487 * Parity recovery is only relevant for PF driver.
12490 int other_engine
= BP_PATH(bp
) ? 0 : 1;
12491 bool other_load_status
, load_status
;
12492 bool global
= false;
12494 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
12495 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
12496 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
12497 bnx2x_chk_parity_attn(bp
, &global
, true)) {
12499 /* If there are attentions and they are in a
12500 * global blocks, set the GLOBAL_RESET bit
12501 * regardless whether it will be this function
12502 * that will complete the recovery or not.
12505 bnx2x_set_reset_global(bp
);
12507 /* Only the first function on the current
12508 * engine should try to recover in open. In case
12509 * of attentions in global blocks only the first
12510 * in the chip should try to recover.
12512 if ((!load_status
&&
12513 (!global
|| !other_load_status
)) &&
12514 bnx2x_trylock_leader_lock(bp
) &&
12515 !bnx2x_leader_reset(bp
)) {
12516 netdev_info(bp
->dev
,
12517 "Recovered in open\n");
12521 /* recovery has failed... */
12522 bnx2x_set_power_state(bp
, PCI_D3hot
);
12523 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
12525 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12526 "If you still see this message after a few retries then power cycle is required.\n");
12533 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
12534 rc
= bnx2x_nic_load(bp
, LOAD_OPEN
);
12539 udp_tunnel_get_rx_info(dev
);
12544 /* called with rtnl_lock */
12545 static int bnx2x_close(struct net_device
*dev
)
12547 struct bnx2x
*bp
= netdev_priv(dev
);
12549 /* Unload the driver, release IRQs */
12550 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
, false);
12555 static int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
12556 struct bnx2x_mcast_ramrod_params
*p
)
12558 int mc_count
= netdev_mc_count(bp
->dev
);
12559 struct bnx2x_mcast_list_elem
*mc_mac
=
12560 kcalloc(mc_count
, sizeof(*mc_mac
), GFP_ATOMIC
);
12561 struct netdev_hw_addr
*ha
;
12566 INIT_LIST_HEAD(&p
->mcast_list
);
12568 netdev_for_each_mc_addr(ha
, bp
->dev
) {
12569 mc_mac
->mac
= bnx2x_mc_addr(ha
);
12570 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
12574 p
->mcast_list_len
= mc_count
;
12579 static void bnx2x_free_mcast_macs_list(
12580 struct bnx2x_mcast_ramrod_params
*p
)
12582 struct bnx2x_mcast_list_elem
*mc_mac
=
12583 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
12591 * bnx2x_set_uc_list - configure a new unicast MACs list.
12593 * @bp: driver handle
12595 * We will use zero (0) as a MAC type for these MACs.
12597 static int bnx2x_set_uc_list(struct bnx2x
*bp
)
12600 struct net_device
*dev
= bp
->dev
;
12601 struct netdev_hw_addr
*ha
;
12602 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->sp_objs
->mac_obj
;
12603 unsigned long ramrod_flags
= 0;
12605 /* First schedule a cleanup up of old configuration */
12606 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
12608 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
12612 netdev_for_each_uc_addr(ha
, dev
) {
12613 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
12614 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
12615 if (rc
== -EEXIST
) {
12617 "Failed to schedule ADD operations: %d\n", rc
);
12618 /* do not treat adding same MAC as error */
12621 } else if (rc
< 0) {
12623 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12629 /* Execute the pending commands */
12630 __set_bit(RAMROD_CONT
, &ramrod_flags
);
12631 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
12632 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
12635 static int bnx2x_set_mc_list(struct bnx2x
*bp
)
12637 struct net_device
*dev
= bp
->dev
;
12638 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
12641 rparam
.mcast_obj
= &bp
->mcast_obj
;
12643 /* first, clear all configured multicast MACs */
12644 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
12646 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc
);
12650 /* then, configure a new MACs list */
12651 if (netdev_mc_count(dev
)) {
12652 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
12654 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12659 /* Now add the new MACs */
12660 rc
= bnx2x_config_mcast(bp
, &rparam
,
12661 BNX2X_MCAST_CMD_ADD
);
12663 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12666 bnx2x_free_mcast_macs_list(&rparam
);
12672 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12673 static void bnx2x_set_rx_mode(struct net_device
*dev
)
12675 struct bnx2x
*bp
= netdev_priv(dev
);
12677 if (bp
->state
!= BNX2X_STATE_OPEN
) {
12678 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
12681 /* Schedule an SP task to handle rest of change */
12682 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_RX_MODE
,
12687 void bnx2x_set_rx_mode_inner(struct bnx2x
*bp
)
12689 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
12691 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
12693 netif_addr_lock_bh(bp
->dev
);
12695 if (bp
->dev
->flags
& IFF_PROMISC
) {
12696 rx_mode
= BNX2X_RX_MODE_PROMISC
;
12697 } else if ((bp
->dev
->flags
& IFF_ALLMULTI
) ||
12698 ((netdev_mc_count(bp
->dev
) > BNX2X_MAX_MULTICAST
) &&
12700 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
12703 /* some multicasts */
12704 if (bnx2x_set_mc_list(bp
) < 0)
12705 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
12707 /* release bh lock, as bnx2x_set_uc_list might sleep */
12708 netif_addr_unlock_bh(bp
->dev
);
12709 if (bnx2x_set_uc_list(bp
) < 0)
12710 rx_mode
= BNX2X_RX_MODE_PROMISC
;
12711 netif_addr_lock_bh(bp
->dev
);
12713 /* configuring mcast to a vf involves sleeping (when we
12714 * wait for the pf's response).
12716 bnx2x_schedule_sp_rtnl(bp
,
12717 BNX2X_SP_RTNL_VFPF_MCAST
, 0);
12721 bp
->rx_mode
= rx_mode
;
12722 /* handle ISCSI SD mode */
12723 if (IS_MF_ISCSI_ONLY(bp
))
12724 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
12726 /* Schedule the rx_mode command */
12727 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
12728 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
12729 netif_addr_unlock_bh(bp
->dev
);
12734 bnx2x_set_storm_rx_mode(bp
);
12735 netif_addr_unlock_bh(bp
->dev
);
12737 /* VF will need to request the PF to make this change, and so
12738 * the VF needs to release the bottom-half lock prior to the
12739 * request (as it will likely require sleep on the VF side)
12741 netif_addr_unlock_bh(bp
->dev
);
12742 bnx2x_vfpf_storm_rx_mode(bp
);
12746 /* called with rtnl_lock */
12747 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
12748 int devad
, u16 addr
)
12750 struct bnx2x
*bp
= netdev_priv(netdev
);
12754 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12755 prtad
, devad
, addr
);
12757 /* The HW expects different devad if CL22 is used */
12758 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
12760 bnx2x_acquire_phy_lock(bp
);
12761 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
12762 bnx2x_release_phy_lock(bp
);
12763 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
12770 /* called with rtnl_lock */
12771 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
12772 u16 addr
, u16 value
)
12774 struct bnx2x
*bp
= netdev_priv(netdev
);
12778 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12779 prtad
, devad
, addr
, value
);
12781 /* The HW expects different devad if CL22 is used */
12782 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
12784 bnx2x_acquire_phy_lock(bp
);
12785 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
12786 bnx2x_release_phy_lock(bp
);
12790 /* called with rtnl_lock */
12791 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
12793 struct bnx2x
*bp
= netdev_priv(dev
);
12794 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
12796 if (!netif_running(dev
))
12800 case SIOCSHWTSTAMP
:
12801 return bnx2x_hwtstamp_ioctl(bp
, ifr
);
12803 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12804 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
12805 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
12809 #ifdef CONFIG_NET_POLL_CONTROLLER
12810 static void poll_bnx2x(struct net_device
*dev
)
12812 struct bnx2x
*bp
= netdev_priv(dev
);
12815 for_each_eth_queue(bp
, i
) {
12816 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
12817 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
12822 static int bnx2x_validate_addr(struct net_device
*dev
)
12824 struct bnx2x
*bp
= netdev_priv(dev
);
12826 /* query the bulletin board for mac address configured by the PF */
12828 bnx2x_sample_bulletin(bp
);
12830 if (!is_valid_ether_addr(dev
->dev_addr
)) {
12831 BNX2X_ERR("Non-valid Ethernet address\n");
12832 return -EADDRNOTAVAIL
;
12837 static int bnx2x_get_phys_port_id(struct net_device
*netdev
,
12838 struct netdev_phys_item_id
*ppid
)
12840 struct bnx2x
*bp
= netdev_priv(netdev
);
12842 if (!(bp
->flags
& HAS_PHYS_PORT_ID
))
12843 return -EOPNOTSUPP
;
12845 ppid
->id_len
= sizeof(bp
->phys_port_id
);
12846 memcpy(ppid
->id
, bp
->phys_port_id
, ppid
->id_len
);
12851 static netdev_features_t
bnx2x_features_check(struct sk_buff
*skb
,
12852 struct net_device
*dev
,
12853 netdev_features_t features
)
12855 features
= vlan_features_check(skb
, features
);
12856 return vxlan_features_check(skb
, features
);
12859 static int __bnx2x_vlan_configure_vid(struct bnx2x
*bp
, u16 vid
, bool add
)
12864 unsigned long ramrod_flags
= 0;
12866 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
12867 rc
= bnx2x_set_vlan_one(bp
, vid
, &bp
->sp_objs
->vlan_obj
,
12868 add
, &ramrod_flags
);
12870 rc
= bnx2x_vfpf_update_vlan(bp
, vid
, bp
->fp
->index
, add
);
12876 static int bnx2x_vlan_configure_vid_list(struct bnx2x
*bp
)
12878 struct bnx2x_vlan_entry
*vlan
;
12881 /* Configure all non-configured entries */
12882 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
) {
12886 if (bp
->vlan_cnt
>= bp
->vlan_credit
)
12889 rc
= __bnx2x_vlan_configure_vid(bp
, vlan
->vid
, true);
12891 BNX2X_ERR("Unable to config VLAN %d\n", vlan
->vid
);
12895 DP(NETIF_MSG_IFUP
, "HW configured for VLAN %d\n", vlan
->vid
);
12903 static void bnx2x_vlan_configure(struct bnx2x
*bp
, bool set_rx_mode
)
12905 bool need_accept_any_vlan
;
12907 need_accept_any_vlan
= !!bnx2x_vlan_configure_vid_list(bp
);
12909 if (bp
->accept_any_vlan
!= need_accept_any_vlan
) {
12910 bp
->accept_any_vlan
= need_accept_any_vlan
;
12911 DP(NETIF_MSG_IFUP
, "Accept all VLAN %s\n",
12912 bp
->accept_any_vlan
? "raised" : "cleared");
12915 bnx2x_set_rx_mode_inner(bp
);
12917 bnx2x_vfpf_storm_rx_mode(bp
);
12922 int bnx2x_vlan_reconfigure_vid(struct bnx2x
*bp
)
12924 struct bnx2x_vlan_entry
*vlan
;
12926 /* The hw forgot all entries after reload */
12927 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
)
12931 /* Don't set rx mode here. Our caller will do it. */
12932 bnx2x_vlan_configure(bp
, false);
12937 static int bnx2x_vlan_rx_add_vid(struct net_device
*dev
, __be16 proto
, u16 vid
)
12939 struct bnx2x
*bp
= netdev_priv(dev
);
12940 struct bnx2x_vlan_entry
*vlan
;
12942 DP(NETIF_MSG_IFUP
, "Adding VLAN %d\n", vid
);
12944 vlan
= kmalloc(sizeof(*vlan
), GFP_KERNEL
);
12950 list_add_tail(&vlan
->link
, &bp
->vlan_reg
);
12952 if (netif_running(dev
))
12953 bnx2x_vlan_configure(bp
, true);
12958 static int bnx2x_vlan_rx_kill_vid(struct net_device
*dev
, __be16 proto
, u16 vid
)
12960 struct bnx2x
*bp
= netdev_priv(dev
);
12961 struct bnx2x_vlan_entry
*vlan
;
12962 bool found
= false;
12965 DP(NETIF_MSG_IFUP
, "Removing VLAN %d\n", vid
);
12967 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
)
12968 if (vlan
->vid
== vid
) {
12974 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid
);
12978 if (netif_running(dev
) && vlan
->hw
) {
12979 rc
= __bnx2x_vlan_configure_vid(bp
, vid
, false);
12980 DP(NETIF_MSG_IFUP
, "HW deconfigured for VLAN %d\n", vid
);
12984 list_del(&vlan
->link
);
12987 if (netif_running(dev
))
12988 bnx2x_vlan_configure(bp
, true);
12990 DP(NETIF_MSG_IFUP
, "Removing VLAN result %d\n", rc
);
12995 static const struct net_device_ops bnx2x_netdev_ops
= {
12996 .ndo_open
= bnx2x_open
,
12997 .ndo_stop
= bnx2x_close
,
12998 .ndo_start_xmit
= bnx2x_start_xmit
,
12999 .ndo_select_queue
= bnx2x_select_queue
,
13000 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
13001 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
13002 .ndo_validate_addr
= bnx2x_validate_addr
,
13003 .ndo_do_ioctl
= bnx2x_ioctl
,
13004 .ndo_change_mtu
= bnx2x_change_mtu
,
13005 .ndo_fix_features
= bnx2x_fix_features
,
13006 .ndo_set_features
= bnx2x_set_features
,
13007 .ndo_tx_timeout
= bnx2x_tx_timeout
,
13008 .ndo_vlan_rx_add_vid
= bnx2x_vlan_rx_add_vid
,
13009 .ndo_vlan_rx_kill_vid
= bnx2x_vlan_rx_kill_vid
,
13010 #ifdef CONFIG_NET_POLL_CONTROLLER
13011 .ndo_poll_controller
= poll_bnx2x
,
13013 .ndo_setup_tc
= __bnx2x_setup_tc
,
13014 #ifdef CONFIG_BNX2X_SRIOV
13015 .ndo_set_vf_mac
= bnx2x_set_vf_mac
,
13016 .ndo_set_vf_vlan
= bnx2x_set_vf_vlan
,
13017 .ndo_get_vf_config
= bnx2x_get_vf_config
,
13019 #ifdef NETDEV_FCOE_WWNN
13020 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
13023 .ndo_get_phys_port_id
= bnx2x_get_phys_port_id
,
13024 .ndo_set_vf_link_state
= bnx2x_set_vf_link_state
,
13025 .ndo_features_check
= bnx2x_features_check
,
13026 .ndo_udp_tunnel_add
= bnx2x_udp_tunnel_add
,
13027 .ndo_udp_tunnel_del
= bnx2x_udp_tunnel_del
,
13030 static int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
13032 struct device
*dev
= &bp
->pdev
->dev
;
13034 if (dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(64)) != 0 &&
13035 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32)) != 0) {
13036 dev_err(dev
, "System does not support DMA, aborting\n");
13043 static void bnx2x_disable_pcie_error_reporting(struct bnx2x
*bp
)
13045 if (bp
->flags
& AER_ENABLED
) {
13046 pci_disable_pcie_error_reporting(bp
->pdev
);
13047 bp
->flags
&= ~AER_ENABLED
;
13051 static int bnx2x_init_dev(struct bnx2x
*bp
, struct pci_dev
*pdev
,
13052 struct net_device
*dev
, unsigned long board_type
)
13056 bool chip_is_e1x
= (board_type
== BCM57710
||
13057 board_type
== BCM57711
||
13058 board_type
== BCM57711E
);
13060 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13065 rc
= pci_enable_device(pdev
);
13067 dev_err(&bp
->pdev
->dev
,
13068 "Cannot enable PCI device, aborting\n");
13072 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
13073 dev_err(&bp
->pdev
->dev
,
13074 "Cannot find PCI device base address, aborting\n");
13076 goto err_out_disable
;
13079 if (IS_PF(bp
) && !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
13080 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device base address, aborting\n");
13082 goto err_out_disable
;
13085 pci_read_config_dword(pdev
, PCICFG_REVISION_ID_OFFSET
, &pci_cfg_dword
);
13086 if ((pci_cfg_dword
& PCICFG_REVESION_ID_MASK
) ==
13087 PCICFG_REVESION_ID_ERROR_VAL
) {
13088 pr_err("PCI device error, probably due to fan failure, aborting\n");
13090 goto err_out_disable
;
13093 if (atomic_read(&pdev
->enable_cnt
) == 1) {
13094 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13096 dev_err(&bp
->pdev
->dev
,
13097 "Cannot obtain PCI resources, aborting\n");
13098 goto err_out_disable
;
13101 pci_set_master(pdev
);
13102 pci_save_state(pdev
);
13106 if (!pdev
->pm_cap
) {
13107 dev_err(&bp
->pdev
->dev
,
13108 "Cannot find power management capability, aborting\n");
13110 goto err_out_release
;
13114 if (!pci_is_pcie(pdev
)) {
13115 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
13117 goto err_out_release
;
13120 rc
= bnx2x_set_coherency_mask(bp
);
13122 goto err_out_release
;
13124 dev
->mem_start
= pci_resource_start(pdev
, 0);
13125 dev
->base_addr
= dev
->mem_start
;
13126 dev
->mem_end
= pci_resource_end(pdev
, 0);
13128 dev
->irq
= pdev
->irq
;
13130 bp
->regview
= pci_ioremap_bar(pdev
, 0);
13131 if (!bp
->regview
) {
13132 dev_err(&bp
->pdev
->dev
,
13133 "Cannot map register space, aborting\n");
13135 goto err_out_release
;
13138 /* In E1/E1H use pci device function given by kernel.
13139 * In E2/E3 read physical function from ME register since these chips
13140 * support Physical Device Assignment where kernel BDF maybe arbitrary
13141 * (depending on hypervisor).
13144 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
13147 pci_read_config_dword(bp
->pdev
,
13148 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
13149 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
13150 ME_REG_ABS_PF_NUM_SHIFT
);
13152 BNX2X_DEV_INFO("me reg PF num: %d\n", bp
->pf_num
);
13154 /* clean indirect addresses */
13155 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
13156 PCICFG_VENDOR_ID_OFFSET
);
13158 /* Set PCIe reset type to fundamental for EEH recovery */
13159 pdev
->needs_freset
= 1;
13161 /* AER (Advanced Error reporting) configuration */
13162 rc
= pci_enable_pcie_error_reporting(pdev
);
13164 bp
->flags
|= AER_ENABLED
;
13166 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc
);
13169 * Clean the following indirect addresses for all functions since it
13170 * is not used by the driver.
13173 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
13174 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
13175 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
13176 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
13179 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
13180 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
13181 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
13182 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
13185 /* Enable internal target-read (in case we are probed after PF
13186 * FLR). Must be done prior to any BAR read access. Only for
13191 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
13194 dev
->watchdog_timeo
= TX_TIMEOUT
;
13196 dev
->netdev_ops
= &bnx2x_netdev_ops
;
13197 bnx2x_set_ethtool_ops(bp
, dev
);
13199 dev
->priv_flags
|= IFF_UNICAST_FLT
;
13201 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
13202 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
13203 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
|
13204 NETIF_F_RXHASH
| NETIF_F_HW_VLAN_CTAG_TX
;
13205 if (!chip_is_e1x
) {
13206 dev
->hw_features
|= NETIF_F_GSO_GRE
| NETIF_F_GSO_UDP_TUNNEL
|
13207 NETIF_F_GSO_IPXIP4
;
13208 dev
->hw_enc_features
=
13209 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
13210 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
13211 NETIF_F_GSO_IPXIP4
|
13212 NETIF_F_GSO_GRE
| NETIF_F_GSO_UDP_TUNNEL
;
13215 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
13216 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
13218 /* VF with OLD Hypervisor or old PF do not support filtering */
13221 bp
->accept_any_vlan
= true;
13223 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
13224 #ifdef CONFIG_BNX2X_SRIOV
13225 } else if (bp
->acquire_resp
.pfdev_info
.pf_cap
& PFVF_CAP_VLAN_FILTER
) {
13226 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
13230 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_CTAG_RX
;
13231 dev
->features
|= NETIF_F_HIGHDMA
;
13233 /* Add Loopback capability to the device */
13234 dev
->hw_features
|= NETIF_F_LOOPBACK
;
13237 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
13240 /* get_port_hwinfo() will set prtad and mmds properly */
13241 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
13243 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
13244 bp
->mdio
.dev
= dev
;
13245 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
13246 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
13251 if (atomic_read(&pdev
->enable_cnt
) == 1)
13252 pci_release_regions(pdev
);
13255 pci_disable_device(pdev
);
13261 static int bnx2x_check_firmware(struct bnx2x
*bp
)
13263 const struct firmware
*firmware
= bp
->firmware
;
13264 struct bnx2x_fw_file_hdr
*fw_hdr
;
13265 struct bnx2x_fw_file_section
*sections
;
13266 u32 offset
, len
, num_ops
;
13267 __be16
*ops_offsets
;
13271 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
)) {
13272 BNX2X_ERR("Wrong FW size\n");
13276 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
13277 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
13279 /* Make sure none of the offsets and sizes make us read beyond
13280 * the end of the firmware data */
13281 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
13282 offset
= be32_to_cpu(sections
[i
].offset
);
13283 len
= be32_to_cpu(sections
[i
].len
);
13284 if (offset
+ len
> firmware
->size
) {
13285 BNX2X_ERR("Section %d length is out of bounds\n", i
);
13290 /* Likewise for the init_ops offsets */
13291 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
13292 ops_offsets
= (__force __be16
*)(firmware
->data
+ offset
);
13293 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
13295 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
13296 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
13297 BNX2X_ERR("Section offset %d is out of bounds\n", i
);
13302 /* Check FW version */
13303 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
13304 fw_ver
= firmware
->data
+ offset
;
13305 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
13306 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
13307 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
13308 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
13309 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13310 fw_ver
[0], fw_ver
[1], fw_ver
[2], fw_ver
[3],
13311 BCM_5710_FW_MAJOR_VERSION
,
13312 BCM_5710_FW_MINOR_VERSION
,
13313 BCM_5710_FW_REVISION_VERSION
,
13314 BCM_5710_FW_ENGINEERING_VERSION
);
13321 static void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
13323 const __be32
*source
= (const __be32
*)_source
;
13324 u32
*target
= (u32
*)_target
;
13327 for (i
= 0; i
< n
/4; i
++)
13328 target
[i
] = be32_to_cpu(source
[i
]);
13332 Ops array is stored in the following format:
13333 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13335 static void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
13337 const __be32
*source
= (const __be32
*)_source
;
13338 struct raw_op
*target
= (struct raw_op
*)_target
;
13341 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
13342 tmp
= be32_to_cpu(source
[j
]);
13343 target
[i
].op
= (tmp
>> 24) & 0xff;
13344 target
[i
].offset
= tmp
& 0xffffff;
13345 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
13349 /* IRO array is stored in the following format:
13350 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13352 static void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
13354 const __be32
*source
= (const __be32
*)_source
;
13355 struct iro
*target
= (struct iro
*)_target
;
13358 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
13359 target
[i
].base
= be32_to_cpu(source
[j
]);
13361 tmp
= be32_to_cpu(source
[j
]);
13362 target
[i
].m1
= (tmp
>> 16) & 0xffff;
13363 target
[i
].m2
= tmp
& 0xffff;
13365 tmp
= be32_to_cpu(source
[j
]);
13366 target
[i
].m3
= (tmp
>> 16) & 0xffff;
13367 target
[i
].size
= tmp
& 0xffff;
13372 static void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
13374 const __be16
*source
= (const __be16
*)_source
;
13375 u16
*target
= (u16
*)_target
;
13378 for (i
= 0; i
< n
/2; i
++)
13379 target
[i
] = be16_to_cpu(source
[i
]);
13382 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13384 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13385 bp->arr = kmalloc(len, GFP_KERNEL); \
13388 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13389 (u8 *)bp->arr, len); \
13392 static int bnx2x_init_firmware(struct bnx2x
*bp
)
13394 const char *fw_file_name
;
13395 struct bnx2x_fw_file_hdr
*fw_hdr
;
13401 if (CHIP_IS_E1(bp
))
13402 fw_file_name
= FW_FILE_NAME_E1
;
13403 else if (CHIP_IS_E1H(bp
))
13404 fw_file_name
= FW_FILE_NAME_E1H
;
13405 else if (!CHIP_IS_E1x(bp
))
13406 fw_file_name
= FW_FILE_NAME_E2
;
13408 BNX2X_ERR("Unsupported chip revision\n");
13411 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
13413 rc
= request_firmware(&bp
->firmware
, fw_file_name
, &bp
->pdev
->dev
);
13415 BNX2X_ERR("Can't load firmware file %s\n",
13417 goto request_firmware_exit
;
13420 rc
= bnx2x_check_firmware(bp
);
13422 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
13423 goto request_firmware_exit
;
13426 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
13428 /* Initialize the pointers to the init arrays */
13430 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
13433 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
13436 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
13439 /* STORMs firmware */
13440 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13441 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
13442 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13443 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
13444 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13445 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
13446 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13447 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
13448 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13449 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
13450 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13451 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
13452 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13453 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
13454 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13455 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
13457 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
13462 kfree(bp
->init_ops_offsets
);
13463 init_offsets_alloc_err
:
13464 kfree(bp
->init_ops
);
13465 init_ops_alloc_err
:
13466 kfree(bp
->init_data
);
13467 request_firmware_exit
:
13468 release_firmware(bp
->firmware
);
13469 bp
->firmware
= NULL
;
13474 static void bnx2x_release_firmware(struct bnx2x
*bp
)
13476 kfree(bp
->init_ops_offsets
);
13477 kfree(bp
->init_ops
);
13478 kfree(bp
->init_data
);
13479 release_firmware(bp
->firmware
);
13480 bp
->firmware
= NULL
;
13483 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
13484 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
13485 .init_hw_cmn
= bnx2x_init_hw_common
,
13486 .init_hw_port
= bnx2x_init_hw_port
,
13487 .init_hw_func
= bnx2x_init_hw_func
,
13489 .reset_hw_cmn
= bnx2x_reset_common
,
13490 .reset_hw_port
= bnx2x_reset_port
,
13491 .reset_hw_func
= bnx2x_reset_func
,
13493 .gunzip_init
= bnx2x_gunzip_init
,
13494 .gunzip_end
= bnx2x_gunzip_end
,
13496 .init_fw
= bnx2x_init_firmware
,
13497 .release_fw
= bnx2x_release_firmware
,
13500 void bnx2x__init_func_obj(struct bnx2x
*bp
)
13502 /* Prepare DMAE related driver resources */
13503 bnx2x_setup_dmae(bp
);
13505 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
13506 bnx2x_sp(bp
, func_rdata
),
13507 bnx2x_sp_mapping(bp
, func_rdata
),
13508 bnx2x_sp(bp
, func_afex_rdata
),
13509 bnx2x_sp_mapping(bp
, func_afex_rdata
),
13510 &bnx2x_func_sp_drv
);
13513 /* must be called after sriov-enable */
13514 static int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
13516 int cid_count
= BNX2X_L2_MAX_CID(bp
);
13519 cid_count
+= BNX2X_VF_CIDS
;
13521 if (CNIC_SUPPORT(bp
))
13522 cid_count
+= CNIC_CID_MAX
;
13524 return roundup(cid_count
, QM_CID_ROUND
);
13528 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13533 static int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
, int cnic_cnt
)
13539 * If MSI-X is not supported - return number of SBs needed to support
13540 * one fast path queue: one FP queue + SB for CNIC
13542 if (!pdev
->msix_cap
) {
13543 dev_info(&pdev
->dev
, "no msix capability found\n");
13544 return 1 + cnic_cnt
;
13546 dev_info(&pdev
->dev
, "msix capability found\n");
13549 * The value in the PCI configuration space is the index of the last
13550 * entry, namely one less than the actual size of the table, which is
13551 * exactly what we want to return from this function: number of all SBs
13552 * without the default SB.
13553 * For VFs there is no default SB, then we return (index+1).
13555 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
13557 index
= control
& PCI_MSIX_FLAGS_QSIZE
;
13562 static int set_max_cos_est(int chip_id
)
13568 return BNX2X_MULTI_TX_COS_E1X
;
13571 return BNX2X_MULTI_TX_COS_E2_E3A0
;
13576 case BCM57840_4_10
:
13577 case BCM57840_2_20
:
13583 return BNX2X_MULTI_TX_COS_E3B0
;
13591 pr_err("Unknown board_type (%d), aborting\n", chip_id
);
13596 static int set_is_vf(int chip_id
)
13610 /* nig_tsgen registers relative address */
13611 #define tsgen_ctrl 0x0
13612 #define tsgen_freecount 0x10
13613 #define tsgen_synctime_t0 0x20
13614 #define tsgen_offset_t0 0x28
13615 #define tsgen_drift_t0 0x30
13616 #define tsgen_synctime_t1 0x58
13617 #define tsgen_offset_t1 0x60
13618 #define tsgen_drift_t1 0x68
13620 /* FW workaround for setting drift */
13621 static int bnx2x_send_update_drift_ramrod(struct bnx2x
*bp
, int drift_dir
,
13622 int best_val
, int best_period
)
13624 struct bnx2x_func_state_params func_params
= {NULL
};
13625 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
13626 &func_params
.params
.set_timesync
;
13628 /* Prepare parameters for function state transitions */
13629 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
13630 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
13632 func_params
.f_obj
= &bp
->func_obj
;
13633 func_params
.cmd
= BNX2X_F_CMD_SET_TIMESYNC
;
13635 /* Function parameters */
13636 set_timesync_params
->drift_adjust_cmd
= TS_DRIFT_ADJUST_SET
;
13637 set_timesync_params
->offset_cmd
= TS_OFFSET_KEEP
;
13638 set_timesync_params
->add_sub_drift_adjust_value
=
13639 drift_dir
? TS_ADD_VALUE
: TS_SUB_VALUE
;
13640 set_timesync_params
->drift_adjust_value
= best_val
;
13641 set_timesync_params
->drift_adjust_period
= best_period
;
13643 return bnx2x_func_state_change(bp
, &func_params
);
13646 static int bnx2x_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
13648 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13651 int val
, period
, period1
, period2
, dif
, dif1
, dif2
;
13652 int best_dif
= BNX2X_MAX_PHC_DRIFT
, best_period
= 0, best_val
= 0;
13654 DP(BNX2X_MSG_PTP
, "PTP adjfreq called, ppb = %d\n", ppb
);
13656 if (!netif_running(bp
->dev
)) {
13658 "PTP adjfreq called while the interface is down\n");
13669 best_period
= 0x1FFFFFF;
13670 } else if (ppb
>= BNX2X_MAX_PHC_DRIFT
) {
13674 /* Changed not to allow val = 8, 16, 24 as these values
13675 * are not supported in workaround.
13677 for (val
= 0; val
<= 31; val
++) {
13678 if ((val
& 0x7) == 0)
13680 period1
= val
* 1000000 / ppb
;
13681 period2
= period1
+ 1;
13683 dif1
= ppb
- (val
* 1000000 / period1
);
13685 dif1
= BNX2X_MAX_PHC_DRIFT
;
13688 dif2
= ppb
- (val
* 1000000 / period2
);
13691 dif
= (dif1
< dif2
) ? dif1
: dif2
;
13692 period
= (dif1
< dif2
) ? period1
: period2
;
13693 if (dif
< best_dif
) {
13696 best_period
= period
;
13701 rc
= bnx2x_send_update_drift_ramrod(bp
, drift_dir
, best_val
,
13704 BNX2X_ERR("Failed to set drift\n");
13708 DP(BNX2X_MSG_PTP
, "Configured val = %d, period = %d\n", best_val
,
13714 static int bnx2x_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
13716 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13718 DP(BNX2X_MSG_PTP
, "PTP adjtime called, delta = %llx\n", delta
);
13720 timecounter_adjtime(&bp
->timecounter
, delta
);
13725 static int bnx2x_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec64
*ts
)
13727 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13730 ns
= timecounter_read(&bp
->timecounter
);
13732 DP(BNX2X_MSG_PTP
, "PTP gettime called, ns = %llu\n", ns
);
13734 *ts
= ns_to_timespec64(ns
);
13739 static int bnx2x_ptp_settime(struct ptp_clock_info
*ptp
,
13740 const struct timespec64
*ts
)
13742 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13745 ns
= timespec64_to_ns(ts
);
13747 DP(BNX2X_MSG_PTP
, "PTP settime called, ns = %llu\n", ns
);
13749 /* Re-init the timecounter */
13750 timecounter_init(&bp
->timecounter
, &bp
->cyclecounter
, ns
);
13755 /* Enable (or disable) ancillary features of the phc subsystem */
13756 static int bnx2x_ptp_enable(struct ptp_clock_info
*ptp
,
13757 struct ptp_clock_request
*rq
, int on
)
13759 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13761 BNX2X_ERR("PHC ancillary features are not supported\n");
13765 static void bnx2x_register_phc(struct bnx2x
*bp
)
13767 /* Fill the ptp_clock_info struct and register PTP clock*/
13768 bp
->ptp_clock_info
.owner
= THIS_MODULE
;
13769 snprintf(bp
->ptp_clock_info
.name
, 16, "%s", bp
->dev
->name
);
13770 bp
->ptp_clock_info
.max_adj
= BNX2X_MAX_PHC_DRIFT
; /* In PPB */
13771 bp
->ptp_clock_info
.n_alarm
= 0;
13772 bp
->ptp_clock_info
.n_ext_ts
= 0;
13773 bp
->ptp_clock_info
.n_per_out
= 0;
13774 bp
->ptp_clock_info
.pps
= 0;
13775 bp
->ptp_clock_info
.adjfreq
= bnx2x_ptp_adjfreq
;
13776 bp
->ptp_clock_info
.adjtime
= bnx2x_ptp_adjtime
;
13777 bp
->ptp_clock_info
.gettime64
= bnx2x_ptp_gettime
;
13778 bp
->ptp_clock_info
.settime64
= bnx2x_ptp_settime
;
13779 bp
->ptp_clock_info
.enable
= bnx2x_ptp_enable
;
13781 bp
->ptp_clock
= ptp_clock_register(&bp
->ptp_clock_info
, &bp
->pdev
->dev
);
13782 if (IS_ERR(bp
->ptp_clock
)) {
13783 bp
->ptp_clock
= NULL
;
13784 BNX2X_ERR("PTP clock registeration failed\n");
13788 static int bnx2x_init_one(struct pci_dev
*pdev
,
13789 const struct pci_device_id
*ent
)
13791 struct net_device
*dev
= NULL
;
13793 enum pcie_link_width pcie_width
;
13794 enum pci_bus_speed pcie_speed
;
13795 int rc
, max_non_def_sbs
;
13796 int rx_count
, tx_count
, rss_count
, doorbell_size
;
13801 /* Management FW 'remembers' living interfaces. Allow it some time
13802 * to forget previously living interfaces, allowing a proper re-load.
13804 if (is_kdump_kernel()) {
13805 ktime_t now
= ktime_get_boottime();
13806 ktime_t fw_ready_time
= ktime_set(5, 0);
13808 if (ktime_before(now
, fw_ready_time
))
13809 msleep(ktime_ms_delta(fw_ready_time
, now
));
13812 /* An estimated maximum supported CoS number according to the chip
13814 * We will try to roughly estimate the maximum number of CoSes this chip
13815 * may support in order to minimize the memory allocated for Tx
13816 * netdev_queue's. This number will be accurately calculated during the
13817 * initialization of bp->max_cos based on the chip versions AND chip
13818 * revision in the bnx2x_init_bp().
13820 max_cos_est
= set_max_cos_est(ent
->driver_data
);
13821 if (max_cos_est
< 0)
13822 return max_cos_est
;
13823 is_vf
= set_is_vf(ent
->driver_data
);
13824 cnic_cnt
= is_vf
? 0 : 1;
13826 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
, cnic_cnt
);
13828 /* add another SB for VF as it has no default SB */
13829 max_non_def_sbs
+= is_vf
? 1 : 0;
13831 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13832 rss_count
= max_non_def_sbs
- cnic_cnt
;
13837 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13838 rx_count
= rss_count
+ cnic_cnt
;
13840 /* Maximum number of netdev Tx queues:
13841 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13843 tx_count
= rss_count
* max_cos_est
+ cnic_cnt
;
13845 /* dev zeroed in init_etherdev */
13846 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
13850 bp
= netdev_priv(dev
);
13854 bp
->flags
|= IS_VF_FLAG
;
13856 bp
->igu_sb_cnt
= max_non_def_sbs
;
13857 bp
->igu_base_addr
= IS_VF(bp
) ? PXP_VF_ADDR_IGU_START
: BAR_IGU_INTMEM
;
13858 bp
->msg_enable
= debug
;
13859 bp
->cnic_support
= cnic_cnt
;
13860 bp
->cnic_probe
= bnx2x_cnic_probe
;
13862 pci_set_drvdata(pdev
, dev
);
13864 rc
= bnx2x_init_dev(bp
, pdev
, dev
, ent
->driver_data
);
13870 BNX2X_DEV_INFO("This is a %s function\n",
13871 IS_PF(bp
) ? "physical" : "virtual");
13872 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp
) ? "on" : "off");
13873 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs
);
13874 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13875 tx_count
, rx_count
);
13877 rc
= bnx2x_init_bp(bp
);
13879 goto init_one_exit
;
13881 /* Map doorbells here as we need the real value of bp->max_cos which
13882 * is initialized in bnx2x_init_bp() to determine the number of
13886 bp
->doorbells
= bnx2x_vf_doorbells(bp
);
13887 rc
= bnx2x_vf_pci_alloc(bp
);
13889 goto init_one_freemem
;
13891 doorbell_size
= BNX2X_L2_MAX_CID(bp
) * (1 << BNX2X_DB_SHIFT
);
13892 if (doorbell_size
> pci_resource_len(pdev
, 2)) {
13893 dev_err(&bp
->pdev
->dev
,
13894 "Cannot map doorbells, bar size too small, aborting\n");
13896 goto init_one_freemem
;
13898 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
13901 if (!bp
->doorbells
) {
13902 dev_err(&bp
->pdev
->dev
,
13903 "Cannot map doorbell space, aborting\n");
13905 goto init_one_freemem
;
13909 rc
= bnx2x_vfpf_acquire(bp
, tx_count
, rx_count
);
13911 goto init_one_freemem
;
13914 /* Enable SRIOV if capability found in configuration space */
13915 rc
= bnx2x_iov_init_one(bp
, int_mode
, BNX2X_MAX_NUM_OF_VFS
);
13917 goto init_one_freemem
;
13919 /* calc qm_cid_count */
13920 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
13921 BNX2X_DEV_INFO("qm_cid_count %d\n", bp
->qm_cid_count
);
13923 /* disable FCOE L2 queue for E1x*/
13924 if (CHIP_IS_E1x(bp
))
13925 bp
->flags
|= NO_FCOE_FLAG
;
13927 /* Set bp->num_queues for MSI-X mode*/
13928 bnx2x_set_num_queues(bp
);
13930 /* Configure interrupt mode: try to enable MSI-X/MSI if
13933 rc
= bnx2x_set_int_mode(bp
);
13935 dev_err(&pdev
->dev
, "Cannot set interrupts\n");
13936 goto init_one_freemem
;
13938 BNX2X_DEV_INFO("set interrupts successfully\n");
13940 /* register the net device */
13941 rc
= register_netdev(dev
);
13943 dev_err(&pdev
->dev
, "Cannot register net device\n");
13944 goto init_one_freemem
;
13946 BNX2X_DEV_INFO("device name after netdev register %s\n", dev
->name
);
13948 if (!NO_FCOE(bp
)) {
13949 /* Add storage MAC address */
13951 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
13954 if (pcie_get_minimum_link(bp
->pdev
, &pcie_speed
, &pcie_width
) ||
13955 pcie_speed
== PCI_SPEED_UNKNOWN
||
13956 pcie_width
== PCIE_LNK_WIDTH_UNKNOWN
)
13957 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13960 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13961 board_info
[ent
->driver_data
].name
,
13962 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
13964 pcie_speed
== PCIE_SPEED_2_5GT
? "2.5GHz" :
13965 pcie_speed
== PCIE_SPEED_5_0GT
? "5.0GHz" :
13966 pcie_speed
== PCIE_SPEED_8_0GT
? "8.0GHz" :
13968 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
13970 bnx2x_register_phc(bp
);
13972 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp
))
13973 bnx2x_set_os_driver_state(bp
, OS_DRIVER_STATE_DISABLED
);
13978 bnx2x_free_mem_bp(bp
);
13981 bnx2x_disable_pcie_error_reporting(bp
);
13984 iounmap(bp
->regview
);
13986 if (IS_PF(bp
) && bp
->doorbells
)
13987 iounmap(bp
->doorbells
);
13991 if (atomic_read(&pdev
->enable_cnt
) == 1)
13992 pci_release_regions(pdev
);
13994 pci_disable_device(pdev
);
13999 static void __bnx2x_remove(struct pci_dev
*pdev
,
14000 struct net_device
*dev
,
14002 bool remove_netdev
)
14004 if (bp
->ptp_clock
) {
14005 ptp_clock_unregister(bp
->ptp_clock
);
14006 bp
->ptp_clock
= NULL
;
14009 /* Delete storage MAC address */
14010 if (!NO_FCOE(bp
)) {
14012 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
14017 /* Delete app tlvs from dcbnl */
14018 bnx2x_dcbnl_update_applist(bp
, true);
14023 (bp
->flags
& BC_SUPPORTS_RMMOD_CMD
))
14024 bnx2x_fw_command(bp
, DRV_MSG_CODE_RMMOD
, 0);
14026 /* Close the interface - either directly or implicitly */
14027 if (remove_netdev
) {
14028 unregister_netdev(dev
);
14035 bnx2x_iov_remove_one(bp
);
14037 /* Power on: we can't let PCI layer write to us while we are in D3 */
14039 bnx2x_set_power_state(bp
, PCI_D0
);
14040 bnx2x_set_os_driver_state(bp
, OS_DRIVER_STATE_NOT_LOADED
);
14042 /* Set endianity registers to reset values in case next driver
14043 * boots in different endianty environment.
14045 bnx2x_reset_endianity(bp
);
14048 /* Disable MSI/MSI-X */
14049 bnx2x_disable_msi(bp
);
14053 bnx2x_set_power_state(bp
, PCI_D3hot
);
14055 /* Make sure RESET task is not scheduled before continuing */
14056 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
14058 /* send message via vfpf channel to release the resources of this vf */
14060 bnx2x_vfpf_release(bp
);
14062 /* Assumes no further PCIe PM changes will occur */
14063 if (system_state
== SYSTEM_POWER_OFF
) {
14064 pci_wake_from_d3(pdev
, bp
->wol
);
14065 pci_set_power_state(pdev
, PCI_D3hot
);
14068 bnx2x_disable_pcie_error_reporting(bp
);
14069 if (remove_netdev
) {
14071 iounmap(bp
->regview
);
14073 /* For vfs, doorbells are part of the regview and were unmapped
14074 * along with it. FW is only loaded by PF.
14078 iounmap(bp
->doorbells
);
14080 bnx2x_release_firmware(bp
);
14082 bnx2x_vf_pci_dealloc(bp
);
14084 bnx2x_free_mem_bp(bp
);
14088 if (atomic_read(&pdev
->enable_cnt
) == 1)
14089 pci_release_regions(pdev
);
14091 pci_disable_device(pdev
);
14095 static void bnx2x_remove_one(struct pci_dev
*pdev
)
14097 struct net_device
*dev
= pci_get_drvdata(pdev
);
14101 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
14104 bp
= netdev_priv(dev
);
14106 __bnx2x_remove(pdev
, dev
, bp
, true);
14109 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
14111 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_HALT
;
14113 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
14115 if (CNIC_LOADED(bp
))
14116 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
14119 bnx2x_tx_disable(bp
);
14120 /* Delete all NAPI objects */
14121 bnx2x_del_all_napi(bp
);
14122 if (CNIC_LOADED(bp
))
14123 bnx2x_del_all_napi_cnic(bp
);
14124 netdev_reset_tc(bp
->dev
);
14126 del_timer_sync(&bp
->timer
);
14127 cancel_delayed_work_sync(&bp
->sp_task
);
14128 cancel_delayed_work_sync(&bp
->period_task
);
14130 if (!down_timeout(&bp
->stats_lock
, HZ
/ 10)) {
14131 bp
->stats_state
= STATS_STATE_DISABLED
;
14132 up(&bp
->stats_lock
);
14135 bnx2x_save_statistics(bp
);
14137 netif_carrier_off(bp
->dev
);
14143 * bnx2x_io_error_detected - called when PCI error is detected
14144 * @pdev: Pointer to PCI device
14145 * @state: The current pci connection state
14147 * This function is called after a PCI bus error affecting
14148 * this device has been detected.
14150 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
14151 pci_channel_state_t state
)
14153 struct net_device
*dev
= pci_get_drvdata(pdev
);
14154 struct bnx2x
*bp
= netdev_priv(dev
);
14158 BNX2X_ERR("IO error detected\n");
14160 netif_device_detach(dev
);
14162 if (state
== pci_channel_io_perm_failure
) {
14164 return PCI_ERS_RESULT_DISCONNECT
;
14167 if (netif_running(dev
))
14168 bnx2x_eeh_nic_unload(bp
);
14170 bnx2x_prev_path_mark_eeh(bp
);
14172 pci_disable_device(pdev
);
14176 /* Request a slot reset */
14177 return PCI_ERS_RESULT_NEED_RESET
;
14181 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14182 * @pdev: Pointer to PCI device
14184 * Restart the card from scratch, as if from a cold-boot.
14186 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
14188 struct net_device
*dev
= pci_get_drvdata(pdev
);
14189 struct bnx2x
*bp
= netdev_priv(dev
);
14193 BNX2X_ERR("IO slot reset initializing...\n");
14194 if (pci_enable_device(pdev
)) {
14195 dev_err(&pdev
->dev
,
14196 "Cannot re-enable PCI device after reset\n");
14198 return PCI_ERS_RESULT_DISCONNECT
;
14201 pci_set_master(pdev
);
14202 pci_restore_state(pdev
);
14203 pci_save_state(pdev
);
14205 if (netif_running(dev
))
14206 bnx2x_set_power_state(bp
, PCI_D0
);
14208 if (netif_running(dev
)) {
14209 BNX2X_ERR("IO slot reset --> driver unload\n");
14211 /* MCP should have been reset; Need to wait for validity */
14212 bnx2x_init_shmem(bp
);
14214 if (IS_PF(bp
) && SHMEM2_HAS(bp
, drv_capabilities_flag
)) {
14218 drv_capabilities_flag
[BP_FW_MB_IDX(bp
)]);
14219 SHMEM2_WR(bp
, drv_capabilities_flag
[BP_FW_MB_IDX(bp
)],
14220 v
& ~DRV_FLAGS_CAPABILITIES_LOADED_L2
);
14222 bnx2x_drain_tx_queues(bp
);
14223 bnx2x_send_unload_req(bp
, UNLOAD_RECOVERY
);
14224 bnx2x_netif_stop(bp
, 1);
14225 bnx2x_free_irq(bp
);
14227 /* Report UNLOAD_DONE to MCP */
14228 bnx2x_send_unload_done(bp
, true);
14233 bnx2x_prev_unload(bp
);
14235 /* We should have reseted the engine, so It's fair to
14236 * assume the FW will no longer write to the bnx2x driver.
14238 bnx2x_squeeze_objects(bp
);
14239 bnx2x_free_skbs(bp
);
14240 for_each_rx_queue(bp
, i
)
14241 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
14242 bnx2x_free_fp_mem(bp
);
14243 bnx2x_free_mem(bp
);
14245 bp
->state
= BNX2X_STATE_CLOSED
;
14250 /* If AER, perform cleanup of the PCIe registers */
14251 if (bp
->flags
& AER_ENABLED
) {
14252 if (pci_cleanup_aer_uncorrect_error_status(pdev
))
14253 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14255 DP(NETIF_MSG_HW
, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14258 return PCI_ERS_RESULT_RECOVERED
;
14262 * bnx2x_io_resume - called when traffic can start flowing again
14263 * @pdev: Pointer to PCI device
14265 * This callback is called when the error recovery driver tells us that
14266 * its OK to resume normal operation.
14268 static void bnx2x_io_resume(struct pci_dev
*pdev
)
14270 struct net_device
*dev
= pci_get_drvdata(pdev
);
14271 struct bnx2x
*bp
= netdev_priv(dev
);
14273 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
14274 netdev_err(bp
->dev
, "Handling parity error recovery. Try again later\n");
14280 bp
->fw_seq
= SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
14281 DRV_MSG_SEQ_NUMBER_MASK
;
14283 if (netif_running(dev
))
14284 bnx2x_nic_load(bp
, LOAD_NORMAL
);
14286 netif_device_attach(dev
);
14291 static const struct pci_error_handlers bnx2x_err_handler
= {
14292 .error_detected
= bnx2x_io_error_detected
,
14293 .slot_reset
= bnx2x_io_slot_reset
,
14294 .resume
= bnx2x_io_resume
,
14297 static void bnx2x_shutdown(struct pci_dev
*pdev
)
14299 struct net_device
*dev
= pci_get_drvdata(pdev
);
14305 bp
= netdev_priv(dev
);
14310 netif_device_detach(dev
);
14313 /* Don't remove the netdevice, as there are scenarios which will cause
14314 * the kernel to hang, e.g., when trying to remove bnx2i while the
14315 * rootfs is mounted from SAN.
14317 __bnx2x_remove(pdev
, dev
, bp
, false);
14320 static struct pci_driver bnx2x_pci_driver
= {
14321 .name
= DRV_MODULE_NAME
,
14322 .id_table
= bnx2x_pci_tbl
,
14323 .probe
= bnx2x_init_one
,
14324 .remove
= bnx2x_remove_one
,
14325 .suspend
= bnx2x_suspend
,
14326 .resume
= bnx2x_resume
,
14327 .err_handler
= &bnx2x_err_handler
,
14328 #ifdef CONFIG_BNX2X_SRIOV
14329 .sriov_configure
= bnx2x_sriov_configure
,
14331 .shutdown
= bnx2x_shutdown
,
14334 static int __init
bnx2x_init(void)
14338 pr_info("%s", version
);
14340 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
14341 if (bnx2x_wq
== NULL
) {
14342 pr_err("Cannot create workqueue\n");
14345 bnx2x_iov_wq
= create_singlethread_workqueue("bnx2x_iov");
14346 if (!bnx2x_iov_wq
) {
14347 pr_err("Cannot create iov workqueue\n");
14348 destroy_workqueue(bnx2x_wq
);
14352 ret
= pci_register_driver(&bnx2x_pci_driver
);
14354 pr_err("Cannot register driver\n");
14355 destroy_workqueue(bnx2x_wq
);
14356 destroy_workqueue(bnx2x_iov_wq
);
14361 static void __exit
bnx2x_cleanup(void)
14363 struct list_head
*pos
, *q
;
14365 pci_unregister_driver(&bnx2x_pci_driver
);
14367 destroy_workqueue(bnx2x_wq
);
14368 destroy_workqueue(bnx2x_iov_wq
);
14370 /* Free globally allocated resources */
14371 list_for_each_safe(pos
, q
, &bnx2x_prev_list
) {
14372 struct bnx2x_prev_path_list
*tmp
=
14373 list_entry(pos
, struct bnx2x_prev_path_list
, list
);
14379 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
14381 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
14384 module_init(bnx2x_init
);
14385 module_exit(bnx2x_cleanup
);
14388 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14390 * @bp: driver handle
14391 * @set: set or clear the CAM entry
14393 * This function will wait until the ramrod completion returns.
14394 * Return 0 if success, -ENODEV if ramrod doesn't return.
14396 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
14398 unsigned long ramrod_flags
= 0;
14400 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
14401 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
14402 &bp
->iscsi_l2_mac_obj
, true,
14403 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
14406 /* count denotes the number of new completions we have seen */
14407 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
14409 struct eth_spe
*spe
;
14410 int cxt_index
, cxt_offset
;
14412 #ifdef BNX2X_STOP_ON_ERROR
14413 if (unlikely(bp
->panic
))
14417 spin_lock_bh(&bp
->spq_lock
);
14418 BUG_ON(bp
->cnic_spq_pending
< count
);
14419 bp
->cnic_spq_pending
-= count
;
14421 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
14422 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
14423 & SPE_HDR_CONN_TYPE
) >>
14424 SPE_HDR_CONN_TYPE_SHIFT
;
14425 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
14426 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
14428 /* Set validation for iSCSI L2 client before sending SETUP
14431 if (type
== ETH_CONNECTION_TYPE
) {
14432 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
) {
14433 cxt_index
= BNX2X_ISCSI_ETH_CID(bp
) /
14435 cxt_offset
= BNX2X_ISCSI_ETH_CID(bp
) -
14436 (cxt_index
* ILT_PAGE_CIDS
);
14437 bnx2x_set_ctx_validation(bp
,
14438 &bp
->context
[cxt_index
].
14439 vcxt
[cxt_offset
].eth
,
14440 BNX2X_ISCSI_ETH_CID(bp
));
14445 * There may be not more than 8 L2, not more than 8 L5 SPEs
14446 * and in the air. We also check that number of outstanding
14447 * COMMON ramrods is not more than the EQ and SPQ can
14450 if (type
== ETH_CONNECTION_TYPE
) {
14451 if (!atomic_read(&bp
->cq_spq_left
))
14454 atomic_dec(&bp
->cq_spq_left
);
14455 } else if (type
== NONE_CONNECTION_TYPE
) {
14456 if (!atomic_read(&bp
->eq_spq_left
))
14459 atomic_dec(&bp
->eq_spq_left
);
14460 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
14461 (type
== FCOE_CONNECTION_TYPE
)) {
14462 if (bp
->cnic_spq_pending
>=
14463 bp
->cnic_eth_dev
.max_kwqe_pending
)
14466 bp
->cnic_spq_pending
++;
14468 BNX2X_ERR("Unknown SPE type: %d\n", type
);
14473 spe
= bnx2x_sp_get_next(bp
);
14474 *spe
= *bp
->cnic_kwq_cons
;
14476 DP(BNX2X_MSG_SP
, "pending on SPQ %d, on KWQ %d count %d\n",
14477 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
14479 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
14480 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
14482 bp
->cnic_kwq_cons
++;
14484 bnx2x_sp_prod_update(bp
);
14485 spin_unlock_bh(&bp
->spq_lock
);
14488 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
14489 struct kwqe_16
*kwqes
[], u32 count
)
14491 struct bnx2x
*bp
= netdev_priv(dev
);
14494 #ifdef BNX2X_STOP_ON_ERROR
14495 if (unlikely(bp
->panic
)) {
14496 BNX2X_ERR("Can't post to SP queue while panic\n");
14501 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
14502 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
14503 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14507 spin_lock_bh(&bp
->spq_lock
);
14509 for (i
= 0; i
< count
; i
++) {
14510 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
14512 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
14515 *bp
->cnic_kwq_prod
= *spe
;
14517 bp
->cnic_kwq_pending
++;
14519 DP(BNX2X_MSG_SP
, "L5 SPQE %x %x %x:%x pos %d\n",
14520 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
14521 spe
->data
.update_data_addr
.hi
,
14522 spe
->data
.update_data_addr
.lo
,
14523 bp
->cnic_kwq_pending
);
14525 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
14526 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
14528 bp
->cnic_kwq_prod
++;
14531 spin_unlock_bh(&bp
->spq_lock
);
14533 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
14534 bnx2x_cnic_sp_post(bp
, 0);
14539 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
14541 struct cnic_ops
*c_ops
;
14544 mutex_lock(&bp
->cnic_mutex
);
14545 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
14546 lockdep_is_held(&bp
->cnic_mutex
));
14548 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
14549 mutex_unlock(&bp
->cnic_mutex
);
14554 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
14556 struct cnic_ops
*c_ops
;
14560 c_ops
= rcu_dereference(bp
->cnic_ops
);
14562 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
14569 * for commands that have no data
14571 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
14573 struct cnic_ctl_info ctl
= {0};
14577 return bnx2x_cnic_ctl_send(bp
, &ctl
);
14580 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
14582 struct cnic_ctl_info ctl
= {0};
14584 /* first we tell CNIC and only then we count this as a completion */
14585 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
14586 ctl
.data
.comp
.cid
= cid
;
14587 ctl
.data
.comp
.error
= err
;
14589 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
14590 bnx2x_cnic_sp_post(bp
, 0);
14593 /* Called with netif_addr_lock_bh() taken.
14594 * Sets an rx_mode config for an iSCSI ETH client.
14596 * Completion should be checked outside.
14598 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
14600 unsigned long accept_flags
= 0, ramrod_flags
= 0;
14601 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
14602 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
14605 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14606 * because it's the only way for UIO Queue to accept
14607 * multicasts (in non-promiscuous mode only one Queue per
14608 * function will receive multicast packets (leading in our
14611 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
14612 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
14613 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
14614 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
14616 /* Clear STOP_PENDING bit if START is requested */
14617 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
14619 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
14621 /* Clear START_PENDING bit if STOP is requested */
14622 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
14624 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
14625 set_bit(sched_state
, &bp
->sp_state
);
14627 __set_bit(RAMROD_RX
, &ramrod_flags
);
14628 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
14633 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
14635 struct bnx2x
*bp
= netdev_priv(dev
);
14638 switch (ctl
->cmd
) {
14639 case DRV_CTL_CTXTBL_WR_CMD
: {
14640 u32 index
= ctl
->data
.io
.offset
;
14641 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
14643 bnx2x_ilt_wr(bp
, index
, addr
);
14647 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
14648 int count
= ctl
->data
.credit
.credit_count
;
14650 bnx2x_cnic_sp_post(bp
, count
);
14654 /* rtnl_lock is held. */
14655 case DRV_CTL_START_L2_CMD
: {
14656 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14657 unsigned long sp_bits
= 0;
14659 /* Configure the iSCSI classification object */
14660 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
14661 cp
->iscsi_l2_client_id
,
14662 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
14663 bnx2x_sp(bp
, mac_rdata
),
14664 bnx2x_sp_mapping(bp
, mac_rdata
),
14665 BNX2X_FILTER_MAC_PENDING
,
14666 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
14669 /* Set iSCSI MAC address */
14670 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
14677 /* Start accepting on iSCSI L2 ring */
14679 netif_addr_lock_bh(dev
);
14680 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
14681 netif_addr_unlock_bh(dev
);
14683 /* bits to wait on */
14684 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
14685 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
14687 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
14688 BNX2X_ERR("rx_mode completion timed out!\n");
14693 /* rtnl_lock is held. */
14694 case DRV_CTL_STOP_L2_CMD
: {
14695 unsigned long sp_bits
= 0;
14697 /* Stop accepting on iSCSI L2 ring */
14698 netif_addr_lock_bh(dev
);
14699 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
14700 netif_addr_unlock_bh(dev
);
14702 /* bits to wait on */
14703 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
14704 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
14706 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
14707 BNX2X_ERR("rx_mode completion timed out!\n");
14712 /* Unset iSCSI L2 MAC */
14713 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
14714 BNX2X_ISCSI_ETH_MAC
, true);
14717 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
14718 int count
= ctl
->data
.credit
.credit_count
;
14720 smp_mb__before_atomic();
14721 atomic_add(count
, &bp
->cq_spq_left
);
14722 smp_mb__after_atomic();
14725 case DRV_CTL_ULP_REGISTER_CMD
: {
14726 int ulp_type
= ctl
->data
.register_data
.ulp_type
;
14728 if (CHIP_IS_E3(bp
)) {
14729 int idx
= BP_FW_MB_IDX(bp
);
14730 u32 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
14731 int path
= BP_PATH(bp
);
14732 int port
= BP_PORT(bp
);
14734 u32 scratch_offset
;
14737 /* first write capability to shmem2 */
14738 if (ulp_type
== CNIC_ULP_ISCSI
)
14739 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
14740 else if (ulp_type
== CNIC_ULP_FCOE
)
14741 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
14742 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
14744 if ((ulp_type
!= CNIC_ULP_FCOE
) ||
14745 (!SHMEM2_HAS(bp
, ncsi_oem_data_addr
)) ||
14746 (!(bp
->flags
& BC_SUPPORTS_FCOE_FEATURES
)))
14749 /* if reached here - should write fcoe capabilities */
14750 scratch_offset
= SHMEM2_RD(bp
, ncsi_oem_data_addr
);
14751 if (!scratch_offset
)
14753 scratch_offset
+= offsetof(struct glob_ncsi_oem_data
,
14754 fcoe_features
[path
][port
]);
14755 host_addr
= (u32
*) &(ctl
->data
.register_data
.
14757 for (i
= 0; i
< sizeof(struct fcoe_capabilities
);
14759 REG_WR(bp
, scratch_offset
+ i
,
14760 *(host_addr
+ i
/4));
14762 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14766 case DRV_CTL_ULP_UNREGISTER_CMD
: {
14767 int ulp_type
= ctl
->data
.ulp_type
;
14769 if (CHIP_IS_E3(bp
)) {
14770 int idx
= BP_FW_MB_IDX(bp
);
14773 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
14774 if (ulp_type
== CNIC_ULP_ISCSI
)
14775 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
14776 else if (ulp_type
== CNIC_ULP_FCOE
)
14777 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
14778 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
14780 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14785 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
14789 /* For storage-only interfaces, change driver state */
14790 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp
)) {
14791 switch (ctl
->drv_state
) {
14795 bnx2x_set_os_driver_state(bp
,
14796 OS_DRIVER_STATE_ACTIVE
);
14799 bnx2x_set_os_driver_state(bp
,
14800 OS_DRIVER_STATE_DISABLED
);
14803 bnx2x_set_os_driver_state(bp
,
14804 OS_DRIVER_STATE_NOT_LOADED
);
14807 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl
->drv_state
);
14814 static int bnx2x_get_fc_npiv(struct net_device
*dev
,
14815 struct cnic_fc_npiv_tbl
*cnic_tbl
)
14817 struct bnx2x
*bp
= netdev_priv(dev
);
14818 struct bdn_fc_npiv_tbl
*tbl
= NULL
;
14819 u32 offset
, entries
;
14823 if (!SHMEM2_HAS(bp
, fc_npiv_nvram_tbl_addr
[0]))
14826 DP(BNX2X_MSG_MCP
, "About to read the FC-NPIV table\n");
14828 tbl
= kmalloc(sizeof(*tbl
), GFP_KERNEL
);
14830 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14834 offset
= SHMEM2_RD(bp
, fc_npiv_nvram_tbl_addr
[BP_PORT(bp
)]);
14836 DP(BNX2X_MSG_MCP
, "No FC-NPIV in NVRAM\n");
14839 DP(BNX2X_MSG_MCP
, "Offset of FC-NPIV in NVRAM: %08x\n", offset
);
14841 /* Read the table contents from nvram */
14842 if (bnx2x_nvram_read(bp
, offset
, (u8
*)tbl
, sizeof(*tbl
))) {
14843 BNX2X_ERR("Failed to read FC-NPIV table\n");
14847 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14848 * the number of entries back to cpu endianness.
14850 entries
= tbl
->fc_npiv_cfg
.num_of_npiv
;
14851 entries
= (__force u32
)be32_to_cpu((__force __be32
)entries
);
14852 tbl
->fc_npiv_cfg
.num_of_npiv
= entries
;
14854 if (!tbl
->fc_npiv_cfg
.num_of_npiv
) {
14856 "No FC-NPIV table [valid, simply not present]\n");
14858 } else if (tbl
->fc_npiv_cfg
.num_of_npiv
> MAX_NUMBER_NPIV
) {
14859 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14860 tbl
->fc_npiv_cfg
.num_of_npiv
);
14863 DP(BNX2X_MSG_MCP
, "Read 0x%08x entries from NVRAM\n",
14864 tbl
->fc_npiv_cfg
.num_of_npiv
);
14867 /* Copy the data into cnic-provided struct */
14868 cnic_tbl
->count
= tbl
->fc_npiv_cfg
.num_of_npiv
;
14869 for (i
= 0; i
< cnic_tbl
->count
; i
++) {
14870 memcpy(cnic_tbl
->wwpn
[i
], tbl
->settings
[i
].npiv_wwpn
, 8);
14871 memcpy(cnic_tbl
->wwnn
[i
], tbl
->settings
[i
].npiv_wwnn
, 8);
14880 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
14882 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14884 if (bp
->flags
& USING_MSIX_FLAG
) {
14885 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
14886 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
14887 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
14889 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
14890 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
14892 if (!CHIP_IS_E1x(bp
))
14893 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
14895 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
14897 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
14898 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
14899 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
14900 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
14901 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
14906 void bnx2x_setup_cnic_info(struct bnx2x
*bp
)
14908 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14910 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
14911 bnx2x_cid_ilt_lines(bp
);
14912 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
14913 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
14914 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
14916 DP(NETIF_MSG_IFUP
, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14917 BNX2X_1st_NON_L2_ETH_CID(bp
), cp
->starting_cid
, cp
->fcoe_init_cid
,
14920 if (NO_ISCSI_OOO(bp
))
14921 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
14924 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
14927 struct bnx2x
*bp
= netdev_priv(dev
);
14928 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14931 DP(NETIF_MSG_IFUP
, "Register_cnic called\n");
14934 BNX2X_ERR("NULL ops received\n");
14938 if (!CNIC_SUPPORT(bp
)) {
14939 BNX2X_ERR("Can't register CNIC when not supported\n");
14940 return -EOPNOTSUPP
;
14943 if (!CNIC_LOADED(bp
)) {
14944 rc
= bnx2x_load_cnic(bp
);
14946 BNX2X_ERR("CNIC-related load failed\n");
14951 bp
->cnic_enabled
= true;
14953 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
14957 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
14958 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
14959 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
14961 bp
->cnic_spq_pending
= 0;
14962 bp
->cnic_kwq_pending
= 0;
14964 bp
->cnic_data
= data
;
14967 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
14968 cp
->iro_arr
= bp
->iro_arr
;
14970 bnx2x_setup_cnic_irq_info(bp
);
14972 rcu_assign_pointer(bp
->cnic_ops
, ops
);
14974 /* Schedule driver to read CNIC driver versions */
14975 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14980 static int bnx2x_unregister_cnic(struct net_device
*dev
)
14982 struct bnx2x
*bp
= netdev_priv(dev
);
14983 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14985 mutex_lock(&bp
->cnic_mutex
);
14987 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
14988 mutex_unlock(&bp
->cnic_mutex
);
14990 bp
->cnic_enabled
= false;
14991 kfree(bp
->cnic_kwq
);
14992 bp
->cnic_kwq
= NULL
;
14997 static struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
14999 struct bnx2x
*bp
= netdev_priv(dev
);
15000 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15002 /* If both iSCSI and FCoE are disabled - return NULL in
15003 * order to indicate CNIC that it should not try to work
15004 * with this device.
15006 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
15009 cp
->drv_owner
= THIS_MODULE
;
15010 cp
->chip_id
= CHIP_ID(bp
);
15011 cp
->pdev
= bp
->pdev
;
15012 cp
->io_base
= bp
->regview
;
15013 cp
->io_base2
= bp
->doorbells
;
15014 cp
->max_kwqe_pending
= 8;
15015 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
15016 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
15017 bnx2x_cid_ilt_lines(bp
);
15018 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
15019 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
15020 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
15021 cp
->drv_ctl
= bnx2x_drv_ctl
;
15022 cp
->drv_get_fc_npiv_tbl
= bnx2x_get_fc_npiv
;
15023 cp
->drv_register_cnic
= bnx2x_register_cnic
;
15024 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
15025 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
15026 cp
->iscsi_l2_client_id
=
15027 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
15028 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
15030 if (NO_ISCSI_OOO(bp
))
15031 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
15034 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
15037 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
15040 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15042 cp
->ctx_tbl_offset
,
15048 static u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
)
15050 struct bnx2x
*bp
= fp
->bp
;
15051 u32 offset
= BAR_USTRORM_INTMEM
;
15054 return bnx2x_vf_ustorm_prods_offset(bp
, fp
);
15055 else if (!CHIP_IS_E1x(bp
))
15056 offset
+= USTORM_RX_PRODS_E2_OFFSET(fp
->cl_qzone_id
);
15058 offset
+= USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp
), fp
->cl_id
);
15063 /* called only on E1H or E2.
15064 * When pretending to be PF, the pretend value is the function number 0...7
15065 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15068 int bnx2x_pretend_func(struct bnx2x
*bp
, u16 pretend_func_val
)
15072 if (CHIP_IS_E1H(bp
) && pretend_func_val
>= E1H_FUNC_MAX
)
15075 /* get my own pretend register */
15076 pretend_reg
= bnx2x_get_pretend_reg(bp
);
15077 REG_WR(bp
, pretend_reg
, pretend_func_val
);
15078 REG_RD(bp
, pretend_reg
);
15082 static void bnx2x_ptp_task(struct work_struct
*work
)
15084 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, ptp_task
);
15085 int port
= BP_PORT(bp
);
15088 struct skb_shared_hwtstamps shhwtstamps
;
15090 /* Read Tx timestamp registers */
15091 val_seq
= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15092 NIG_REG_P0_TLLH_PTP_BUF_SEQID
);
15093 if (val_seq
& 0x10000) {
15094 /* There is a valid timestamp value */
15095 timestamp
= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB
:
15096 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB
);
15098 timestamp
|= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB
:
15099 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB
);
15100 /* Reset timestamp register to allow new timestamp */
15101 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15102 NIG_REG_P0_TLLH_PTP_BUF_SEQID
, 0x10000);
15103 ns
= timecounter_cyc2time(&bp
->timecounter
, timestamp
);
15105 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
15106 shhwtstamps
.hwtstamp
= ns_to_ktime(ns
);
15107 skb_tstamp_tx(bp
->ptp_tx_skb
, &shhwtstamps
);
15108 dev_kfree_skb_any(bp
->ptp_tx_skb
);
15109 bp
->ptp_tx_skb
= NULL
;
15111 DP(BNX2X_MSG_PTP
, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15114 DP(BNX2X_MSG_PTP
, "There is no valid Tx timestamp yet\n");
15115 /* Reschedule to keep checking for a valid timestamp value */
15116 schedule_work(&bp
->ptp_task
);
15120 void bnx2x_set_rx_ts(struct bnx2x
*bp
, struct sk_buff
*skb
)
15122 int port
= BP_PORT(bp
);
15125 timestamp
= REG_RD(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB
:
15126 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB
);
15128 timestamp
|= REG_RD(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB
:
15129 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB
);
15131 /* Reset timestamp register to allow new timestamp */
15132 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID
:
15133 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID
, 0x10000);
15135 ns
= timecounter_cyc2time(&bp
->timecounter
, timestamp
);
15137 skb_hwtstamps(skb
)->hwtstamp
= ns_to_ktime(ns
);
15139 DP(BNX2X_MSG_PTP
, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15144 static cycle_t
bnx2x_cyclecounter_read(const struct cyclecounter
*cc
)
15146 struct bnx2x
*bp
= container_of(cc
, struct bnx2x
, cyclecounter
);
15147 int port
= BP_PORT(bp
);
15151 REG_RD_DMAE(bp
, port
? NIG_REG_TIMESYNC_GEN_REG
+ tsgen_synctime_t1
:
15152 NIG_REG_TIMESYNC_GEN_REG
+ tsgen_synctime_t0
, wb_data
, 2);
15153 phc_cycles
= wb_data
[1];
15154 phc_cycles
= (phc_cycles
<< 32) + wb_data
[0];
15156 DP(BNX2X_MSG_PTP
, "PHC read cycles = %llu\n", phc_cycles
);
15161 static void bnx2x_init_cyclecounter(struct bnx2x
*bp
)
15163 memset(&bp
->cyclecounter
, 0, sizeof(bp
->cyclecounter
));
15164 bp
->cyclecounter
.read
= bnx2x_cyclecounter_read
;
15165 bp
->cyclecounter
.mask
= CYCLECOUNTER_MASK(64);
15166 bp
->cyclecounter
.shift
= 1;
15167 bp
->cyclecounter
.mult
= 1;
15170 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x
*bp
)
15172 struct bnx2x_func_state_params func_params
= {NULL
};
15173 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
15174 &func_params
.params
.set_timesync
;
15176 /* Prepare parameters for function state transitions */
15177 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
15178 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
15180 func_params
.f_obj
= &bp
->func_obj
;
15181 func_params
.cmd
= BNX2X_F_CMD_SET_TIMESYNC
;
15183 /* Function parameters */
15184 set_timesync_params
->drift_adjust_cmd
= TS_DRIFT_ADJUST_RESET
;
15185 set_timesync_params
->offset_cmd
= TS_OFFSET_KEEP
;
15187 return bnx2x_func_state_change(bp
, &func_params
);
15190 static int bnx2x_enable_ptp_packets(struct bnx2x
*bp
)
15192 struct bnx2x_queue_state_params q_params
;
15195 /* send queue update ramrod to enable PTP packets */
15196 memset(&q_params
, 0, sizeof(q_params
));
15197 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
15198 q_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
15199 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG
,
15200 &q_params
.params
.update
.update_flags
);
15201 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS
,
15202 &q_params
.params
.update
.update_flags
);
15204 /* send the ramrod on all the queues of the PF */
15205 for_each_eth_queue(bp
, i
) {
15206 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
15208 /* Set the appropriate Queue object */
15209 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
15211 /* Update the Queue state */
15212 rc
= bnx2x_queue_state_change(bp
, &q_params
);
15214 BNX2X_ERR("Failed to enable PTP packets\n");
15222 int bnx2x_configure_ptp_filters(struct bnx2x
*bp
)
15224 int port
= BP_PORT(bp
);
15227 if (!bp
->hwtstamp_ioctl_called
)
15230 switch (bp
->tx_type
) {
15231 case HWTSTAMP_TX_ON
:
15232 bp
->flags
|= TX_TIMESTAMPING_EN
;
15233 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
15234 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x6AA);
15235 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
15236 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3EEE);
15238 case HWTSTAMP_TX_ONESTEP_SYNC
:
15239 BNX2X_ERR("One-step timestamping is not supported\n");
15243 switch (bp
->rx_filter
) {
15244 case HWTSTAMP_FILTER_NONE
:
15246 case HWTSTAMP_FILTER_ALL
:
15247 case HWTSTAMP_FILTER_SOME
:
15248 bp
->rx_filter
= HWTSTAMP_FILTER_NONE
;
15250 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
15251 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
15252 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
15253 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
15254 /* Initialize PTP detection for UDP/IPv4 events */
15255 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15256 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7EE);
15257 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15258 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFE);
15260 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
15261 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
15262 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
15263 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
15264 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15265 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15266 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7EA);
15267 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15268 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FEE);
15270 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
15271 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
15272 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
15273 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_EVENT
;
15274 /* Initialize PTP detection L2 events */
15275 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15276 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x6BF);
15277 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15278 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3EFF);
15281 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
15282 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
15283 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
15284 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
15285 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15286 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15287 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x6AA);
15288 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15289 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3EEE);
15293 /* Indicate to FW that this PF expects recorded PTP packets */
15294 rc
= bnx2x_enable_ptp_packets(bp
);
15298 /* Enable sending PTP packets to host */
15299 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
15300 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x1);
15305 static int bnx2x_hwtstamp_ioctl(struct bnx2x
*bp
, struct ifreq
*ifr
)
15307 struct hwtstamp_config config
;
15310 DP(BNX2X_MSG_PTP
, "HWTSTAMP IOCTL called\n");
15312 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
15315 DP(BNX2X_MSG_PTP
, "Requested tx_type: %d, requested rx_filters = %d\n",
15316 config
.tx_type
, config
.rx_filter
);
15318 if (config
.flags
) {
15319 BNX2X_ERR("config.flags is reserved for future use\n");
15323 bp
->hwtstamp_ioctl_called
= 1;
15324 bp
->tx_type
= config
.tx_type
;
15325 bp
->rx_filter
= config
.rx_filter
;
15327 rc
= bnx2x_configure_ptp_filters(bp
);
15331 config
.rx_filter
= bp
->rx_filter
;
15333 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
15337 /* Configures HW for PTP */
15338 static int bnx2x_configure_ptp(struct bnx2x
*bp
)
15340 int rc
, port
= BP_PORT(bp
);
15343 /* Reset PTP event detection rules - will be configured in the IOCTL */
15344 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15345 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7FF);
15346 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15347 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFF);
15348 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
15349 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x7FF);
15350 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
15351 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3FFF);
15353 /* Disable PTP packets to host - will be configured in the IOCTL*/
15354 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
15355 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x0);
15357 /* Enable the PTP feature */
15358 REG_WR(bp
, port
? NIG_REG_P1_PTP_EN
:
15359 NIG_REG_P0_PTP_EN
, 0x3F);
15361 /* Enable the free-running counter */
15364 REG_WR_DMAE(bp
, NIG_REG_TIMESYNC_GEN_REG
+ tsgen_ctrl
, wb_data
, 2);
15366 /* Reset drift register (offset register is not reset) */
15367 rc
= bnx2x_send_reset_timesync_ramrod(bp
);
15369 BNX2X_ERR("Failed to reset PHC drift register\n");
15373 /* Reset possibly old timestamps */
15374 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID
:
15375 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID
, 0x10000);
15376 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15377 NIG_REG_P0_TLLH_PTP_BUF_SEQID
, 0x10000);
15382 /* Called during load, to initialize PTP-related stuff */
15383 void bnx2x_init_ptp(struct bnx2x
*bp
)
15387 /* Configure PTP in HW */
15388 rc
= bnx2x_configure_ptp(bp
);
15390 BNX2X_ERR("Stopping PTP initialization\n");
15394 /* Init work queue for Tx timestamping */
15395 INIT_WORK(&bp
->ptp_task
, bnx2x_ptp_task
);
15397 /* Init cyclecounter and timecounter. This is done only in the first
15398 * load. If done in every load, PTP application will fail when doing
15399 * unload / load (e.g. MTU change) while it is running.
15401 if (!bp
->timecounter_init_done
) {
15402 bnx2x_init_cyclecounter(bp
);
15403 timecounter_init(&bp
->timecounter
, &bp
->cyclecounter
,
15404 ktime_to_ns(ktime_get_real()));
15405 bp
->timecounter_init_done
= 1;
15408 DP(BNX2X_MSG_PTP
, "PTP initialization ended successfully\n");