1 /* bnx2x_sp.c: Qlogic Everest network driver.
3 * Copyright 2011-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * Unless you and Qlogic execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2, available
10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
12 * Notwithstanding the above, under no circumstances may you combine this
13 * software in any way with any other Qlogic software provided under a
14 * license other than the GPL, without Qlogic's express prior written
17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
18 * Written by: Vladislav Zolotarov
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/module.h>
25 #include <linux/crc32.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/crc32c.h>
30 #include "bnx2x_cmn.h"
33 #define BNX2X_MAX_EMUL_MULTI 16
35 /**** Exe Queue interfaces ****/
38 * bnx2x_exe_queue_init - init the Exe Queue object
40 * @o: pointer to the object
42 * @owner: pointer to the owner
43 * @validate: validate function pointer
44 * @optimize: optimize function pointer
45 * @exec: execute function pointer
46 * @get: get function pointer
48 static inline void bnx2x_exe_queue_init(struct bnx2x
*bp
,
49 struct bnx2x_exe_queue_obj
*o
,
51 union bnx2x_qable_obj
*owner
,
52 exe_q_validate validate
,
54 exe_q_optimize optimize
,
58 memset(o
, 0, sizeof(*o
));
60 INIT_LIST_HEAD(&o
->exe_queue
);
61 INIT_LIST_HEAD(&o
->pending_comp
);
63 spin_lock_init(&o
->lock
);
65 o
->exe_chunk_len
= exe_len
;
68 /* Owner specific callbacks */
69 o
->validate
= validate
;
71 o
->optimize
= optimize
;
75 DP(BNX2X_MSG_SP
, "Setup the execution queue with the chunk length of %d\n",
79 static inline void bnx2x_exe_queue_free_elem(struct bnx2x
*bp
,
80 struct bnx2x_exeq_elem
*elem
)
82 DP(BNX2X_MSG_SP
, "Deleting an exe_queue element\n");
86 static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj
*o
)
88 struct bnx2x_exeq_elem
*elem
;
91 spin_lock_bh(&o
->lock
);
93 list_for_each_entry(elem
, &o
->exe_queue
, link
)
96 spin_unlock_bh(&o
->lock
);
102 * bnx2x_exe_queue_add - add a new element to the execution queue
106 * @cmd: new command to add
107 * @restore: true - do not optimize the command
109 * If the element is optimized or is illegal, frees it.
111 static inline int bnx2x_exe_queue_add(struct bnx2x
*bp
,
112 struct bnx2x_exe_queue_obj
*o
,
113 struct bnx2x_exeq_elem
*elem
,
118 spin_lock_bh(&o
->lock
);
121 /* Try to cancel this element queue */
122 rc
= o
->optimize(bp
, o
->owner
, elem
);
126 /* Check if this request is ok */
127 rc
= o
->validate(bp
, o
->owner
, elem
);
129 DP(BNX2X_MSG_SP
, "Preamble failed: %d\n", rc
);
134 /* If so, add it to the execution queue */
135 list_add_tail(&elem
->link
, &o
->exe_queue
);
137 spin_unlock_bh(&o
->lock
);
142 bnx2x_exe_queue_free_elem(bp
, elem
);
144 spin_unlock_bh(&o
->lock
);
149 static inline void __bnx2x_exe_queue_reset_pending(
151 struct bnx2x_exe_queue_obj
*o
)
153 struct bnx2x_exeq_elem
*elem
;
155 while (!list_empty(&o
->pending_comp
)) {
156 elem
= list_first_entry(&o
->pending_comp
,
157 struct bnx2x_exeq_elem
, link
);
159 list_del(&elem
->link
);
160 bnx2x_exe_queue_free_elem(bp
, elem
);
165 * bnx2x_exe_queue_step - execute one execution chunk atomically
169 * @ramrod_flags: flags
171 * (Should be called while holding the exe_queue->lock).
173 static inline int bnx2x_exe_queue_step(struct bnx2x
*bp
,
174 struct bnx2x_exe_queue_obj
*o
,
175 unsigned long *ramrod_flags
)
177 struct bnx2x_exeq_elem
*elem
, spacer
;
180 memset(&spacer
, 0, sizeof(spacer
));
182 /* Next step should not be performed until the current is finished,
183 * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to
184 * properly clear object internals without sending any command to the FW
185 * which also implies there won't be any completion to clear the
188 if (!list_empty(&o
->pending_comp
)) {
189 if (test_bit(RAMROD_DRV_CLR_ONLY
, ramrod_flags
)) {
190 DP(BNX2X_MSG_SP
, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
191 __bnx2x_exe_queue_reset_pending(bp
, o
);
197 /* Run through the pending commands list and create a next
200 while (!list_empty(&o
->exe_queue
)) {
201 elem
= list_first_entry(&o
->exe_queue
, struct bnx2x_exeq_elem
,
203 WARN_ON(!elem
->cmd_len
);
205 if (cur_len
+ elem
->cmd_len
<= o
->exe_chunk_len
) {
206 cur_len
+= elem
->cmd_len
;
207 /* Prevent from both lists being empty when moving an
208 * element. This will allow the call of
209 * bnx2x_exe_queue_empty() without locking.
211 list_add_tail(&spacer
.link
, &o
->pending_comp
);
213 list_move_tail(&elem
->link
, &o
->pending_comp
);
214 list_del(&spacer
.link
);
223 rc
= o
->execute(bp
, o
->owner
, &o
->pending_comp
, ramrod_flags
);
225 /* In case of an error return the commands back to the queue
226 * and reset the pending_comp.
228 list_splice_init(&o
->pending_comp
, &o
->exe_queue
);
230 /* If zero is returned, means there are no outstanding pending
231 * completions and we may dismiss the pending list.
233 __bnx2x_exe_queue_reset_pending(bp
, o
);
238 static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj
*o
)
240 bool empty
= list_empty(&o
->exe_queue
);
242 /* Don't reorder!!! */
245 return empty
&& list_empty(&o
->pending_comp
);
248 static inline struct bnx2x_exeq_elem
*bnx2x_exe_queue_alloc_elem(
251 DP(BNX2X_MSG_SP
, "Allocating a new exe_queue element\n");
252 return kzalloc(sizeof(struct bnx2x_exeq_elem
), GFP_ATOMIC
);
255 /************************ raw_obj functions ***********************************/
256 static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj
*o
)
258 return !!test_bit(o
->state
, o
->pstate
);
261 static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj
*o
)
263 smp_mb__before_atomic();
264 clear_bit(o
->state
, o
->pstate
);
265 smp_mb__after_atomic();
268 static void bnx2x_raw_set_pending(struct bnx2x_raw_obj
*o
)
270 smp_mb__before_atomic();
271 set_bit(o
->state
, o
->pstate
);
272 smp_mb__after_atomic();
276 * bnx2x_state_wait - wait until the given bit(state) is cleared
279 * @state: state which is to be cleared
280 * @state_p: state buffer
283 static inline int bnx2x_state_wait(struct bnx2x
*bp
, int state
,
284 unsigned long *pstate
)
286 /* can take a while if any port is running */
289 if (CHIP_REV_IS_EMUL(bp
))
292 DP(BNX2X_MSG_SP
, "waiting for state to become %d\n", state
);
296 if (!test_bit(state
, pstate
)) {
297 #ifdef BNX2X_STOP_ON_ERROR
298 DP(BNX2X_MSG_SP
, "exit (cnt %d)\n", 5000 - cnt
);
303 usleep_range(1000, 2000);
310 BNX2X_ERR("timeout waiting for state %d\n", state
);
311 #ifdef BNX2X_STOP_ON_ERROR
318 static int bnx2x_raw_wait(struct bnx2x
*bp
, struct bnx2x_raw_obj
*raw
)
320 return bnx2x_state_wait(bp
, raw
->state
, raw
->pstate
);
323 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
324 /* credit handling callbacks */
325 static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj
*o
, int *offset
)
327 struct bnx2x_credit_pool_obj
*mp
= o
->macs_pool
;
331 return mp
->get_entry(mp
, offset
);
334 static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj
*o
)
336 struct bnx2x_credit_pool_obj
*mp
= o
->macs_pool
;
340 return mp
->get(mp
, 1);
343 static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj
*o
, int *offset
)
345 struct bnx2x_credit_pool_obj
*vp
= o
->vlans_pool
;
349 return vp
->get_entry(vp
, offset
);
352 static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj
*o
)
354 struct bnx2x_credit_pool_obj
*vp
= o
->vlans_pool
;
358 return vp
->get(vp
, 1);
361 static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj
*o
)
363 struct bnx2x_credit_pool_obj
*mp
= o
->macs_pool
;
364 struct bnx2x_credit_pool_obj
*vp
= o
->vlans_pool
;
369 if (!vp
->get(vp
, 1)) {
377 static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj
*o
, int offset
)
379 struct bnx2x_credit_pool_obj
*mp
= o
->macs_pool
;
381 return mp
->put_entry(mp
, offset
);
384 static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj
*o
)
386 struct bnx2x_credit_pool_obj
*mp
= o
->macs_pool
;
388 return mp
->put(mp
, 1);
391 static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj
*o
, int offset
)
393 struct bnx2x_credit_pool_obj
*vp
= o
->vlans_pool
;
395 return vp
->put_entry(vp
, offset
);
398 static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj
*o
)
400 struct bnx2x_credit_pool_obj
*vp
= o
->vlans_pool
;
402 return vp
->put(vp
, 1);
405 static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj
*o
)
407 struct bnx2x_credit_pool_obj
*mp
= o
->macs_pool
;
408 struct bnx2x_credit_pool_obj
*vp
= o
->vlans_pool
;
413 if (!vp
->put(vp
, 1)) {
422 * __bnx2x_vlan_mac_h_write_trylock - try getting the vlan mac writer lock
425 * @o: vlan_mac object
427 * @details: Non-blocking implementation; should be called under execution
430 static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x
*bp
,
431 struct bnx2x_vlan_mac_obj
*o
)
433 if (o
->head_reader
) {
434 DP(BNX2X_MSG_SP
, "vlan_mac_lock writer - There are readers; Busy\n");
438 DP(BNX2X_MSG_SP
, "vlan_mac_lock writer - Taken\n");
443 * __bnx2x_vlan_mac_h_exec_pending - execute step instead of a previous step
446 * @o: vlan_mac object
448 * @details Should be called under execution queue lock; notice it might release
449 * and reclaim it during its run.
451 static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x
*bp
,
452 struct bnx2x_vlan_mac_obj
*o
)
455 unsigned long ramrod_flags
= o
->saved_ramrod_flags
;
457 DP(BNX2X_MSG_SP
, "vlan_mac_lock execute pending command with ramrod flags %lu\n",
459 o
->head_exe_request
= false;
460 o
->saved_ramrod_flags
= 0;
461 rc
= bnx2x_exe_queue_step(bp
, &o
->exe_queue
, &ramrod_flags
);
462 if ((rc
!= 0) && (rc
!= 1)) {
463 BNX2X_ERR("execution of pending commands failed with rc %d\n",
465 #ifdef BNX2X_STOP_ON_ERROR
472 * __bnx2x_vlan_mac_h_pend - Pend an execution step which couldn't run
475 * @o: vlan_mac object
476 * @ramrod_flags: ramrod flags of missed execution
478 * @details Should be called under execution queue lock.
480 static void __bnx2x_vlan_mac_h_pend(struct bnx2x
*bp
,
481 struct bnx2x_vlan_mac_obj
*o
,
482 unsigned long ramrod_flags
)
484 o
->head_exe_request
= true;
485 o
->saved_ramrod_flags
= ramrod_flags
;
486 DP(BNX2X_MSG_SP
, "Placing pending execution with ramrod flags %lu\n",
491 * __bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock
494 * @o: vlan_mac object
496 * @details Should be called under execution queue lock. Notice if a pending
497 * execution exists, it would perform it - possibly releasing and
498 * reclaiming the execution queue lock.
500 static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x
*bp
,
501 struct bnx2x_vlan_mac_obj
*o
)
503 /* It's possible a new pending execution was added since this writer
504 * executed. If so, execute again. [Ad infinitum]
506 while (o
->head_exe_request
) {
507 DP(BNX2X_MSG_SP
, "vlan_mac_lock - writer release encountered a pending request\n");
508 __bnx2x_vlan_mac_h_exec_pending(bp
, o
);
514 * __bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
517 * @o: vlan_mac object
519 * @details Should be called under the execution queue lock. May sleep. May
520 * release and reclaim execution queue lock during its run.
522 static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x
*bp
,
523 struct bnx2x_vlan_mac_obj
*o
)
525 /* If we got here, we're holding lock --> no WRITER exists */
527 DP(BNX2X_MSG_SP
, "vlan_mac_lock - locked reader - number %d\n",
534 * bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
537 * @o: vlan_mac object
539 * @details May sleep. Claims and releases execution queue lock during its run.
541 int bnx2x_vlan_mac_h_read_lock(struct bnx2x
*bp
,
542 struct bnx2x_vlan_mac_obj
*o
)
546 spin_lock_bh(&o
->exe_queue
.lock
);
547 rc
= __bnx2x_vlan_mac_h_read_lock(bp
, o
);
548 spin_unlock_bh(&o
->exe_queue
.lock
);
554 * __bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
557 * @o: vlan_mac object
559 * @details Should be called under execution queue lock. Notice if a pending
560 * execution exists, it would be performed if this was the last
561 * reader. possibly releasing and reclaiming the execution queue lock.
563 static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x
*bp
,
564 struct bnx2x_vlan_mac_obj
*o
)
566 if (!o
->head_reader
) {
567 BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n");
568 #ifdef BNX2X_STOP_ON_ERROR
573 DP(BNX2X_MSG_SP
, "vlan_mac_lock - decreased readers to %d\n",
577 /* It's possible a new pending execution was added, and that this reader
578 * was last - if so we need to execute the command.
580 if (!o
->head_reader
&& o
->head_exe_request
) {
581 DP(BNX2X_MSG_SP
, "vlan_mac_lock - reader release encountered a pending request\n");
583 /* Writer release will do the trick */
584 __bnx2x_vlan_mac_h_write_unlock(bp
, o
);
589 * bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
592 * @o: vlan_mac object
594 * @details Notice if a pending execution exists, it would be performed if this
595 * was the last reader. Claims and releases the execution queue lock
598 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x
*bp
,
599 struct bnx2x_vlan_mac_obj
*o
)
601 spin_lock_bh(&o
->exe_queue
.lock
);
602 __bnx2x_vlan_mac_h_read_unlock(bp
, o
);
603 spin_unlock_bh(&o
->exe_queue
.lock
);
606 static int bnx2x_get_n_elements(struct bnx2x
*bp
, struct bnx2x_vlan_mac_obj
*o
,
607 int n
, u8
*base
, u8 stride
, u8 size
)
609 struct bnx2x_vlan_mac_registry_elem
*pos
;
614 DP(BNX2X_MSG_SP
, "get_n_elements - taking vlan_mac_lock (reader)\n");
615 read_lock
= bnx2x_vlan_mac_h_read_lock(bp
, o
);
617 BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n");
620 list_for_each_entry(pos
, &o
->head
, link
) {
622 memcpy(next
, &pos
->u
, size
);
624 DP(BNX2X_MSG_SP
, "copied element number %d to address %p element was:\n",
626 next
+= stride
+ size
;
630 if (read_lock
== 0) {
631 DP(BNX2X_MSG_SP
, "get_n_elements - releasing vlan_mac_lock (reader)\n");
632 bnx2x_vlan_mac_h_read_unlock(bp
, o
);
635 return counter
* ETH_ALEN
;
638 /* check_add() callbacks */
639 static int bnx2x_check_mac_add(struct bnx2x
*bp
,
640 struct bnx2x_vlan_mac_obj
*o
,
641 union bnx2x_classification_ramrod_data
*data
)
643 struct bnx2x_vlan_mac_registry_elem
*pos
;
645 DP(BNX2X_MSG_SP
, "Checking MAC %pM for ADD command\n", data
->mac
.mac
);
647 if (!is_valid_ether_addr(data
->mac
.mac
))
650 /* Check if a requested MAC already exists */
651 list_for_each_entry(pos
, &o
->head
, link
)
652 if (ether_addr_equal(data
->mac
.mac
, pos
->u
.mac
.mac
) &&
653 (data
->mac
.is_inner_mac
== pos
->u
.mac
.is_inner_mac
))
659 static int bnx2x_check_vlan_add(struct bnx2x
*bp
,
660 struct bnx2x_vlan_mac_obj
*o
,
661 union bnx2x_classification_ramrod_data
*data
)
663 struct bnx2x_vlan_mac_registry_elem
*pos
;
665 DP(BNX2X_MSG_SP
, "Checking VLAN %d for ADD command\n", data
->vlan
.vlan
);
667 list_for_each_entry(pos
, &o
->head
, link
)
668 if (data
->vlan
.vlan
== pos
->u
.vlan
.vlan
)
674 static int bnx2x_check_vlan_mac_add(struct bnx2x
*bp
,
675 struct bnx2x_vlan_mac_obj
*o
,
676 union bnx2x_classification_ramrod_data
*data
)
678 struct bnx2x_vlan_mac_registry_elem
*pos
;
680 DP(BNX2X_MSG_SP
, "Checking VLAN_MAC (%pM, %d) for ADD command\n",
681 data
->vlan_mac
.mac
, data
->vlan_mac
.vlan
);
683 list_for_each_entry(pos
, &o
->head
, link
)
684 if ((data
->vlan_mac
.vlan
== pos
->u
.vlan_mac
.vlan
) &&
685 (!memcmp(data
->vlan_mac
.mac
, pos
->u
.vlan_mac
.mac
,
687 (data
->vlan_mac
.is_inner_mac
==
688 pos
->u
.vlan_mac
.is_inner_mac
))
694 /* check_del() callbacks */
695 static struct bnx2x_vlan_mac_registry_elem
*
696 bnx2x_check_mac_del(struct bnx2x
*bp
,
697 struct bnx2x_vlan_mac_obj
*o
,
698 union bnx2x_classification_ramrod_data
*data
)
700 struct bnx2x_vlan_mac_registry_elem
*pos
;
702 DP(BNX2X_MSG_SP
, "Checking MAC %pM for DEL command\n", data
->mac
.mac
);
704 list_for_each_entry(pos
, &o
->head
, link
)
705 if (ether_addr_equal(data
->mac
.mac
, pos
->u
.mac
.mac
) &&
706 (data
->mac
.is_inner_mac
== pos
->u
.mac
.is_inner_mac
))
712 static struct bnx2x_vlan_mac_registry_elem
*
713 bnx2x_check_vlan_del(struct bnx2x
*bp
,
714 struct bnx2x_vlan_mac_obj
*o
,
715 union bnx2x_classification_ramrod_data
*data
)
717 struct bnx2x_vlan_mac_registry_elem
*pos
;
719 DP(BNX2X_MSG_SP
, "Checking VLAN %d for DEL command\n", data
->vlan
.vlan
);
721 list_for_each_entry(pos
, &o
->head
, link
)
722 if (data
->vlan
.vlan
== pos
->u
.vlan
.vlan
)
728 static struct bnx2x_vlan_mac_registry_elem
*
729 bnx2x_check_vlan_mac_del(struct bnx2x
*bp
,
730 struct bnx2x_vlan_mac_obj
*o
,
731 union bnx2x_classification_ramrod_data
*data
)
733 struct bnx2x_vlan_mac_registry_elem
*pos
;
735 DP(BNX2X_MSG_SP
, "Checking VLAN_MAC (%pM, %d) for DEL command\n",
736 data
->vlan_mac
.mac
, data
->vlan_mac
.vlan
);
738 list_for_each_entry(pos
, &o
->head
, link
)
739 if ((data
->vlan_mac
.vlan
== pos
->u
.vlan_mac
.vlan
) &&
740 (!memcmp(data
->vlan_mac
.mac
, pos
->u
.vlan_mac
.mac
,
742 (data
->vlan_mac
.is_inner_mac
==
743 pos
->u
.vlan_mac
.is_inner_mac
))
749 /* check_move() callback */
750 static bool bnx2x_check_move(struct bnx2x
*bp
,
751 struct bnx2x_vlan_mac_obj
*src_o
,
752 struct bnx2x_vlan_mac_obj
*dst_o
,
753 union bnx2x_classification_ramrod_data
*data
)
755 struct bnx2x_vlan_mac_registry_elem
*pos
;
758 /* Check if we can delete the requested configuration from the first
761 pos
= src_o
->check_del(bp
, src_o
, data
);
763 /* check if configuration can be added */
764 rc
= dst_o
->check_add(bp
, dst_o
, data
);
766 /* If this classification can not be added (is already set)
767 * or can't be deleted - return an error.
775 static bool bnx2x_check_move_always_err(
777 struct bnx2x_vlan_mac_obj
*src_o
,
778 struct bnx2x_vlan_mac_obj
*dst_o
,
779 union bnx2x_classification_ramrod_data
*data
)
784 static inline u8
bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj
*o
)
786 struct bnx2x_raw_obj
*raw
= &o
->raw
;
789 if ((raw
->obj_type
== BNX2X_OBJ_TYPE_TX
) ||
790 (raw
->obj_type
== BNX2X_OBJ_TYPE_RX_TX
))
791 rx_tx_flag
|= ETH_CLASSIFY_CMD_HEADER_TX_CMD
;
793 if ((raw
->obj_type
== BNX2X_OBJ_TYPE_RX
) ||
794 (raw
->obj_type
== BNX2X_OBJ_TYPE_RX_TX
))
795 rx_tx_flag
|= ETH_CLASSIFY_CMD_HEADER_RX_CMD
;
800 static void bnx2x_set_mac_in_nig(struct bnx2x
*bp
,
801 bool add
, unsigned char *dev_addr
, int index
)
804 u32 reg_offset
= BP_PORT(bp
) ? NIG_REG_LLH1_FUNC_MEM
:
805 NIG_REG_LLH0_FUNC_MEM
;
807 if (!IS_MF_SI(bp
) && !IS_MF_AFEX(bp
))
810 if (index
> BNX2X_LLH_CAM_MAX_PF_LINE
)
813 DP(BNX2X_MSG_SP
, "Going to %s LLH configuration at entry %d\n",
814 (add
? "ADD" : "DELETE"), index
);
817 /* LLH_FUNC_MEM is a u64 WB register */
818 reg_offset
+= 8*index
;
820 wb_data
[0] = ((dev_addr
[2] << 24) | (dev_addr
[3] << 16) |
821 (dev_addr
[4] << 8) | dev_addr
[5]);
822 wb_data
[1] = ((dev_addr
[0] << 8) | dev_addr
[1]);
824 REG_WR_DMAE(bp
, reg_offset
, wb_data
, 2);
827 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_FUNC_MEM_ENABLE
:
828 NIG_REG_LLH0_FUNC_MEM_ENABLE
) + 4*index
, add
);
832 * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod
835 * @o: queue for which we want to configure this rule
836 * @add: if true the command is an ADD command, DEL otherwise
837 * @opcode: CLASSIFY_RULE_OPCODE_XXX
838 * @hdr: pointer to a header to setup
841 static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x
*bp
,
842 struct bnx2x_vlan_mac_obj
*o
, bool add
, int opcode
,
843 struct eth_classify_cmd_header
*hdr
)
845 struct bnx2x_raw_obj
*raw
= &o
->raw
;
847 hdr
->client_id
= raw
->cl_id
;
848 hdr
->func_id
= raw
->func_id
;
850 /* Rx or/and Tx (internal switching) configuration ? */
851 hdr
->cmd_general_data
|=
852 bnx2x_vlan_mac_get_rx_tx_flag(o
);
855 hdr
->cmd_general_data
|= ETH_CLASSIFY_CMD_HEADER_IS_ADD
;
857 hdr
->cmd_general_data
|=
858 (opcode
<< ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT
);
862 * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header
864 * @cid: connection id
865 * @type: BNX2X_FILTER_XXX_PENDING
866 * @hdr: pointer to header to setup
869 * currently we always configure one rule and echo field to contain a CID and an
872 static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid
, int type
,
873 struct eth_classify_header
*hdr
, int rule_cnt
)
875 hdr
->echo
= cpu_to_le32((cid
& BNX2X_SWCID_MASK
) |
876 (type
<< BNX2X_SWCID_SHIFT
));
877 hdr
->rule_cnt
= (u8
)rule_cnt
;
880 /* hw_config() callbacks */
881 static void bnx2x_set_one_mac_e2(struct bnx2x
*bp
,
882 struct bnx2x_vlan_mac_obj
*o
,
883 struct bnx2x_exeq_elem
*elem
, int rule_idx
,
886 struct bnx2x_raw_obj
*raw
= &o
->raw
;
887 struct eth_classify_rules_ramrod_data
*data
=
888 (struct eth_classify_rules_ramrod_data
*)(raw
->rdata
);
889 int rule_cnt
= rule_idx
+ 1, cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
890 union eth_classify_rule_cmd
*rule_entry
= &data
->rules
[rule_idx
];
891 bool add
= (cmd
== BNX2X_VLAN_MAC_ADD
) ? true : false;
892 unsigned long *vlan_mac_flags
= &elem
->cmd_data
.vlan_mac
.vlan_mac_flags
;
893 u8
*mac
= elem
->cmd_data
.vlan_mac
.u
.mac
.mac
;
895 /* Set LLH CAM entry: currently only iSCSI and ETH macs are
896 * relevant. In addition, current implementation is tuned for a
899 * When multiple unicast ETH MACs PF configuration in switch
900 * independent mode is required (NetQ, multiple netdev MACs,
901 * etc.), consider better utilisation of 8 per function MAC
902 * entries in the LLH register. There is also
903 * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the
904 * total number of CAM entries to 16.
906 * Currently we won't configure NIG for MACs other than a primary ETH
907 * MAC and iSCSI L2 MAC.
909 * If this MAC is moving from one Queue to another, no need to change
912 if (cmd
!= BNX2X_VLAN_MAC_MOVE
) {
913 if (test_bit(BNX2X_ISCSI_ETH_MAC
, vlan_mac_flags
))
914 bnx2x_set_mac_in_nig(bp
, add
, mac
,
915 BNX2X_LLH_CAM_ISCSI_ETH_LINE
);
916 else if (test_bit(BNX2X_ETH_MAC
, vlan_mac_flags
))
917 bnx2x_set_mac_in_nig(bp
, add
, mac
,
918 BNX2X_LLH_CAM_ETH_LINE
);
921 /* Reset the ramrod data buffer for the first rule */
923 memset(data
, 0, sizeof(*data
));
925 /* Setup a command header */
926 bnx2x_vlan_mac_set_cmd_hdr_e2(bp
, o
, add
, CLASSIFY_RULE_OPCODE_MAC
,
927 &rule_entry
->mac
.header
);
929 DP(BNX2X_MSG_SP
, "About to %s MAC %pM for Queue %d\n",
930 (add
? "add" : "delete"), mac
, raw
->cl_id
);
932 /* Set a MAC itself */
933 bnx2x_set_fw_mac_addr(&rule_entry
->mac
.mac_msb
,
934 &rule_entry
->mac
.mac_mid
,
935 &rule_entry
->mac
.mac_lsb
, mac
);
936 rule_entry
->mac
.inner_mac
=
937 cpu_to_le16(elem
->cmd_data
.vlan_mac
.u
.mac
.is_inner_mac
);
939 /* MOVE: Add a rule that will add this MAC to the target Queue */
940 if (cmd
== BNX2X_VLAN_MAC_MOVE
) {
944 /* Setup ramrod data */
945 bnx2x_vlan_mac_set_cmd_hdr_e2(bp
,
946 elem
->cmd_data
.vlan_mac
.target_obj
,
947 true, CLASSIFY_RULE_OPCODE_MAC
,
948 &rule_entry
->mac
.header
);
950 /* Set a MAC itself */
951 bnx2x_set_fw_mac_addr(&rule_entry
->mac
.mac_msb
,
952 &rule_entry
->mac
.mac_mid
,
953 &rule_entry
->mac
.mac_lsb
, mac
);
954 rule_entry
->mac
.inner_mac
=
955 cpu_to_le16(elem
->cmd_data
.vlan_mac
.
959 /* Set the ramrod data header */
960 /* TODO: take this to the higher level in order to prevent multiple
962 bnx2x_vlan_mac_set_rdata_hdr_e2(raw
->cid
, raw
->state
, &data
->header
,
967 * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod
972 * @cam_offset: offset in cam memory
973 * @hdr: pointer to a header to setup
977 static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x
*bp
,
978 struct bnx2x_vlan_mac_obj
*o
, int type
, int cam_offset
,
979 struct mac_configuration_hdr
*hdr
)
981 struct bnx2x_raw_obj
*r
= &o
->raw
;
984 hdr
->offset
= (u8
)cam_offset
;
985 hdr
->client_id
= cpu_to_le16(0xff);
986 hdr
->echo
= cpu_to_le32((r
->cid
& BNX2X_SWCID_MASK
) |
987 (type
<< BNX2X_SWCID_SHIFT
));
990 static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x
*bp
,
991 struct bnx2x_vlan_mac_obj
*o
, bool add
, int opcode
, u8
*mac
,
992 u16 vlan_id
, struct mac_configuration_entry
*cfg_entry
)
994 struct bnx2x_raw_obj
*r
= &o
->raw
;
995 u32 cl_bit_vec
= (1 << r
->cl_id
);
997 cfg_entry
->clients_bit_vector
= cpu_to_le32(cl_bit_vec
);
998 cfg_entry
->pf_id
= r
->func_id
;
999 cfg_entry
->vlan_id
= cpu_to_le16(vlan_id
);
1002 SET_FLAG(cfg_entry
->flags
, MAC_CONFIGURATION_ENTRY_ACTION_TYPE
,
1003 T_ETH_MAC_COMMAND_SET
);
1004 SET_FLAG(cfg_entry
->flags
,
1005 MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE
, opcode
);
1007 /* Set a MAC in a ramrod data */
1008 bnx2x_set_fw_mac_addr(&cfg_entry
->msb_mac_addr
,
1009 &cfg_entry
->middle_mac_addr
,
1010 &cfg_entry
->lsb_mac_addr
, mac
);
1012 SET_FLAG(cfg_entry
->flags
, MAC_CONFIGURATION_ENTRY_ACTION_TYPE
,
1013 T_ETH_MAC_COMMAND_INVALIDATE
);
1016 static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x
*bp
,
1017 struct bnx2x_vlan_mac_obj
*o
, int type
, int cam_offset
, bool add
,
1018 u8
*mac
, u16 vlan_id
, int opcode
, struct mac_configuration_cmd
*config
)
1020 struct mac_configuration_entry
*cfg_entry
= &config
->config_table
[0];
1021 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1023 bnx2x_vlan_mac_set_rdata_hdr_e1x(bp
, o
, type
, cam_offset
,
1025 bnx2x_vlan_mac_set_cfg_entry_e1x(bp
, o
, add
, opcode
, mac
, vlan_id
,
1028 DP(BNX2X_MSG_SP
, "%s MAC %pM CLID %d CAM offset %d\n",
1029 (add
? "setting" : "clearing"),
1030 mac
, raw
->cl_id
, cam_offset
);
1034 * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data
1036 * @bp: device handle
1037 * @o: bnx2x_vlan_mac_obj
1038 * @elem: bnx2x_exeq_elem
1039 * @rule_idx: rule_idx
1040 * @cam_offset: cam_offset
1042 static void bnx2x_set_one_mac_e1x(struct bnx2x
*bp
,
1043 struct bnx2x_vlan_mac_obj
*o
,
1044 struct bnx2x_exeq_elem
*elem
, int rule_idx
,
1047 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1048 struct mac_configuration_cmd
*config
=
1049 (struct mac_configuration_cmd
*)(raw
->rdata
);
1050 /* 57710 and 57711 do not support MOVE command,
1051 * so it's either ADD or DEL
1053 bool add
= (elem
->cmd_data
.vlan_mac
.cmd
== BNX2X_VLAN_MAC_ADD
) ?
1056 /* Reset the ramrod data buffer */
1057 memset(config
, 0, sizeof(*config
));
1059 bnx2x_vlan_mac_set_rdata_e1x(bp
, o
, raw
->state
,
1061 elem
->cmd_data
.vlan_mac
.u
.mac
.mac
, 0,
1062 ETH_VLAN_FILTER_ANY_VLAN
, config
);
1065 static void bnx2x_set_one_vlan_e2(struct bnx2x
*bp
,
1066 struct bnx2x_vlan_mac_obj
*o
,
1067 struct bnx2x_exeq_elem
*elem
, int rule_idx
,
1070 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1071 struct eth_classify_rules_ramrod_data
*data
=
1072 (struct eth_classify_rules_ramrod_data
*)(raw
->rdata
);
1073 int rule_cnt
= rule_idx
+ 1;
1074 union eth_classify_rule_cmd
*rule_entry
= &data
->rules
[rule_idx
];
1075 enum bnx2x_vlan_mac_cmd cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
1076 bool add
= (cmd
== BNX2X_VLAN_MAC_ADD
) ? true : false;
1077 u16 vlan
= elem
->cmd_data
.vlan_mac
.u
.vlan
.vlan
;
1079 /* Reset the ramrod data buffer for the first rule */
1081 memset(data
, 0, sizeof(*data
));
1083 /* Set a rule header */
1084 bnx2x_vlan_mac_set_cmd_hdr_e2(bp
, o
, add
, CLASSIFY_RULE_OPCODE_VLAN
,
1085 &rule_entry
->vlan
.header
);
1087 DP(BNX2X_MSG_SP
, "About to %s VLAN %d\n", (add
? "add" : "delete"),
1090 /* Set a VLAN itself */
1091 rule_entry
->vlan
.vlan
= cpu_to_le16(vlan
);
1093 /* MOVE: Add a rule that will add this MAC to the target Queue */
1094 if (cmd
== BNX2X_VLAN_MAC_MOVE
) {
1098 /* Setup ramrod data */
1099 bnx2x_vlan_mac_set_cmd_hdr_e2(bp
,
1100 elem
->cmd_data
.vlan_mac
.target_obj
,
1101 true, CLASSIFY_RULE_OPCODE_VLAN
,
1102 &rule_entry
->vlan
.header
);
1104 /* Set a VLAN itself */
1105 rule_entry
->vlan
.vlan
= cpu_to_le16(vlan
);
1108 /* Set the ramrod data header */
1109 /* TODO: take this to the higher level in order to prevent multiple
1111 bnx2x_vlan_mac_set_rdata_hdr_e2(raw
->cid
, raw
->state
, &data
->header
,
1115 static void bnx2x_set_one_vlan_mac_e2(struct bnx2x
*bp
,
1116 struct bnx2x_vlan_mac_obj
*o
,
1117 struct bnx2x_exeq_elem
*elem
,
1118 int rule_idx
, int cam_offset
)
1120 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1121 struct eth_classify_rules_ramrod_data
*data
=
1122 (struct eth_classify_rules_ramrod_data
*)(raw
->rdata
);
1123 int rule_cnt
= rule_idx
+ 1;
1124 union eth_classify_rule_cmd
*rule_entry
= &data
->rules
[rule_idx
];
1125 enum bnx2x_vlan_mac_cmd cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
1126 bool add
= (cmd
== BNX2X_VLAN_MAC_ADD
) ? true : false;
1127 u16 vlan
= elem
->cmd_data
.vlan_mac
.u
.vlan_mac
.vlan
;
1128 u8
*mac
= elem
->cmd_data
.vlan_mac
.u
.vlan_mac
.mac
;
1131 /* Reset the ramrod data buffer for the first rule */
1133 memset(data
, 0, sizeof(*data
));
1135 /* Set a rule header */
1136 bnx2x_vlan_mac_set_cmd_hdr_e2(bp
, o
, add
, CLASSIFY_RULE_OPCODE_PAIR
,
1137 &rule_entry
->pair
.header
);
1139 /* Set VLAN and MAC themselves */
1140 rule_entry
->pair
.vlan
= cpu_to_le16(vlan
);
1141 bnx2x_set_fw_mac_addr(&rule_entry
->pair
.mac_msb
,
1142 &rule_entry
->pair
.mac_mid
,
1143 &rule_entry
->pair
.mac_lsb
, mac
);
1144 inner_mac
= elem
->cmd_data
.vlan_mac
.u
.vlan_mac
.is_inner_mac
;
1145 rule_entry
->pair
.inner_mac
= cpu_to_le16(inner_mac
);
1146 /* MOVE: Add a rule that will add this MAC/VLAN to the target Queue */
1147 if (cmd
== BNX2X_VLAN_MAC_MOVE
) {
1148 struct bnx2x_vlan_mac_obj
*target_obj
;
1153 /* Setup ramrod data */
1154 target_obj
= elem
->cmd_data
.vlan_mac
.target_obj
;
1155 bnx2x_vlan_mac_set_cmd_hdr_e2(bp
, target_obj
,
1156 true, CLASSIFY_RULE_OPCODE_PAIR
,
1157 &rule_entry
->pair
.header
);
1159 /* Set a VLAN itself */
1160 rule_entry
->pair
.vlan
= cpu_to_le16(vlan
);
1161 bnx2x_set_fw_mac_addr(&rule_entry
->pair
.mac_msb
,
1162 &rule_entry
->pair
.mac_mid
,
1163 &rule_entry
->pair
.mac_lsb
, mac
);
1164 rule_entry
->pair
.inner_mac
= cpu_to_le16(inner_mac
);
1167 /* Set the ramrod data header */
1168 bnx2x_vlan_mac_set_rdata_hdr_e2(raw
->cid
, raw
->state
, &data
->header
,
1173 * bnx2x_set_one_vlan_mac_e1h -
1175 * @bp: device handle
1176 * @o: bnx2x_vlan_mac_obj
1177 * @elem: bnx2x_exeq_elem
1178 * @rule_idx: rule_idx
1179 * @cam_offset: cam_offset
1181 static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x
*bp
,
1182 struct bnx2x_vlan_mac_obj
*o
,
1183 struct bnx2x_exeq_elem
*elem
,
1184 int rule_idx
, int cam_offset
)
1186 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1187 struct mac_configuration_cmd
*config
=
1188 (struct mac_configuration_cmd
*)(raw
->rdata
);
1189 /* 57710 and 57711 do not support MOVE command,
1190 * so it's either ADD or DEL
1192 bool add
= (elem
->cmd_data
.vlan_mac
.cmd
== BNX2X_VLAN_MAC_ADD
) ?
1195 /* Reset the ramrod data buffer */
1196 memset(config
, 0, sizeof(*config
));
1198 bnx2x_vlan_mac_set_rdata_e1x(bp
, o
, BNX2X_FILTER_VLAN_MAC_PENDING
,
1200 elem
->cmd_data
.vlan_mac
.u
.vlan_mac
.mac
,
1201 elem
->cmd_data
.vlan_mac
.u
.vlan_mac
.vlan
,
1202 ETH_VLAN_FILTER_CLASSIFY
, config
);
1206 * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element
1208 * @bp: device handle
1209 * @p: command parameters
1210 * @ppos: pointer to the cookie
1212 * reconfigure next MAC/VLAN/VLAN-MAC element from the
1213 * previously configured elements list.
1215 * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken
1218 * pointer to the cookie - that should be given back in the next call to make
1219 * function handle the next element. If *ppos is set to NULL it will restart the
1220 * iterator. If returned *ppos == NULL this means that the last element has been
1224 static int bnx2x_vlan_mac_restore(struct bnx2x
*bp
,
1225 struct bnx2x_vlan_mac_ramrod_params
*p
,
1226 struct bnx2x_vlan_mac_registry_elem
**ppos
)
1228 struct bnx2x_vlan_mac_registry_elem
*pos
;
1229 struct bnx2x_vlan_mac_obj
*o
= p
->vlan_mac_obj
;
1231 /* If list is empty - there is nothing to do here */
1232 if (list_empty(&o
->head
)) {
1237 /* make a step... */
1239 *ppos
= list_first_entry(&o
->head
,
1240 struct bnx2x_vlan_mac_registry_elem
,
1243 *ppos
= list_next_entry(*ppos
, link
);
1247 /* If it's the last step - return NULL */
1248 if (list_is_last(&pos
->link
, &o
->head
))
1251 /* Prepare a 'user_req' */
1252 memcpy(&p
->user_req
.u
, &pos
->u
, sizeof(pos
->u
));
1254 /* Set the command */
1255 p
->user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
1257 /* Set vlan_mac_flags */
1258 p
->user_req
.vlan_mac_flags
= pos
->vlan_mac_flags
;
1260 /* Set a restore bit */
1261 __set_bit(RAMROD_RESTORE
, &p
->ramrod_flags
);
1263 return bnx2x_config_vlan_mac(bp
, p
);
1266 /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a
1267 * pointer to an element with a specific criteria and NULL if such an element
1268 * hasn't been found.
1270 static struct bnx2x_exeq_elem
*bnx2x_exeq_get_mac(
1271 struct bnx2x_exe_queue_obj
*o
,
1272 struct bnx2x_exeq_elem
*elem
)
1274 struct bnx2x_exeq_elem
*pos
;
1275 struct bnx2x_mac_ramrod_data
*data
= &elem
->cmd_data
.vlan_mac
.u
.mac
;
1277 /* Check pending for execution commands */
1278 list_for_each_entry(pos
, &o
->exe_queue
, link
)
1279 if (!memcmp(&pos
->cmd_data
.vlan_mac
.u
.mac
, data
,
1281 (pos
->cmd_data
.vlan_mac
.cmd
== elem
->cmd_data
.vlan_mac
.cmd
))
1287 static struct bnx2x_exeq_elem
*bnx2x_exeq_get_vlan(
1288 struct bnx2x_exe_queue_obj
*o
,
1289 struct bnx2x_exeq_elem
*elem
)
1291 struct bnx2x_exeq_elem
*pos
;
1292 struct bnx2x_vlan_ramrod_data
*data
= &elem
->cmd_data
.vlan_mac
.u
.vlan
;
1294 /* Check pending for execution commands */
1295 list_for_each_entry(pos
, &o
->exe_queue
, link
)
1296 if (!memcmp(&pos
->cmd_data
.vlan_mac
.u
.vlan
, data
,
1298 (pos
->cmd_data
.vlan_mac
.cmd
== elem
->cmd_data
.vlan_mac
.cmd
))
1304 static struct bnx2x_exeq_elem
*bnx2x_exeq_get_vlan_mac(
1305 struct bnx2x_exe_queue_obj
*o
,
1306 struct bnx2x_exeq_elem
*elem
)
1308 struct bnx2x_exeq_elem
*pos
;
1309 struct bnx2x_vlan_mac_ramrod_data
*data
=
1310 &elem
->cmd_data
.vlan_mac
.u
.vlan_mac
;
1312 /* Check pending for execution commands */
1313 list_for_each_entry(pos
, &o
->exe_queue
, link
)
1314 if (!memcmp(&pos
->cmd_data
.vlan_mac
.u
.vlan_mac
, data
,
1316 (pos
->cmd_data
.vlan_mac
.cmd
==
1317 elem
->cmd_data
.vlan_mac
.cmd
))
1324 * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed
1326 * @bp: device handle
1327 * @qo: bnx2x_qable_obj
1328 * @elem: bnx2x_exeq_elem
1330 * Checks that the requested configuration can be added. If yes and if
1331 * requested, consume CAM credit.
1333 * The 'validate' is run after the 'optimize'.
1336 static inline int bnx2x_validate_vlan_mac_add(struct bnx2x
*bp
,
1337 union bnx2x_qable_obj
*qo
,
1338 struct bnx2x_exeq_elem
*elem
)
1340 struct bnx2x_vlan_mac_obj
*o
= &qo
->vlan_mac
;
1341 struct bnx2x_exe_queue_obj
*exeq
= &o
->exe_queue
;
1344 /* Check the registry */
1345 rc
= o
->check_add(bp
, o
, &elem
->cmd_data
.vlan_mac
.u
);
1347 DP(BNX2X_MSG_SP
, "ADD command is not allowed considering current registry state.\n");
1351 /* Check if there is a pending ADD command for this
1352 * MAC/VLAN/VLAN-MAC. Return an error if there is.
1354 if (exeq
->get(exeq
, elem
)) {
1355 DP(BNX2X_MSG_SP
, "There is a pending ADD command already\n");
1359 /* TODO: Check the pending MOVE from other objects where this
1360 * object is a destination object.
1363 /* Consume the credit if not requested not to */
1364 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT
,
1365 &elem
->cmd_data
.vlan_mac
.vlan_mac_flags
) ||
1373 * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed
1375 * @bp: device handle
1376 * @qo: quable object to check
1377 * @elem: element that needs to be deleted
1379 * Checks that the requested configuration can be deleted. If yes and if
1380 * requested, returns a CAM credit.
1382 * The 'validate' is run after the 'optimize'.
1384 static inline int bnx2x_validate_vlan_mac_del(struct bnx2x
*bp
,
1385 union bnx2x_qable_obj
*qo
,
1386 struct bnx2x_exeq_elem
*elem
)
1388 struct bnx2x_vlan_mac_obj
*o
= &qo
->vlan_mac
;
1389 struct bnx2x_vlan_mac_registry_elem
*pos
;
1390 struct bnx2x_exe_queue_obj
*exeq
= &o
->exe_queue
;
1391 struct bnx2x_exeq_elem query_elem
;
1393 /* If this classification can not be deleted (doesn't exist)
1394 * - return a BNX2X_EXIST.
1396 pos
= o
->check_del(bp
, o
, &elem
->cmd_data
.vlan_mac
.u
);
1398 DP(BNX2X_MSG_SP
, "DEL command is not allowed considering current registry state\n");
1402 /* Check if there are pending DEL or MOVE commands for this
1403 * MAC/VLAN/VLAN-MAC. Return an error if so.
1405 memcpy(&query_elem
, elem
, sizeof(query_elem
));
1407 /* Check for MOVE commands */
1408 query_elem
.cmd_data
.vlan_mac
.cmd
= BNX2X_VLAN_MAC_MOVE
;
1409 if (exeq
->get(exeq
, &query_elem
)) {
1410 BNX2X_ERR("There is a pending MOVE command already\n");
1414 /* Check for DEL commands */
1415 if (exeq
->get(exeq
, elem
)) {
1416 DP(BNX2X_MSG_SP
, "There is a pending DEL command already\n");
1420 /* Return the credit to the credit pool if not requested not to */
1421 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT
,
1422 &elem
->cmd_data
.vlan_mac
.vlan_mac_flags
) ||
1423 o
->put_credit(o
))) {
1424 BNX2X_ERR("Failed to return a credit\n");
1432 * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed
1434 * @bp: device handle
1435 * @qo: quable object to check (source)
1436 * @elem: element that needs to be moved
1438 * Checks that the requested configuration can be moved. If yes and if
1439 * requested, returns a CAM credit.
1441 * The 'validate' is run after the 'optimize'.
1443 static inline int bnx2x_validate_vlan_mac_move(struct bnx2x
*bp
,
1444 union bnx2x_qable_obj
*qo
,
1445 struct bnx2x_exeq_elem
*elem
)
1447 struct bnx2x_vlan_mac_obj
*src_o
= &qo
->vlan_mac
;
1448 struct bnx2x_vlan_mac_obj
*dest_o
= elem
->cmd_data
.vlan_mac
.target_obj
;
1449 struct bnx2x_exeq_elem query_elem
;
1450 struct bnx2x_exe_queue_obj
*src_exeq
= &src_o
->exe_queue
;
1451 struct bnx2x_exe_queue_obj
*dest_exeq
= &dest_o
->exe_queue
;
1453 /* Check if we can perform this operation based on the current registry
1456 if (!src_o
->check_move(bp
, src_o
, dest_o
,
1457 &elem
->cmd_data
.vlan_mac
.u
)) {
1458 DP(BNX2X_MSG_SP
, "MOVE command is not allowed considering current registry state\n");
1462 /* Check if there is an already pending DEL or MOVE command for the
1463 * source object or ADD command for a destination object. Return an
1466 memcpy(&query_elem
, elem
, sizeof(query_elem
));
1468 /* Check DEL on source */
1469 query_elem
.cmd_data
.vlan_mac
.cmd
= BNX2X_VLAN_MAC_DEL
;
1470 if (src_exeq
->get(src_exeq
, &query_elem
)) {
1471 BNX2X_ERR("There is a pending DEL command on the source queue already\n");
1475 /* Check MOVE on source */
1476 if (src_exeq
->get(src_exeq
, elem
)) {
1477 DP(BNX2X_MSG_SP
, "There is a pending MOVE command already\n");
1481 /* Check ADD on destination */
1482 query_elem
.cmd_data
.vlan_mac
.cmd
= BNX2X_VLAN_MAC_ADD
;
1483 if (dest_exeq
->get(dest_exeq
, &query_elem
)) {
1484 BNX2X_ERR("There is a pending ADD command on the destination queue already\n");
1488 /* Consume the credit if not requested not to */
1489 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST
,
1490 &elem
->cmd_data
.vlan_mac
.vlan_mac_flags
) ||
1491 dest_o
->get_credit(dest_o
)))
1494 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT
,
1495 &elem
->cmd_data
.vlan_mac
.vlan_mac_flags
) ||
1496 src_o
->put_credit(src_o
))) {
1497 /* return the credit taken from dest... */
1498 dest_o
->put_credit(dest_o
);
1505 static int bnx2x_validate_vlan_mac(struct bnx2x
*bp
,
1506 union bnx2x_qable_obj
*qo
,
1507 struct bnx2x_exeq_elem
*elem
)
1509 switch (elem
->cmd_data
.vlan_mac
.cmd
) {
1510 case BNX2X_VLAN_MAC_ADD
:
1511 return bnx2x_validate_vlan_mac_add(bp
, qo
, elem
);
1512 case BNX2X_VLAN_MAC_DEL
:
1513 return bnx2x_validate_vlan_mac_del(bp
, qo
, elem
);
1514 case BNX2X_VLAN_MAC_MOVE
:
1515 return bnx2x_validate_vlan_mac_move(bp
, qo
, elem
);
1521 static int bnx2x_remove_vlan_mac(struct bnx2x
*bp
,
1522 union bnx2x_qable_obj
*qo
,
1523 struct bnx2x_exeq_elem
*elem
)
1527 /* If consumption wasn't required, nothing to do */
1528 if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT
,
1529 &elem
->cmd_data
.vlan_mac
.vlan_mac_flags
))
1532 switch (elem
->cmd_data
.vlan_mac
.cmd
) {
1533 case BNX2X_VLAN_MAC_ADD
:
1534 case BNX2X_VLAN_MAC_MOVE
:
1535 rc
= qo
->vlan_mac
.put_credit(&qo
->vlan_mac
);
1537 case BNX2X_VLAN_MAC_DEL
:
1538 rc
= qo
->vlan_mac
.get_credit(&qo
->vlan_mac
);
1551 * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes.
1553 * @bp: device handle
1554 * @o: bnx2x_vlan_mac_obj
1557 static int bnx2x_wait_vlan_mac(struct bnx2x
*bp
,
1558 struct bnx2x_vlan_mac_obj
*o
)
1561 struct bnx2x_exe_queue_obj
*exeq
= &o
->exe_queue
;
1562 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1565 /* Wait for the current command to complete */
1566 rc
= raw
->wait_comp(bp
, raw
);
1570 /* Wait until there are no pending commands */
1571 if (!bnx2x_exe_queue_empty(exeq
))
1572 usleep_range(1000, 2000);
1580 static int __bnx2x_vlan_mac_execute_step(struct bnx2x
*bp
,
1581 struct bnx2x_vlan_mac_obj
*o
,
1582 unsigned long *ramrod_flags
)
1586 spin_lock_bh(&o
->exe_queue
.lock
);
1588 DP(BNX2X_MSG_SP
, "vlan_mac_execute_step - trying to take writer lock\n");
1589 rc
= __bnx2x_vlan_mac_h_write_trylock(bp
, o
);
1592 __bnx2x_vlan_mac_h_pend(bp
, o
, *ramrod_flags
);
1594 /* Calling function should not diffrentiate between this case
1595 * and the case in which there is already a pending ramrod
1599 rc
= bnx2x_exe_queue_step(bp
, &o
->exe_queue
, ramrod_flags
);
1601 spin_unlock_bh(&o
->exe_queue
.lock
);
1607 * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod
1609 * @bp: device handle
1610 * @o: bnx2x_vlan_mac_obj
1612 * @cont: if true schedule next execution chunk
1615 static int bnx2x_complete_vlan_mac(struct bnx2x
*bp
,
1616 struct bnx2x_vlan_mac_obj
*o
,
1617 union event_ring_elem
*cqe
,
1618 unsigned long *ramrod_flags
)
1620 struct bnx2x_raw_obj
*r
= &o
->raw
;
1623 /* Clearing the pending list & raw state should be made
1624 * atomically (as execution flow assumes they represent the same).
1626 spin_lock_bh(&o
->exe_queue
.lock
);
1628 /* Reset pending list */
1629 __bnx2x_exe_queue_reset_pending(bp
, &o
->exe_queue
);
1632 r
->clear_pending(r
);
1634 spin_unlock_bh(&o
->exe_queue
.lock
);
1636 /* If ramrod failed this is most likely a SW bug */
1637 if (cqe
->message
.error
)
1640 /* Run the next bulk of pending commands if requested */
1641 if (test_bit(RAMROD_CONT
, ramrod_flags
)) {
1642 rc
= __bnx2x_vlan_mac_execute_step(bp
, o
, ramrod_flags
);
1648 /* If there is more work to do return PENDING */
1649 if (!bnx2x_exe_queue_empty(&o
->exe_queue
))
1656 * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands.
1658 * @bp: device handle
1659 * @o: bnx2x_qable_obj
1660 * @elem: bnx2x_exeq_elem
1662 static int bnx2x_optimize_vlan_mac(struct bnx2x
*bp
,
1663 union bnx2x_qable_obj
*qo
,
1664 struct bnx2x_exeq_elem
*elem
)
1666 struct bnx2x_exeq_elem query
, *pos
;
1667 struct bnx2x_vlan_mac_obj
*o
= &qo
->vlan_mac
;
1668 struct bnx2x_exe_queue_obj
*exeq
= &o
->exe_queue
;
1670 memcpy(&query
, elem
, sizeof(query
));
1672 switch (elem
->cmd_data
.vlan_mac
.cmd
) {
1673 case BNX2X_VLAN_MAC_ADD
:
1674 query
.cmd_data
.vlan_mac
.cmd
= BNX2X_VLAN_MAC_DEL
;
1676 case BNX2X_VLAN_MAC_DEL
:
1677 query
.cmd_data
.vlan_mac
.cmd
= BNX2X_VLAN_MAC_ADD
;
1680 /* Don't handle anything other than ADD or DEL */
1684 /* If we found the appropriate element - delete it */
1685 pos
= exeq
->get(exeq
, &query
);
1688 /* Return the credit of the optimized command */
1689 if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT
,
1690 &pos
->cmd_data
.vlan_mac
.vlan_mac_flags
)) {
1691 if ((query
.cmd_data
.vlan_mac
.cmd
==
1692 BNX2X_VLAN_MAC_ADD
) && !o
->put_credit(o
)) {
1693 BNX2X_ERR("Failed to return the credit for the optimized ADD command\n");
1695 } else if (!o
->get_credit(o
)) { /* VLAN_MAC_DEL */
1696 BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n");
1701 DP(BNX2X_MSG_SP
, "Optimizing %s command\n",
1702 (elem
->cmd_data
.vlan_mac
.cmd
== BNX2X_VLAN_MAC_ADD
) ?
1705 list_del(&pos
->link
);
1706 bnx2x_exe_queue_free_elem(bp
, pos
);
1714 * bnx2x_vlan_mac_get_registry_elem - prepare a registry element
1716 * @bp: device handle
1722 * prepare a registry element according to the current command request.
1724 static inline int bnx2x_vlan_mac_get_registry_elem(
1726 struct bnx2x_vlan_mac_obj
*o
,
1727 struct bnx2x_exeq_elem
*elem
,
1729 struct bnx2x_vlan_mac_registry_elem
**re
)
1731 enum bnx2x_vlan_mac_cmd cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
1732 struct bnx2x_vlan_mac_registry_elem
*reg_elem
;
1734 /* Allocate a new registry element if needed. */
1736 ((cmd
== BNX2X_VLAN_MAC_ADD
) || (cmd
== BNX2X_VLAN_MAC_MOVE
))) {
1737 reg_elem
= kzalloc(sizeof(*reg_elem
), GFP_ATOMIC
);
1741 /* Get a new CAM offset */
1742 if (!o
->get_cam_offset(o
, ®_elem
->cam_offset
)) {
1743 /* This shall never happen, because we have checked the
1744 * CAM availability in the 'validate'.
1751 DP(BNX2X_MSG_SP
, "Got cam offset %d\n", reg_elem
->cam_offset
);
1753 /* Set a VLAN-MAC data */
1754 memcpy(®_elem
->u
, &elem
->cmd_data
.vlan_mac
.u
,
1755 sizeof(reg_elem
->u
));
1757 /* Copy the flags (needed for DEL and RESTORE flows) */
1758 reg_elem
->vlan_mac_flags
=
1759 elem
->cmd_data
.vlan_mac
.vlan_mac_flags
;
1760 } else /* DEL, RESTORE */
1761 reg_elem
= o
->check_del(bp
, o
, &elem
->cmd_data
.vlan_mac
.u
);
1768 * bnx2x_execute_vlan_mac - execute vlan mac command
1770 * @bp: device handle
1775 * go and send a ramrod!
1777 static int bnx2x_execute_vlan_mac(struct bnx2x
*bp
,
1778 union bnx2x_qable_obj
*qo
,
1779 struct list_head
*exe_chunk
,
1780 unsigned long *ramrod_flags
)
1782 struct bnx2x_exeq_elem
*elem
;
1783 struct bnx2x_vlan_mac_obj
*o
= &qo
->vlan_mac
, *cam_obj
;
1784 struct bnx2x_raw_obj
*r
= &o
->raw
;
1786 bool restore
= test_bit(RAMROD_RESTORE
, ramrod_flags
);
1787 bool drv_only
= test_bit(RAMROD_DRV_CLR_ONLY
, ramrod_flags
);
1788 struct bnx2x_vlan_mac_registry_elem
*reg_elem
;
1789 enum bnx2x_vlan_mac_cmd cmd
;
1791 /* If DRIVER_ONLY execution is requested, cleanup a registry
1792 * and exit. Otherwise send a ramrod to FW.
1795 WARN_ON(r
->check_pending(r
));
1800 /* Fill the ramrod data */
1801 list_for_each_entry(elem
, exe_chunk
, link
) {
1802 cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
1803 /* We will add to the target object in MOVE command, so
1804 * change the object for a CAM search.
1806 if (cmd
== BNX2X_VLAN_MAC_MOVE
)
1807 cam_obj
= elem
->cmd_data
.vlan_mac
.target_obj
;
1811 rc
= bnx2x_vlan_mac_get_registry_elem(bp
, cam_obj
,
1819 /* Push a new entry into the registry */
1821 ((cmd
== BNX2X_VLAN_MAC_ADD
) ||
1822 (cmd
== BNX2X_VLAN_MAC_MOVE
)))
1823 list_add(®_elem
->link
, &cam_obj
->head
);
1825 /* Configure a single command in a ramrod data buffer */
1826 o
->set_one_rule(bp
, o
, elem
, idx
,
1827 reg_elem
->cam_offset
);
1829 /* MOVE command consumes 2 entries in the ramrod data */
1830 if (cmd
== BNX2X_VLAN_MAC_MOVE
)
1836 /* No need for an explicit memory barrier here as long we would
1837 * need to ensure the ordering of writing to the SPQ element
1838 * and updating of the SPQ producer which involves a memory
1839 * read and we will have to put a full memory barrier there
1840 * (inside bnx2x_sp_post()).
1843 rc
= bnx2x_sp_post(bp
, o
->ramrod_cmd
, r
->cid
,
1844 U64_HI(r
->rdata_mapping
),
1845 U64_LO(r
->rdata_mapping
),
1846 ETH_CONNECTION_TYPE
);
1851 /* Now, when we are done with the ramrod - clean up the registry */
1852 list_for_each_entry(elem
, exe_chunk
, link
) {
1853 cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
1854 if ((cmd
== BNX2X_VLAN_MAC_DEL
) ||
1855 (cmd
== BNX2X_VLAN_MAC_MOVE
)) {
1856 reg_elem
= o
->check_del(bp
, o
,
1857 &elem
->cmd_data
.vlan_mac
.u
);
1861 o
->put_cam_offset(o
, reg_elem
->cam_offset
);
1862 list_del(®_elem
->link
);
1873 r
->clear_pending(r
);
1875 /* Cleanup a registry in case of a failure */
1876 list_for_each_entry(elem
, exe_chunk
, link
) {
1877 cmd
= elem
->cmd_data
.vlan_mac
.cmd
;
1879 if (cmd
== BNX2X_VLAN_MAC_MOVE
)
1880 cam_obj
= elem
->cmd_data
.vlan_mac
.target_obj
;
1884 /* Delete all newly added above entries */
1886 ((cmd
== BNX2X_VLAN_MAC_ADD
) ||
1887 (cmd
== BNX2X_VLAN_MAC_MOVE
))) {
1888 reg_elem
= o
->check_del(bp
, cam_obj
,
1889 &elem
->cmd_data
.vlan_mac
.u
);
1891 list_del(®_elem
->link
);
1900 static inline int bnx2x_vlan_mac_push_new_cmd(
1902 struct bnx2x_vlan_mac_ramrod_params
*p
)
1904 struct bnx2x_exeq_elem
*elem
;
1905 struct bnx2x_vlan_mac_obj
*o
= p
->vlan_mac_obj
;
1906 bool restore
= test_bit(RAMROD_RESTORE
, &p
->ramrod_flags
);
1908 /* Allocate the execution queue element */
1909 elem
= bnx2x_exe_queue_alloc_elem(bp
);
1913 /* Set the command 'length' */
1914 switch (p
->user_req
.cmd
) {
1915 case BNX2X_VLAN_MAC_MOVE
:
1922 /* Fill the object specific info */
1923 memcpy(&elem
->cmd_data
.vlan_mac
, &p
->user_req
, sizeof(p
->user_req
));
1925 /* Try to add a new command to the pending list */
1926 return bnx2x_exe_queue_add(bp
, &o
->exe_queue
, elem
, restore
);
1930 * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules.
1932 * @bp: device handle
1936 int bnx2x_config_vlan_mac(struct bnx2x
*bp
,
1937 struct bnx2x_vlan_mac_ramrod_params
*p
)
1940 struct bnx2x_vlan_mac_obj
*o
= p
->vlan_mac_obj
;
1941 unsigned long *ramrod_flags
= &p
->ramrod_flags
;
1942 bool cont
= test_bit(RAMROD_CONT
, ramrod_flags
);
1943 struct bnx2x_raw_obj
*raw
= &o
->raw
;
1946 * Add new elements to the execution list for commands that require it.
1949 rc
= bnx2x_vlan_mac_push_new_cmd(bp
, p
);
1954 /* If nothing will be executed further in this iteration we want to
1955 * return PENDING if there are pending commands
1957 if (!bnx2x_exe_queue_empty(&o
->exe_queue
))
1960 if (test_bit(RAMROD_DRV_CLR_ONLY
, ramrod_flags
)) {
1961 DP(BNX2X_MSG_SP
, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
1962 raw
->clear_pending(raw
);
1965 /* Execute commands if required */
1966 if (cont
|| test_bit(RAMROD_EXEC
, ramrod_flags
) ||
1967 test_bit(RAMROD_COMP_WAIT
, ramrod_flags
)) {
1968 rc
= __bnx2x_vlan_mac_execute_step(bp
, p
->vlan_mac_obj
,
1974 /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set
1975 * then user want to wait until the last command is done.
1977 if (test_bit(RAMROD_COMP_WAIT
, &p
->ramrod_flags
)) {
1978 /* Wait maximum for the current exe_queue length iterations plus
1979 * one (for the current pending command).
1981 int max_iterations
= bnx2x_exe_queue_length(&o
->exe_queue
) + 1;
1983 while (!bnx2x_exe_queue_empty(&o
->exe_queue
) &&
1986 /* Wait for the current command to complete */
1987 rc
= raw
->wait_comp(bp
, raw
);
1991 /* Make a next step */
1992 rc
= __bnx2x_vlan_mac_execute_step(bp
,
2006 * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec
2008 * @bp: device handle
2011 * @ramrod_flags: execution flags to be used for this deletion
2013 * if the last operation has completed successfully and there are no
2014 * more elements left, positive value if the last operation has completed
2015 * successfully and there are more previously configured elements, negative
2016 * value is current operation has failed.
2018 static int bnx2x_vlan_mac_del_all(struct bnx2x
*bp
,
2019 struct bnx2x_vlan_mac_obj
*o
,
2020 unsigned long *vlan_mac_flags
,
2021 unsigned long *ramrod_flags
)
2023 struct bnx2x_vlan_mac_registry_elem
*pos
= NULL
;
2024 struct bnx2x_vlan_mac_ramrod_params p
;
2025 struct bnx2x_exe_queue_obj
*exeq
= &o
->exe_queue
;
2026 struct bnx2x_exeq_elem
*exeq_pos
, *exeq_pos_n
;
2027 unsigned long flags
;
2031 /* Clear pending commands first */
2033 spin_lock_bh(&exeq
->lock
);
2035 list_for_each_entry_safe(exeq_pos
, exeq_pos_n
, &exeq
->exe_queue
, link
) {
2036 flags
= exeq_pos
->cmd_data
.vlan_mac
.vlan_mac_flags
;
2037 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags
) ==
2038 BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags
)) {
2039 rc
= exeq
->remove(bp
, exeq
->owner
, exeq_pos
);
2041 BNX2X_ERR("Failed to remove command\n");
2042 spin_unlock_bh(&exeq
->lock
);
2045 list_del(&exeq_pos
->link
);
2046 bnx2x_exe_queue_free_elem(bp
, exeq_pos
);
2050 spin_unlock_bh(&exeq
->lock
);
2052 /* Prepare a command request */
2053 memset(&p
, 0, sizeof(p
));
2055 p
.ramrod_flags
= *ramrod_flags
;
2056 p
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
2058 /* Add all but the last VLAN-MAC to the execution queue without actually
2059 * execution anything.
2061 __clear_bit(RAMROD_COMP_WAIT
, &p
.ramrod_flags
);
2062 __clear_bit(RAMROD_EXEC
, &p
.ramrod_flags
);
2063 __clear_bit(RAMROD_CONT
, &p
.ramrod_flags
);
2065 DP(BNX2X_MSG_SP
, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n");
2066 read_lock
= bnx2x_vlan_mac_h_read_lock(bp
, o
);
2070 list_for_each_entry(pos
, &o
->head
, link
) {
2071 flags
= pos
->vlan_mac_flags
;
2072 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags
) ==
2073 BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags
)) {
2074 p
.user_req
.vlan_mac_flags
= pos
->vlan_mac_flags
;
2075 memcpy(&p
.user_req
.u
, &pos
->u
, sizeof(pos
->u
));
2076 rc
= bnx2x_config_vlan_mac(bp
, &p
);
2078 BNX2X_ERR("Failed to add a new DEL command\n");
2079 bnx2x_vlan_mac_h_read_unlock(bp
, o
);
2085 DP(BNX2X_MSG_SP
, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n");
2086 bnx2x_vlan_mac_h_read_unlock(bp
, o
);
2088 p
.ramrod_flags
= *ramrod_flags
;
2089 __set_bit(RAMROD_CONT
, &p
.ramrod_flags
);
2091 return bnx2x_config_vlan_mac(bp
, &p
);
2094 static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj
*raw
, u8 cl_id
,
2095 u32 cid
, u8 func_id
, void *rdata
, dma_addr_t rdata_mapping
, int state
,
2096 unsigned long *pstate
, bnx2x_obj_type type
)
2098 raw
->func_id
= func_id
;
2102 raw
->rdata_mapping
= rdata_mapping
;
2104 raw
->pstate
= pstate
;
2105 raw
->obj_type
= type
;
2106 raw
->check_pending
= bnx2x_raw_check_pending
;
2107 raw
->clear_pending
= bnx2x_raw_clear_pending
;
2108 raw
->set_pending
= bnx2x_raw_set_pending
;
2109 raw
->wait_comp
= bnx2x_raw_wait
;
2112 static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj
*o
,
2113 u8 cl_id
, u32 cid
, u8 func_id
, void *rdata
, dma_addr_t rdata_mapping
,
2114 int state
, unsigned long *pstate
, bnx2x_obj_type type
,
2115 struct bnx2x_credit_pool_obj
*macs_pool
,
2116 struct bnx2x_credit_pool_obj
*vlans_pool
)
2118 INIT_LIST_HEAD(&o
->head
);
2120 o
->head_exe_request
= false;
2121 o
->saved_ramrod_flags
= 0;
2123 o
->macs_pool
= macs_pool
;
2124 o
->vlans_pool
= vlans_pool
;
2126 o
->delete_all
= bnx2x_vlan_mac_del_all
;
2127 o
->restore
= bnx2x_vlan_mac_restore
;
2128 o
->complete
= bnx2x_complete_vlan_mac
;
2129 o
->wait
= bnx2x_wait_vlan_mac
;
2131 bnx2x_init_raw_obj(&o
->raw
, cl_id
, cid
, func_id
, rdata
, rdata_mapping
,
2132 state
, pstate
, type
);
2135 void bnx2x_init_mac_obj(struct bnx2x
*bp
,
2136 struct bnx2x_vlan_mac_obj
*mac_obj
,
2137 u8 cl_id
, u32 cid
, u8 func_id
, void *rdata
,
2138 dma_addr_t rdata_mapping
, int state
,
2139 unsigned long *pstate
, bnx2x_obj_type type
,
2140 struct bnx2x_credit_pool_obj
*macs_pool
)
2142 union bnx2x_qable_obj
*qable_obj
= (union bnx2x_qable_obj
*)mac_obj
;
2144 bnx2x_init_vlan_mac_common(mac_obj
, cl_id
, cid
, func_id
, rdata
,
2145 rdata_mapping
, state
, pstate
, type
,
2148 /* CAM credit pool handling */
2149 mac_obj
->get_credit
= bnx2x_get_credit_mac
;
2150 mac_obj
->put_credit
= bnx2x_put_credit_mac
;
2151 mac_obj
->get_cam_offset
= bnx2x_get_cam_offset_mac
;
2152 mac_obj
->put_cam_offset
= bnx2x_put_cam_offset_mac
;
2154 if (CHIP_IS_E1x(bp
)) {
2155 mac_obj
->set_one_rule
= bnx2x_set_one_mac_e1x
;
2156 mac_obj
->check_del
= bnx2x_check_mac_del
;
2157 mac_obj
->check_add
= bnx2x_check_mac_add
;
2158 mac_obj
->check_move
= bnx2x_check_move_always_err
;
2159 mac_obj
->ramrod_cmd
= RAMROD_CMD_ID_ETH_SET_MAC
;
2162 bnx2x_exe_queue_init(bp
,
2163 &mac_obj
->exe_queue
, 1, qable_obj
,
2164 bnx2x_validate_vlan_mac
,
2165 bnx2x_remove_vlan_mac
,
2166 bnx2x_optimize_vlan_mac
,
2167 bnx2x_execute_vlan_mac
,
2168 bnx2x_exeq_get_mac
);
2170 mac_obj
->set_one_rule
= bnx2x_set_one_mac_e2
;
2171 mac_obj
->check_del
= bnx2x_check_mac_del
;
2172 mac_obj
->check_add
= bnx2x_check_mac_add
;
2173 mac_obj
->check_move
= bnx2x_check_move
;
2174 mac_obj
->ramrod_cmd
=
2175 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
;
2176 mac_obj
->get_n_elements
= bnx2x_get_n_elements
;
2179 bnx2x_exe_queue_init(bp
,
2180 &mac_obj
->exe_queue
, CLASSIFY_RULES_COUNT
,
2181 qable_obj
, bnx2x_validate_vlan_mac
,
2182 bnx2x_remove_vlan_mac
,
2183 bnx2x_optimize_vlan_mac
,
2184 bnx2x_execute_vlan_mac
,
2185 bnx2x_exeq_get_mac
);
2189 void bnx2x_init_vlan_obj(struct bnx2x
*bp
,
2190 struct bnx2x_vlan_mac_obj
*vlan_obj
,
2191 u8 cl_id
, u32 cid
, u8 func_id
, void *rdata
,
2192 dma_addr_t rdata_mapping
, int state
,
2193 unsigned long *pstate
, bnx2x_obj_type type
,
2194 struct bnx2x_credit_pool_obj
*vlans_pool
)
2196 union bnx2x_qable_obj
*qable_obj
= (union bnx2x_qable_obj
*)vlan_obj
;
2198 bnx2x_init_vlan_mac_common(vlan_obj
, cl_id
, cid
, func_id
, rdata
,
2199 rdata_mapping
, state
, pstate
, type
, NULL
,
2202 vlan_obj
->get_credit
= bnx2x_get_credit_vlan
;
2203 vlan_obj
->put_credit
= bnx2x_put_credit_vlan
;
2204 vlan_obj
->get_cam_offset
= bnx2x_get_cam_offset_vlan
;
2205 vlan_obj
->put_cam_offset
= bnx2x_put_cam_offset_vlan
;
2207 if (CHIP_IS_E1x(bp
)) {
2208 BNX2X_ERR("Do not support chips others than E2 and newer\n");
2211 vlan_obj
->set_one_rule
= bnx2x_set_one_vlan_e2
;
2212 vlan_obj
->check_del
= bnx2x_check_vlan_del
;
2213 vlan_obj
->check_add
= bnx2x_check_vlan_add
;
2214 vlan_obj
->check_move
= bnx2x_check_move
;
2215 vlan_obj
->ramrod_cmd
=
2216 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
;
2217 vlan_obj
->get_n_elements
= bnx2x_get_n_elements
;
2220 bnx2x_exe_queue_init(bp
,
2221 &vlan_obj
->exe_queue
, CLASSIFY_RULES_COUNT
,
2222 qable_obj
, bnx2x_validate_vlan_mac
,
2223 bnx2x_remove_vlan_mac
,
2224 bnx2x_optimize_vlan_mac
,
2225 bnx2x_execute_vlan_mac
,
2226 bnx2x_exeq_get_vlan
);
2230 void bnx2x_init_vlan_mac_obj(struct bnx2x
*bp
,
2231 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
,
2232 u8 cl_id
, u32 cid
, u8 func_id
, void *rdata
,
2233 dma_addr_t rdata_mapping
, int state
,
2234 unsigned long *pstate
, bnx2x_obj_type type
,
2235 struct bnx2x_credit_pool_obj
*macs_pool
,
2236 struct bnx2x_credit_pool_obj
*vlans_pool
)
2238 union bnx2x_qable_obj
*qable_obj
=
2239 (union bnx2x_qable_obj
*)vlan_mac_obj
;
2241 bnx2x_init_vlan_mac_common(vlan_mac_obj
, cl_id
, cid
, func_id
, rdata
,
2242 rdata_mapping
, state
, pstate
, type
,
2243 macs_pool
, vlans_pool
);
2245 /* CAM pool handling */
2246 vlan_mac_obj
->get_credit
= bnx2x_get_credit_vlan_mac
;
2247 vlan_mac_obj
->put_credit
= bnx2x_put_credit_vlan_mac
;
2248 /* CAM offset is relevant for 57710 and 57711 chips only which have a
2249 * single CAM for both MACs and VLAN-MAC pairs. So the offset
2250 * will be taken from MACs' pool object only.
2252 vlan_mac_obj
->get_cam_offset
= bnx2x_get_cam_offset_mac
;
2253 vlan_mac_obj
->put_cam_offset
= bnx2x_put_cam_offset_mac
;
2255 if (CHIP_IS_E1(bp
)) {
2256 BNX2X_ERR("Do not support chips others than E2\n");
2258 } else if (CHIP_IS_E1H(bp
)) {
2259 vlan_mac_obj
->set_one_rule
= bnx2x_set_one_vlan_mac_e1h
;
2260 vlan_mac_obj
->check_del
= bnx2x_check_vlan_mac_del
;
2261 vlan_mac_obj
->check_add
= bnx2x_check_vlan_mac_add
;
2262 vlan_mac_obj
->check_move
= bnx2x_check_move_always_err
;
2263 vlan_mac_obj
->ramrod_cmd
= RAMROD_CMD_ID_ETH_SET_MAC
;
2266 bnx2x_exe_queue_init(bp
,
2267 &vlan_mac_obj
->exe_queue
, 1, qable_obj
,
2268 bnx2x_validate_vlan_mac
,
2269 bnx2x_remove_vlan_mac
,
2270 bnx2x_optimize_vlan_mac
,
2271 bnx2x_execute_vlan_mac
,
2272 bnx2x_exeq_get_vlan_mac
);
2274 vlan_mac_obj
->set_one_rule
= bnx2x_set_one_vlan_mac_e2
;
2275 vlan_mac_obj
->check_del
= bnx2x_check_vlan_mac_del
;
2276 vlan_mac_obj
->check_add
= bnx2x_check_vlan_mac_add
;
2277 vlan_mac_obj
->check_move
= bnx2x_check_move
;
2278 vlan_mac_obj
->ramrod_cmd
=
2279 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
;
2282 bnx2x_exe_queue_init(bp
,
2283 &vlan_mac_obj
->exe_queue
,
2284 CLASSIFY_RULES_COUNT
,
2285 qable_obj
, bnx2x_validate_vlan_mac
,
2286 bnx2x_remove_vlan_mac
,
2287 bnx2x_optimize_vlan_mac
,
2288 bnx2x_execute_vlan_mac
,
2289 bnx2x_exeq_get_vlan_mac
);
2292 /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
2293 static inline void __storm_memset_mac_filters(struct bnx2x
*bp
,
2294 struct tstorm_eth_mac_filter_config
*mac_filters
,
2297 size_t size
= sizeof(struct tstorm_eth_mac_filter_config
);
2299 u32 addr
= BAR_TSTRORM_INTMEM
+
2300 TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id
);
2302 __storm_memset_struct(bp
, addr
, size
, (u32
*)mac_filters
);
2305 static int bnx2x_set_rx_mode_e1x(struct bnx2x
*bp
,
2306 struct bnx2x_rx_mode_ramrod_params
*p
)
2308 /* update the bp MAC filter structure */
2309 u32 mask
= (1 << p
->cl_id
);
2311 struct tstorm_eth_mac_filter_config
*mac_filters
=
2312 (struct tstorm_eth_mac_filter_config
*)p
->rdata
;
2314 /* initial setting is drop-all */
2315 u8 drop_all_ucast
= 1, drop_all_mcast
= 1;
2316 u8 accp_all_ucast
= 0, accp_all_bcast
= 0, accp_all_mcast
= 0;
2317 u8 unmatched_unicast
= 0;
2319 /* In e1x there we only take into account rx accept flag since tx switching
2321 if (test_bit(BNX2X_ACCEPT_UNICAST
, &p
->rx_accept_flags
))
2322 /* accept matched ucast */
2325 if (test_bit(BNX2X_ACCEPT_MULTICAST
, &p
->rx_accept_flags
))
2326 /* accept matched mcast */
2329 if (test_bit(BNX2X_ACCEPT_ALL_UNICAST
, &p
->rx_accept_flags
)) {
2330 /* accept all mcast */
2334 if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &p
->rx_accept_flags
)) {
2335 /* accept all mcast */
2339 if (test_bit(BNX2X_ACCEPT_BROADCAST
, &p
->rx_accept_flags
))
2340 /* accept (all) bcast */
2342 if (test_bit(BNX2X_ACCEPT_UNMATCHED
, &p
->rx_accept_flags
))
2343 /* accept unmatched unicasts */
2344 unmatched_unicast
= 1;
2346 mac_filters
->ucast_drop_all
= drop_all_ucast
?
2347 mac_filters
->ucast_drop_all
| mask
:
2348 mac_filters
->ucast_drop_all
& ~mask
;
2350 mac_filters
->mcast_drop_all
= drop_all_mcast
?
2351 mac_filters
->mcast_drop_all
| mask
:
2352 mac_filters
->mcast_drop_all
& ~mask
;
2354 mac_filters
->ucast_accept_all
= accp_all_ucast
?
2355 mac_filters
->ucast_accept_all
| mask
:
2356 mac_filters
->ucast_accept_all
& ~mask
;
2358 mac_filters
->mcast_accept_all
= accp_all_mcast
?
2359 mac_filters
->mcast_accept_all
| mask
:
2360 mac_filters
->mcast_accept_all
& ~mask
;
2362 mac_filters
->bcast_accept_all
= accp_all_bcast
?
2363 mac_filters
->bcast_accept_all
| mask
:
2364 mac_filters
->bcast_accept_all
& ~mask
;
2366 mac_filters
->unmatched_unicast
= unmatched_unicast
?
2367 mac_filters
->unmatched_unicast
| mask
:
2368 mac_filters
->unmatched_unicast
& ~mask
;
2370 DP(BNX2X_MSG_SP
, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2371 "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2372 mac_filters
->ucast_drop_all
, mac_filters
->mcast_drop_all
,
2373 mac_filters
->ucast_accept_all
, mac_filters
->mcast_accept_all
,
2374 mac_filters
->bcast_accept_all
);
2376 /* write the MAC filter structure*/
2377 __storm_memset_mac_filters(bp
, mac_filters
, p
->func_id
);
2379 /* The operation is completed */
2380 clear_bit(p
->state
, p
->pstate
);
2381 smp_mb__after_atomic();
2386 /* Setup ramrod data */
2387 static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid
,
2388 struct eth_classify_header
*hdr
,
2391 hdr
->echo
= cpu_to_le32(cid
);
2392 hdr
->rule_cnt
= rule_cnt
;
2395 static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x
*bp
,
2396 unsigned long *accept_flags
,
2397 struct eth_filter_rules_cmd
*cmd
,
2398 bool clear_accept_all
)
2402 /* start with 'drop-all' */
2403 state
= ETH_FILTER_RULES_CMD_UCAST_DROP_ALL
|
2404 ETH_FILTER_RULES_CMD_MCAST_DROP_ALL
;
2406 if (test_bit(BNX2X_ACCEPT_UNICAST
, accept_flags
))
2407 state
&= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL
;
2409 if (test_bit(BNX2X_ACCEPT_MULTICAST
, accept_flags
))
2410 state
&= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL
;
2412 if (test_bit(BNX2X_ACCEPT_ALL_UNICAST
, accept_flags
)) {
2413 state
&= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL
;
2414 state
|= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL
;
2417 if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST
, accept_flags
)) {
2418 state
|= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL
;
2419 state
&= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL
;
2422 if (test_bit(BNX2X_ACCEPT_BROADCAST
, accept_flags
))
2423 state
|= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL
;
2425 if (test_bit(BNX2X_ACCEPT_UNMATCHED
, accept_flags
)) {
2426 state
&= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL
;
2427 state
|= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED
;
2430 if (test_bit(BNX2X_ACCEPT_ANY_VLAN
, accept_flags
))
2431 state
|= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN
;
2433 /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */
2434 if (clear_accept_all
) {
2435 state
&= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL
;
2436 state
&= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL
;
2437 state
&= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL
;
2438 state
&= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED
;
2441 cmd
->state
= cpu_to_le16(state
);
2444 static int bnx2x_set_rx_mode_e2(struct bnx2x
*bp
,
2445 struct bnx2x_rx_mode_ramrod_params
*p
)
2447 struct eth_filter_rules_ramrod_data
*data
= p
->rdata
;
2451 /* Reset the ramrod data buffer */
2452 memset(data
, 0, sizeof(*data
));
2454 /* Setup ramrod data */
2456 /* Tx (internal switching) */
2457 if (test_bit(RAMROD_TX
, &p
->ramrod_flags
)) {
2458 data
->rules
[rule_idx
].client_id
= p
->cl_id
;
2459 data
->rules
[rule_idx
].func_id
= p
->func_id
;
2461 data
->rules
[rule_idx
].cmd_general_data
=
2462 ETH_FILTER_RULES_CMD_TX_CMD
;
2464 bnx2x_rx_mode_set_cmd_state_e2(bp
, &p
->tx_accept_flags
,
2465 &(data
->rules
[rule_idx
++]),
2470 if (test_bit(RAMROD_RX
, &p
->ramrod_flags
)) {
2471 data
->rules
[rule_idx
].client_id
= p
->cl_id
;
2472 data
->rules
[rule_idx
].func_id
= p
->func_id
;
2474 data
->rules
[rule_idx
].cmd_general_data
=
2475 ETH_FILTER_RULES_CMD_RX_CMD
;
2477 bnx2x_rx_mode_set_cmd_state_e2(bp
, &p
->rx_accept_flags
,
2478 &(data
->rules
[rule_idx
++]),
2482 /* If FCoE Queue configuration has been requested configure the Rx and
2483 * internal switching modes for this queue in separate rules.
2485 * FCoE queue shell never be set to ACCEPT_ALL packets of any sort:
2486 * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED.
2488 if (test_bit(BNX2X_RX_MODE_FCOE_ETH
, &p
->rx_mode_flags
)) {
2489 /* Tx (internal switching) */
2490 if (test_bit(RAMROD_TX
, &p
->ramrod_flags
)) {
2491 data
->rules
[rule_idx
].client_id
= bnx2x_fcoe(bp
, cl_id
);
2492 data
->rules
[rule_idx
].func_id
= p
->func_id
;
2494 data
->rules
[rule_idx
].cmd_general_data
=
2495 ETH_FILTER_RULES_CMD_TX_CMD
;
2497 bnx2x_rx_mode_set_cmd_state_e2(bp
, &p
->tx_accept_flags
,
2498 &(data
->rules
[rule_idx
]),
2504 if (test_bit(RAMROD_RX
, &p
->ramrod_flags
)) {
2505 data
->rules
[rule_idx
].client_id
= bnx2x_fcoe(bp
, cl_id
);
2506 data
->rules
[rule_idx
].func_id
= p
->func_id
;
2508 data
->rules
[rule_idx
].cmd_general_data
=
2509 ETH_FILTER_RULES_CMD_RX_CMD
;
2511 bnx2x_rx_mode_set_cmd_state_e2(bp
, &p
->rx_accept_flags
,
2512 &(data
->rules
[rule_idx
]),
2518 /* Set the ramrod header (most importantly - number of rules to
2521 bnx2x_rx_mode_set_rdata_hdr_e2(p
->cid
, &data
->header
, rule_idx
);
2523 DP(BNX2X_MSG_SP
, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2524 data
->header
.rule_cnt
, p
->rx_accept_flags
,
2525 p
->tx_accept_flags
);
2527 /* No need for an explicit memory barrier here as long as we
2528 * ensure the ordering of writing to the SPQ element
2529 * and updating of the SPQ producer which involves a memory
2530 * read. If the memory read is removed we will have to put a
2531 * full memory barrier there (inside bnx2x_sp_post()).
2535 rc
= bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_FILTER_RULES
, p
->cid
,
2536 U64_HI(p
->rdata_mapping
),
2537 U64_LO(p
->rdata_mapping
),
2538 ETH_CONNECTION_TYPE
);
2542 /* Ramrod completion is pending */
2546 static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x
*bp
,
2547 struct bnx2x_rx_mode_ramrod_params
*p
)
2549 return bnx2x_state_wait(bp
, p
->state
, p
->pstate
);
2552 static int bnx2x_empty_rx_mode_wait(struct bnx2x
*bp
,
2553 struct bnx2x_rx_mode_ramrod_params
*p
)
2559 int bnx2x_config_rx_mode(struct bnx2x
*bp
,
2560 struct bnx2x_rx_mode_ramrod_params
*p
)
2564 /* Configure the new classification in the chip */
2565 rc
= p
->rx_mode_obj
->config_rx_mode(bp
, p
);
2569 /* Wait for a ramrod completion if was requested */
2570 if (test_bit(RAMROD_COMP_WAIT
, &p
->ramrod_flags
)) {
2571 rc
= p
->rx_mode_obj
->wait_comp(bp
, p
);
2579 void bnx2x_init_rx_mode_obj(struct bnx2x
*bp
,
2580 struct bnx2x_rx_mode_obj
*o
)
2582 if (CHIP_IS_E1x(bp
)) {
2583 o
->wait_comp
= bnx2x_empty_rx_mode_wait
;
2584 o
->config_rx_mode
= bnx2x_set_rx_mode_e1x
;
2586 o
->wait_comp
= bnx2x_wait_rx_mode_comp_e2
;
2587 o
->config_rx_mode
= bnx2x_set_rx_mode_e2
;
2591 /********************* Multicast verbs: SET, CLEAR ****************************/
2592 static inline u8
bnx2x_mcast_bin_from_mac(u8
*mac
)
2594 return (crc32c_le(0, mac
, ETH_ALEN
) >> 24) & 0xff;
2597 struct bnx2x_mcast_mac_elem
{
2598 struct list_head link
;
2600 u8 pad
[2]; /* For a natural alignment of the following buffer */
2603 struct bnx2x_mcast_bin_elem
{
2604 struct list_head link
;
2606 int type
; /* BNX2X_MCAST_CMD_SET_{ADD, DEL} */
2609 struct bnx2x_pending_mcast_cmd
{
2610 struct list_head link
;
2611 int type
; /* BNX2X_MCAST_CMD_X */
2613 struct list_head macs_head
;
2614 u32 macs_num
; /* Needed for DEL command */
2615 int next_bin
; /* Needed for RESTORE flow with aprox match */
2618 bool set_convert
; /* in case type == BNX2X_MCAST_CMD_SET, this is set
2619 * when macs_head had been converted to a list of
2620 * bnx2x_mcast_bin_elem.
2623 bool done
; /* set to true, when the command has been handled,
2624 * practically used in 57712 handling only, where one pending
2625 * command may be handled in a few operations. As long as for
2626 * other chips every operation handling is completed in a
2627 * single ramrod, there is no need to utilize this field.
2631 static int bnx2x_mcast_wait(struct bnx2x
*bp
,
2632 struct bnx2x_mcast_obj
*o
)
2634 if (bnx2x_state_wait(bp
, o
->sched_state
, o
->raw
.pstate
) ||
2635 o
->raw
.wait_comp(bp
, &o
->raw
))
2641 static int bnx2x_mcast_enqueue_cmd(struct bnx2x
*bp
,
2642 struct bnx2x_mcast_obj
*o
,
2643 struct bnx2x_mcast_ramrod_params
*p
,
2644 enum bnx2x_mcast_cmd cmd
)
2647 struct bnx2x_pending_mcast_cmd
*new_cmd
;
2648 struct bnx2x_mcast_mac_elem
*cur_mac
= NULL
;
2649 struct bnx2x_mcast_list_elem
*pos
;
2650 int macs_list_len
= 0, macs_list_len_size
;
2652 /* When adding MACs we'll need to store their values */
2653 if (cmd
== BNX2X_MCAST_CMD_ADD
|| cmd
== BNX2X_MCAST_CMD_SET
)
2654 macs_list_len
= p
->mcast_list_len
;
2656 /* If the command is empty ("handle pending commands only"), break */
2657 if (!p
->mcast_list_len
)
2660 /* For a set command, we need to allocate sufficient memory for all
2661 * the bins, since we can't analyze at this point how much memory would
2664 macs_list_len_size
= macs_list_len
*
2665 sizeof(struct bnx2x_mcast_mac_elem
);
2666 if (cmd
== BNX2X_MCAST_CMD_SET
) {
2667 int bin_size
= BNX2X_MCAST_BINS_NUM
*
2668 sizeof(struct bnx2x_mcast_bin_elem
);
2670 if (bin_size
> macs_list_len_size
)
2671 macs_list_len_size
= bin_size
;
2673 total_sz
= sizeof(*new_cmd
) + macs_list_len_size
;
2675 /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */
2676 new_cmd
= kzalloc(total_sz
, GFP_ATOMIC
);
2681 DP(BNX2X_MSG_SP
, "About to enqueue a new %d command. macs_list_len=%d\n",
2682 cmd
, macs_list_len
);
2684 INIT_LIST_HEAD(&new_cmd
->data
.macs_head
);
2686 new_cmd
->type
= cmd
;
2687 new_cmd
->done
= false;
2690 case BNX2X_MCAST_CMD_ADD
:
2691 case BNX2X_MCAST_CMD_SET
:
2692 cur_mac
= (struct bnx2x_mcast_mac_elem
*)
2693 ((u8
*)new_cmd
+ sizeof(*new_cmd
));
2695 /* Push the MACs of the current command into the pending command
2698 list_for_each_entry(pos
, &p
->mcast_list
, link
) {
2699 memcpy(cur_mac
->mac
, pos
->mac
, ETH_ALEN
);
2700 list_add_tail(&cur_mac
->link
, &new_cmd
->data
.macs_head
);
2706 case BNX2X_MCAST_CMD_DEL
:
2707 new_cmd
->data
.macs_num
= p
->mcast_list_len
;
2710 case BNX2X_MCAST_CMD_RESTORE
:
2711 new_cmd
->data
.next_bin
= 0;
2716 BNX2X_ERR("Unknown command: %d\n", cmd
);
2720 /* Push the new pending command to the tail of the pending list: FIFO */
2721 list_add_tail(&new_cmd
->link
, &o
->pending_cmds_head
);
2729 * bnx2x_mcast_get_next_bin - get the next set bin (index)
2732 * @last: index to start looking from (including)
2734 * returns the next found (set) bin or a negative value if none is found.
2736 static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj
*o
, int last
)
2738 int i
, j
, inner_start
= last
% BIT_VEC64_ELEM_SZ
;
2740 for (i
= last
/ BIT_VEC64_ELEM_SZ
; i
< BNX2X_MCAST_VEC_SZ
; i
++) {
2741 if (o
->registry
.aprox_match
.vec
[i
])
2742 for (j
= inner_start
; j
< BIT_VEC64_ELEM_SZ
; j
++) {
2743 int cur_bit
= j
+ BIT_VEC64_ELEM_SZ
* i
;
2744 if (BIT_VEC64_TEST_BIT(o
->registry
.aprox_match
.
2757 * bnx2x_mcast_clear_first_bin - find the first set bin and clear it
2761 * returns the index of the found bin or -1 if none is found
2763 static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj
*o
)
2765 int cur_bit
= bnx2x_mcast_get_next_bin(o
, 0);
2768 BIT_VEC64_CLEAR_BIT(o
->registry
.aprox_match
.vec
, cur_bit
);
2773 static inline u8
bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj
*o
)
2775 struct bnx2x_raw_obj
*raw
= &o
->raw
;
2778 if ((raw
->obj_type
== BNX2X_OBJ_TYPE_TX
) ||
2779 (raw
->obj_type
== BNX2X_OBJ_TYPE_RX_TX
))
2780 rx_tx_flag
|= ETH_MULTICAST_RULES_CMD_TX_CMD
;
2782 if ((raw
->obj_type
== BNX2X_OBJ_TYPE_RX
) ||
2783 (raw
->obj_type
== BNX2X_OBJ_TYPE_RX_TX
))
2784 rx_tx_flag
|= ETH_MULTICAST_RULES_CMD_RX_CMD
;
2789 static void bnx2x_mcast_set_one_rule_e2(struct bnx2x
*bp
,
2790 struct bnx2x_mcast_obj
*o
, int idx
,
2791 union bnx2x_mcast_config_data
*cfg_data
,
2792 enum bnx2x_mcast_cmd cmd
)
2794 struct bnx2x_raw_obj
*r
= &o
->raw
;
2795 struct eth_multicast_rules_ramrod_data
*data
=
2796 (struct eth_multicast_rules_ramrod_data
*)(r
->rdata
);
2797 u8 func_id
= r
->func_id
;
2798 u8 rx_tx_add_flag
= bnx2x_mcast_get_rx_tx_flag(o
);
2801 if ((cmd
== BNX2X_MCAST_CMD_ADD
) || (cmd
== BNX2X_MCAST_CMD_RESTORE
) ||
2802 (cmd
== BNX2X_MCAST_CMD_SET_ADD
))
2803 rx_tx_add_flag
|= ETH_MULTICAST_RULES_CMD_IS_ADD
;
2805 data
->rules
[idx
].cmd_general_data
|= rx_tx_add_flag
;
2807 /* Get a bin and update a bins' vector */
2809 case BNX2X_MCAST_CMD_ADD
:
2810 bin
= bnx2x_mcast_bin_from_mac(cfg_data
->mac
);
2811 BIT_VEC64_SET_BIT(o
->registry
.aprox_match
.vec
, bin
);
2814 case BNX2X_MCAST_CMD_DEL
:
2815 /* If there were no more bins to clear
2816 * (bnx2x_mcast_clear_first_bin() returns -1) then we would
2817 * clear any (0xff) bin.
2818 * See bnx2x_mcast_validate_e2() for explanation when it may
2821 bin
= bnx2x_mcast_clear_first_bin(o
);
2824 case BNX2X_MCAST_CMD_RESTORE
:
2825 bin
= cfg_data
->bin
;
2828 case BNX2X_MCAST_CMD_SET_ADD
:
2829 bin
= cfg_data
->bin
;
2830 BIT_VEC64_SET_BIT(o
->registry
.aprox_match
.vec
, bin
);
2833 case BNX2X_MCAST_CMD_SET_DEL
:
2834 bin
= cfg_data
->bin
;
2835 BIT_VEC64_CLEAR_BIT(o
->registry
.aprox_match
.vec
, bin
);
2839 BNX2X_ERR("Unknown command: %d\n", cmd
);
2843 DP(BNX2X_MSG_SP
, "%s bin %d\n",
2844 ((rx_tx_add_flag
& ETH_MULTICAST_RULES_CMD_IS_ADD
) ?
2845 "Setting" : "Clearing"), bin
);
2847 data
->rules
[idx
].bin_id
= (u8
)bin
;
2848 data
->rules
[idx
].func_id
= func_id
;
2849 data
->rules
[idx
].engine_id
= o
->engine_id
;
2853 * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry
2855 * @bp: device handle
2857 * @start_bin: index in the registry to start from (including)
2858 * @rdata_idx: index in the ramrod data to start from
2860 * returns last handled bin index or -1 if all bins have been handled
2862 static inline int bnx2x_mcast_handle_restore_cmd_e2(
2863 struct bnx2x
*bp
, struct bnx2x_mcast_obj
*o
, int start_bin
,
2866 int cur_bin
, cnt
= *rdata_idx
;
2867 union bnx2x_mcast_config_data cfg_data
= {NULL
};
2869 /* go through the registry and configure the bins from it */
2870 for (cur_bin
= bnx2x_mcast_get_next_bin(o
, start_bin
); cur_bin
>= 0;
2871 cur_bin
= bnx2x_mcast_get_next_bin(o
, cur_bin
+ 1)) {
2873 cfg_data
.bin
= (u8
)cur_bin
;
2874 o
->set_one_rule(bp
, o
, cnt
, &cfg_data
,
2875 BNX2X_MCAST_CMD_RESTORE
);
2879 DP(BNX2X_MSG_SP
, "About to configure a bin %d\n", cur_bin
);
2881 /* Break if we reached the maximum number
2884 if (cnt
>= o
->max_cmd_len
)
2893 static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x
*bp
,
2894 struct bnx2x_mcast_obj
*o
, struct bnx2x_pending_mcast_cmd
*cmd_pos
,
2897 struct bnx2x_mcast_mac_elem
*pmac_pos
, *pmac_pos_n
;
2898 int cnt
= *line_idx
;
2899 union bnx2x_mcast_config_data cfg_data
= {NULL
};
2901 list_for_each_entry_safe(pmac_pos
, pmac_pos_n
, &cmd_pos
->data
.macs_head
,
2904 cfg_data
.mac
= &pmac_pos
->mac
[0];
2905 o
->set_one_rule(bp
, o
, cnt
, &cfg_data
, cmd_pos
->type
);
2909 DP(BNX2X_MSG_SP
, "About to configure %pM mcast MAC\n",
2912 list_del(&pmac_pos
->link
);
2914 /* Break if we reached the maximum number
2917 if (cnt
>= o
->max_cmd_len
)
2923 /* if no more MACs to configure - we are done */
2924 if (list_empty(&cmd_pos
->data
.macs_head
))
2925 cmd_pos
->done
= true;
2928 static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x
*bp
,
2929 struct bnx2x_mcast_obj
*o
, struct bnx2x_pending_mcast_cmd
*cmd_pos
,
2932 int cnt
= *line_idx
;
2934 while (cmd_pos
->data
.macs_num
) {
2935 o
->set_one_rule(bp
, o
, cnt
, NULL
, cmd_pos
->type
);
2939 cmd_pos
->data
.macs_num
--;
2941 DP(BNX2X_MSG_SP
, "Deleting MAC. %d left,cnt is %d\n",
2942 cmd_pos
->data
.macs_num
, cnt
);
2944 /* Break if we reached the maximum
2947 if (cnt
>= o
->max_cmd_len
)
2953 /* If we cleared all bins - we are done */
2954 if (!cmd_pos
->data
.macs_num
)
2955 cmd_pos
->done
= true;
2958 static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x
*bp
,
2959 struct bnx2x_mcast_obj
*o
, struct bnx2x_pending_mcast_cmd
*cmd_pos
,
2962 cmd_pos
->data
.next_bin
= o
->hdl_restore(bp
, o
, cmd_pos
->data
.next_bin
,
2965 if (cmd_pos
->data
.next_bin
< 0)
2966 /* If o->set_restore returned -1 we are done */
2967 cmd_pos
->done
= true;
2969 /* Start from the next bin next time */
2970 cmd_pos
->data
.next_bin
++;
2974 bnx2x_mcast_hdl_pending_set_e2_convert(struct bnx2x
*bp
,
2975 struct bnx2x_mcast_obj
*o
,
2976 struct bnx2x_pending_mcast_cmd
*cmd_pos
)
2978 u64 cur
[BNX2X_MCAST_VEC_SZ
], req
[BNX2X_MCAST_VEC_SZ
];
2979 struct bnx2x_mcast_mac_elem
*pmac_pos
, *pmac_pos_n
;
2980 struct bnx2x_mcast_bin_elem
*p_item
;
2981 int i
, cnt
= 0, mac_cnt
= 0;
2983 memset(req
, 0, sizeof(u64
) * BNX2X_MCAST_VEC_SZ
);
2984 memcpy(cur
, o
->registry
.aprox_match
.vec
,
2985 sizeof(u64
) * BNX2X_MCAST_VEC_SZ
);
2987 /* Fill `current' with the required set of bins to configure */
2988 list_for_each_entry_safe(pmac_pos
, pmac_pos_n
, &cmd_pos
->data
.macs_head
,
2990 int bin
= bnx2x_mcast_bin_from_mac(pmac_pos
->mac
);
2992 DP(BNX2X_MSG_SP
, "Set contains %pM mcast MAC\n",
2995 BIT_VEC64_SET_BIT(req
, bin
);
2996 list_del(&pmac_pos
->link
);
3000 /* We no longer have use for the MACs; Need to re-use memory for
3001 * a list that will be used to configure bins.
3003 cmd_pos
->set_convert
= true;
3004 p_item
= (struct bnx2x_mcast_bin_elem
*)(cmd_pos
+ 1);
3005 INIT_LIST_HEAD(&cmd_pos
->data
.macs_head
);
3007 for (i
= 0; i
< BNX2X_MCAST_BINS_NUM
; i
++) {
3008 bool b_current
= !!BIT_VEC64_TEST_BIT(cur
, i
);
3009 bool b_required
= !!BIT_VEC64_TEST_BIT(req
, i
);
3011 if (b_current
== b_required
)
3015 p_item
->type
= b_required
? BNX2X_MCAST_CMD_SET_ADD
3016 : BNX2X_MCAST_CMD_SET_DEL
;
3017 list_add_tail(&p_item
->link
, &cmd_pos
->data
.macs_head
);
3022 /* We now definitely know how many commands are hiding here.
3023 * Also need to correct the disruption we've added to guarantee this
3024 * would be enqueued.
3026 o
->total_pending_num
-= (o
->max_cmd_len
+ mac_cnt
);
3027 o
->total_pending_num
+= cnt
;
3029 DP(BNX2X_MSG_SP
, "o->total_pending_num=%d\n", o
->total_pending_num
);
3033 bnx2x_mcast_hdl_pending_set_e2(struct bnx2x
*bp
,
3034 struct bnx2x_mcast_obj
*o
,
3035 struct bnx2x_pending_mcast_cmd
*cmd_pos
,
3038 union bnx2x_mcast_config_data cfg_data
= {NULL
};
3039 struct bnx2x_mcast_bin_elem
*p_item
, *p_item_n
;
3041 /* This is actually a 2-part scheme - it starts by converting the MACs
3042 * into a list of bins to be added/removed, and correcting the numbers
3043 * on the object. this is now allowed, as we're now sure that all
3044 * previous configured requests have already applied.
3045 * The second part is actually adding rules for the newly introduced
3046 * entries [like all the rest of the hdl_pending functions].
3048 if (!cmd_pos
->set_convert
)
3049 bnx2x_mcast_hdl_pending_set_e2_convert(bp
, o
, cmd_pos
);
3051 list_for_each_entry_safe(p_item
, p_item_n
, &cmd_pos
->data
.macs_head
,
3053 cfg_data
.bin
= (u8
)p_item
->bin
;
3054 o
->set_one_rule(bp
, o
, *cnt
, &cfg_data
, p_item
->type
);
3057 list_del(&p_item
->link
);
3059 /* Break if we reached the maximum number of rules. */
3060 if (*cnt
>= o
->max_cmd_len
)
3064 /* if no more MACs to configure - we are done */
3065 if (list_empty(&cmd_pos
->data
.macs_head
))
3066 cmd_pos
->done
= true;
3069 static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x
*bp
,
3070 struct bnx2x_mcast_ramrod_params
*p
)
3072 struct bnx2x_pending_mcast_cmd
*cmd_pos
, *cmd_pos_n
;
3074 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3076 list_for_each_entry_safe(cmd_pos
, cmd_pos_n
, &o
->pending_cmds_head
,
3078 switch (cmd_pos
->type
) {
3079 case BNX2X_MCAST_CMD_ADD
:
3080 bnx2x_mcast_hdl_pending_add_e2(bp
, o
, cmd_pos
, &cnt
);
3083 case BNX2X_MCAST_CMD_DEL
:
3084 bnx2x_mcast_hdl_pending_del_e2(bp
, o
, cmd_pos
, &cnt
);
3087 case BNX2X_MCAST_CMD_RESTORE
:
3088 bnx2x_mcast_hdl_pending_restore_e2(bp
, o
, cmd_pos
,
3092 case BNX2X_MCAST_CMD_SET
:
3093 bnx2x_mcast_hdl_pending_set_e2(bp
, o
, cmd_pos
, &cnt
);
3097 BNX2X_ERR("Unknown command: %d\n", cmd_pos
->type
);
3101 /* If the command has been completed - remove it from the list
3102 * and free the memory
3104 if (cmd_pos
->done
) {
3105 list_del(&cmd_pos
->link
);
3109 /* Break if we reached the maximum number of rules */
3110 if (cnt
>= o
->max_cmd_len
)
3117 static inline void bnx2x_mcast_hdl_add(struct bnx2x
*bp
,
3118 struct bnx2x_mcast_obj
*o
, struct bnx2x_mcast_ramrod_params
*p
,
3121 struct bnx2x_mcast_list_elem
*mlist_pos
;
3122 union bnx2x_mcast_config_data cfg_data
= {NULL
};
3123 int cnt
= *line_idx
;
3125 list_for_each_entry(mlist_pos
, &p
->mcast_list
, link
) {
3126 cfg_data
.mac
= mlist_pos
->mac
;
3127 o
->set_one_rule(bp
, o
, cnt
, &cfg_data
, BNX2X_MCAST_CMD_ADD
);
3131 DP(BNX2X_MSG_SP
, "About to configure %pM mcast MAC\n",
3138 static inline void bnx2x_mcast_hdl_del(struct bnx2x
*bp
,
3139 struct bnx2x_mcast_obj
*o
, struct bnx2x_mcast_ramrod_params
*p
,
3142 int cnt
= *line_idx
, i
;
3144 for (i
= 0; i
< p
->mcast_list_len
; i
++) {
3145 o
->set_one_rule(bp
, o
, cnt
, NULL
, BNX2X_MCAST_CMD_DEL
);
3149 DP(BNX2X_MSG_SP
, "Deleting MAC. %d left\n",
3150 p
->mcast_list_len
- i
- 1);
3157 * bnx2x_mcast_handle_current_cmd -
3159 * @bp: device handle
3162 * @start_cnt: first line in the ramrod data that may be used
3164 * This function is called iff there is enough place for the current command in
3166 * Returns number of lines filled in the ramrod data in total.
3168 static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x
*bp
,
3169 struct bnx2x_mcast_ramrod_params
*p
,
3170 enum bnx2x_mcast_cmd cmd
,
3173 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3174 int cnt
= start_cnt
;
3176 DP(BNX2X_MSG_SP
, "p->mcast_list_len=%d\n", p
->mcast_list_len
);
3179 case BNX2X_MCAST_CMD_ADD
:
3180 bnx2x_mcast_hdl_add(bp
, o
, p
, &cnt
);
3183 case BNX2X_MCAST_CMD_DEL
:
3184 bnx2x_mcast_hdl_del(bp
, o
, p
, &cnt
);
3187 case BNX2X_MCAST_CMD_RESTORE
:
3188 o
->hdl_restore(bp
, o
, 0, &cnt
);
3192 BNX2X_ERR("Unknown command: %d\n", cmd
);
3196 /* The current command has been handled */
3197 p
->mcast_list_len
= 0;
3202 static int bnx2x_mcast_validate_e2(struct bnx2x
*bp
,
3203 struct bnx2x_mcast_ramrod_params
*p
,
3204 enum bnx2x_mcast_cmd cmd
)
3206 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3207 int reg_sz
= o
->get_registry_size(o
);
3210 /* DEL command deletes all currently configured MACs */
3211 case BNX2X_MCAST_CMD_DEL
:
3212 o
->set_registry_size(o
, 0);
3215 /* RESTORE command will restore the entire multicast configuration */
3216 case BNX2X_MCAST_CMD_RESTORE
:
3217 /* Here we set the approximate amount of work to do, which in
3218 * fact may be only less as some MACs in postponed ADD
3219 * command(s) scheduled before this command may fall into
3220 * the same bin and the actual number of bins set in the
3221 * registry would be less than we estimated here. See
3222 * bnx2x_mcast_set_one_rule_e2() for further details.
3224 p
->mcast_list_len
= reg_sz
;
3227 case BNX2X_MCAST_CMD_ADD
:
3228 case BNX2X_MCAST_CMD_CONT
:
3229 /* Here we assume that all new MACs will fall into new bins.
3230 * However we will correct the real registry size after we
3231 * handle all pending commands.
3233 o
->set_registry_size(o
, reg_sz
+ p
->mcast_list_len
);
3236 case BNX2X_MCAST_CMD_SET
:
3237 /* We can only learn how many commands would actually be used
3238 * when this is being configured. So for now, simply guarantee
3239 * the command will be enqueued [to refrain from adding logic
3240 * that handles this and THEN learns it needs several ramrods].
3241 * Just like for ADD/Cont, the mcast_list_len might be an over
3242 * estimation; or even more so, since we don't take into
3243 * account the possibility of removal of existing bins.
3245 o
->set_registry_size(o
, reg_sz
+ p
->mcast_list_len
);
3246 o
->total_pending_num
+= o
->max_cmd_len
;
3250 BNX2X_ERR("Unknown command: %d\n", cmd
);
3254 /* Increase the total number of MACs pending to be configured */
3255 o
->total_pending_num
+= p
->mcast_list_len
;
3260 static void bnx2x_mcast_revert_e2(struct bnx2x
*bp
,
3261 struct bnx2x_mcast_ramrod_params
*p
,
3263 enum bnx2x_mcast_cmd cmd
)
3265 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3267 o
->set_registry_size(o
, old_num_bins
);
3268 o
->total_pending_num
-= p
->mcast_list_len
;
3270 if (cmd
== BNX2X_MCAST_CMD_SET
)
3271 o
->total_pending_num
-= o
->max_cmd_len
;
3275 * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values
3277 * @bp: device handle
3279 * @len: number of rules to handle
3281 static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x
*bp
,
3282 struct bnx2x_mcast_ramrod_params
*p
,
3285 struct bnx2x_raw_obj
*r
= &p
->mcast_obj
->raw
;
3286 struct eth_multicast_rules_ramrod_data
*data
=
3287 (struct eth_multicast_rules_ramrod_data
*)(r
->rdata
);
3289 data
->header
.echo
= cpu_to_le32((r
->cid
& BNX2X_SWCID_MASK
) |
3290 (BNX2X_FILTER_MCAST_PENDING
<<
3291 BNX2X_SWCID_SHIFT
));
3292 data
->header
.rule_cnt
= len
;
3296 * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins
3298 * @bp: device handle
3301 * Recalculate the actual number of set bins in the registry using Brian
3302 * Kernighan's algorithm: it's execution complexity is as a number of set bins.
3304 * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1().
3306 static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x
*bp
,
3307 struct bnx2x_mcast_obj
*o
)
3312 for (i
= 0; i
< BNX2X_MCAST_VEC_SZ
; i
++) {
3313 elem
= o
->registry
.aprox_match
.vec
[i
];
3318 o
->set_registry_size(o
, cnt
);
3323 static int bnx2x_mcast_setup_e2(struct bnx2x
*bp
,
3324 struct bnx2x_mcast_ramrod_params
*p
,
3325 enum bnx2x_mcast_cmd cmd
)
3327 struct bnx2x_raw_obj
*raw
= &p
->mcast_obj
->raw
;
3328 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3329 struct eth_multicast_rules_ramrod_data
*data
=
3330 (struct eth_multicast_rules_ramrod_data
*)(raw
->rdata
);
3333 /* Reset the ramrod data buffer */
3334 memset(data
, 0, sizeof(*data
));
3336 cnt
= bnx2x_mcast_handle_pending_cmds_e2(bp
, p
);
3338 /* If there are no more pending commands - clear SCHEDULED state */
3339 if (list_empty(&o
->pending_cmds_head
))
3342 /* The below may be true iff there was enough room in ramrod
3343 * data for all pending commands and for the current
3344 * command. Otherwise the current command would have been added
3345 * to the pending commands and p->mcast_list_len would have been
3348 if (p
->mcast_list_len
> 0)
3349 cnt
= bnx2x_mcast_handle_current_cmd(bp
, p
, cmd
, cnt
);
3351 /* We've pulled out some MACs - update the total number of
3354 o
->total_pending_num
-= cnt
;
3357 WARN_ON(o
->total_pending_num
< 0);
3358 WARN_ON(cnt
> o
->max_cmd_len
);
3360 bnx2x_mcast_set_rdata_hdr_e2(bp
, p
, (u8
)cnt
);
3362 /* Update a registry size if there are no more pending operations.
3364 * We don't want to change the value of the registry size if there are
3365 * pending operations because we want it to always be equal to the
3366 * exact or the approximate number (see bnx2x_mcast_validate_e2()) of
3367 * set bins after the last requested operation in order to properly
3368 * evaluate the size of the next DEL/RESTORE operation.
3370 * Note that we update the registry itself during command(s) handling
3371 * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we
3372 * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but
3373 * with a limited amount of update commands (per MAC/bin) and we don't
3374 * know in this scope what the actual state of bins configuration is
3375 * going to be after this ramrod.
3377 if (!o
->total_pending_num
)
3378 bnx2x_mcast_refresh_registry_e2(bp
, o
);
3380 /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3381 * RAMROD_PENDING status immediately. due to the SET option, it's also
3382 * possible that after evaluating the differences there's no need for
3383 * a ramrod. In that case, we can skip it as well.
3385 if (test_bit(RAMROD_DRV_CLR_ONLY
, &p
->ramrod_flags
) || !cnt
) {
3386 raw
->clear_pending(raw
);
3389 /* No need for an explicit memory barrier here as long as we
3390 * ensure the ordering of writing to the SPQ element
3391 * and updating of the SPQ producer which involves a memory
3392 * read. If the memory read is removed we will have to put a
3393 * full memory barrier there (inside bnx2x_sp_post()).
3397 rc
= bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_MULTICAST_RULES
,
3398 raw
->cid
, U64_HI(raw
->rdata_mapping
),
3399 U64_LO(raw
->rdata_mapping
),
3400 ETH_CONNECTION_TYPE
);
3404 /* Ramrod completion is pending */
3409 static int bnx2x_mcast_validate_e1h(struct bnx2x
*bp
,
3410 struct bnx2x_mcast_ramrod_params
*p
,
3411 enum bnx2x_mcast_cmd cmd
)
3413 if (cmd
== BNX2X_MCAST_CMD_SET
) {
3414 BNX2X_ERR("Can't use `set' command on e1h!\n");
3418 /* Mark, that there is a work to do */
3419 if ((cmd
== BNX2X_MCAST_CMD_DEL
) || (cmd
== BNX2X_MCAST_CMD_RESTORE
))
3420 p
->mcast_list_len
= 1;
3425 static void bnx2x_mcast_revert_e1h(struct bnx2x
*bp
,
3426 struct bnx2x_mcast_ramrod_params
*p
,
3428 enum bnx2x_mcast_cmd cmd
)
3433 #define BNX2X_57711_SET_MC_FILTER(filter, bit) \
3435 (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \
3438 static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x
*bp
,
3439 struct bnx2x_mcast_obj
*o
,
3440 struct bnx2x_mcast_ramrod_params
*p
,
3443 struct bnx2x_mcast_list_elem
*mlist_pos
;
3446 list_for_each_entry(mlist_pos
, &p
->mcast_list
, link
) {
3447 bit
= bnx2x_mcast_bin_from_mac(mlist_pos
->mac
);
3448 BNX2X_57711_SET_MC_FILTER(mc_filter
, bit
);
3450 DP(BNX2X_MSG_SP
, "About to configure %pM mcast MAC, bin %d\n",
3451 mlist_pos
->mac
, bit
);
3453 /* bookkeeping... */
3454 BIT_VEC64_SET_BIT(o
->registry
.aprox_match
.vec
,
3459 static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x
*bp
,
3460 struct bnx2x_mcast_obj
*o
, struct bnx2x_mcast_ramrod_params
*p
,
3465 for (bit
= bnx2x_mcast_get_next_bin(o
, 0);
3467 bit
= bnx2x_mcast_get_next_bin(o
, bit
+ 1)) {
3468 BNX2X_57711_SET_MC_FILTER(mc_filter
, bit
);
3469 DP(BNX2X_MSG_SP
, "About to set bin %d\n", bit
);
3473 /* On 57711 we write the multicast MACs' approximate match
3474 * table by directly into the TSTORM's internal RAM. So we don't
3475 * really need to handle any tricks to make it work.
3477 static int bnx2x_mcast_setup_e1h(struct bnx2x
*bp
,
3478 struct bnx2x_mcast_ramrod_params
*p
,
3479 enum bnx2x_mcast_cmd cmd
)
3482 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3483 struct bnx2x_raw_obj
*r
= &o
->raw
;
3485 /* If CLEAR_ONLY has been requested - clear the registry
3486 * and clear a pending bit.
3488 if (!test_bit(RAMROD_DRV_CLR_ONLY
, &p
->ramrod_flags
)) {
3489 u32 mc_filter
[MC_HASH_SIZE
] = {0};
3491 /* Set the multicast filter bits before writing it into
3492 * the internal memory.
3495 case BNX2X_MCAST_CMD_ADD
:
3496 bnx2x_mcast_hdl_add_e1h(bp
, o
, p
, mc_filter
);
3499 case BNX2X_MCAST_CMD_DEL
:
3501 "Invalidating multicast MACs configuration\n");
3503 /* clear the registry */
3504 memset(o
->registry
.aprox_match
.vec
, 0,
3505 sizeof(o
->registry
.aprox_match
.vec
));
3508 case BNX2X_MCAST_CMD_RESTORE
:
3509 bnx2x_mcast_hdl_restore_e1h(bp
, o
, p
, mc_filter
);
3513 BNX2X_ERR("Unknown command: %d\n", cmd
);
3517 /* Set the mcast filter in the internal memory */
3518 for (i
= 0; i
< MC_HASH_SIZE
; i
++)
3519 REG_WR(bp
, MC_HASH_OFFSET(bp
, i
), mc_filter
[i
]);
3521 /* clear the registry */
3522 memset(o
->registry
.aprox_match
.vec
, 0,
3523 sizeof(o
->registry
.aprox_match
.vec
));
3526 r
->clear_pending(r
);
3531 static int bnx2x_mcast_validate_e1(struct bnx2x
*bp
,
3532 struct bnx2x_mcast_ramrod_params
*p
,
3533 enum bnx2x_mcast_cmd cmd
)
3535 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3536 int reg_sz
= o
->get_registry_size(o
);
3538 if (cmd
== BNX2X_MCAST_CMD_SET
) {
3539 BNX2X_ERR("Can't use `set' command on e1!\n");
3544 /* DEL command deletes all currently configured MACs */
3545 case BNX2X_MCAST_CMD_DEL
:
3546 o
->set_registry_size(o
, 0);
3549 /* RESTORE command will restore the entire multicast configuration */
3550 case BNX2X_MCAST_CMD_RESTORE
:
3551 p
->mcast_list_len
= reg_sz
;
3552 DP(BNX2X_MSG_SP
, "Command %d, p->mcast_list_len=%d\n",
3553 cmd
, p
->mcast_list_len
);
3556 case BNX2X_MCAST_CMD_ADD
:
3557 case BNX2X_MCAST_CMD_CONT
:
3558 /* Multicast MACs on 57710 are configured as unicast MACs and
3559 * there is only a limited number of CAM entries for that
3562 if (p
->mcast_list_len
> o
->max_cmd_len
) {
3563 BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n",
3567 /* Every configured MAC should be cleared if DEL command is
3568 * called. Only the last ADD command is relevant as long as
3569 * every ADD commands overrides the previous configuration.
3571 DP(BNX2X_MSG_SP
, "p->mcast_list_len=%d\n", p
->mcast_list_len
);
3572 if (p
->mcast_list_len
> 0)
3573 o
->set_registry_size(o
, p
->mcast_list_len
);
3578 BNX2X_ERR("Unknown command: %d\n", cmd
);
3582 /* We want to ensure that commands are executed one by one for 57710.
3583 * Therefore each none-empty command will consume o->max_cmd_len.
3585 if (p
->mcast_list_len
)
3586 o
->total_pending_num
+= o
->max_cmd_len
;
3591 static void bnx2x_mcast_revert_e1(struct bnx2x
*bp
,
3592 struct bnx2x_mcast_ramrod_params
*p
,
3594 enum bnx2x_mcast_cmd cmd
)
3596 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3598 o
->set_registry_size(o
, old_num_macs
);
3600 /* If current command hasn't been handled yet and we are
3601 * here means that it's meant to be dropped and we have to
3602 * update the number of outstanding MACs accordingly.
3604 if (p
->mcast_list_len
)
3605 o
->total_pending_num
-= o
->max_cmd_len
;
3608 static void bnx2x_mcast_set_one_rule_e1(struct bnx2x
*bp
,
3609 struct bnx2x_mcast_obj
*o
, int idx
,
3610 union bnx2x_mcast_config_data
*cfg_data
,
3611 enum bnx2x_mcast_cmd cmd
)
3613 struct bnx2x_raw_obj
*r
= &o
->raw
;
3614 struct mac_configuration_cmd
*data
=
3615 (struct mac_configuration_cmd
*)(r
->rdata
);
3618 if ((cmd
== BNX2X_MCAST_CMD_ADD
) || (cmd
== BNX2X_MCAST_CMD_RESTORE
)) {
3619 bnx2x_set_fw_mac_addr(&data
->config_table
[idx
].msb_mac_addr
,
3620 &data
->config_table
[idx
].middle_mac_addr
,
3621 &data
->config_table
[idx
].lsb_mac_addr
,
3624 data
->config_table
[idx
].vlan_id
= 0;
3625 data
->config_table
[idx
].pf_id
= r
->func_id
;
3626 data
->config_table
[idx
].clients_bit_vector
=
3627 cpu_to_le32(1 << r
->cl_id
);
3629 SET_FLAG(data
->config_table
[idx
].flags
,
3630 MAC_CONFIGURATION_ENTRY_ACTION_TYPE
,
3631 T_ETH_MAC_COMMAND_SET
);
3636 * bnx2x_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd
3638 * @bp: device handle
3640 * @len: number of rules to handle
3642 static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x
*bp
,
3643 struct bnx2x_mcast_ramrod_params
*p
,
3646 struct bnx2x_raw_obj
*r
= &p
->mcast_obj
->raw
;
3647 struct mac_configuration_cmd
*data
=
3648 (struct mac_configuration_cmd
*)(r
->rdata
);
3650 u8 offset
= (CHIP_REV_IS_SLOW(bp
) ?
3651 BNX2X_MAX_EMUL_MULTI
*(1 + r
->func_id
) :
3652 BNX2X_MAX_MULTICAST
*(1 + r
->func_id
));
3654 data
->hdr
.offset
= offset
;
3655 data
->hdr
.client_id
= cpu_to_le16(0xff);
3656 data
->hdr
.echo
= cpu_to_le32((r
->cid
& BNX2X_SWCID_MASK
) |
3657 (BNX2X_FILTER_MCAST_PENDING
<<
3658 BNX2X_SWCID_SHIFT
));
3659 data
->hdr
.length
= len
;
3663 * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710
3665 * @bp: device handle
3667 * @start_idx: index in the registry to start from
3668 * @rdata_idx: index in the ramrod data to start from
3670 * restore command for 57710 is like all other commands - always a stand alone
3671 * command - start_idx and rdata_idx will always be 0. This function will always
3673 * returns -1 to comply with 57712 variant.
3675 static inline int bnx2x_mcast_handle_restore_cmd_e1(
3676 struct bnx2x
*bp
, struct bnx2x_mcast_obj
*o
, int start_idx
,
3679 struct bnx2x_mcast_mac_elem
*elem
;
3681 union bnx2x_mcast_config_data cfg_data
= {NULL
};
3683 /* go through the registry and configure the MACs from it. */
3684 list_for_each_entry(elem
, &o
->registry
.exact_match
.macs
, link
) {
3685 cfg_data
.mac
= &elem
->mac
[0];
3686 o
->set_one_rule(bp
, o
, i
, &cfg_data
, BNX2X_MCAST_CMD_RESTORE
);
3690 DP(BNX2X_MSG_SP
, "About to configure %pM mcast MAC\n",
3699 static inline int bnx2x_mcast_handle_pending_cmds_e1(
3700 struct bnx2x
*bp
, struct bnx2x_mcast_ramrod_params
*p
)
3702 struct bnx2x_pending_mcast_cmd
*cmd_pos
;
3703 struct bnx2x_mcast_mac_elem
*pmac_pos
;
3704 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3705 union bnx2x_mcast_config_data cfg_data
= {NULL
};
3708 /* If nothing to be done - return */
3709 if (list_empty(&o
->pending_cmds_head
))
3712 /* Handle the first command */
3713 cmd_pos
= list_first_entry(&o
->pending_cmds_head
,
3714 struct bnx2x_pending_mcast_cmd
, link
);
3716 switch (cmd_pos
->type
) {
3717 case BNX2X_MCAST_CMD_ADD
:
3718 list_for_each_entry(pmac_pos
, &cmd_pos
->data
.macs_head
, link
) {
3719 cfg_data
.mac
= &pmac_pos
->mac
[0];
3720 o
->set_one_rule(bp
, o
, cnt
, &cfg_data
, cmd_pos
->type
);
3724 DP(BNX2X_MSG_SP
, "About to configure %pM mcast MAC\n",
3729 case BNX2X_MCAST_CMD_DEL
:
3730 cnt
= cmd_pos
->data
.macs_num
;
3731 DP(BNX2X_MSG_SP
, "About to delete %d multicast MACs\n", cnt
);
3734 case BNX2X_MCAST_CMD_RESTORE
:
3735 o
->hdl_restore(bp
, o
, 0, &cnt
);
3739 BNX2X_ERR("Unknown command: %d\n", cmd_pos
->type
);
3743 list_del(&cmd_pos
->link
);
3750 * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr().
3757 static inline void bnx2x_get_fw_mac_addr(__le16
*fw_hi
, __le16
*fw_mid
,
3758 __le16
*fw_lo
, u8
*mac
)
3760 mac
[1] = ((u8
*)fw_hi
)[0];
3761 mac
[0] = ((u8
*)fw_hi
)[1];
3762 mac
[3] = ((u8
*)fw_mid
)[0];
3763 mac
[2] = ((u8
*)fw_mid
)[1];
3764 mac
[5] = ((u8
*)fw_lo
)[0];
3765 mac
[4] = ((u8
*)fw_lo
)[1];
3769 * bnx2x_mcast_refresh_registry_e1 -
3771 * @bp: device handle
3774 * Check the ramrod data first entry flag to see if it's a DELETE or ADD command
3775 * and update the registry correspondingly: if ADD - allocate a memory and add
3776 * the entries to the registry (list), if DELETE - clear the registry and free
3779 static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x
*bp
,
3780 struct bnx2x_mcast_obj
*o
)
3782 struct bnx2x_raw_obj
*raw
= &o
->raw
;
3783 struct bnx2x_mcast_mac_elem
*elem
;
3784 struct mac_configuration_cmd
*data
=
3785 (struct mac_configuration_cmd
*)(raw
->rdata
);
3787 /* If first entry contains a SET bit - the command was ADD,
3788 * otherwise - DEL_ALL
3790 if (GET_FLAG(data
->config_table
[0].flags
,
3791 MAC_CONFIGURATION_ENTRY_ACTION_TYPE
)) {
3792 int i
, len
= data
->hdr
.length
;
3794 /* Break if it was a RESTORE command */
3795 if (!list_empty(&o
->registry
.exact_match
.macs
))
3798 elem
= kcalloc(len
, sizeof(*elem
), GFP_ATOMIC
);
3800 BNX2X_ERR("Failed to allocate registry memory\n");
3804 for (i
= 0; i
< len
; i
++, elem
++) {
3805 bnx2x_get_fw_mac_addr(
3806 &data
->config_table
[i
].msb_mac_addr
,
3807 &data
->config_table
[i
].middle_mac_addr
,
3808 &data
->config_table
[i
].lsb_mac_addr
,
3810 DP(BNX2X_MSG_SP
, "Adding registry entry for [%pM]\n",
3812 list_add_tail(&elem
->link
,
3813 &o
->registry
.exact_match
.macs
);
3816 elem
= list_first_entry(&o
->registry
.exact_match
.macs
,
3817 struct bnx2x_mcast_mac_elem
, link
);
3818 DP(BNX2X_MSG_SP
, "Deleting a registry\n");
3820 INIT_LIST_HEAD(&o
->registry
.exact_match
.macs
);
3826 static int bnx2x_mcast_setup_e1(struct bnx2x
*bp
,
3827 struct bnx2x_mcast_ramrod_params
*p
,
3828 enum bnx2x_mcast_cmd cmd
)
3830 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3831 struct bnx2x_raw_obj
*raw
= &o
->raw
;
3832 struct mac_configuration_cmd
*data
=
3833 (struct mac_configuration_cmd
*)(raw
->rdata
);
3836 /* Reset the ramrod data buffer */
3837 memset(data
, 0, sizeof(*data
));
3839 /* First set all entries as invalid */
3840 for (i
= 0; i
< o
->max_cmd_len
; i
++)
3841 SET_FLAG(data
->config_table
[i
].flags
,
3842 MAC_CONFIGURATION_ENTRY_ACTION_TYPE
,
3843 T_ETH_MAC_COMMAND_INVALIDATE
);
3845 /* Handle pending commands first */
3846 cnt
= bnx2x_mcast_handle_pending_cmds_e1(bp
, p
);
3848 /* If there are no more pending commands - clear SCHEDULED state */
3849 if (list_empty(&o
->pending_cmds_head
))
3852 /* The below may be true iff there were no pending commands */
3854 cnt
= bnx2x_mcast_handle_current_cmd(bp
, p
, cmd
, 0);
3856 /* For 57710 every command has o->max_cmd_len length to ensure that
3857 * commands are done one at a time.
3859 o
->total_pending_num
-= o
->max_cmd_len
;
3863 WARN_ON(cnt
> o
->max_cmd_len
);
3865 /* Set ramrod header (in particular, a number of entries to update) */
3866 bnx2x_mcast_set_rdata_hdr_e1(bp
, p
, (u8
)cnt
);
3868 /* update a registry: we need the registry contents to be always up
3869 * to date in order to be able to execute a RESTORE opcode. Here
3870 * we use the fact that for 57710 we sent one command at a time
3871 * hence we may take the registry update out of the command handling
3872 * and do it in a simpler way here.
3874 rc
= bnx2x_mcast_refresh_registry_e1(bp
, o
);
3878 /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3879 * RAMROD_PENDING status immediately.
3881 if (test_bit(RAMROD_DRV_CLR_ONLY
, &p
->ramrod_flags
)) {
3882 raw
->clear_pending(raw
);
3885 /* No need for an explicit memory barrier here as long as we
3886 * ensure the ordering of writing to the SPQ element
3887 * and updating of the SPQ producer which involves a memory
3888 * read. If the memory read is removed we will have to put a
3889 * full memory barrier there (inside bnx2x_sp_post()).
3893 rc
= bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_SET_MAC
, raw
->cid
,
3894 U64_HI(raw
->rdata_mapping
),
3895 U64_LO(raw
->rdata_mapping
),
3896 ETH_CONNECTION_TYPE
);
3900 /* Ramrod completion is pending */
3905 static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj
*o
)
3907 return o
->registry
.exact_match
.num_macs_set
;
3910 static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj
*o
)
3912 return o
->registry
.aprox_match
.num_bins_set
;
3915 static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj
*o
,
3918 o
->registry
.exact_match
.num_macs_set
= n
;
3921 static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj
*o
,
3924 o
->registry
.aprox_match
.num_bins_set
= n
;
3927 int bnx2x_config_mcast(struct bnx2x
*bp
,
3928 struct bnx2x_mcast_ramrod_params
*p
,
3929 enum bnx2x_mcast_cmd cmd
)
3931 struct bnx2x_mcast_obj
*o
= p
->mcast_obj
;
3932 struct bnx2x_raw_obj
*r
= &o
->raw
;
3933 int rc
= 0, old_reg_size
;
3935 /* This is needed to recover number of currently configured mcast macs
3936 * in case of failure.
3938 old_reg_size
= o
->get_registry_size(o
);
3940 /* Do some calculations and checks */
3941 rc
= o
->validate(bp
, p
, cmd
);
3945 /* Return if there is no work to do */
3946 if ((!p
->mcast_list_len
) && (!o
->check_sched(o
)))
3949 DP(BNX2X_MSG_SP
, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3950 o
->total_pending_num
, p
->mcast_list_len
, o
->max_cmd_len
);
3952 /* Enqueue the current command to the pending list if we can't complete
3953 * it in the current iteration
3955 if (r
->check_pending(r
) ||
3956 ((o
->max_cmd_len
> 0) && (o
->total_pending_num
> o
->max_cmd_len
))) {
3957 rc
= o
->enqueue_cmd(bp
, p
->mcast_obj
, p
, cmd
);
3961 /* As long as the current command is in a command list we
3962 * don't need to handle it separately.
3964 p
->mcast_list_len
= 0;
3967 if (!r
->check_pending(r
)) {
3969 /* Set 'pending' state */
3972 /* Configure the new classification in the chip */
3973 rc
= o
->config_mcast(bp
, p
, cmd
);
3977 /* Wait for a ramrod completion if was requested */
3978 if (test_bit(RAMROD_COMP_WAIT
, &p
->ramrod_flags
))
3979 rc
= o
->wait_comp(bp
, o
);
3985 r
->clear_pending(r
);
3988 o
->revert(bp
, p
, old_reg_size
, cmd
);
3993 static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj
*o
)
3995 smp_mb__before_atomic();
3996 clear_bit(o
->sched_state
, o
->raw
.pstate
);
3997 smp_mb__after_atomic();
4000 static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj
*o
)
4002 smp_mb__before_atomic();
4003 set_bit(o
->sched_state
, o
->raw
.pstate
);
4004 smp_mb__after_atomic();
4007 static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj
*o
)
4009 return !!test_bit(o
->sched_state
, o
->raw
.pstate
);
4012 static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj
*o
)
4014 return o
->raw
.check_pending(&o
->raw
) || o
->check_sched(o
);
4017 void bnx2x_init_mcast_obj(struct bnx2x
*bp
,
4018 struct bnx2x_mcast_obj
*mcast_obj
,
4019 u8 mcast_cl_id
, u32 mcast_cid
, u8 func_id
,
4020 u8 engine_id
, void *rdata
, dma_addr_t rdata_mapping
,
4021 int state
, unsigned long *pstate
, bnx2x_obj_type type
)
4023 memset(mcast_obj
, 0, sizeof(*mcast_obj
));
4025 bnx2x_init_raw_obj(&mcast_obj
->raw
, mcast_cl_id
, mcast_cid
, func_id
,
4026 rdata
, rdata_mapping
, state
, pstate
, type
);
4028 mcast_obj
->engine_id
= engine_id
;
4030 INIT_LIST_HEAD(&mcast_obj
->pending_cmds_head
);
4032 mcast_obj
->sched_state
= BNX2X_FILTER_MCAST_SCHED
;
4033 mcast_obj
->check_sched
= bnx2x_mcast_check_sched
;
4034 mcast_obj
->set_sched
= bnx2x_mcast_set_sched
;
4035 mcast_obj
->clear_sched
= bnx2x_mcast_clear_sched
;
4037 if (CHIP_IS_E1(bp
)) {
4038 mcast_obj
->config_mcast
= bnx2x_mcast_setup_e1
;
4039 mcast_obj
->enqueue_cmd
= bnx2x_mcast_enqueue_cmd
;
4040 mcast_obj
->hdl_restore
=
4041 bnx2x_mcast_handle_restore_cmd_e1
;
4042 mcast_obj
->check_pending
= bnx2x_mcast_check_pending
;
4044 if (CHIP_REV_IS_SLOW(bp
))
4045 mcast_obj
->max_cmd_len
= BNX2X_MAX_EMUL_MULTI
;
4047 mcast_obj
->max_cmd_len
= BNX2X_MAX_MULTICAST
;
4049 mcast_obj
->wait_comp
= bnx2x_mcast_wait
;
4050 mcast_obj
->set_one_rule
= bnx2x_mcast_set_one_rule_e1
;
4051 mcast_obj
->validate
= bnx2x_mcast_validate_e1
;
4052 mcast_obj
->revert
= bnx2x_mcast_revert_e1
;
4053 mcast_obj
->get_registry_size
=
4054 bnx2x_mcast_get_registry_size_exact
;
4055 mcast_obj
->set_registry_size
=
4056 bnx2x_mcast_set_registry_size_exact
;
4058 /* 57710 is the only chip that uses the exact match for mcast
4061 INIT_LIST_HEAD(&mcast_obj
->registry
.exact_match
.macs
);
4063 } else if (CHIP_IS_E1H(bp
)) {
4064 mcast_obj
->config_mcast
= bnx2x_mcast_setup_e1h
;
4065 mcast_obj
->enqueue_cmd
= NULL
;
4066 mcast_obj
->hdl_restore
= NULL
;
4067 mcast_obj
->check_pending
= bnx2x_mcast_check_pending
;
4069 /* 57711 doesn't send a ramrod, so it has unlimited credit
4072 mcast_obj
->max_cmd_len
= -1;
4073 mcast_obj
->wait_comp
= bnx2x_mcast_wait
;
4074 mcast_obj
->set_one_rule
= NULL
;
4075 mcast_obj
->validate
= bnx2x_mcast_validate_e1h
;
4076 mcast_obj
->revert
= bnx2x_mcast_revert_e1h
;
4077 mcast_obj
->get_registry_size
=
4078 bnx2x_mcast_get_registry_size_aprox
;
4079 mcast_obj
->set_registry_size
=
4080 bnx2x_mcast_set_registry_size_aprox
;
4082 mcast_obj
->config_mcast
= bnx2x_mcast_setup_e2
;
4083 mcast_obj
->enqueue_cmd
= bnx2x_mcast_enqueue_cmd
;
4084 mcast_obj
->hdl_restore
=
4085 bnx2x_mcast_handle_restore_cmd_e2
;
4086 mcast_obj
->check_pending
= bnx2x_mcast_check_pending
;
4087 /* TODO: There should be a proper HSI define for this number!!!
4089 mcast_obj
->max_cmd_len
= 16;
4090 mcast_obj
->wait_comp
= bnx2x_mcast_wait
;
4091 mcast_obj
->set_one_rule
= bnx2x_mcast_set_one_rule_e2
;
4092 mcast_obj
->validate
= bnx2x_mcast_validate_e2
;
4093 mcast_obj
->revert
= bnx2x_mcast_revert_e2
;
4094 mcast_obj
->get_registry_size
=
4095 bnx2x_mcast_get_registry_size_aprox
;
4096 mcast_obj
->set_registry_size
=
4097 bnx2x_mcast_set_registry_size_aprox
;
4101 /*************************** Credit handling **********************************/
4104 * atomic_add_ifless - add if the result is less than a given value.
4106 * @v: pointer of type atomic_t
4107 * @a: the amount to add to v...
4108 * @u: ...if (v + a) is less than u.
4110 * returns true if (v + a) was less than u, and false otherwise.
4113 static inline bool __atomic_add_ifless(atomic_t
*v
, int a
, int u
)
4119 if (unlikely(c
+ a
>= u
))
4122 old
= atomic_cmpxchg((v
), c
, c
+ a
);
4123 if (likely(old
== c
))
4132 * atomic_dec_ifmoe - dec if the result is more or equal than a given value.
4134 * @v: pointer of type atomic_t
4135 * @a: the amount to dec from v...
4136 * @u: ...if (v - a) is more or equal than u.
4138 * returns true if (v - a) was more or equal than u, and false
4141 static inline bool __atomic_dec_ifmoe(atomic_t
*v
, int a
, int u
)
4147 if (unlikely(c
- a
< u
))
4150 old
= atomic_cmpxchg((v
), c
, c
- a
);
4151 if (likely(old
== c
))
4159 static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj
*o
, int cnt
)
4164 rc
= __atomic_dec_ifmoe(&o
->credit
, cnt
, 0);
4170 static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj
*o
, int cnt
)
4176 /* Don't let to refill if credit + cnt > pool_sz */
4177 rc
= __atomic_add_ifless(&o
->credit
, cnt
, o
->pool_sz
+ 1);
4184 static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj
*o
)
4189 cur_credit
= atomic_read(&o
->credit
);
4194 static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj
*o
,
4200 static bool bnx2x_credit_pool_get_entry(
4201 struct bnx2x_credit_pool_obj
*o
,
4208 /* Find "internal cam-offset" then add to base for this object... */
4209 for (vec
= 0; vec
< BNX2X_POOL_VEC_SIZE
; vec
++) {
4211 /* Skip the current vector if there are no free entries in it */
4212 if (!o
->pool_mirror
[vec
])
4215 /* If we've got here we are going to find a free entry */
4216 for (idx
= vec
* BIT_VEC64_ELEM_SZ
, i
= 0;
4217 i
< BIT_VEC64_ELEM_SZ
; idx
++, i
++)
4219 if (BIT_VEC64_TEST_BIT(o
->pool_mirror
, idx
)) {
4221 BIT_VEC64_CLEAR_BIT(o
->pool_mirror
, idx
);
4222 *offset
= o
->base_pool_offset
+ idx
;
4230 static bool bnx2x_credit_pool_put_entry(
4231 struct bnx2x_credit_pool_obj
*o
,
4234 if (offset
< o
->base_pool_offset
)
4237 offset
-= o
->base_pool_offset
;
4239 if (offset
>= o
->pool_sz
)
4242 /* Return the entry to the pool */
4243 BIT_VEC64_SET_BIT(o
->pool_mirror
, offset
);
4248 static bool bnx2x_credit_pool_put_entry_always_true(
4249 struct bnx2x_credit_pool_obj
*o
,
4255 static bool bnx2x_credit_pool_get_entry_always_true(
4256 struct bnx2x_credit_pool_obj
*o
,
4263 * bnx2x_init_credit_pool - initialize credit pool internals.
4266 * @base: Base entry in the CAM to use.
4267 * @credit: pool size.
4269 * If base is negative no CAM entries handling will be performed.
4270 * If credit is negative pool operations will always succeed (unlimited pool).
4273 void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj
*p
,
4274 int base
, int credit
)
4276 /* Zero the object first */
4277 memset(p
, 0, sizeof(*p
));
4279 /* Set the table to all 1s */
4280 memset(&p
->pool_mirror
, 0xff, sizeof(p
->pool_mirror
));
4282 /* Init a pool as full */
4283 atomic_set(&p
->credit
, credit
);
4285 /* The total poll size */
4286 p
->pool_sz
= credit
;
4288 p
->base_pool_offset
= base
;
4290 /* Commit the change */
4293 p
->check
= bnx2x_credit_pool_check
;
4295 /* if pool credit is negative - disable the checks */
4297 p
->put
= bnx2x_credit_pool_put
;
4298 p
->get
= bnx2x_credit_pool_get
;
4299 p
->put_entry
= bnx2x_credit_pool_put_entry
;
4300 p
->get_entry
= bnx2x_credit_pool_get_entry
;
4302 p
->put
= bnx2x_credit_pool_always_true
;
4303 p
->get
= bnx2x_credit_pool_always_true
;
4304 p
->put_entry
= bnx2x_credit_pool_put_entry_always_true
;
4305 p
->get_entry
= bnx2x_credit_pool_get_entry_always_true
;
4308 /* If base is negative - disable entries handling */
4310 p
->put_entry
= bnx2x_credit_pool_put_entry_always_true
;
4311 p
->get_entry
= bnx2x_credit_pool_get_entry_always_true
;
4315 void bnx2x_init_mac_credit_pool(struct bnx2x
*bp
,
4316 struct bnx2x_credit_pool_obj
*p
, u8 func_id
,
4319 /* TODO: this will be defined in consts as well... */
4320 #define BNX2X_CAM_SIZE_EMUL 5
4324 if (CHIP_IS_E1(bp
)) {
4325 /* In E1, Multicast is saved in cam... */
4326 if (!CHIP_REV_IS_SLOW(bp
))
4327 cam_sz
= (MAX_MAC_CREDIT_E1
/ 2) - BNX2X_MAX_MULTICAST
;
4329 cam_sz
= BNX2X_CAM_SIZE_EMUL
- BNX2X_MAX_EMUL_MULTI
;
4331 bnx2x_init_credit_pool(p
, func_id
* cam_sz
, cam_sz
);
4333 } else if (CHIP_IS_E1H(bp
)) {
4334 /* CAM credit is equaly divided between all active functions
4337 if ((func_num
> 0)) {
4338 if (!CHIP_REV_IS_SLOW(bp
))
4339 cam_sz
= (MAX_MAC_CREDIT_E1H
/ (2*func_num
));
4341 cam_sz
= BNX2X_CAM_SIZE_EMUL
;
4342 bnx2x_init_credit_pool(p
, func_id
* cam_sz
, cam_sz
);
4344 /* this should never happen! Block MAC operations. */
4345 bnx2x_init_credit_pool(p
, 0, 0);
4350 /* CAM credit is equaly divided between all active functions
4354 if (!CHIP_REV_IS_SLOW(bp
))
4355 cam_sz
= PF_MAC_CREDIT_E2(bp
, func_num
);
4357 cam_sz
= BNX2X_CAM_SIZE_EMUL
;
4359 /* No need for CAM entries handling for 57712 and
4362 bnx2x_init_credit_pool(p
, -1, cam_sz
);
4364 /* this should never happen! Block MAC operations. */
4365 bnx2x_init_credit_pool(p
, 0, 0);
4370 void bnx2x_init_vlan_credit_pool(struct bnx2x
*bp
,
4371 struct bnx2x_credit_pool_obj
*p
,
4375 if (CHIP_IS_E1x(bp
)) {
4376 /* There is no VLAN credit in HW on 57710 and 57711 only
4377 * MAC / MAC-VLAN can be set
4379 bnx2x_init_credit_pool(p
, 0, -1);
4381 /* CAM credit is equally divided between all active functions
4385 int credit
= PF_VLAN_CREDIT_E2(bp
, func_num
);
4387 bnx2x_init_credit_pool(p
, -1/*unused for E2*/, credit
);
4389 /* this should never happen! Block VLAN operations. */
4390 bnx2x_init_credit_pool(p
, 0, 0);
4394 /****************** RSS Configuration ******************/
4396 * bnx2x_debug_print_ind_table - prints the indirection table configuration.
4398 * @bp: driver handle
4399 * @p: pointer to rss configuration
4401 * Prints it when NETIF_MSG_IFUP debug level is configured.
4403 static inline void bnx2x_debug_print_ind_table(struct bnx2x
*bp
,
4404 struct bnx2x_config_rss_params
*p
)
4408 DP(BNX2X_MSG_SP
, "Setting indirection table to:\n");
4409 DP(BNX2X_MSG_SP
, "0x0000: ");
4410 for (i
= 0; i
< T_ETH_INDIRECTION_TABLE_SIZE
; i
++) {
4411 DP_CONT(BNX2X_MSG_SP
, "0x%02x ", p
->ind_table
[i
]);
4413 /* Print 4 bytes in a line */
4414 if ((i
+ 1 < T_ETH_INDIRECTION_TABLE_SIZE
) &&
4415 (((i
+ 1) & 0x3) == 0)) {
4416 DP_CONT(BNX2X_MSG_SP
, "\n");
4417 DP(BNX2X_MSG_SP
, "0x%04x: ", i
+ 1);
4421 DP_CONT(BNX2X_MSG_SP
, "\n");
4425 * bnx2x_setup_rss - configure RSS
4427 * @bp: device handle
4428 * @p: rss configuration
4430 * sends on UPDATE ramrod for that matter.
4432 static int bnx2x_setup_rss(struct bnx2x
*bp
,
4433 struct bnx2x_config_rss_params
*p
)
4435 struct bnx2x_rss_config_obj
*o
= p
->rss_obj
;
4436 struct bnx2x_raw_obj
*r
= &o
->raw
;
4437 struct eth_rss_update_ramrod_data
*data
=
4438 (struct eth_rss_update_ramrod_data
*)(r
->rdata
);
4443 memset(data
, 0, sizeof(*data
));
4445 DP(BNX2X_MSG_SP
, "Configuring RSS\n");
4447 /* Set an echo field */
4448 data
->echo
= cpu_to_le32((r
->cid
& BNX2X_SWCID_MASK
) |
4449 (r
->state
<< BNX2X_SWCID_SHIFT
));
4452 if (test_bit(BNX2X_RSS_MODE_DISABLED
, &p
->rss_flags
))
4453 rss_mode
= ETH_RSS_MODE_DISABLED
;
4454 else if (test_bit(BNX2X_RSS_MODE_REGULAR
, &p
->rss_flags
))
4455 rss_mode
= ETH_RSS_MODE_REGULAR
;
4457 data
->rss_mode
= rss_mode
;
4459 DP(BNX2X_MSG_SP
, "rss_mode=%d\n", rss_mode
);
4461 /* RSS capabilities */
4462 if (test_bit(BNX2X_RSS_IPV4
, &p
->rss_flags
))
4463 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY
;
4465 if (test_bit(BNX2X_RSS_IPV4_TCP
, &p
->rss_flags
))
4466 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY
;
4468 if (test_bit(BNX2X_RSS_IPV4_UDP
, &p
->rss_flags
))
4469 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY
;
4471 if (test_bit(BNX2X_RSS_IPV6
, &p
->rss_flags
))
4472 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY
;
4474 if (test_bit(BNX2X_RSS_IPV6_TCP
, &p
->rss_flags
))
4475 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY
;
4477 if (test_bit(BNX2X_RSS_IPV6_UDP
, &p
->rss_flags
))
4478 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY
;
4480 if (test_bit(BNX2X_RSS_IPV4_VXLAN
, &p
->rss_flags
))
4481 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY
;
4483 if (test_bit(BNX2X_RSS_IPV6_VXLAN
, &p
->rss_flags
))
4484 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY
;
4486 if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS
, &p
->rss_flags
))
4487 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY
;
4490 if (test_bit(BNX2X_RSS_SET_SRCH
, &p
->rss_flags
)) {
4491 u8
*dst
= (u8
*)(data
->rss_key
) + sizeof(data
->rss_key
);
4492 const u8
*src
= (const u8
*)p
->rss_key
;
4495 /* Apparently, bnx2x reads this array in reverse order
4496 * We need to byte swap rss_key to comply with Toeplitz specs.
4498 for (i
= 0; i
< sizeof(data
->rss_key
); i
++)
4501 caps
|= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY
;
4504 data
->capabilities
= cpu_to_le16(caps
);
4507 data
->rss_result_mask
= p
->rss_result_mask
;
4510 data
->rss_engine_id
= o
->engine_id
;
4512 DP(BNX2X_MSG_SP
, "rss_engine_id=%d\n", data
->rss_engine_id
);
4514 /* Indirection table */
4515 memcpy(data
->indirection_table
, p
->ind_table
,
4516 T_ETH_INDIRECTION_TABLE_SIZE
);
4518 /* Remember the last configuration */
4519 memcpy(o
->ind_table
, p
->ind_table
, T_ETH_INDIRECTION_TABLE_SIZE
);
4521 /* Print the indirection table */
4522 if (netif_msg_ifup(bp
))
4523 bnx2x_debug_print_ind_table(bp
, p
);
4525 /* No need for an explicit memory barrier here as long as we
4526 * ensure the ordering of writing to the SPQ element
4527 * and updating of the SPQ producer which involves a memory
4528 * read. If the memory read is removed we will have to put a
4529 * full memory barrier there (inside bnx2x_sp_post()).
4533 rc
= bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_RSS_UPDATE
, r
->cid
,
4534 U64_HI(r
->rdata_mapping
),
4535 U64_LO(r
->rdata_mapping
),
4536 ETH_CONNECTION_TYPE
);
4544 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj
*rss_obj
,
4547 memcpy(ind_table
, rss_obj
->ind_table
, sizeof(rss_obj
->ind_table
));
4550 int bnx2x_config_rss(struct bnx2x
*bp
,
4551 struct bnx2x_config_rss_params
*p
)
4554 struct bnx2x_rss_config_obj
*o
= p
->rss_obj
;
4555 struct bnx2x_raw_obj
*r
= &o
->raw
;
4557 /* Do nothing if only driver cleanup was requested */
4558 if (test_bit(RAMROD_DRV_CLR_ONLY
, &p
->ramrod_flags
)) {
4559 DP(BNX2X_MSG_SP
, "Not configuring RSS ramrod_flags=%lx\n",
4566 rc
= o
->config_rss(bp
, p
);
4568 r
->clear_pending(r
);
4572 if (test_bit(RAMROD_COMP_WAIT
, &p
->ramrod_flags
))
4573 rc
= r
->wait_comp(bp
, r
);
4578 void bnx2x_init_rss_config_obj(struct bnx2x
*bp
,
4579 struct bnx2x_rss_config_obj
*rss_obj
,
4580 u8 cl_id
, u32 cid
, u8 func_id
, u8 engine_id
,
4581 void *rdata
, dma_addr_t rdata_mapping
,
4582 int state
, unsigned long *pstate
,
4583 bnx2x_obj_type type
)
4585 bnx2x_init_raw_obj(&rss_obj
->raw
, cl_id
, cid
, func_id
, rdata
,
4586 rdata_mapping
, state
, pstate
, type
);
4588 rss_obj
->engine_id
= engine_id
;
4589 rss_obj
->config_rss
= bnx2x_setup_rss
;
4592 /********************** Queue state object ***********************************/
4595 * bnx2x_queue_state_change - perform Queue state change transition
4597 * @bp: device handle
4598 * @params: parameters to perform the transition
4600 * returns 0 in case of successfully completed transition, negative error
4601 * code in case of failure, positive (EBUSY) value if there is a completion
4602 * to that is still pending (possible only if RAMROD_COMP_WAIT is
4603 * not set in params->ramrod_flags for asynchronous commands).
4606 int bnx2x_queue_state_change(struct bnx2x
*bp
,
4607 struct bnx2x_queue_state_params
*params
)
4609 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
4610 int rc
, pending_bit
;
4611 unsigned long *pending
= &o
->pending
;
4613 /* Check that the requested transition is legal */
4614 rc
= o
->check_transition(bp
, o
, params
);
4616 BNX2X_ERR("check transition returned an error. rc %d\n", rc
);
4620 /* Set "pending" bit */
4621 DP(BNX2X_MSG_SP
, "pending bit was=%lx\n", o
->pending
);
4622 pending_bit
= o
->set_pending(o
, params
);
4623 DP(BNX2X_MSG_SP
, "pending bit now=%lx\n", o
->pending
);
4625 /* Don't send a command if only driver cleanup was requested */
4626 if (test_bit(RAMROD_DRV_CLR_ONLY
, ¶ms
->ramrod_flags
))
4627 o
->complete_cmd(bp
, o
, pending_bit
);
4630 rc
= o
->send_cmd(bp
, params
);
4632 o
->next_state
= BNX2X_Q_STATE_MAX
;
4633 clear_bit(pending_bit
, pending
);
4634 smp_mb__after_atomic();
4638 if (test_bit(RAMROD_COMP_WAIT
, ¶ms
->ramrod_flags
)) {
4639 rc
= o
->wait_comp(bp
, o
, pending_bit
);
4647 return !!test_bit(pending_bit
, pending
);
4650 static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj
*obj
,
4651 struct bnx2x_queue_state_params
*params
)
4653 enum bnx2x_queue_cmd cmd
= params
->cmd
, bit
;
4655 /* ACTIVATE and DEACTIVATE commands are implemented on top of
4658 if ((cmd
== BNX2X_Q_CMD_ACTIVATE
) ||
4659 (cmd
== BNX2X_Q_CMD_DEACTIVATE
))
4660 bit
= BNX2X_Q_CMD_UPDATE
;
4664 set_bit(bit
, &obj
->pending
);
4668 static int bnx2x_queue_wait_comp(struct bnx2x
*bp
,
4669 struct bnx2x_queue_sp_obj
*o
,
4670 enum bnx2x_queue_cmd cmd
)
4672 return bnx2x_state_wait(bp
, cmd
, &o
->pending
);
4676 * bnx2x_queue_comp_cmd - complete the state change command.
4678 * @bp: device handle
4682 * Checks that the arrived completion is expected.
4684 static int bnx2x_queue_comp_cmd(struct bnx2x
*bp
,
4685 struct bnx2x_queue_sp_obj
*o
,
4686 enum bnx2x_queue_cmd cmd
)
4688 unsigned long cur_pending
= o
->pending
;
4690 if (!test_and_clear_bit(cmd
, &cur_pending
)) {
4691 BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4692 cmd
, o
->cids
[BNX2X_PRIMARY_CID_INDEX
],
4693 o
->state
, cur_pending
, o
->next_state
);
4697 if (o
->next_tx_only
>= o
->max_cos
)
4698 /* >= because tx only must always be smaller than cos since the
4699 * primary connection supports COS 0
4701 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d",
4702 o
->next_tx_only
, o
->max_cos
);
4705 "Completing command %d for queue %d, setting state to %d\n",
4706 cmd
, o
->cids
[BNX2X_PRIMARY_CID_INDEX
], o
->next_state
);
4708 if (o
->next_tx_only
) /* print num tx-only if any exist */
4709 DP(BNX2X_MSG_SP
, "primary cid %d: num tx-only cons %d\n",
4710 o
->cids
[BNX2X_PRIMARY_CID_INDEX
], o
->next_tx_only
);
4712 o
->state
= o
->next_state
;
4713 o
->num_tx_only
= o
->next_tx_only
;
4714 o
->next_state
= BNX2X_Q_STATE_MAX
;
4716 /* It's important that o->state and o->next_state are
4717 * updated before o->pending.
4721 clear_bit(cmd
, &o
->pending
);
4722 smp_mb__after_atomic();
4727 static void bnx2x_q_fill_setup_data_e2(struct bnx2x
*bp
,
4728 struct bnx2x_queue_state_params
*cmd_params
,
4729 struct client_init_ramrod_data
*data
)
4731 struct bnx2x_queue_setup_params
*params
= &cmd_params
->params
.setup
;
4735 /* IPv6 TPA supported for E2 and above only */
4736 data
->rx
.tpa_en
|= test_bit(BNX2X_Q_FLG_TPA_IPV6
, ¶ms
->flags
) *
4737 CLIENT_INIT_RX_DATA_TPA_EN_IPV6
;
4740 static void bnx2x_q_fill_init_general_data(struct bnx2x
*bp
,
4741 struct bnx2x_queue_sp_obj
*o
,
4742 struct bnx2x_general_setup_params
*params
,
4743 struct client_init_general_data
*gen_data
,
4744 unsigned long *flags
)
4746 gen_data
->client_id
= o
->cl_id
;
4748 if (test_bit(BNX2X_Q_FLG_STATS
, flags
)) {
4749 gen_data
->statistics_counter_id
=
4751 gen_data
->statistics_en_flg
= 1;
4752 gen_data
->statistics_zero_flg
=
4753 test_bit(BNX2X_Q_FLG_ZERO_STATS
, flags
);
4755 gen_data
->statistics_counter_id
=
4756 DISABLE_STATISTIC_COUNTER_ID_VALUE
;
4758 gen_data
->is_fcoe_flg
= test_bit(BNX2X_Q_FLG_FCOE
, flags
);
4759 gen_data
->activate_flg
= test_bit(BNX2X_Q_FLG_ACTIVE
, flags
);
4760 gen_data
->sp_client_id
= params
->spcl_id
;
4761 gen_data
->mtu
= cpu_to_le16(params
->mtu
);
4762 gen_data
->func_id
= o
->func_id
;
4764 gen_data
->cos
= params
->cos
;
4766 gen_data
->traffic_type
=
4767 test_bit(BNX2X_Q_FLG_FCOE
, flags
) ?
4768 LLFC_TRAFFIC_TYPE_FCOE
: LLFC_TRAFFIC_TYPE_NW
;
4770 gen_data
->fp_hsi_ver
= params
->fp_hsi
;
4772 DP(BNX2X_MSG_SP
, "flags: active %d, cos %d, stats en %d\n",
4773 gen_data
->activate_flg
, gen_data
->cos
, gen_data
->statistics_en_flg
);
4776 static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj
*o
,
4777 struct bnx2x_txq_setup_params
*params
,
4778 struct client_init_tx_data
*tx_data
,
4779 unsigned long *flags
)
4781 tx_data
->enforce_security_flg
=
4782 test_bit(BNX2X_Q_FLG_TX_SEC
, flags
);
4783 tx_data
->default_vlan
=
4784 cpu_to_le16(params
->default_vlan
);
4785 tx_data
->default_vlan_flg
=
4786 test_bit(BNX2X_Q_FLG_DEF_VLAN
, flags
);
4787 tx_data
->tx_switching_flg
=
4788 test_bit(BNX2X_Q_FLG_TX_SWITCH
, flags
);
4789 tx_data
->anti_spoofing_flg
=
4790 test_bit(BNX2X_Q_FLG_ANTI_SPOOF
, flags
);
4791 tx_data
->force_default_pri_flg
=
4792 test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI
, flags
);
4793 tx_data
->refuse_outband_vlan_flg
=
4794 test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN
, flags
);
4795 tx_data
->tunnel_lso_inc_ip_id
=
4796 test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
, flags
);
4797 tx_data
->tunnel_non_lso_pcsum_location
=
4798 test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT
, flags
) ? CSUM_ON_PKT
:
4801 tx_data
->tx_status_block_id
= params
->fw_sb_id
;
4802 tx_data
->tx_sb_index_number
= params
->sb_cq_index
;
4803 tx_data
->tss_leading_client_id
= params
->tss_leading_cl_id
;
4805 tx_data
->tx_bd_page_base
.lo
=
4806 cpu_to_le32(U64_LO(params
->dscr_map
));
4807 tx_data
->tx_bd_page_base
.hi
=
4808 cpu_to_le32(U64_HI(params
->dscr_map
));
4810 /* Don't configure any Tx switching mode during queue SETUP */
4814 static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj
*o
,
4815 struct rxq_pause_params
*params
,
4816 struct client_init_rx_data
*rx_data
)
4818 /* flow control data */
4819 rx_data
->cqe_pause_thr_low
= cpu_to_le16(params
->rcq_th_lo
);
4820 rx_data
->cqe_pause_thr_high
= cpu_to_le16(params
->rcq_th_hi
);
4821 rx_data
->bd_pause_thr_low
= cpu_to_le16(params
->bd_th_lo
);
4822 rx_data
->bd_pause_thr_high
= cpu_to_le16(params
->bd_th_hi
);
4823 rx_data
->sge_pause_thr_low
= cpu_to_le16(params
->sge_th_lo
);
4824 rx_data
->sge_pause_thr_high
= cpu_to_le16(params
->sge_th_hi
);
4825 rx_data
->rx_cos_mask
= cpu_to_le16(params
->pri_map
);
4828 static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj
*o
,
4829 struct bnx2x_rxq_setup_params
*params
,
4830 struct client_init_rx_data
*rx_data
,
4831 unsigned long *flags
)
4833 rx_data
->tpa_en
= test_bit(BNX2X_Q_FLG_TPA
, flags
) *
4834 CLIENT_INIT_RX_DATA_TPA_EN_IPV4
;
4835 rx_data
->tpa_en
|= test_bit(BNX2X_Q_FLG_TPA_GRO
, flags
) *
4836 CLIENT_INIT_RX_DATA_TPA_MODE
;
4837 rx_data
->vmqueue_mode_en_flg
= 0;
4839 rx_data
->cache_line_alignment_log_size
=
4840 params
->cache_line_log
;
4841 rx_data
->enable_dynamic_hc
=
4842 test_bit(BNX2X_Q_FLG_DHC
, flags
);
4843 rx_data
->max_sges_for_packet
= params
->max_sges_pkt
;
4844 rx_data
->client_qzone_id
= params
->cl_qzone_id
;
4845 rx_data
->max_agg_size
= cpu_to_le16(params
->tpa_agg_sz
);
4847 /* Always start in DROP_ALL mode */
4848 rx_data
->state
= cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL
|
4849 CLIENT_INIT_RX_DATA_MCAST_DROP_ALL
);
4851 /* We don't set drop flags */
4852 rx_data
->drop_ip_cs_err_flg
= 0;
4853 rx_data
->drop_tcp_cs_err_flg
= 0;
4854 rx_data
->drop_ttl0_flg
= 0;
4855 rx_data
->drop_udp_cs_err_flg
= 0;
4856 rx_data
->inner_vlan_removal_enable_flg
=
4857 test_bit(BNX2X_Q_FLG_VLAN
, flags
);
4858 rx_data
->outer_vlan_removal_enable_flg
=
4859 test_bit(BNX2X_Q_FLG_OV
, flags
);
4860 rx_data
->status_block_id
= params
->fw_sb_id
;
4861 rx_data
->rx_sb_index_number
= params
->sb_cq_index
;
4862 rx_data
->max_tpa_queues
= params
->max_tpa_queues
;
4863 rx_data
->max_bytes_on_bd
= cpu_to_le16(params
->buf_sz
);
4864 rx_data
->sge_buff_size
= cpu_to_le16(params
->sge_buf_sz
);
4865 rx_data
->bd_page_base
.lo
=
4866 cpu_to_le32(U64_LO(params
->dscr_map
));
4867 rx_data
->bd_page_base
.hi
=
4868 cpu_to_le32(U64_HI(params
->dscr_map
));
4869 rx_data
->sge_page_base
.lo
=
4870 cpu_to_le32(U64_LO(params
->sge_map
));
4871 rx_data
->sge_page_base
.hi
=
4872 cpu_to_le32(U64_HI(params
->sge_map
));
4873 rx_data
->cqe_page_base
.lo
=
4874 cpu_to_le32(U64_LO(params
->rcq_map
));
4875 rx_data
->cqe_page_base
.hi
=
4876 cpu_to_le32(U64_HI(params
->rcq_map
));
4877 rx_data
->is_leading_rss
= test_bit(BNX2X_Q_FLG_LEADING_RSS
, flags
);
4879 if (test_bit(BNX2X_Q_FLG_MCAST
, flags
)) {
4880 rx_data
->approx_mcast_engine_id
= params
->mcast_engine_id
;
4881 rx_data
->is_approx_mcast
= 1;
4884 rx_data
->rss_engine_id
= params
->rss_engine_id
;
4886 /* silent vlan removal */
4887 rx_data
->silent_vlan_removal_flg
=
4888 test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM
, flags
);
4889 rx_data
->silent_vlan_value
=
4890 cpu_to_le16(params
->silent_removal_value
);
4891 rx_data
->silent_vlan_mask
=
4892 cpu_to_le16(params
->silent_removal_mask
);
4895 /* initialize the general, tx and rx parts of a queue object */
4896 static void bnx2x_q_fill_setup_data_cmn(struct bnx2x
*bp
,
4897 struct bnx2x_queue_state_params
*cmd_params
,
4898 struct client_init_ramrod_data
*data
)
4900 bnx2x_q_fill_init_general_data(bp
, cmd_params
->q_obj
,
4901 &cmd_params
->params
.setup
.gen_params
,
4903 &cmd_params
->params
.setup
.flags
);
4905 bnx2x_q_fill_init_tx_data(cmd_params
->q_obj
,
4906 &cmd_params
->params
.setup
.txq_params
,
4908 &cmd_params
->params
.setup
.flags
);
4910 bnx2x_q_fill_init_rx_data(cmd_params
->q_obj
,
4911 &cmd_params
->params
.setup
.rxq_params
,
4913 &cmd_params
->params
.setup
.flags
);
4915 bnx2x_q_fill_init_pause_data(cmd_params
->q_obj
,
4916 &cmd_params
->params
.setup
.pause_params
,
4920 /* initialize the general and tx parts of a tx-only queue object */
4921 static void bnx2x_q_fill_setup_tx_only(struct bnx2x
*bp
,
4922 struct bnx2x_queue_state_params
*cmd_params
,
4923 struct tx_queue_init_ramrod_data
*data
)
4925 bnx2x_q_fill_init_general_data(bp
, cmd_params
->q_obj
,
4926 &cmd_params
->params
.tx_only
.gen_params
,
4928 &cmd_params
->params
.tx_only
.flags
);
4930 bnx2x_q_fill_init_tx_data(cmd_params
->q_obj
,
4931 &cmd_params
->params
.tx_only
.txq_params
,
4933 &cmd_params
->params
.tx_only
.flags
);
4935 DP(BNX2X_MSG_SP
, "cid %d, tx bd page lo %x hi %x",
4936 cmd_params
->q_obj
->cids
[0],
4937 data
->tx
.tx_bd_page_base
.lo
,
4938 data
->tx
.tx_bd_page_base
.hi
);
4942 * bnx2x_q_init - init HW/FW queue
4944 * @bp: device handle
4947 * HW/FW initial Queue configuration:
4949 * - CDU context validation
4952 static inline int bnx2x_q_init(struct bnx2x
*bp
,
4953 struct bnx2x_queue_state_params
*params
)
4955 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
4956 struct bnx2x_queue_init_params
*init
= ¶ms
->params
.init
;
4960 /* Tx HC configuration */
4961 if (test_bit(BNX2X_Q_TYPE_HAS_TX
, &o
->type
) &&
4962 test_bit(BNX2X_Q_FLG_HC
, &init
->tx
.flags
)) {
4963 hc_usec
= init
->tx
.hc_rate
? 1000000 / init
->tx
.hc_rate
: 0;
4965 bnx2x_update_coalesce_sb_index(bp
, init
->tx
.fw_sb_id
,
4966 init
->tx
.sb_cq_index
,
4967 !test_bit(BNX2X_Q_FLG_HC_EN
, &init
->tx
.flags
),
4971 /* Rx HC configuration */
4972 if (test_bit(BNX2X_Q_TYPE_HAS_RX
, &o
->type
) &&
4973 test_bit(BNX2X_Q_FLG_HC
, &init
->rx
.flags
)) {
4974 hc_usec
= init
->rx
.hc_rate
? 1000000 / init
->rx
.hc_rate
: 0;
4976 bnx2x_update_coalesce_sb_index(bp
, init
->rx
.fw_sb_id
,
4977 init
->rx
.sb_cq_index
,
4978 !test_bit(BNX2X_Q_FLG_HC_EN
, &init
->rx
.flags
),
4982 /* Set CDU context validation values */
4983 for (cos
= 0; cos
< o
->max_cos
; cos
++) {
4984 DP(BNX2X_MSG_SP
, "setting context validation. cid %d, cos %d\n",
4986 DP(BNX2X_MSG_SP
, "context pointer %p\n", init
->cxts
[cos
]);
4987 bnx2x_set_ctx_validation(bp
, init
->cxts
[cos
], o
->cids
[cos
]);
4990 /* As no ramrod is sent, complete the command immediately */
4991 o
->complete_cmd(bp
, o
, BNX2X_Q_CMD_INIT
);
4999 static inline int bnx2x_q_send_setup_e1x(struct bnx2x
*bp
,
5000 struct bnx2x_queue_state_params
*params
)
5002 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5003 struct client_init_ramrod_data
*rdata
=
5004 (struct client_init_ramrod_data
*)o
->rdata
;
5005 dma_addr_t data_mapping
= o
->rdata_mapping
;
5006 int ramrod
= RAMROD_CMD_ID_ETH_CLIENT_SETUP
;
5008 /* Clear the ramrod data */
5009 memset(rdata
, 0, sizeof(*rdata
));
5011 /* Fill the ramrod data */
5012 bnx2x_q_fill_setup_data_cmn(bp
, params
, rdata
);
5014 /* No need for an explicit memory barrier here as long as we
5015 * ensure the ordering of writing to the SPQ element
5016 * and updating of the SPQ producer which involves a memory
5017 * read. If the memory read is removed we will have to put a
5018 * full memory barrier there (inside bnx2x_sp_post()).
5020 return bnx2x_sp_post(bp
, ramrod
, o
->cids
[BNX2X_PRIMARY_CID_INDEX
],
5021 U64_HI(data_mapping
),
5022 U64_LO(data_mapping
), ETH_CONNECTION_TYPE
);
5025 static inline int bnx2x_q_send_setup_e2(struct bnx2x
*bp
,
5026 struct bnx2x_queue_state_params
*params
)
5028 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5029 struct client_init_ramrod_data
*rdata
=
5030 (struct client_init_ramrod_data
*)o
->rdata
;
5031 dma_addr_t data_mapping
= o
->rdata_mapping
;
5032 int ramrod
= RAMROD_CMD_ID_ETH_CLIENT_SETUP
;
5034 /* Clear the ramrod data */
5035 memset(rdata
, 0, sizeof(*rdata
));
5037 /* Fill the ramrod data */
5038 bnx2x_q_fill_setup_data_cmn(bp
, params
, rdata
);
5039 bnx2x_q_fill_setup_data_e2(bp
, params
, rdata
);
5041 /* No need for an explicit memory barrier here as long as we
5042 * ensure the ordering of writing to the SPQ element
5043 * and updating of the SPQ producer which involves a memory
5044 * read. If the memory read is removed we will have to put a
5045 * full memory barrier there (inside bnx2x_sp_post()).
5047 return bnx2x_sp_post(bp
, ramrod
, o
->cids
[BNX2X_PRIMARY_CID_INDEX
],
5048 U64_HI(data_mapping
),
5049 U64_LO(data_mapping
), ETH_CONNECTION_TYPE
);
5052 static inline int bnx2x_q_send_setup_tx_only(struct bnx2x
*bp
,
5053 struct bnx2x_queue_state_params
*params
)
5055 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5056 struct tx_queue_init_ramrod_data
*rdata
=
5057 (struct tx_queue_init_ramrod_data
*)o
->rdata
;
5058 dma_addr_t data_mapping
= o
->rdata_mapping
;
5059 int ramrod
= RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
;
5060 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
5061 ¶ms
->params
.tx_only
;
5062 u8 cid_index
= tx_only_params
->cid_index
;
5064 if (cid_index
>= o
->max_cos
) {
5065 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5066 o
->cl_id
, cid_index
);
5070 DP(BNX2X_MSG_SP
, "parameters received: cos: %d sp-id: %d\n",
5071 tx_only_params
->gen_params
.cos
,
5072 tx_only_params
->gen_params
.spcl_id
);
5074 /* Clear the ramrod data */
5075 memset(rdata
, 0, sizeof(*rdata
));
5077 /* Fill the ramrod data */
5078 bnx2x_q_fill_setup_tx_only(bp
, params
, rdata
);
5080 DP(BNX2X_MSG_SP
, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
5081 o
->cids
[cid_index
], rdata
->general
.client_id
,
5082 rdata
->general
.sp_client_id
, rdata
->general
.cos
);
5084 /* No need for an explicit memory barrier here as long as we
5085 * ensure the ordering of writing to the SPQ element
5086 * and updating of the SPQ producer which involves a memory
5087 * read. If the memory read is removed we will have to put a
5088 * full memory barrier there (inside bnx2x_sp_post()).
5090 return bnx2x_sp_post(bp
, ramrod
, o
->cids
[cid_index
],
5091 U64_HI(data_mapping
),
5092 U64_LO(data_mapping
), ETH_CONNECTION_TYPE
);
5095 static void bnx2x_q_fill_update_data(struct bnx2x
*bp
,
5096 struct bnx2x_queue_sp_obj
*obj
,
5097 struct bnx2x_queue_update_params
*params
,
5098 struct client_update_ramrod_data
*data
)
5100 /* Client ID of the client to update */
5101 data
->client_id
= obj
->cl_id
;
5103 /* Function ID of the client to update */
5104 data
->func_id
= obj
->func_id
;
5106 /* Default VLAN value */
5107 data
->default_vlan
= cpu_to_le16(params
->def_vlan
);
5109 /* Inner VLAN stripping */
5110 data
->inner_vlan_removal_enable_flg
=
5111 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM
, ¶ms
->update_flags
);
5112 data
->inner_vlan_removal_change_flg
=
5113 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG
,
5114 ¶ms
->update_flags
);
5116 /* Outer VLAN stripping */
5117 data
->outer_vlan_removal_enable_flg
=
5118 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM
, ¶ms
->update_flags
);
5119 data
->outer_vlan_removal_change_flg
=
5120 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG
,
5121 ¶ms
->update_flags
);
5123 /* Drop packets that have source MAC that doesn't belong to this
5126 data
->anti_spoofing_enable_flg
=
5127 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF
, ¶ms
->update_flags
);
5128 data
->anti_spoofing_change_flg
=
5129 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG
, ¶ms
->update_flags
);
5131 /* Activate/Deactivate */
5132 data
->activate_flg
=
5133 test_bit(BNX2X_Q_UPDATE_ACTIVATE
, ¶ms
->update_flags
);
5134 data
->activate_change_flg
=
5135 test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG
, ¶ms
->update_flags
);
5137 /* Enable default VLAN */
5138 data
->default_vlan_enable_flg
=
5139 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN
, ¶ms
->update_flags
);
5140 data
->default_vlan_change_flg
=
5141 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG
,
5142 ¶ms
->update_flags
);
5144 /* silent vlan removal */
5145 data
->silent_vlan_change_flg
=
5146 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
,
5147 ¶ms
->update_flags
);
5148 data
->silent_vlan_removal_flg
=
5149 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM
, ¶ms
->update_flags
);
5150 data
->silent_vlan_value
= cpu_to_le16(params
->silent_removal_value
);
5151 data
->silent_vlan_mask
= cpu_to_le16(params
->silent_removal_mask
);
5154 data
->tx_switching_flg
=
5155 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING
, ¶ms
->update_flags
);
5156 data
->tx_switching_change_flg
=
5157 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG
,
5158 ¶ms
->update_flags
);
5161 data
->handle_ptp_pkts_flg
=
5162 test_bit(BNX2X_Q_UPDATE_PTP_PKTS
, ¶ms
->update_flags
);
5163 data
->handle_ptp_pkts_change_flg
=
5164 test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG
, ¶ms
->update_flags
);
5167 static inline int bnx2x_q_send_update(struct bnx2x
*bp
,
5168 struct bnx2x_queue_state_params
*params
)
5170 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5171 struct client_update_ramrod_data
*rdata
=
5172 (struct client_update_ramrod_data
*)o
->rdata
;
5173 dma_addr_t data_mapping
= o
->rdata_mapping
;
5174 struct bnx2x_queue_update_params
*update_params
=
5175 ¶ms
->params
.update
;
5176 u8 cid_index
= update_params
->cid_index
;
5178 if (cid_index
>= o
->max_cos
) {
5179 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5180 o
->cl_id
, cid_index
);
5184 /* Clear the ramrod data */
5185 memset(rdata
, 0, sizeof(*rdata
));
5187 /* Fill the ramrod data */
5188 bnx2x_q_fill_update_data(bp
, o
, update_params
, rdata
);
5190 /* No need for an explicit memory barrier here as long as we
5191 * ensure the ordering of writing to the SPQ element
5192 * and updating of the SPQ producer which involves a memory
5193 * read. If the memory read is removed we will have to put a
5194 * full memory barrier there (inside bnx2x_sp_post()).
5196 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_CLIENT_UPDATE
,
5197 o
->cids
[cid_index
], U64_HI(data_mapping
),
5198 U64_LO(data_mapping
), ETH_CONNECTION_TYPE
);
5202 * bnx2x_q_send_deactivate - send DEACTIVATE command
5204 * @bp: device handle
5207 * implemented using the UPDATE command.
5209 static inline int bnx2x_q_send_deactivate(struct bnx2x
*bp
,
5210 struct bnx2x_queue_state_params
*params
)
5212 struct bnx2x_queue_update_params
*update
= ¶ms
->params
.update
;
5214 memset(update
, 0, sizeof(*update
));
5216 __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG
, &update
->update_flags
);
5218 return bnx2x_q_send_update(bp
, params
);
5222 * bnx2x_q_send_activate - send ACTIVATE command
5224 * @bp: device handle
5227 * implemented using the UPDATE command.
5229 static inline int bnx2x_q_send_activate(struct bnx2x
*bp
,
5230 struct bnx2x_queue_state_params
*params
)
5232 struct bnx2x_queue_update_params
*update
= ¶ms
->params
.update
;
5234 memset(update
, 0, sizeof(*update
));
5236 __set_bit(BNX2X_Q_UPDATE_ACTIVATE
, &update
->update_flags
);
5237 __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG
, &update
->update_flags
);
5239 return bnx2x_q_send_update(bp
, params
);
5242 static void bnx2x_q_fill_update_tpa_data(struct bnx2x
*bp
,
5243 struct bnx2x_queue_sp_obj
*obj
,
5244 struct bnx2x_queue_update_tpa_params
*params
,
5245 struct tpa_update_ramrod_data
*data
)
5247 data
->client_id
= obj
->cl_id
;
5248 data
->complete_on_both_clients
= params
->complete_on_both_clients
;
5249 data
->dont_verify_rings_pause_thr_flg
=
5250 params
->dont_verify_thr
;
5251 data
->max_agg_size
= cpu_to_le16(params
->max_agg_sz
);
5252 data
->max_sges_for_packet
= params
->max_sges_pkt
;
5253 data
->max_tpa_queues
= params
->max_tpa_queues
;
5254 data
->sge_buff_size
= cpu_to_le16(params
->sge_buff_sz
);
5255 data
->sge_page_base_hi
= cpu_to_le32(U64_HI(params
->sge_map
));
5256 data
->sge_page_base_lo
= cpu_to_le32(U64_LO(params
->sge_map
));
5257 data
->sge_pause_thr_high
= cpu_to_le16(params
->sge_pause_thr_high
);
5258 data
->sge_pause_thr_low
= cpu_to_le16(params
->sge_pause_thr_low
);
5259 data
->tpa_mode
= params
->tpa_mode
;
5260 data
->update_ipv4
= params
->update_ipv4
;
5261 data
->update_ipv6
= params
->update_ipv6
;
5264 static inline int bnx2x_q_send_update_tpa(struct bnx2x
*bp
,
5265 struct bnx2x_queue_state_params
*params
)
5267 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5268 struct tpa_update_ramrod_data
*rdata
=
5269 (struct tpa_update_ramrod_data
*)o
->rdata
;
5270 dma_addr_t data_mapping
= o
->rdata_mapping
;
5271 struct bnx2x_queue_update_tpa_params
*update_tpa_params
=
5272 ¶ms
->params
.update_tpa
;
5275 /* Clear the ramrod data */
5276 memset(rdata
, 0, sizeof(*rdata
));
5278 /* Fill the ramrod data */
5279 bnx2x_q_fill_update_tpa_data(bp
, o
, update_tpa_params
, rdata
);
5281 /* Add the function id inside the type, so that sp post function
5282 * doesn't automatically add the PF func-id, this is required
5283 * for operations done by PFs on behalf of their VFs
5285 type
= ETH_CONNECTION_TYPE
|
5286 ((o
->func_id
) << SPE_HDR_FUNCTION_ID_SHIFT
);
5288 /* No need for an explicit memory barrier here as long as we
5289 * ensure the ordering of writing to the SPQ element
5290 * and updating of the SPQ producer which involves a memory
5291 * read. If the memory read is removed we will have to put a
5292 * full memory barrier there (inside bnx2x_sp_post()).
5294 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_TPA_UPDATE
,
5295 o
->cids
[BNX2X_PRIMARY_CID_INDEX
],
5296 U64_HI(data_mapping
),
5297 U64_LO(data_mapping
), type
);
5300 static inline int bnx2x_q_send_halt(struct bnx2x
*bp
,
5301 struct bnx2x_queue_state_params
*params
)
5303 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5305 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_HALT
,
5306 o
->cids
[BNX2X_PRIMARY_CID_INDEX
], 0, o
->cl_id
,
5307 ETH_CONNECTION_TYPE
);
5310 static inline int bnx2x_q_send_cfc_del(struct bnx2x
*bp
,
5311 struct bnx2x_queue_state_params
*params
)
5313 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5314 u8 cid_idx
= params
->params
.cfc_del
.cid_index
;
5316 if (cid_idx
>= o
->max_cos
) {
5317 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5322 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_CFC_DEL
,
5323 o
->cids
[cid_idx
], 0, 0, NONE_CONNECTION_TYPE
);
5326 static inline int bnx2x_q_send_terminate(struct bnx2x
*bp
,
5327 struct bnx2x_queue_state_params
*params
)
5329 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5330 u8 cid_index
= params
->params
.terminate
.cid_index
;
5332 if (cid_index
>= o
->max_cos
) {
5333 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5334 o
->cl_id
, cid_index
);
5338 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_TERMINATE
,
5339 o
->cids
[cid_index
], 0, 0, ETH_CONNECTION_TYPE
);
5342 static inline int bnx2x_q_send_empty(struct bnx2x
*bp
,
5343 struct bnx2x_queue_state_params
*params
)
5345 struct bnx2x_queue_sp_obj
*o
= params
->q_obj
;
5347 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_ETH_EMPTY
,
5348 o
->cids
[BNX2X_PRIMARY_CID_INDEX
], 0, 0,
5349 ETH_CONNECTION_TYPE
);
5352 static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x
*bp
,
5353 struct bnx2x_queue_state_params
*params
)
5355 switch (params
->cmd
) {
5356 case BNX2X_Q_CMD_INIT
:
5357 return bnx2x_q_init(bp
, params
);
5358 case BNX2X_Q_CMD_SETUP_TX_ONLY
:
5359 return bnx2x_q_send_setup_tx_only(bp
, params
);
5360 case BNX2X_Q_CMD_DEACTIVATE
:
5361 return bnx2x_q_send_deactivate(bp
, params
);
5362 case BNX2X_Q_CMD_ACTIVATE
:
5363 return bnx2x_q_send_activate(bp
, params
);
5364 case BNX2X_Q_CMD_UPDATE
:
5365 return bnx2x_q_send_update(bp
, params
);
5366 case BNX2X_Q_CMD_UPDATE_TPA
:
5367 return bnx2x_q_send_update_tpa(bp
, params
);
5368 case BNX2X_Q_CMD_HALT
:
5369 return bnx2x_q_send_halt(bp
, params
);
5370 case BNX2X_Q_CMD_CFC_DEL
:
5371 return bnx2x_q_send_cfc_del(bp
, params
);
5372 case BNX2X_Q_CMD_TERMINATE
:
5373 return bnx2x_q_send_terminate(bp
, params
);
5374 case BNX2X_Q_CMD_EMPTY
:
5375 return bnx2x_q_send_empty(bp
, params
);
5377 BNX2X_ERR("Unknown command: %d\n", params
->cmd
);
5382 static int bnx2x_queue_send_cmd_e1x(struct bnx2x
*bp
,
5383 struct bnx2x_queue_state_params
*params
)
5385 switch (params
->cmd
) {
5386 case BNX2X_Q_CMD_SETUP
:
5387 return bnx2x_q_send_setup_e1x(bp
, params
);
5388 case BNX2X_Q_CMD_INIT
:
5389 case BNX2X_Q_CMD_SETUP_TX_ONLY
:
5390 case BNX2X_Q_CMD_DEACTIVATE
:
5391 case BNX2X_Q_CMD_ACTIVATE
:
5392 case BNX2X_Q_CMD_UPDATE
:
5393 case BNX2X_Q_CMD_UPDATE_TPA
:
5394 case BNX2X_Q_CMD_HALT
:
5395 case BNX2X_Q_CMD_CFC_DEL
:
5396 case BNX2X_Q_CMD_TERMINATE
:
5397 case BNX2X_Q_CMD_EMPTY
:
5398 return bnx2x_queue_send_cmd_cmn(bp
, params
);
5400 BNX2X_ERR("Unknown command: %d\n", params
->cmd
);
5405 static int bnx2x_queue_send_cmd_e2(struct bnx2x
*bp
,
5406 struct bnx2x_queue_state_params
*params
)
5408 switch (params
->cmd
) {
5409 case BNX2X_Q_CMD_SETUP
:
5410 return bnx2x_q_send_setup_e2(bp
, params
);
5411 case BNX2X_Q_CMD_INIT
:
5412 case BNX2X_Q_CMD_SETUP_TX_ONLY
:
5413 case BNX2X_Q_CMD_DEACTIVATE
:
5414 case BNX2X_Q_CMD_ACTIVATE
:
5415 case BNX2X_Q_CMD_UPDATE
:
5416 case BNX2X_Q_CMD_UPDATE_TPA
:
5417 case BNX2X_Q_CMD_HALT
:
5418 case BNX2X_Q_CMD_CFC_DEL
:
5419 case BNX2X_Q_CMD_TERMINATE
:
5420 case BNX2X_Q_CMD_EMPTY
:
5421 return bnx2x_queue_send_cmd_cmn(bp
, params
);
5423 BNX2X_ERR("Unknown command: %d\n", params
->cmd
);
5429 * bnx2x_queue_chk_transition - check state machine of a regular Queue
5431 * @bp: device handle
5436 * It both checks if the requested command is legal in a current
5437 * state and, if it's legal, sets a `next_state' in the object
5438 * that will be used in the completion flow to set the `state'
5441 * returns 0 if a requested command is a legal transition,
5442 * -EINVAL otherwise.
5444 static int bnx2x_queue_chk_transition(struct bnx2x
*bp
,
5445 struct bnx2x_queue_sp_obj
*o
,
5446 struct bnx2x_queue_state_params
*params
)
5448 enum bnx2x_q_state state
= o
->state
, next_state
= BNX2X_Q_STATE_MAX
;
5449 enum bnx2x_queue_cmd cmd
= params
->cmd
;
5450 struct bnx2x_queue_update_params
*update_params
=
5451 ¶ms
->params
.update
;
5452 u8 next_tx_only
= o
->num_tx_only
;
5454 /* Forget all pending for completion commands if a driver only state
5455 * transition has been requested.
5457 if (test_bit(RAMROD_DRV_CLR_ONLY
, ¶ms
->ramrod_flags
)) {
5459 o
->next_state
= BNX2X_Q_STATE_MAX
;
5462 /* Don't allow a next state transition if we are in the middle of
5466 BNX2X_ERR("Blocking transition since pending was %lx\n",
5472 case BNX2X_Q_STATE_RESET
:
5473 if (cmd
== BNX2X_Q_CMD_INIT
)
5474 next_state
= BNX2X_Q_STATE_INITIALIZED
;
5477 case BNX2X_Q_STATE_INITIALIZED
:
5478 if (cmd
== BNX2X_Q_CMD_SETUP
) {
5479 if (test_bit(BNX2X_Q_FLG_ACTIVE
,
5480 ¶ms
->params
.setup
.flags
))
5481 next_state
= BNX2X_Q_STATE_ACTIVE
;
5483 next_state
= BNX2X_Q_STATE_INACTIVE
;
5487 case BNX2X_Q_STATE_ACTIVE
:
5488 if (cmd
== BNX2X_Q_CMD_DEACTIVATE
)
5489 next_state
= BNX2X_Q_STATE_INACTIVE
;
5491 else if ((cmd
== BNX2X_Q_CMD_EMPTY
) ||
5492 (cmd
== BNX2X_Q_CMD_UPDATE_TPA
))
5493 next_state
= BNX2X_Q_STATE_ACTIVE
;
5495 else if (cmd
== BNX2X_Q_CMD_SETUP_TX_ONLY
) {
5496 next_state
= BNX2X_Q_STATE_MULTI_COS
;
5500 else if (cmd
== BNX2X_Q_CMD_HALT
)
5501 next_state
= BNX2X_Q_STATE_STOPPED
;
5503 else if (cmd
== BNX2X_Q_CMD_UPDATE
) {
5504 /* If "active" state change is requested, update the
5505 * state accordingly.
5507 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG
,
5508 &update_params
->update_flags
) &&
5509 !test_bit(BNX2X_Q_UPDATE_ACTIVATE
,
5510 &update_params
->update_flags
))
5511 next_state
= BNX2X_Q_STATE_INACTIVE
;
5513 next_state
= BNX2X_Q_STATE_ACTIVE
;
5517 case BNX2X_Q_STATE_MULTI_COS
:
5518 if (cmd
== BNX2X_Q_CMD_TERMINATE
)
5519 next_state
= BNX2X_Q_STATE_MCOS_TERMINATED
;
5521 else if (cmd
== BNX2X_Q_CMD_SETUP_TX_ONLY
) {
5522 next_state
= BNX2X_Q_STATE_MULTI_COS
;
5523 next_tx_only
= o
->num_tx_only
+ 1;
5526 else if ((cmd
== BNX2X_Q_CMD_EMPTY
) ||
5527 (cmd
== BNX2X_Q_CMD_UPDATE_TPA
))
5528 next_state
= BNX2X_Q_STATE_MULTI_COS
;
5530 else if (cmd
== BNX2X_Q_CMD_UPDATE
) {
5531 /* If "active" state change is requested, update the
5532 * state accordingly.
5534 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG
,
5535 &update_params
->update_flags
) &&
5536 !test_bit(BNX2X_Q_UPDATE_ACTIVATE
,
5537 &update_params
->update_flags
))
5538 next_state
= BNX2X_Q_STATE_INACTIVE
;
5540 next_state
= BNX2X_Q_STATE_MULTI_COS
;
5544 case BNX2X_Q_STATE_MCOS_TERMINATED
:
5545 if (cmd
== BNX2X_Q_CMD_CFC_DEL
) {
5546 next_tx_only
= o
->num_tx_only
- 1;
5547 if (next_tx_only
== 0)
5548 next_state
= BNX2X_Q_STATE_ACTIVE
;
5550 next_state
= BNX2X_Q_STATE_MULTI_COS
;
5554 case BNX2X_Q_STATE_INACTIVE
:
5555 if (cmd
== BNX2X_Q_CMD_ACTIVATE
)
5556 next_state
= BNX2X_Q_STATE_ACTIVE
;
5558 else if ((cmd
== BNX2X_Q_CMD_EMPTY
) ||
5559 (cmd
== BNX2X_Q_CMD_UPDATE_TPA
))
5560 next_state
= BNX2X_Q_STATE_INACTIVE
;
5562 else if (cmd
== BNX2X_Q_CMD_HALT
)
5563 next_state
= BNX2X_Q_STATE_STOPPED
;
5565 else if (cmd
== BNX2X_Q_CMD_UPDATE
) {
5566 /* If "active" state change is requested, update the
5567 * state accordingly.
5569 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG
,
5570 &update_params
->update_flags
) &&
5571 test_bit(BNX2X_Q_UPDATE_ACTIVATE
,
5572 &update_params
->update_flags
)){
5573 if (o
->num_tx_only
== 0)
5574 next_state
= BNX2X_Q_STATE_ACTIVE
;
5575 else /* tx only queues exist for this queue */
5576 next_state
= BNX2X_Q_STATE_MULTI_COS
;
5578 next_state
= BNX2X_Q_STATE_INACTIVE
;
5582 case BNX2X_Q_STATE_STOPPED
:
5583 if (cmd
== BNX2X_Q_CMD_TERMINATE
)
5584 next_state
= BNX2X_Q_STATE_TERMINATED
;
5587 case BNX2X_Q_STATE_TERMINATED
:
5588 if (cmd
== BNX2X_Q_CMD_CFC_DEL
)
5589 next_state
= BNX2X_Q_STATE_RESET
;
5593 BNX2X_ERR("Illegal state: %d\n", state
);
5596 /* Transition is assured */
5597 if (next_state
!= BNX2X_Q_STATE_MAX
) {
5598 DP(BNX2X_MSG_SP
, "Good state transition: %d(%d)->%d\n",
5599 state
, cmd
, next_state
);
5600 o
->next_state
= next_state
;
5601 o
->next_tx_only
= next_tx_only
;
5605 DP(BNX2X_MSG_SP
, "Bad state transition request: %d %d\n", state
, cmd
);
5610 void bnx2x_init_queue_obj(struct bnx2x
*bp
,
5611 struct bnx2x_queue_sp_obj
*obj
,
5612 u8 cl_id
, u32
*cids
, u8 cid_cnt
, u8 func_id
,
5614 dma_addr_t rdata_mapping
, unsigned long type
)
5616 memset(obj
, 0, sizeof(*obj
));
5618 /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */
5619 BUG_ON(BNX2X_MULTI_TX_COS
< cid_cnt
);
5621 memcpy(obj
->cids
, cids
, sizeof(obj
->cids
[0]) * cid_cnt
);
5622 obj
->max_cos
= cid_cnt
;
5624 obj
->func_id
= func_id
;
5626 obj
->rdata_mapping
= rdata_mapping
;
5628 obj
->next_state
= BNX2X_Q_STATE_MAX
;
5630 if (CHIP_IS_E1x(bp
))
5631 obj
->send_cmd
= bnx2x_queue_send_cmd_e1x
;
5633 obj
->send_cmd
= bnx2x_queue_send_cmd_e2
;
5635 obj
->check_transition
= bnx2x_queue_chk_transition
;
5637 obj
->complete_cmd
= bnx2x_queue_comp_cmd
;
5638 obj
->wait_comp
= bnx2x_queue_wait_comp
;
5639 obj
->set_pending
= bnx2x_queue_set_pending
;
5642 /* return a queue object's logical state*/
5643 int bnx2x_get_q_logical_state(struct bnx2x
*bp
,
5644 struct bnx2x_queue_sp_obj
*obj
)
5646 switch (obj
->state
) {
5647 case BNX2X_Q_STATE_ACTIVE
:
5648 case BNX2X_Q_STATE_MULTI_COS
:
5649 return BNX2X_Q_LOGICAL_STATE_ACTIVE
;
5650 case BNX2X_Q_STATE_RESET
:
5651 case BNX2X_Q_STATE_INITIALIZED
:
5652 case BNX2X_Q_STATE_MCOS_TERMINATED
:
5653 case BNX2X_Q_STATE_INACTIVE
:
5654 case BNX2X_Q_STATE_STOPPED
:
5655 case BNX2X_Q_STATE_TERMINATED
:
5656 case BNX2X_Q_STATE_FLRED
:
5657 return BNX2X_Q_LOGICAL_STATE_STOPPED
;
5663 /********************** Function state object *********************************/
5664 enum bnx2x_func_state
bnx2x_func_get_state(struct bnx2x
*bp
,
5665 struct bnx2x_func_sp_obj
*o
)
5667 /* in the middle of transaction - return INVALID state */
5669 return BNX2X_F_STATE_MAX
;
5671 /* unsure the order of reading of o->pending and o->state
5672 * o->pending should be read first
5679 static int bnx2x_func_wait_comp(struct bnx2x
*bp
,
5680 struct bnx2x_func_sp_obj
*o
,
5681 enum bnx2x_func_cmd cmd
)
5683 return bnx2x_state_wait(bp
, cmd
, &o
->pending
);
5687 * bnx2x_func_state_change_comp - complete the state machine transition
5689 * @bp: device handle
5693 * Called on state change transition. Completes the state
5694 * machine transition only - no HW interaction.
5696 static inline int bnx2x_func_state_change_comp(struct bnx2x
*bp
,
5697 struct bnx2x_func_sp_obj
*o
,
5698 enum bnx2x_func_cmd cmd
)
5700 unsigned long cur_pending
= o
->pending
;
5702 if (!test_and_clear_bit(cmd
, &cur_pending
)) {
5703 BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5704 cmd
, BP_FUNC(bp
), o
->state
,
5705 cur_pending
, o
->next_state
);
5710 "Completing command %d for func %d, setting state to %d\n",
5711 cmd
, BP_FUNC(bp
), o
->next_state
);
5713 o
->state
= o
->next_state
;
5714 o
->next_state
= BNX2X_F_STATE_MAX
;
5716 /* It's important that o->state and o->next_state are
5717 * updated before o->pending.
5721 clear_bit(cmd
, &o
->pending
);
5722 smp_mb__after_atomic();
5728 * bnx2x_func_comp_cmd - complete the state change command
5730 * @bp: device handle
5734 * Checks that the arrived completion is expected.
5736 static int bnx2x_func_comp_cmd(struct bnx2x
*bp
,
5737 struct bnx2x_func_sp_obj
*o
,
5738 enum bnx2x_func_cmd cmd
)
5740 /* Complete the state machine part first, check if it's a
5743 int rc
= bnx2x_func_state_change_comp(bp
, o
, cmd
);
5748 * bnx2x_func_chk_transition - perform function state machine transition
5750 * @bp: device handle
5754 * It both checks if the requested command is legal in a current
5755 * state and, if it's legal, sets a `next_state' in the object
5756 * that will be used in the completion flow to set the `state'
5759 * returns 0 if a requested command is a legal transition,
5760 * -EINVAL otherwise.
5762 static int bnx2x_func_chk_transition(struct bnx2x
*bp
,
5763 struct bnx2x_func_sp_obj
*o
,
5764 struct bnx2x_func_state_params
*params
)
5766 enum bnx2x_func_state state
= o
->state
, next_state
= BNX2X_F_STATE_MAX
;
5767 enum bnx2x_func_cmd cmd
= params
->cmd
;
5769 /* Forget all pending for completion commands if a driver only state
5770 * transition has been requested.
5772 if (test_bit(RAMROD_DRV_CLR_ONLY
, ¶ms
->ramrod_flags
)) {
5774 o
->next_state
= BNX2X_F_STATE_MAX
;
5777 /* Don't allow a next state transition if we are in the middle of
5784 case BNX2X_F_STATE_RESET
:
5785 if (cmd
== BNX2X_F_CMD_HW_INIT
)
5786 next_state
= BNX2X_F_STATE_INITIALIZED
;
5789 case BNX2X_F_STATE_INITIALIZED
:
5790 if (cmd
== BNX2X_F_CMD_START
)
5791 next_state
= BNX2X_F_STATE_STARTED
;
5793 else if (cmd
== BNX2X_F_CMD_HW_RESET
)
5794 next_state
= BNX2X_F_STATE_RESET
;
5797 case BNX2X_F_STATE_STARTED
:
5798 if (cmd
== BNX2X_F_CMD_STOP
)
5799 next_state
= BNX2X_F_STATE_INITIALIZED
;
5800 /* afex ramrods can be sent only in started mode, and only
5801 * if not pending for function_stop ramrod completion
5802 * for these events - next state remained STARTED.
5804 else if ((cmd
== BNX2X_F_CMD_AFEX_UPDATE
) &&
5805 (!test_bit(BNX2X_F_CMD_STOP
, &o
->pending
)))
5806 next_state
= BNX2X_F_STATE_STARTED
;
5808 else if ((cmd
== BNX2X_F_CMD_AFEX_VIFLISTS
) &&
5809 (!test_bit(BNX2X_F_CMD_STOP
, &o
->pending
)))
5810 next_state
= BNX2X_F_STATE_STARTED
;
5812 /* Switch_update ramrod can be sent in either started or
5813 * tx_stopped state, and it doesn't change the state.
5815 else if ((cmd
== BNX2X_F_CMD_SWITCH_UPDATE
) &&
5816 (!test_bit(BNX2X_F_CMD_STOP
, &o
->pending
)))
5817 next_state
= BNX2X_F_STATE_STARTED
;
5819 else if ((cmd
== BNX2X_F_CMD_SET_TIMESYNC
) &&
5820 (!test_bit(BNX2X_F_CMD_STOP
, &o
->pending
)))
5821 next_state
= BNX2X_F_STATE_STARTED
;
5823 else if (cmd
== BNX2X_F_CMD_TX_STOP
)
5824 next_state
= BNX2X_F_STATE_TX_STOPPED
;
5827 case BNX2X_F_STATE_TX_STOPPED
:
5828 if ((cmd
== BNX2X_F_CMD_SWITCH_UPDATE
) &&
5829 (!test_bit(BNX2X_F_CMD_STOP
, &o
->pending
)))
5830 next_state
= BNX2X_F_STATE_TX_STOPPED
;
5832 else if ((cmd
== BNX2X_F_CMD_SET_TIMESYNC
) &&
5833 (!test_bit(BNX2X_F_CMD_STOP
, &o
->pending
)))
5834 next_state
= BNX2X_F_STATE_TX_STOPPED
;
5836 else if (cmd
== BNX2X_F_CMD_TX_START
)
5837 next_state
= BNX2X_F_STATE_STARTED
;
5841 BNX2X_ERR("Unknown state: %d\n", state
);
5844 /* Transition is assured */
5845 if (next_state
!= BNX2X_F_STATE_MAX
) {
5846 DP(BNX2X_MSG_SP
, "Good function state transition: %d(%d)->%d\n",
5847 state
, cmd
, next_state
);
5848 o
->next_state
= next_state
;
5852 DP(BNX2X_MSG_SP
, "Bad function state transition request: %d %d\n",
5859 * bnx2x_func_init_func - performs HW init at function stage
5861 * @bp: device handle
5864 * Init HW when the current phase is
5865 * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only
5868 static inline int bnx2x_func_init_func(struct bnx2x
*bp
,
5869 const struct bnx2x_func_sp_drv_ops
*drv
)
5871 return drv
->init_hw_func(bp
);
5875 * bnx2x_func_init_port - performs HW init at port stage
5877 * @bp: device handle
5880 * Init HW when the current phase is
5881 * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and
5882 * FUNCTION-only HW blocks.
5885 static inline int bnx2x_func_init_port(struct bnx2x
*bp
,
5886 const struct bnx2x_func_sp_drv_ops
*drv
)
5888 int rc
= drv
->init_hw_port(bp
);
5892 return bnx2x_func_init_func(bp
, drv
);
5896 * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage
5898 * @bp: device handle
5901 * Init HW when the current phase is
5902 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP,
5903 * PORT-only and FUNCTION-only HW blocks.
5905 static inline int bnx2x_func_init_cmn_chip(struct bnx2x
*bp
,
5906 const struct bnx2x_func_sp_drv_ops
*drv
)
5908 int rc
= drv
->init_hw_cmn_chip(bp
);
5912 return bnx2x_func_init_port(bp
, drv
);
5916 * bnx2x_func_init_cmn - performs HW init at common stage
5918 * @bp: device handle
5921 * Init HW when the current phase is
5922 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON,
5923 * PORT-only and FUNCTION-only HW blocks.
5925 static inline int bnx2x_func_init_cmn(struct bnx2x
*bp
,
5926 const struct bnx2x_func_sp_drv_ops
*drv
)
5928 int rc
= drv
->init_hw_cmn(bp
);
5932 return bnx2x_func_init_port(bp
, drv
);
5935 static int bnx2x_func_hw_init(struct bnx2x
*bp
,
5936 struct bnx2x_func_state_params
*params
)
5938 u32 load_code
= params
->params
.hw_init
.load_phase
;
5939 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
5940 const struct bnx2x_func_sp_drv_ops
*drv
= o
->drv
;
5943 DP(BNX2X_MSG_SP
, "function %d load_code %x\n",
5944 BP_ABS_FUNC(bp
), load_code
);
5946 /* Prepare buffers for unzipping the FW */
5947 rc
= drv
->gunzip_init(bp
);
5952 rc
= drv
->init_fw(bp
);
5954 BNX2X_ERR("Error loading firmware\n");
5958 /* Handle the beginning of COMMON_XXX pases separately... */
5959 switch (load_code
) {
5960 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
5961 rc
= bnx2x_func_init_cmn_chip(bp
, drv
);
5966 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5967 rc
= bnx2x_func_init_cmn(bp
, drv
);
5972 case FW_MSG_CODE_DRV_LOAD_PORT
:
5973 rc
= bnx2x_func_init_port(bp
, drv
);
5978 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5979 rc
= bnx2x_func_init_func(bp
, drv
);
5985 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5990 drv
->gunzip_end(bp
);
5992 /* In case of success, complete the command immediately: no ramrods
5996 o
->complete_cmd(bp
, o
, BNX2X_F_CMD_HW_INIT
);
6002 * bnx2x_func_reset_func - reset HW at function stage
6004 * @bp: device handle
6007 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only
6008 * FUNCTION-only HW blocks.
6010 static inline void bnx2x_func_reset_func(struct bnx2x
*bp
,
6011 const struct bnx2x_func_sp_drv_ops
*drv
)
6013 drv
->reset_hw_func(bp
);
6017 * bnx2x_func_reset_port - reset HW at port stage
6019 * @bp: device handle
6022 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset
6023 * FUNCTION-only and PORT-only HW blocks.
6027 * It's important to call reset_port before reset_func() as the last thing
6028 * reset_func does is pf_disable() thus disabling PGLUE_B, which
6029 * makes impossible any DMAE transactions.
6031 static inline void bnx2x_func_reset_port(struct bnx2x
*bp
,
6032 const struct bnx2x_func_sp_drv_ops
*drv
)
6034 drv
->reset_hw_port(bp
);
6035 bnx2x_func_reset_func(bp
, drv
);
6039 * bnx2x_func_reset_cmn - reset HW at common stage
6041 * @bp: device handle
6044 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and
6045 * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON,
6046 * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks.
6048 static inline void bnx2x_func_reset_cmn(struct bnx2x
*bp
,
6049 const struct bnx2x_func_sp_drv_ops
*drv
)
6051 bnx2x_func_reset_port(bp
, drv
);
6052 drv
->reset_hw_cmn(bp
);
6055 static inline int bnx2x_func_hw_reset(struct bnx2x
*bp
,
6056 struct bnx2x_func_state_params
*params
)
6058 u32 reset_phase
= params
->params
.hw_reset
.reset_phase
;
6059 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6060 const struct bnx2x_func_sp_drv_ops
*drv
= o
->drv
;
6062 DP(BNX2X_MSG_SP
, "function %d reset_phase %x\n", BP_ABS_FUNC(bp
),
6065 switch (reset_phase
) {
6066 case FW_MSG_CODE_DRV_UNLOAD_COMMON
:
6067 bnx2x_func_reset_cmn(bp
, drv
);
6069 case FW_MSG_CODE_DRV_UNLOAD_PORT
:
6070 bnx2x_func_reset_port(bp
, drv
);
6072 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION
:
6073 bnx2x_func_reset_func(bp
, drv
);
6076 BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n",
6081 /* Complete the command immediately: no ramrods have been sent. */
6082 o
->complete_cmd(bp
, o
, BNX2X_F_CMD_HW_RESET
);
6087 static inline int bnx2x_func_send_start(struct bnx2x
*bp
,
6088 struct bnx2x_func_state_params
*params
)
6090 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6091 struct function_start_data
*rdata
=
6092 (struct function_start_data
*)o
->rdata
;
6093 dma_addr_t data_mapping
= o
->rdata_mapping
;
6094 struct bnx2x_func_start_params
*start_params
= ¶ms
->params
.start
;
6096 memset(rdata
, 0, sizeof(*rdata
));
6098 /* Fill the ramrod data with provided parameters */
6099 rdata
->function_mode
= (u8
)start_params
->mf_mode
;
6100 rdata
->sd_vlan_tag
= cpu_to_le16(start_params
->sd_vlan_tag
);
6101 rdata
->path_id
= BP_PATH(bp
);
6102 rdata
->network_cos_mode
= start_params
->network_cos_mode
;
6104 rdata
->vxlan_dst_port
= cpu_to_le16(start_params
->vxlan_dst_port
);
6105 rdata
->geneve_dst_port
= cpu_to_le16(start_params
->geneve_dst_port
);
6106 rdata
->inner_clss_l2gre
= start_params
->inner_clss_l2gre
;
6107 rdata
->inner_clss_l2geneve
= start_params
->inner_clss_l2geneve
;
6108 rdata
->inner_clss_vxlan
= start_params
->inner_clss_vxlan
;
6109 rdata
->inner_rss
= start_params
->inner_rss
;
6111 rdata
->sd_accept_mf_clss_fail
= start_params
->class_fail
;
6112 if (start_params
->class_fail_ethtype
) {
6113 rdata
->sd_accept_mf_clss_fail_match_ethtype
= 1;
6114 rdata
->sd_accept_mf_clss_fail_ethtype
=
6115 cpu_to_le16(start_params
->class_fail_ethtype
);
6118 rdata
->sd_vlan_force_pri_flg
= start_params
->sd_vlan_force_pri
;
6119 rdata
->sd_vlan_force_pri_val
= start_params
->sd_vlan_force_pri_val
;
6120 if (start_params
->sd_vlan_eth_type
)
6121 rdata
->sd_vlan_eth_type
=
6122 cpu_to_le16(start_params
->sd_vlan_eth_type
);
6124 rdata
->sd_vlan_eth_type
=
6125 cpu_to_le16(0x8100);
6127 rdata
->no_added_tags
= start_params
->no_added_tags
;
6129 rdata
->c2s_pri_tt_valid
= start_params
->c2s_pri_valid
;
6130 if (rdata
->c2s_pri_tt_valid
) {
6131 memcpy(rdata
->c2s_pri_trans_table
.val
,
6132 start_params
->c2s_pri
,
6133 MAX_VLAN_PRIORITIES
);
6134 rdata
->c2s_pri_default
= start_params
->c2s_pri_default
;
6136 /* No need for an explicit memory barrier here as long we would
6137 * need to ensure the ordering of writing to the SPQ element
6138 * and updating of the SPQ producer which involves a memory
6139 * read and we will have to put a full memory barrier there
6140 * (inside bnx2x_sp_post()).
6143 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_FUNCTION_START
, 0,
6144 U64_HI(data_mapping
),
6145 U64_LO(data_mapping
), NONE_CONNECTION_TYPE
);
6148 static inline int bnx2x_func_send_switch_update(struct bnx2x
*bp
,
6149 struct bnx2x_func_state_params
*params
)
6151 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6152 struct function_update_data
*rdata
=
6153 (struct function_update_data
*)o
->rdata
;
6154 dma_addr_t data_mapping
= o
->rdata_mapping
;
6155 struct bnx2x_func_switch_update_params
*switch_update_params
=
6156 ¶ms
->params
.switch_update
;
6158 memset(rdata
, 0, sizeof(*rdata
));
6160 /* Fill the ramrod data with provided parameters */
6161 if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG
,
6162 &switch_update_params
->changes
)) {
6163 rdata
->tx_switch_suspend_change_flg
= 1;
6164 rdata
->tx_switch_suspend
=
6165 test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND
,
6166 &switch_update_params
->changes
);
6169 if (test_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG
,
6170 &switch_update_params
->changes
)) {
6171 rdata
->sd_vlan_tag_change_flg
= 1;
6172 rdata
->sd_vlan_tag
=
6173 cpu_to_le16(switch_update_params
->vlan
);
6176 if (test_bit(BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG
,
6177 &switch_update_params
->changes
)) {
6178 rdata
->sd_vlan_eth_type_change_flg
= 1;
6179 rdata
->sd_vlan_eth_type
=
6180 cpu_to_le16(switch_update_params
->vlan_eth_type
);
6183 if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG
,
6184 &switch_update_params
->changes
)) {
6185 rdata
->sd_vlan_force_pri_change_flg
= 1;
6186 if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG
,
6187 &switch_update_params
->changes
))
6188 rdata
->sd_vlan_force_pri_flg
= 1;
6189 rdata
->sd_vlan_force_pri_flg
=
6190 switch_update_params
->vlan_force_prio
;
6193 if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG
,
6194 &switch_update_params
->changes
)) {
6195 rdata
->update_tunn_cfg_flg
= 1;
6196 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE
,
6197 &switch_update_params
->changes
))
6198 rdata
->inner_clss_l2gre
= 1;
6199 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN
,
6200 &switch_update_params
->changes
))
6201 rdata
->inner_clss_vxlan
= 1;
6202 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE
,
6203 &switch_update_params
->changes
))
6204 rdata
->inner_clss_l2geneve
= 1;
6205 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS
,
6206 &switch_update_params
->changes
))
6207 rdata
->inner_rss
= 1;
6208 rdata
->vxlan_dst_port
=
6209 cpu_to_le16(switch_update_params
->vxlan_dst_port
);
6210 rdata
->geneve_dst_port
=
6211 cpu_to_le16(switch_update_params
->geneve_dst_port
);
6214 rdata
->echo
= SWITCH_UPDATE
;
6216 /* No need for an explicit memory barrier here as long as we
6217 * ensure the ordering of writing to the SPQ element
6218 * and updating of the SPQ producer which involves a memory
6219 * read. If the memory read is removed we will have to put a
6220 * full memory barrier there (inside bnx2x_sp_post()).
6222 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE
, 0,
6223 U64_HI(data_mapping
),
6224 U64_LO(data_mapping
), NONE_CONNECTION_TYPE
);
6227 static inline int bnx2x_func_send_afex_update(struct bnx2x
*bp
,
6228 struct bnx2x_func_state_params
*params
)
6230 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6231 struct function_update_data
*rdata
=
6232 (struct function_update_data
*)o
->afex_rdata
;
6233 dma_addr_t data_mapping
= o
->afex_rdata_mapping
;
6234 struct bnx2x_func_afex_update_params
*afex_update_params
=
6235 ¶ms
->params
.afex_update
;
6237 memset(rdata
, 0, sizeof(*rdata
));
6239 /* Fill the ramrod data with provided parameters */
6240 rdata
->vif_id_change_flg
= 1;
6241 rdata
->vif_id
= cpu_to_le16(afex_update_params
->vif_id
);
6242 rdata
->afex_default_vlan_change_flg
= 1;
6243 rdata
->afex_default_vlan
=
6244 cpu_to_le16(afex_update_params
->afex_default_vlan
);
6245 rdata
->allowed_priorities_change_flg
= 1;
6246 rdata
->allowed_priorities
= afex_update_params
->allowed_priorities
;
6247 rdata
->echo
= AFEX_UPDATE
;
6249 /* No need for an explicit memory barrier here as long as we
6250 * ensure the ordering of writing to the SPQ element
6251 * and updating of the SPQ producer which involves a memory
6252 * read. If the memory read is removed we will have to put a
6253 * full memory barrier there (inside bnx2x_sp_post()).
6256 "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
6258 rdata
->afex_default_vlan
, rdata
->allowed_priorities
);
6260 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE
, 0,
6261 U64_HI(data_mapping
),
6262 U64_LO(data_mapping
), NONE_CONNECTION_TYPE
);
6266 inline int bnx2x_func_send_afex_viflists(struct bnx2x
*bp
,
6267 struct bnx2x_func_state_params
*params
)
6269 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6270 struct afex_vif_list_ramrod_data
*rdata
=
6271 (struct afex_vif_list_ramrod_data
*)o
->afex_rdata
;
6272 struct bnx2x_func_afex_viflists_params
*afex_vif_params
=
6273 ¶ms
->params
.afex_viflists
;
6274 u64
*p_rdata
= (u64
*)rdata
;
6276 memset(rdata
, 0, sizeof(*rdata
));
6278 /* Fill the ramrod data with provided parameters */
6279 rdata
->vif_list_index
= cpu_to_le16(afex_vif_params
->vif_list_index
);
6280 rdata
->func_bit_map
= afex_vif_params
->func_bit_map
;
6281 rdata
->afex_vif_list_command
= afex_vif_params
->afex_vif_list_command
;
6282 rdata
->func_to_clear
= afex_vif_params
->func_to_clear
;
6284 /* send in echo type of sub command */
6285 rdata
->echo
= afex_vif_params
->afex_vif_list_command
;
6287 /* No need for an explicit memory barrier here as long we would
6288 * need to ensure the ordering of writing to the SPQ element
6289 * and updating of the SPQ producer which involves a memory
6290 * read and we will have to put a full memory barrier there
6291 * (inside bnx2x_sp_post()).
6294 DP(BNX2X_MSG_SP
, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n",
6295 rdata
->afex_vif_list_command
, rdata
->vif_list_index
,
6296 rdata
->func_bit_map
, rdata
->func_to_clear
);
6298 /* this ramrod sends data directly and not through DMA mapping */
6299 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS
, 0,
6300 U64_HI(*p_rdata
), U64_LO(*p_rdata
),
6301 NONE_CONNECTION_TYPE
);
6304 static inline int bnx2x_func_send_stop(struct bnx2x
*bp
,
6305 struct bnx2x_func_state_params
*params
)
6307 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_FUNCTION_STOP
, 0, 0, 0,
6308 NONE_CONNECTION_TYPE
);
6311 static inline int bnx2x_func_send_tx_stop(struct bnx2x
*bp
,
6312 struct bnx2x_func_state_params
*params
)
6314 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC
, 0, 0, 0,
6315 NONE_CONNECTION_TYPE
);
6317 static inline int bnx2x_func_send_tx_start(struct bnx2x
*bp
,
6318 struct bnx2x_func_state_params
*params
)
6320 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6321 struct flow_control_configuration
*rdata
=
6322 (struct flow_control_configuration
*)o
->rdata
;
6323 dma_addr_t data_mapping
= o
->rdata_mapping
;
6324 struct bnx2x_func_tx_start_params
*tx_start_params
=
6325 ¶ms
->params
.tx_start
;
6328 memset(rdata
, 0, sizeof(*rdata
));
6330 rdata
->dcb_enabled
= tx_start_params
->dcb_enabled
;
6331 rdata
->dcb_version
= tx_start_params
->dcb_version
;
6332 rdata
->dont_add_pri_0_en
= tx_start_params
->dont_add_pri_0_en
;
6334 for (i
= 0; i
< ARRAY_SIZE(rdata
->traffic_type_to_priority_cos
); i
++)
6335 rdata
->traffic_type_to_priority_cos
[i
] =
6336 tx_start_params
->traffic_type_to_priority_cos
[i
];
6338 for (i
= 0; i
< MAX_TRAFFIC_TYPES
; i
++)
6339 rdata
->dcb_outer_pri
[i
] = tx_start_params
->dcb_outer_pri
[i
];
6340 /* No need for an explicit memory barrier here as long as we
6341 * ensure the ordering of writing to the SPQ element
6342 * and updating of the SPQ producer which involves a memory
6343 * read. If the memory read is removed we will have to put a
6344 * full memory barrier there (inside bnx2x_sp_post()).
6346 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_START_TRAFFIC
, 0,
6347 U64_HI(data_mapping
),
6348 U64_LO(data_mapping
), NONE_CONNECTION_TYPE
);
6352 int bnx2x_func_send_set_timesync(struct bnx2x
*bp
,
6353 struct bnx2x_func_state_params
*params
)
6355 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6356 struct set_timesync_ramrod_data
*rdata
=
6357 (struct set_timesync_ramrod_data
*)o
->rdata
;
6358 dma_addr_t data_mapping
= o
->rdata_mapping
;
6359 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
6360 ¶ms
->params
.set_timesync
;
6362 memset(rdata
, 0, sizeof(*rdata
));
6364 /* Fill the ramrod data with provided parameters */
6365 rdata
->drift_adjust_cmd
= set_timesync_params
->drift_adjust_cmd
;
6366 rdata
->offset_cmd
= set_timesync_params
->offset_cmd
;
6367 rdata
->add_sub_drift_adjust_value
=
6368 set_timesync_params
->add_sub_drift_adjust_value
;
6369 rdata
->drift_adjust_value
= set_timesync_params
->drift_adjust_value
;
6370 rdata
->drift_adjust_period
= set_timesync_params
->drift_adjust_period
;
6371 rdata
->offset_delta
.lo
=
6372 cpu_to_le32(U64_LO(set_timesync_params
->offset_delta
));
6373 rdata
->offset_delta
.hi
=
6374 cpu_to_le32(U64_HI(set_timesync_params
->offset_delta
));
6376 DP(BNX2X_MSG_SP
, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n",
6377 rdata
->drift_adjust_cmd
, rdata
->offset_cmd
,
6378 rdata
->add_sub_drift_adjust_value
, rdata
->drift_adjust_value
,
6379 rdata
->drift_adjust_period
, rdata
->offset_delta
.lo
,
6380 rdata
->offset_delta
.hi
);
6382 return bnx2x_sp_post(bp
, RAMROD_CMD_ID_COMMON_SET_TIMESYNC
, 0,
6383 U64_HI(data_mapping
),
6384 U64_LO(data_mapping
), NONE_CONNECTION_TYPE
);
6387 static int bnx2x_func_send_cmd(struct bnx2x
*bp
,
6388 struct bnx2x_func_state_params
*params
)
6390 switch (params
->cmd
) {
6391 case BNX2X_F_CMD_HW_INIT
:
6392 return bnx2x_func_hw_init(bp
, params
);
6393 case BNX2X_F_CMD_START
:
6394 return bnx2x_func_send_start(bp
, params
);
6395 case BNX2X_F_CMD_STOP
:
6396 return bnx2x_func_send_stop(bp
, params
);
6397 case BNX2X_F_CMD_HW_RESET
:
6398 return bnx2x_func_hw_reset(bp
, params
);
6399 case BNX2X_F_CMD_AFEX_UPDATE
:
6400 return bnx2x_func_send_afex_update(bp
, params
);
6401 case BNX2X_F_CMD_AFEX_VIFLISTS
:
6402 return bnx2x_func_send_afex_viflists(bp
, params
);
6403 case BNX2X_F_CMD_TX_STOP
:
6404 return bnx2x_func_send_tx_stop(bp
, params
);
6405 case BNX2X_F_CMD_TX_START
:
6406 return bnx2x_func_send_tx_start(bp
, params
);
6407 case BNX2X_F_CMD_SWITCH_UPDATE
:
6408 return bnx2x_func_send_switch_update(bp
, params
);
6409 case BNX2X_F_CMD_SET_TIMESYNC
:
6410 return bnx2x_func_send_set_timesync(bp
, params
);
6412 BNX2X_ERR("Unknown command: %d\n", params
->cmd
);
6417 void bnx2x_init_func_obj(struct bnx2x
*bp
,
6418 struct bnx2x_func_sp_obj
*obj
,
6419 void *rdata
, dma_addr_t rdata_mapping
,
6420 void *afex_rdata
, dma_addr_t afex_rdata_mapping
,
6421 struct bnx2x_func_sp_drv_ops
*drv_iface
)
6423 memset(obj
, 0, sizeof(*obj
));
6425 mutex_init(&obj
->one_pending_mutex
);
6428 obj
->rdata_mapping
= rdata_mapping
;
6429 obj
->afex_rdata
= afex_rdata
;
6430 obj
->afex_rdata_mapping
= afex_rdata_mapping
;
6431 obj
->send_cmd
= bnx2x_func_send_cmd
;
6432 obj
->check_transition
= bnx2x_func_chk_transition
;
6433 obj
->complete_cmd
= bnx2x_func_comp_cmd
;
6434 obj
->wait_comp
= bnx2x_func_wait_comp
;
6436 obj
->drv
= drv_iface
;
6440 * bnx2x_func_state_change - perform Function state change transition
6442 * @bp: device handle
6443 * @params: parameters to perform the transaction
6445 * returns 0 in case of successfully completed transition,
6446 * negative error code in case of failure, positive
6447 * (EBUSY) value if there is a completion to that is
6448 * still pending (possible only if RAMROD_COMP_WAIT is
6449 * not set in params->ramrod_flags for asynchronous
6452 int bnx2x_func_state_change(struct bnx2x
*bp
,
6453 struct bnx2x_func_state_params
*params
)
6455 struct bnx2x_func_sp_obj
*o
= params
->f_obj
;
6457 enum bnx2x_func_cmd cmd
= params
->cmd
;
6458 unsigned long *pending
= &o
->pending
;
6460 mutex_lock(&o
->one_pending_mutex
);
6462 /* Check that the requested transition is legal */
6463 rc
= o
->check_transition(bp
, o
, params
);
6464 if ((rc
== -EBUSY
) &&
6465 (test_bit(RAMROD_RETRY
, ¶ms
->ramrod_flags
))) {
6466 while ((rc
== -EBUSY
) && (--cnt
> 0)) {
6467 mutex_unlock(&o
->one_pending_mutex
);
6469 mutex_lock(&o
->one_pending_mutex
);
6470 rc
= o
->check_transition(bp
, o
, params
);
6473 mutex_unlock(&o
->one_pending_mutex
);
6474 BNX2X_ERR("timeout waiting for previous ramrod completion\n");
6478 mutex_unlock(&o
->one_pending_mutex
);
6482 /* Set "pending" bit */
6483 set_bit(cmd
, pending
);
6485 /* Don't send a command if only driver cleanup was requested */
6486 if (test_bit(RAMROD_DRV_CLR_ONLY
, ¶ms
->ramrod_flags
)) {
6487 bnx2x_func_state_change_comp(bp
, o
, cmd
);
6488 mutex_unlock(&o
->one_pending_mutex
);
6491 rc
= o
->send_cmd(bp
, params
);
6493 mutex_unlock(&o
->one_pending_mutex
);
6496 o
->next_state
= BNX2X_F_STATE_MAX
;
6497 clear_bit(cmd
, pending
);
6498 smp_mb__after_atomic();
6502 if (test_bit(RAMROD_COMP_WAIT
, ¶ms
->ramrod_flags
)) {
6503 rc
= o
->wait_comp(bp
, o
, cmd
);
6511 return !!test_bit(cmd
, pending
);