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[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_sp.h
1 /* bnx2x_sp.h: Qlogic Everest network driver.
2 *
3 * Copyright 2011-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * Unless you and Qlogic execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2, available
10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
11 *
12 * Notwithstanding the above, under no circumstances may you combine this
13 * software in any way with any other Qlogic software provided under a
14 * license other than the GPL, without Qlogic's express prior written
15 * consent.
16 *
17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
18 * Written by: Vladislav Zolotarov
19 *
20 */
21 #ifndef BNX2X_SP_VERBS
22 #define BNX2X_SP_VERBS
23
24 struct bnx2x;
25 struct eth_context;
26
27 /* Bits representing general command's configuration */
28 enum {
29 RAMROD_TX,
30 RAMROD_RX,
31 /* Wait until all pending commands complete */
32 RAMROD_COMP_WAIT,
33 /* Don't send a ramrod, only update a registry */
34 RAMROD_DRV_CLR_ONLY,
35 /* Configure HW according to the current object state */
36 RAMROD_RESTORE,
37 /* Execute the next command now */
38 RAMROD_EXEC,
39 /* Don't add a new command and continue execution of postponed
40 * commands. If not set a new command will be added to the
41 * pending commands list.
42 */
43 RAMROD_CONT,
44 /* If there is another pending ramrod, wait until it finishes and
45 * re-try to submit this one. This flag can be set only in sleepable
46 * context, and should not be set from the context that completes the
47 * ramrods as deadlock will occur.
48 */
49 RAMROD_RETRY,
50 };
51
52 typedef enum {
53 BNX2X_OBJ_TYPE_RX,
54 BNX2X_OBJ_TYPE_TX,
55 BNX2X_OBJ_TYPE_RX_TX,
56 } bnx2x_obj_type;
57
58 /* Public slow path states */
59 enum {
60 BNX2X_FILTER_MAC_PENDING,
61 BNX2X_FILTER_VLAN_PENDING,
62 BNX2X_FILTER_VLAN_MAC_PENDING,
63 BNX2X_FILTER_RX_MODE_PENDING,
64 BNX2X_FILTER_RX_MODE_SCHED,
65 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
66 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
67 BNX2X_FILTER_FCOE_ETH_START_SCHED,
68 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
69 BNX2X_FILTER_MCAST_PENDING,
70 BNX2X_FILTER_MCAST_SCHED,
71 BNX2X_FILTER_RSS_CONF_PENDING,
72 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
73 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
74 };
75
76 struct bnx2x_raw_obj {
77 u8 func_id;
78
79 /* Queue params */
80 u8 cl_id;
81 u32 cid;
82
83 /* Ramrod data buffer params */
84 void *rdata;
85 dma_addr_t rdata_mapping;
86
87 /* Ramrod state params */
88 int state; /* "ramrod is pending" state bit */
89 unsigned long *pstate; /* pointer to state buffer */
90
91 bnx2x_obj_type obj_type;
92
93 int (*wait_comp)(struct bnx2x *bp,
94 struct bnx2x_raw_obj *o);
95
96 bool (*check_pending)(struct bnx2x_raw_obj *o);
97 void (*clear_pending)(struct bnx2x_raw_obj *o);
98 void (*set_pending)(struct bnx2x_raw_obj *o);
99 };
100
101 /************************* VLAN-MAC commands related parameters ***************/
102 struct bnx2x_mac_ramrod_data {
103 u8 mac[ETH_ALEN];
104 u8 is_inner_mac;
105 };
106
107 struct bnx2x_vlan_ramrod_data {
108 u16 vlan;
109 };
110
111 struct bnx2x_vlan_mac_ramrod_data {
112 u8 mac[ETH_ALEN];
113 u8 is_inner_mac;
114 u16 vlan;
115 };
116
117 union bnx2x_classification_ramrod_data {
118 struct bnx2x_mac_ramrod_data mac;
119 struct bnx2x_vlan_ramrod_data vlan;
120 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
121 };
122
123 /* VLAN_MAC commands */
124 enum bnx2x_vlan_mac_cmd {
125 BNX2X_VLAN_MAC_ADD,
126 BNX2X_VLAN_MAC_DEL,
127 BNX2X_VLAN_MAC_MOVE,
128 };
129
130 struct bnx2x_vlan_mac_data {
131 /* Requested command: BNX2X_VLAN_MAC_XX */
132 enum bnx2x_vlan_mac_cmd cmd;
133 /* used to contain the data related vlan_mac_flags bits from
134 * ramrod parameters.
135 */
136 unsigned long vlan_mac_flags;
137
138 /* Needed for MOVE command */
139 struct bnx2x_vlan_mac_obj *target_obj;
140
141 union bnx2x_classification_ramrod_data u;
142 };
143
144 /*************************** Exe Queue obj ************************************/
145 union bnx2x_exe_queue_cmd_data {
146 struct bnx2x_vlan_mac_data vlan_mac;
147
148 struct {
149 /* TODO */
150 } mcast;
151 };
152
153 struct bnx2x_exeq_elem {
154 struct list_head link;
155
156 /* Length of this element in the exe_chunk. */
157 int cmd_len;
158
159 union bnx2x_exe_queue_cmd_data cmd_data;
160 };
161
162 union bnx2x_qable_obj;
163
164 union bnx2x_exeq_comp_elem {
165 union event_ring_elem *elem;
166 };
167
168 struct bnx2x_exe_queue_obj;
169
170 typedef int (*exe_q_validate)(struct bnx2x *bp,
171 union bnx2x_qable_obj *o,
172 struct bnx2x_exeq_elem *elem);
173
174 typedef int (*exe_q_remove)(struct bnx2x *bp,
175 union bnx2x_qable_obj *o,
176 struct bnx2x_exeq_elem *elem);
177
178 /* Return positive if entry was optimized, 0 - if not, negative
179 * in case of an error.
180 */
181 typedef int (*exe_q_optimize)(struct bnx2x *bp,
182 union bnx2x_qable_obj *o,
183 struct bnx2x_exeq_elem *elem);
184 typedef int (*exe_q_execute)(struct bnx2x *bp,
185 union bnx2x_qable_obj *o,
186 struct list_head *exe_chunk,
187 unsigned long *ramrod_flags);
188 typedef struct bnx2x_exeq_elem *
189 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
190 struct bnx2x_exeq_elem *elem);
191
192 struct bnx2x_exe_queue_obj {
193 /* Commands pending for an execution. */
194 struct list_head exe_queue;
195
196 /* Commands pending for an completion. */
197 struct list_head pending_comp;
198
199 spinlock_t lock;
200
201 /* Maximum length of commands' list for one execution */
202 int exe_chunk_len;
203
204 union bnx2x_qable_obj *owner;
205
206 /****** Virtual functions ******/
207 /**
208 * Called before commands execution for commands that are really
209 * going to be executed (after 'optimize').
210 *
211 * Must run under exe_queue->lock
212 */
213 exe_q_validate validate;
214
215 /**
216 * Called before removing pending commands, cleaning allocated
217 * resources (e.g., credits from validate)
218 */
219 exe_q_remove remove;
220
221 /**
222 * This will try to cancel the current pending commands list
223 * considering the new command.
224 *
225 * Returns the number of optimized commands or a negative error code
226 *
227 * Must run under exe_queue->lock
228 */
229 exe_q_optimize optimize;
230
231 /**
232 * Run the next commands chunk (owner specific).
233 */
234 exe_q_execute execute;
235
236 /**
237 * Return the exe_queue element containing the specific command
238 * if any. Otherwise return NULL.
239 */
240 exe_q_get get;
241 };
242 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
243 /*
244 * Element in the VLAN_MAC registry list having all currently configured
245 * rules.
246 */
247 struct bnx2x_vlan_mac_registry_elem {
248 struct list_head link;
249
250 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
251 * Relevant for 57710 and 57711 only. VLANs and MACs share the
252 * same CAM for these chips.
253 */
254 int cam_offset;
255
256 /* Needed for DEL and RESTORE flows */
257 unsigned long vlan_mac_flags;
258
259 union bnx2x_classification_ramrod_data u;
260 };
261
262 /* Bits representing VLAN_MAC commands specific flags */
263 enum {
264 BNX2X_UC_LIST_MAC,
265 BNX2X_ETH_MAC,
266 BNX2X_ISCSI_ETH_MAC,
267 BNX2X_NETQ_ETH_MAC,
268 BNX2X_DONT_CONSUME_CAM_CREDIT,
269 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
270 };
271 /* When looking for matching filters, some flags are not interesting */
272 #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
273 1 << BNX2X_ETH_MAC | \
274 1 << BNX2X_ISCSI_ETH_MAC | \
275 1 << BNX2X_NETQ_ETH_MAC)
276 #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
277 ((flags) & BNX2X_VLAN_MAC_CMP_MASK)
278
279 struct bnx2x_vlan_mac_ramrod_params {
280 /* Object to run the command from */
281 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
282
283 /* General command flags: COMP_WAIT, etc. */
284 unsigned long ramrod_flags;
285
286 /* Command specific configuration request */
287 struct bnx2x_vlan_mac_data user_req;
288 };
289
290 struct bnx2x_vlan_mac_obj {
291 struct bnx2x_raw_obj raw;
292
293 /* Bookkeeping list: will prevent the addition of already existing
294 * entries.
295 */
296 struct list_head head;
297 /* Implement a simple reader/writer lock on the head list.
298 * all these fields should only be accessed under the exe_queue lock
299 */
300 u8 head_reader; /* Num. of readers accessing head list */
301 bool head_exe_request; /* Pending execution request. */
302 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
303
304 /* TODO: Add it's initialization in the init functions */
305 struct bnx2x_exe_queue_obj exe_queue;
306
307 /* MACs credit pool */
308 struct bnx2x_credit_pool_obj *macs_pool;
309
310 /* VLANs credit pool */
311 struct bnx2x_credit_pool_obj *vlans_pool;
312
313 /* RAMROD command to be used */
314 int ramrod_cmd;
315
316 /* copy first n elements onto preallocated buffer
317 *
318 * @param n number of elements to get
319 * @param buf buffer preallocated by caller into which elements
320 * will be copied. Note elements are 4-byte aligned
321 * so buffer size must be able to accommodate the
322 * aligned elements.
323 *
324 * @return number of copied bytes
325 */
326 int (*get_n_elements)(struct bnx2x *bp,
327 struct bnx2x_vlan_mac_obj *o, int n, u8 *base,
328 u8 stride, u8 size);
329
330 /**
331 * Checks if ADD-ramrod with the given params may be performed.
332 *
333 * @return zero if the element may be added
334 */
335
336 int (*check_add)(struct bnx2x *bp,
337 struct bnx2x_vlan_mac_obj *o,
338 union bnx2x_classification_ramrod_data *data);
339
340 /**
341 * Checks if DEL-ramrod with the given params may be performed.
342 *
343 * @return true if the element may be deleted
344 */
345 struct bnx2x_vlan_mac_registry_elem *
346 (*check_del)(struct bnx2x *bp,
347 struct bnx2x_vlan_mac_obj *o,
348 union bnx2x_classification_ramrod_data *data);
349
350 /**
351 * Checks if DEL-ramrod with the given params may be performed.
352 *
353 * @return true if the element may be deleted
354 */
355 bool (*check_move)(struct bnx2x *bp,
356 struct bnx2x_vlan_mac_obj *src_o,
357 struct bnx2x_vlan_mac_obj *dst_o,
358 union bnx2x_classification_ramrod_data *data);
359
360 /**
361 * Update the relevant credit object(s) (consume/return
362 * correspondingly).
363 */
364 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
365 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
366 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
367 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
368
369 /**
370 * Configures one rule in the ramrod data buffer.
371 */
372 void (*set_one_rule)(struct bnx2x *bp,
373 struct bnx2x_vlan_mac_obj *o,
374 struct bnx2x_exeq_elem *elem, int rule_idx,
375 int cam_offset);
376
377 /**
378 * Delete all configured elements having the given
379 * vlan_mac_flags specification. Assumes no pending for
380 * execution commands. Will schedule all all currently
381 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
382 * specification for deletion and will use the given
383 * ramrod_flags for the last DEL operation.
384 *
385 * @param bp
386 * @param o
387 * @param ramrod_flags RAMROD_XX flags
388 *
389 * @return 0 if the last operation has completed successfully
390 * and there are no more elements left, positive value
391 * if there are pending for completion commands,
392 * negative value in case of failure.
393 */
394 int (*delete_all)(struct bnx2x *bp,
395 struct bnx2x_vlan_mac_obj *o,
396 unsigned long *vlan_mac_flags,
397 unsigned long *ramrod_flags);
398
399 /**
400 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
401 * configured elements list.
402 *
403 * @param bp
404 * @param p Command parameters (RAMROD_COMP_WAIT bit in
405 * ramrod_flags is only taken into an account)
406 * @param ppos a pointer to the cookie that should be given back in the
407 * next call to make function handle the next element. If
408 * *ppos is set to NULL it will restart the iterator.
409 * If returned *ppos == NULL this means that the last
410 * element has been handled.
411 *
412 * @return int
413 */
414 int (*restore)(struct bnx2x *bp,
415 struct bnx2x_vlan_mac_ramrod_params *p,
416 struct bnx2x_vlan_mac_registry_elem **ppos);
417
418 /**
419 * Should be called on a completion arrival.
420 *
421 * @param bp
422 * @param o
423 * @param cqe Completion element we are handling
424 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
425 * pending commands will be executed.
426 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
427 * may also be set if needed.
428 *
429 * @return 0 if there are neither pending nor waiting for
430 * completion commands. Positive value if there are
431 * pending for execution or for completion commands.
432 * Negative value in case of an error (including an
433 * error in the cqe).
434 */
435 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
436 union event_ring_elem *cqe,
437 unsigned long *ramrod_flags);
438
439 /**
440 * Wait for completion of all commands. Don't schedule new ones,
441 * just wait. It assumes that the completion code will schedule
442 * for new commands.
443 */
444 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
445 };
446
447 enum {
448 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
449 BNX2X_LLH_CAM_ETH_LINE,
450 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
451 };
452
453 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
454
455 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
456 * a bnx2x_rx_mode_ramrod_params.
457 */
458 enum {
459 BNX2X_RX_MODE_FCOE_ETH,
460 BNX2X_RX_MODE_ISCSI_ETH,
461 };
462
463 enum {
464 BNX2X_ACCEPT_UNICAST,
465 BNX2X_ACCEPT_MULTICAST,
466 BNX2X_ACCEPT_ALL_UNICAST,
467 BNX2X_ACCEPT_ALL_MULTICAST,
468 BNX2X_ACCEPT_BROADCAST,
469 BNX2X_ACCEPT_UNMATCHED,
470 BNX2X_ACCEPT_ANY_VLAN
471 };
472
473 struct bnx2x_rx_mode_ramrod_params {
474 struct bnx2x_rx_mode_obj *rx_mode_obj;
475 unsigned long *pstate;
476 int state;
477 u8 cl_id;
478 u32 cid;
479 u8 func_id;
480 unsigned long ramrod_flags;
481 unsigned long rx_mode_flags;
482
483 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
484 * a tstorm_eth_mac_filter_config (e1x).
485 */
486 void *rdata;
487 dma_addr_t rdata_mapping;
488
489 /* Rx mode settings */
490 unsigned long rx_accept_flags;
491
492 /* internal switching settings */
493 unsigned long tx_accept_flags;
494 };
495
496 struct bnx2x_rx_mode_obj {
497 int (*config_rx_mode)(struct bnx2x *bp,
498 struct bnx2x_rx_mode_ramrod_params *p);
499
500 int (*wait_comp)(struct bnx2x *bp,
501 struct bnx2x_rx_mode_ramrod_params *p);
502 };
503
504 /********************** Set multicast group ***********************************/
505
506 struct bnx2x_mcast_list_elem {
507 struct list_head link;
508 u8 *mac;
509 };
510
511 union bnx2x_mcast_config_data {
512 u8 *mac;
513 u8 bin; /* used in a RESTORE flow */
514 };
515
516 struct bnx2x_mcast_ramrod_params {
517 struct bnx2x_mcast_obj *mcast_obj;
518
519 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
520 unsigned long ramrod_flags;
521
522 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
523 /** TODO:
524 * - rename it to macs_num.
525 * - Add a new command type for handling pending commands
526 * (remove "zero semantics").
527 *
528 * Length of mcast_list. If zero and ADD_CONT command - post
529 * pending commands.
530 */
531 int mcast_list_len;
532 };
533
534 enum bnx2x_mcast_cmd {
535 BNX2X_MCAST_CMD_ADD,
536 BNX2X_MCAST_CMD_CONT,
537 BNX2X_MCAST_CMD_DEL,
538 BNX2X_MCAST_CMD_RESTORE,
539
540 /* Following this, multicast configuration should equal to approx
541 * the set of MACs provided [i.e., remove all else].
542 * The two sub-commands are used internally to decide whether a given
543 * bin is to be added or removed
544 */
545 BNX2X_MCAST_CMD_SET,
546 BNX2X_MCAST_CMD_SET_ADD,
547 BNX2X_MCAST_CMD_SET_DEL,
548 };
549
550 struct bnx2x_mcast_obj {
551 struct bnx2x_raw_obj raw;
552
553 union {
554 struct {
555 #define BNX2X_MCAST_BINS_NUM 256
556 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
557 u64 vec[BNX2X_MCAST_VEC_SZ];
558
559 /** Number of BINs to clear. Should be updated
560 * immediately when a command arrives in order to
561 * properly create DEL commands.
562 */
563 int num_bins_set;
564 } aprox_match;
565
566 struct {
567 struct list_head macs;
568 int num_macs_set;
569 } exact_match;
570 } registry;
571
572 /* Pending commands */
573 struct list_head pending_cmds_head;
574
575 /* A state that is set in raw.pstate, when there are pending commands */
576 int sched_state;
577
578 /* Maximal number of mcast MACs configured in one command */
579 int max_cmd_len;
580
581 /* Total number of currently pending MACs to configure: both
582 * in the pending commands list and in the current command.
583 */
584 int total_pending_num;
585
586 u8 engine_id;
587
588 /**
589 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
590 */
591 int (*config_mcast)(struct bnx2x *bp,
592 struct bnx2x_mcast_ramrod_params *p,
593 enum bnx2x_mcast_cmd cmd);
594
595 /**
596 * Fills the ramrod data during the RESTORE flow.
597 *
598 * @param bp
599 * @param o
600 * @param start_idx Registry index to start from
601 * @param rdata_idx Index in the ramrod data to start from
602 *
603 * @return -1 if we handled the whole registry or index of the last
604 * handled registry element.
605 */
606 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
607 int start_bin, int *rdata_idx);
608
609 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
610 struct bnx2x_mcast_ramrod_params *p,
611 enum bnx2x_mcast_cmd cmd);
612
613 void (*set_one_rule)(struct bnx2x *bp,
614 struct bnx2x_mcast_obj *o, int idx,
615 union bnx2x_mcast_config_data *cfg_data,
616 enum bnx2x_mcast_cmd cmd);
617
618 /** Checks if there are more mcast MACs to be set or a previous
619 * command is still pending.
620 */
621 bool (*check_pending)(struct bnx2x_mcast_obj *o);
622
623 /**
624 * Set/Clear/Check SCHEDULED state of the object
625 */
626 void (*set_sched)(struct bnx2x_mcast_obj *o);
627 void (*clear_sched)(struct bnx2x_mcast_obj *o);
628 bool (*check_sched)(struct bnx2x_mcast_obj *o);
629
630 /* Wait until all pending commands complete */
631 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
632
633 /**
634 * Handle the internal object counters needed for proper
635 * commands handling. Checks that the provided parameters are
636 * feasible.
637 */
638 int (*validate)(struct bnx2x *bp,
639 struct bnx2x_mcast_ramrod_params *p,
640 enum bnx2x_mcast_cmd cmd);
641
642 /**
643 * Restore the values of internal counters in case of a failure.
644 */
645 void (*revert)(struct bnx2x *bp,
646 struct bnx2x_mcast_ramrod_params *p,
647 int old_num_bins,
648 enum bnx2x_mcast_cmd cmd);
649
650 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
651 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
652 };
653
654 /*************************** Credit handling **********************************/
655 struct bnx2x_credit_pool_obj {
656
657 /* Current amount of credit in the pool */
658 atomic_t credit;
659
660 /* Maximum allowed credit. put() will check against it. */
661 int pool_sz;
662
663 /* Allocate a pool table statically.
664 *
665 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
666 *
667 * The set bit in the table will mean that the entry is available.
668 */
669 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
670 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
671
672 /* Base pool offset (initialized differently */
673 int base_pool_offset;
674
675 /**
676 * Get the next free pool entry.
677 *
678 * @return true if there was a free entry in the pool
679 */
680 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
681
682 /**
683 * Return the entry back to the pool.
684 *
685 * @return true if entry is legal and has been successfully
686 * returned to the pool.
687 */
688 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
689
690 /**
691 * Get the requested amount of credit from the pool.
692 *
693 * @param cnt Amount of requested credit
694 * @return true if the operation is successful
695 */
696 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
697
698 /**
699 * Returns the credit to the pool.
700 *
701 * @param cnt Amount of credit to return
702 * @return true if the operation is successful
703 */
704 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
705
706 /**
707 * Reads the current amount of credit.
708 */
709 int (*check)(struct bnx2x_credit_pool_obj *o);
710 };
711
712 /*************************** RSS configuration ********************************/
713 enum {
714 /* RSS_MODE bits are mutually exclusive */
715 BNX2X_RSS_MODE_DISABLED,
716 BNX2X_RSS_MODE_REGULAR,
717
718 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
719
720 BNX2X_RSS_IPV4,
721 BNX2X_RSS_IPV4_TCP,
722 BNX2X_RSS_IPV4_UDP,
723 BNX2X_RSS_IPV6,
724 BNX2X_RSS_IPV6_TCP,
725 BNX2X_RSS_IPV6_UDP,
726
727 BNX2X_RSS_IPV4_VXLAN,
728 BNX2X_RSS_IPV6_VXLAN,
729 BNX2X_RSS_TUNN_INNER_HDRS,
730 };
731
732 struct bnx2x_config_rss_params {
733 struct bnx2x_rss_config_obj *rss_obj;
734
735 /* may have RAMROD_COMP_WAIT set only */
736 unsigned long ramrod_flags;
737
738 /* BNX2X_RSS_X bits */
739 unsigned long rss_flags;
740
741 /* Number hash bits to take into an account */
742 u8 rss_result_mask;
743
744 /* Indirection table */
745 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
746
747 /* RSS hash values */
748 u32 rss_key[10];
749
750 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
751 u16 toe_rss_bitmap;
752 };
753
754 struct bnx2x_rss_config_obj {
755 struct bnx2x_raw_obj raw;
756
757 /* RSS engine to use */
758 u8 engine_id;
759
760 /* Last configured indirection table */
761 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
762
763 /* flags for enabling 4-tupple hash on UDP */
764 u8 udp_rss_v4;
765 u8 udp_rss_v6;
766
767 int (*config_rss)(struct bnx2x *bp,
768 struct bnx2x_config_rss_params *p);
769 };
770
771 /*********************** Queue state update ***********************************/
772
773 /* UPDATE command options */
774 enum {
775 BNX2X_Q_UPDATE_IN_VLAN_REM,
776 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
777 BNX2X_Q_UPDATE_OUT_VLAN_REM,
778 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
779 BNX2X_Q_UPDATE_ANTI_SPOOF,
780 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
781 BNX2X_Q_UPDATE_ACTIVATE,
782 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
783 BNX2X_Q_UPDATE_DEF_VLAN_EN,
784 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
785 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
786 BNX2X_Q_UPDATE_SILENT_VLAN_REM,
787 BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
788 BNX2X_Q_UPDATE_TX_SWITCHING,
789 BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
790 BNX2X_Q_UPDATE_PTP_PKTS,
791 };
792
793 /* Allowed Queue states */
794 enum bnx2x_q_state {
795 BNX2X_Q_STATE_RESET,
796 BNX2X_Q_STATE_INITIALIZED,
797 BNX2X_Q_STATE_ACTIVE,
798 BNX2X_Q_STATE_MULTI_COS,
799 BNX2X_Q_STATE_MCOS_TERMINATED,
800 BNX2X_Q_STATE_INACTIVE,
801 BNX2X_Q_STATE_STOPPED,
802 BNX2X_Q_STATE_TERMINATED,
803 BNX2X_Q_STATE_FLRED,
804 BNX2X_Q_STATE_MAX,
805 };
806
807 /* Allowed Queue states */
808 enum bnx2x_q_logical_state {
809 BNX2X_Q_LOGICAL_STATE_ACTIVE,
810 BNX2X_Q_LOGICAL_STATE_STOPPED,
811 };
812
813 /* Allowed commands */
814 enum bnx2x_queue_cmd {
815 BNX2X_Q_CMD_INIT,
816 BNX2X_Q_CMD_SETUP,
817 BNX2X_Q_CMD_SETUP_TX_ONLY,
818 BNX2X_Q_CMD_DEACTIVATE,
819 BNX2X_Q_CMD_ACTIVATE,
820 BNX2X_Q_CMD_UPDATE,
821 BNX2X_Q_CMD_UPDATE_TPA,
822 BNX2X_Q_CMD_HALT,
823 BNX2X_Q_CMD_CFC_DEL,
824 BNX2X_Q_CMD_TERMINATE,
825 BNX2X_Q_CMD_EMPTY,
826 BNX2X_Q_CMD_MAX,
827 };
828
829 /* queue SETUP + INIT flags */
830 enum {
831 BNX2X_Q_FLG_TPA,
832 BNX2X_Q_FLG_TPA_IPV6,
833 BNX2X_Q_FLG_TPA_GRO,
834 BNX2X_Q_FLG_STATS,
835 BNX2X_Q_FLG_ZERO_STATS,
836 BNX2X_Q_FLG_ACTIVE,
837 BNX2X_Q_FLG_OV,
838 BNX2X_Q_FLG_VLAN,
839 BNX2X_Q_FLG_COS,
840 BNX2X_Q_FLG_HC,
841 BNX2X_Q_FLG_HC_EN,
842 BNX2X_Q_FLG_DHC,
843 BNX2X_Q_FLG_FCOE,
844 BNX2X_Q_FLG_LEADING_RSS,
845 BNX2X_Q_FLG_MCAST,
846 BNX2X_Q_FLG_DEF_VLAN,
847 BNX2X_Q_FLG_TX_SWITCH,
848 BNX2X_Q_FLG_TX_SEC,
849 BNX2X_Q_FLG_ANTI_SPOOF,
850 BNX2X_Q_FLG_SILENT_VLAN_REM,
851 BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
852 BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
853 BNX2X_Q_FLG_PCSUM_ON_PKT,
854 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
855 };
856
857 /* Queue type options: queue type may be a combination of below. */
858 enum bnx2x_q_type {
859 /** TODO: Consider moving both these flags into the init()
860 * ramrod params.
861 */
862 BNX2X_Q_TYPE_HAS_RX,
863 BNX2X_Q_TYPE_HAS_TX,
864 };
865
866 #define BNX2X_PRIMARY_CID_INDEX 0
867 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */
868 #define BNX2X_MULTI_TX_COS_E2_E3A0 2
869 #define BNX2X_MULTI_TX_COS_E3B0 3
870 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */
871
872 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
873 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends
874 * timesync-related ramrods must not use this DMAE command ID.
875 */
876 #define FW_DMAE_CMD_ID 6
877
878 struct bnx2x_queue_init_params {
879 struct {
880 unsigned long flags;
881 u16 hc_rate;
882 u8 fw_sb_id;
883 u8 sb_cq_index;
884 } tx;
885
886 struct {
887 unsigned long flags;
888 u16 hc_rate;
889 u8 fw_sb_id;
890 u8 sb_cq_index;
891 } rx;
892
893 /* CID context in the host memory */
894 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
895
896 /* maximum number of cos supported by hardware */
897 u8 max_cos;
898 };
899
900 struct bnx2x_queue_terminate_params {
901 /* index within the tx_only cids of this queue object */
902 u8 cid_index;
903 };
904
905 struct bnx2x_queue_cfc_del_params {
906 /* index within the tx_only cids of this queue object */
907 u8 cid_index;
908 };
909
910 struct bnx2x_queue_update_params {
911 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */
912 u16 def_vlan;
913 u16 silent_removal_value;
914 u16 silent_removal_mask;
915 /* index within the tx_only cids of this queue object */
916 u8 cid_index;
917 };
918
919 struct bnx2x_queue_update_tpa_params {
920 dma_addr_t sge_map;
921 u8 update_ipv4;
922 u8 update_ipv6;
923 u8 max_tpa_queues;
924 u8 max_sges_pkt;
925 u8 complete_on_both_clients;
926 u8 dont_verify_thr;
927 u8 tpa_mode;
928 u8 _pad;
929
930 u16 sge_buff_sz;
931 u16 max_agg_sz;
932
933 u16 sge_pause_thr_low;
934 u16 sge_pause_thr_high;
935 };
936
937 struct rxq_pause_params {
938 u16 bd_th_lo;
939 u16 bd_th_hi;
940 u16 rcq_th_lo;
941 u16 rcq_th_hi;
942 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
943 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
944 u16 pri_map;
945 };
946
947 /* general */
948 struct bnx2x_general_setup_params {
949 /* valid iff BNX2X_Q_FLG_STATS */
950 u8 stat_id;
951
952 u8 spcl_id;
953 u16 mtu;
954 u8 cos;
955
956 u8 fp_hsi;
957 };
958
959 struct bnx2x_rxq_setup_params {
960 /* dma */
961 dma_addr_t dscr_map;
962 dma_addr_t sge_map;
963 dma_addr_t rcq_map;
964 dma_addr_t rcq_np_map;
965
966 u16 drop_flags;
967 u16 buf_sz;
968 u8 fw_sb_id;
969 u8 cl_qzone_id;
970
971 /* valid iff BNX2X_Q_FLG_TPA */
972 u16 tpa_agg_sz;
973 u16 sge_buf_sz;
974 u8 max_sges_pkt;
975 u8 max_tpa_queues;
976 u8 rss_engine_id;
977
978 /* valid iff BNX2X_Q_FLG_MCAST */
979 u8 mcast_engine_id;
980
981 u8 cache_line_log;
982
983 u8 sb_cq_index;
984
985 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
986 u16 silent_removal_value;
987 u16 silent_removal_mask;
988 };
989
990 struct bnx2x_txq_setup_params {
991 /* dma */
992 dma_addr_t dscr_map;
993
994 u8 fw_sb_id;
995 u8 sb_cq_index;
996 u8 cos; /* valid iff BNX2X_Q_FLG_COS */
997 u16 traffic_type;
998 /* equals to the leading rss client id, used for TX classification*/
999 u8 tss_leading_cl_id;
1000
1001 /* valid iff BNX2X_Q_FLG_DEF_VLAN */
1002 u16 default_vlan;
1003 };
1004
1005 struct bnx2x_queue_setup_params {
1006 struct bnx2x_general_setup_params gen_params;
1007 struct bnx2x_txq_setup_params txq_params;
1008 struct bnx2x_rxq_setup_params rxq_params;
1009 struct rxq_pause_params pause_params;
1010 unsigned long flags;
1011 };
1012
1013 struct bnx2x_queue_setup_tx_only_params {
1014 struct bnx2x_general_setup_params gen_params;
1015 struct bnx2x_txq_setup_params txq_params;
1016 unsigned long flags;
1017 /* index within the tx_only cids of this queue object */
1018 u8 cid_index;
1019 };
1020
1021 struct bnx2x_queue_state_params {
1022 struct bnx2x_queue_sp_obj *q_obj;
1023
1024 /* Current command */
1025 enum bnx2x_queue_cmd cmd;
1026
1027 /* may have RAMROD_COMP_WAIT set only */
1028 unsigned long ramrod_flags;
1029
1030 /* Params according to the current command */
1031 union {
1032 struct bnx2x_queue_update_params update;
1033 struct bnx2x_queue_update_tpa_params update_tpa;
1034 struct bnx2x_queue_setup_params setup;
1035 struct bnx2x_queue_init_params init;
1036 struct bnx2x_queue_setup_tx_only_params tx_only;
1037 struct bnx2x_queue_terminate_params terminate;
1038 struct bnx2x_queue_cfc_del_params cfc_del;
1039 } params;
1040 };
1041
1042 struct bnx2x_viflist_params {
1043 u8 echo_res;
1044 u8 func_bit_map_res;
1045 };
1046
1047 struct bnx2x_queue_sp_obj {
1048 u32 cids[BNX2X_MULTI_TX_COS];
1049 u8 cl_id;
1050 u8 func_id;
1051
1052 /* number of traffic classes supported by queue.
1053 * The primary connection of the queue supports the first traffic
1054 * class. Any further traffic class is supported by a tx-only
1055 * connection.
1056 *
1057 * Therefore max_cos is also a number of valid entries in the cids
1058 * array.
1059 */
1060 u8 max_cos;
1061 u8 num_tx_only, next_tx_only;
1062
1063 enum bnx2x_q_state state, next_state;
1064
1065 /* bits from enum bnx2x_q_type */
1066 unsigned long type;
1067
1068 /* BNX2X_Q_CMD_XX bits. This object implements "one
1069 * pending" paradigm but for debug and tracing purposes it's
1070 * more convenient to have different bits for different
1071 * commands.
1072 */
1073 unsigned long pending;
1074
1075 /* Buffer to use as a ramrod data and its mapping */
1076 void *rdata;
1077 dma_addr_t rdata_mapping;
1078
1079 /**
1080 * Performs one state change according to the given parameters.
1081 *
1082 * @return 0 in case of success and negative value otherwise.
1083 */
1084 int (*send_cmd)(struct bnx2x *bp,
1085 struct bnx2x_queue_state_params *params);
1086
1087 /**
1088 * Sets the pending bit according to the requested transition.
1089 */
1090 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1091 struct bnx2x_queue_state_params *params);
1092
1093 /**
1094 * Checks that the requested state transition is legal.
1095 */
1096 int (*check_transition)(struct bnx2x *bp,
1097 struct bnx2x_queue_sp_obj *o,
1098 struct bnx2x_queue_state_params *params);
1099
1100 /**
1101 * Completes the pending command.
1102 */
1103 int (*complete_cmd)(struct bnx2x *bp,
1104 struct bnx2x_queue_sp_obj *o,
1105 enum bnx2x_queue_cmd);
1106
1107 int (*wait_comp)(struct bnx2x *bp,
1108 struct bnx2x_queue_sp_obj *o,
1109 enum bnx2x_queue_cmd cmd);
1110 };
1111
1112 /********************** Function state update *********************************/
1113
1114 /* UPDATE command options */
1115 enum {
1116 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1117 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
1118 BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
1119 BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
1120 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
1121 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
1122 BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1123 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
1124 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
1125 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
1126 BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
1127 };
1128
1129 /* Allowed Function states */
1130 enum bnx2x_func_state {
1131 BNX2X_F_STATE_RESET,
1132 BNX2X_F_STATE_INITIALIZED,
1133 BNX2X_F_STATE_STARTED,
1134 BNX2X_F_STATE_TX_STOPPED,
1135 BNX2X_F_STATE_MAX,
1136 };
1137
1138 /* Allowed Function commands */
1139 enum bnx2x_func_cmd {
1140 BNX2X_F_CMD_HW_INIT,
1141 BNX2X_F_CMD_START,
1142 BNX2X_F_CMD_STOP,
1143 BNX2X_F_CMD_HW_RESET,
1144 BNX2X_F_CMD_AFEX_UPDATE,
1145 BNX2X_F_CMD_AFEX_VIFLISTS,
1146 BNX2X_F_CMD_TX_STOP,
1147 BNX2X_F_CMD_TX_START,
1148 BNX2X_F_CMD_SWITCH_UPDATE,
1149 BNX2X_F_CMD_SET_TIMESYNC,
1150 BNX2X_F_CMD_MAX,
1151 };
1152
1153 struct bnx2x_func_hw_init_params {
1154 /* A load phase returned by MCP.
1155 *
1156 * May be:
1157 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1158 * FW_MSG_CODE_DRV_LOAD_COMMON
1159 * FW_MSG_CODE_DRV_LOAD_PORT
1160 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1161 */
1162 u32 load_phase;
1163 };
1164
1165 struct bnx2x_func_hw_reset_params {
1166 /* A load phase returned by MCP.
1167 *
1168 * May be:
1169 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1170 * FW_MSG_CODE_DRV_LOAD_COMMON
1171 * FW_MSG_CODE_DRV_LOAD_PORT
1172 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1173 */
1174 u32 reset_phase;
1175 };
1176
1177 struct bnx2x_func_start_params {
1178 /* Multi Function mode:
1179 * - Single Function
1180 * - Switch Dependent
1181 * - Switch Independent
1182 */
1183 u16 mf_mode;
1184
1185 /* Switch Dependent mode outer VLAN tag */
1186 u16 sd_vlan_tag;
1187
1188 /* Function cos mode */
1189 u8 network_cos_mode;
1190
1191 /* UDP dest port for VXLAN */
1192 u16 vxlan_dst_port;
1193
1194 /* UDP dest port for Geneve */
1195 u16 geneve_dst_port;
1196
1197 /* Enable inner Rx classifications for L2GRE packets */
1198 u8 inner_clss_l2gre;
1199
1200 /* Enable inner Rx classifications for L2-Geneve packets */
1201 u8 inner_clss_l2geneve;
1202
1203 /* Enable inner Rx classification for vxlan packets */
1204 u8 inner_clss_vxlan;
1205
1206 /* Enable RSS according to inner header */
1207 u8 inner_rss;
1208
1209 /* Allows accepting of packets failing MF classification, possibly
1210 * only matching a given ethertype
1211 */
1212 u8 class_fail;
1213 u16 class_fail_ethtype;
1214
1215 /* Override priority of output packets */
1216 u8 sd_vlan_force_pri;
1217 u8 sd_vlan_force_pri_val;
1218
1219 /* Replace vlan's ethertype */
1220 u16 sd_vlan_eth_type;
1221
1222 /* Prevent inner vlans from being added by FW */
1223 u8 no_added_tags;
1224
1225 /* Inner-to-Outer vlan priority mapping */
1226 u8 c2s_pri[MAX_VLAN_PRIORITIES];
1227 u8 c2s_pri_default;
1228 u8 c2s_pri_valid;
1229 };
1230
1231 struct bnx2x_func_switch_update_params {
1232 unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
1233 u16 vlan;
1234 u16 vlan_eth_type;
1235 u8 vlan_force_prio;
1236 u16 vxlan_dst_port;
1237 u16 geneve_dst_port;
1238 };
1239
1240 struct bnx2x_func_afex_update_params {
1241 u16 vif_id;
1242 u16 afex_default_vlan;
1243 u8 allowed_priorities;
1244 };
1245
1246 struct bnx2x_func_afex_viflists_params {
1247 u16 vif_list_index;
1248 u8 func_bit_map;
1249 u8 afex_vif_list_command;
1250 u8 func_to_clear;
1251 };
1252
1253 struct bnx2x_func_tx_start_params {
1254 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1255 u8 dcb_enabled;
1256 u8 dcb_version;
1257 u8 dont_add_pri_0_en;
1258 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
1259 };
1260
1261 struct bnx2x_func_set_timesync_params {
1262 /* Reset, set or keep the current drift value */
1263 u8 drift_adjust_cmd;
1264
1265 /* Dec, inc or keep the current offset */
1266 u8 offset_cmd;
1267
1268 /* Drift value direction */
1269 u8 add_sub_drift_adjust_value;
1270
1271 /* Drift, period and offset values to be used according to the commands
1272 * above.
1273 */
1274 u8 drift_adjust_value;
1275 u32 drift_adjust_period;
1276 u64 offset_delta;
1277 };
1278
1279 struct bnx2x_func_state_params {
1280 struct bnx2x_func_sp_obj *f_obj;
1281
1282 /* Current command */
1283 enum bnx2x_func_cmd cmd;
1284
1285 /* may have RAMROD_COMP_WAIT set only */
1286 unsigned long ramrod_flags;
1287
1288 /* Params according to the current command */
1289 union {
1290 struct bnx2x_func_hw_init_params hw_init;
1291 struct bnx2x_func_hw_reset_params hw_reset;
1292 struct bnx2x_func_start_params start;
1293 struct bnx2x_func_switch_update_params switch_update;
1294 struct bnx2x_func_afex_update_params afex_update;
1295 struct bnx2x_func_afex_viflists_params afex_viflists;
1296 struct bnx2x_func_tx_start_params tx_start;
1297 struct bnx2x_func_set_timesync_params set_timesync;
1298 } params;
1299 };
1300
1301 struct bnx2x_func_sp_drv_ops {
1302 /* Init tool + runtime initialization:
1303 * - Common Chip
1304 * - Common (per Path)
1305 * - Port
1306 * - Function phases
1307 */
1308 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1309 int (*init_hw_cmn)(struct bnx2x *bp);
1310 int (*init_hw_port)(struct bnx2x *bp);
1311 int (*init_hw_func)(struct bnx2x *bp);
1312
1313 /* Reset Function HW: Common, Port, Function phases. */
1314 void (*reset_hw_cmn)(struct bnx2x *bp);
1315 void (*reset_hw_port)(struct bnx2x *bp);
1316 void (*reset_hw_func)(struct bnx2x *bp);
1317
1318 /* Init/Free GUNZIP resources */
1319 int (*gunzip_init)(struct bnx2x *bp);
1320 void (*gunzip_end)(struct bnx2x *bp);
1321
1322 /* Prepare/Release FW resources */
1323 int (*init_fw)(struct bnx2x *bp);
1324 void (*release_fw)(struct bnx2x *bp);
1325 };
1326
1327 struct bnx2x_func_sp_obj {
1328 enum bnx2x_func_state state, next_state;
1329
1330 /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1331 * pending" paradigm but for debug and tracing purposes it's
1332 * more convenient to have different bits for different
1333 * commands.
1334 */
1335 unsigned long pending;
1336
1337 /* Buffer to use as a ramrod data and its mapping */
1338 void *rdata;
1339 dma_addr_t rdata_mapping;
1340
1341 /* Buffer to use as a afex ramrod data and its mapping.
1342 * This can't be same rdata as above because afex ramrod requests
1343 * can arrive to the object in parallel to other ramrod requests.
1344 */
1345 void *afex_rdata;
1346 dma_addr_t afex_rdata_mapping;
1347
1348 /* this mutex validates that when pending flag is taken, the next
1349 * ramrod to be sent will be the one set the pending bit
1350 */
1351 struct mutex one_pending_mutex;
1352
1353 /* Driver interface */
1354 struct bnx2x_func_sp_drv_ops *drv;
1355
1356 /**
1357 * Performs one state change according to the given parameters.
1358 *
1359 * @return 0 in case of success and negative value otherwise.
1360 */
1361 int (*send_cmd)(struct bnx2x *bp,
1362 struct bnx2x_func_state_params *params);
1363
1364 /**
1365 * Checks that the requested state transition is legal.
1366 */
1367 int (*check_transition)(struct bnx2x *bp,
1368 struct bnx2x_func_sp_obj *o,
1369 struct bnx2x_func_state_params *params);
1370
1371 /**
1372 * Completes the pending command.
1373 */
1374 int (*complete_cmd)(struct bnx2x *bp,
1375 struct bnx2x_func_sp_obj *o,
1376 enum bnx2x_func_cmd cmd);
1377
1378 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1379 enum bnx2x_func_cmd cmd);
1380 };
1381
1382 /********************** Interfaces ********************************************/
1383 /* Queueable objects set */
1384 union bnx2x_qable_obj {
1385 struct bnx2x_vlan_mac_obj vlan_mac;
1386 };
1387 /************** Function state update *********/
1388 void bnx2x_init_func_obj(struct bnx2x *bp,
1389 struct bnx2x_func_sp_obj *obj,
1390 void *rdata, dma_addr_t rdata_mapping,
1391 void *afex_rdata, dma_addr_t afex_rdata_mapping,
1392 struct bnx2x_func_sp_drv_ops *drv_iface);
1393
1394 int bnx2x_func_state_change(struct bnx2x *bp,
1395 struct bnx2x_func_state_params *params);
1396
1397 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1398 struct bnx2x_func_sp_obj *o);
1399 /******************* Queue State **************/
1400 void bnx2x_init_queue_obj(struct bnx2x *bp,
1401 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1402 u8 cid_cnt, u8 func_id, void *rdata,
1403 dma_addr_t rdata_mapping, unsigned long type);
1404
1405 int bnx2x_queue_state_change(struct bnx2x *bp,
1406 struct bnx2x_queue_state_params *params);
1407
1408 int bnx2x_get_q_logical_state(struct bnx2x *bp,
1409 struct bnx2x_queue_sp_obj *obj);
1410
1411 /********************* VLAN-MAC ****************/
1412 void bnx2x_init_mac_obj(struct bnx2x *bp,
1413 struct bnx2x_vlan_mac_obj *mac_obj,
1414 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1415 dma_addr_t rdata_mapping, int state,
1416 unsigned long *pstate, bnx2x_obj_type type,
1417 struct bnx2x_credit_pool_obj *macs_pool);
1418
1419 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1420 struct bnx2x_vlan_mac_obj *vlan_obj,
1421 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1422 dma_addr_t rdata_mapping, int state,
1423 unsigned long *pstate, bnx2x_obj_type type,
1424 struct bnx2x_credit_pool_obj *vlans_pool);
1425
1426 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1427 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1428 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1429 dma_addr_t rdata_mapping, int state,
1430 unsigned long *pstate, bnx2x_obj_type type,
1431 struct bnx2x_credit_pool_obj *macs_pool,
1432 struct bnx2x_credit_pool_obj *vlans_pool);
1433
1434 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
1435 struct bnx2x_vlan_mac_obj *o);
1436 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
1437 struct bnx2x_vlan_mac_obj *o);
1438 int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp,
1439 struct bnx2x_vlan_mac_obj *o);
1440 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1441 struct bnx2x_vlan_mac_ramrod_params *p);
1442
1443 int bnx2x_vlan_mac_move(struct bnx2x *bp,
1444 struct bnx2x_vlan_mac_ramrod_params *p,
1445 struct bnx2x_vlan_mac_obj *dest_o);
1446
1447 /********************* RX MODE ****************/
1448
1449 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1450 struct bnx2x_rx_mode_obj *o);
1451
1452 /**
1453 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1454 *
1455 * @p: Command parameters
1456 *
1457 * Return: 0 - if operation was successful and there is no pending completions,
1458 * positive number - if there are pending completions,
1459 * negative - if there were errors
1460 */
1461 int bnx2x_config_rx_mode(struct bnx2x *bp,
1462 struct bnx2x_rx_mode_ramrod_params *p);
1463
1464 /****************** MULTICASTS ****************/
1465
1466 void bnx2x_init_mcast_obj(struct bnx2x *bp,
1467 struct bnx2x_mcast_obj *mcast_obj,
1468 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1469 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1470 int state, unsigned long *pstate,
1471 bnx2x_obj_type type);
1472
1473 /**
1474 * bnx2x_config_mcast - Configure multicast MACs list.
1475 *
1476 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1477 *
1478 * May configure a new list
1479 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1480 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1481 * configuration, continue to execute the pending commands
1482 * (BNX2X_MCAST_CMD_CONT).
1483 *
1484 * If previous command is still pending or if number of MACs to
1485 * configure is more that maximum number of MACs in one command,
1486 * the current command will be enqueued to the tail of the
1487 * pending commands list.
1488 *
1489 * Return: 0 is operation was successful and there are no pending completions,
1490 * negative if there were errors, positive if there are pending
1491 * completions.
1492 */
1493 int bnx2x_config_mcast(struct bnx2x *bp,
1494 struct bnx2x_mcast_ramrod_params *p,
1495 enum bnx2x_mcast_cmd cmd);
1496
1497 /****************** CREDIT POOL ****************/
1498 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1499 struct bnx2x_credit_pool_obj *p, u8 func_id,
1500 u8 func_num);
1501 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1502 struct bnx2x_credit_pool_obj *p, u8 func_id,
1503 u8 func_num);
1504 void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
1505 int base, int credit);
1506
1507 /****************** RSS CONFIGURATION ****************/
1508 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1509 struct bnx2x_rss_config_obj *rss_obj,
1510 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1511 void *rdata, dma_addr_t rdata_mapping,
1512 int state, unsigned long *pstate,
1513 bnx2x_obj_type type);
1514
1515 /**
1516 * bnx2x_config_rss - Updates RSS configuration according to provided parameters
1517 *
1518 * Return: 0 in case of success
1519 */
1520 int bnx2x_config_rss(struct bnx2x *bp,
1521 struct bnx2x_config_rss_params *p);
1522
1523 /**
1524 * bnx2x_get_rss_ind_table - Return the current ind_table configuration.
1525 *
1526 * @ind_table: buffer to fill with the current indirection
1527 * table content. Should be at least
1528 * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1529 */
1530 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1531 u8 *ind_table);
1532
1533 #define PF_MAC_CREDIT_E2(bp, func_num) \
1534 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_MAC_CREDIT_CNT) / \
1535 func_num + GET_NUM_VFS_PER_PF(bp) * VF_MAC_CREDIT_CNT)
1536
1537 #define PF_VLAN_CREDIT_E2(bp, func_num) \
1538 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_VLAN_CREDIT_CNT) / \
1539 func_num + GET_NUM_VFS_PER_PF(bp) * VF_VLAN_CREDIT_CNT)
1540
1541 #endif /* BNX2X_SP_VERBS */
Linux kernel - Deliverables
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