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fb: adv7393: off by one in probe function
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_sp.h
1 /* bnx2x_sp.h: Qlogic Everest network driver.
2 *
3 * Copyright 2011-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * Unless you and Qlogic execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2, available
10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
11 *
12 * Notwithstanding the above, under no circumstances may you combine this
13 * software in any way with any other Qlogic software provided under a
14 * license other than the GPL, without Qlogic's express prior written
15 * consent.
16 *
17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
18 * Written by: Vladislav Zolotarov
19 *
20 */
21 #ifndef BNX2X_SP_VERBS
22 #define BNX2X_SP_VERBS
23
24 struct bnx2x;
25 struct eth_context;
26
27 /* Bits representing general command's configuration */
28 enum {
29 RAMROD_TX,
30 RAMROD_RX,
31 /* Wait until all pending commands complete */
32 RAMROD_COMP_WAIT,
33 /* Don't send a ramrod, only update a registry */
34 RAMROD_DRV_CLR_ONLY,
35 /* Configure HW according to the current object state */
36 RAMROD_RESTORE,
37 /* Execute the next command now */
38 RAMROD_EXEC,
39 /* Don't add a new command and continue execution of postponed
40 * commands. If not set a new command will be added to the
41 * pending commands list.
42 */
43 RAMROD_CONT,
44 /* If there is another pending ramrod, wait until it finishes and
45 * re-try to submit this one. This flag can be set only in sleepable
46 * context, and should not be set from the context that completes the
47 * ramrods as deadlock will occur.
48 */
49 RAMROD_RETRY,
50 };
51
52 typedef enum {
53 BNX2X_OBJ_TYPE_RX,
54 BNX2X_OBJ_TYPE_TX,
55 BNX2X_OBJ_TYPE_RX_TX,
56 } bnx2x_obj_type;
57
58 /* Public slow path states */
59 enum {
60 BNX2X_FILTER_MAC_PENDING,
61 BNX2X_FILTER_VLAN_PENDING,
62 BNX2X_FILTER_VLAN_MAC_PENDING,
63 BNX2X_FILTER_RX_MODE_PENDING,
64 BNX2X_FILTER_RX_MODE_SCHED,
65 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
66 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
67 BNX2X_FILTER_FCOE_ETH_START_SCHED,
68 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
69 BNX2X_FILTER_MCAST_PENDING,
70 BNX2X_FILTER_MCAST_SCHED,
71 BNX2X_FILTER_RSS_CONF_PENDING,
72 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
73 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
74 };
75
76 struct bnx2x_raw_obj {
77 u8 func_id;
78
79 /* Queue params */
80 u8 cl_id;
81 u32 cid;
82
83 /* Ramrod data buffer params */
84 void *rdata;
85 dma_addr_t rdata_mapping;
86
87 /* Ramrod state params */
88 int state; /* "ramrod is pending" state bit */
89 unsigned long *pstate; /* pointer to state buffer */
90
91 bnx2x_obj_type obj_type;
92
93 int (*wait_comp)(struct bnx2x *bp,
94 struct bnx2x_raw_obj *o);
95
96 bool (*check_pending)(struct bnx2x_raw_obj *o);
97 void (*clear_pending)(struct bnx2x_raw_obj *o);
98 void (*set_pending)(struct bnx2x_raw_obj *o);
99 };
100
101 /************************* VLAN-MAC commands related parameters ***************/
102 struct bnx2x_mac_ramrod_data {
103 u8 mac[ETH_ALEN];
104 u8 is_inner_mac;
105 };
106
107 struct bnx2x_vlan_ramrod_data {
108 u16 vlan;
109 };
110
111 struct bnx2x_vlan_mac_ramrod_data {
112 u8 mac[ETH_ALEN];
113 u8 is_inner_mac;
114 u16 vlan;
115 };
116
117 union bnx2x_classification_ramrod_data {
118 struct bnx2x_mac_ramrod_data mac;
119 struct bnx2x_vlan_ramrod_data vlan;
120 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
121 };
122
123 /* VLAN_MAC commands */
124 enum bnx2x_vlan_mac_cmd {
125 BNX2X_VLAN_MAC_ADD,
126 BNX2X_VLAN_MAC_DEL,
127 BNX2X_VLAN_MAC_MOVE,
128 };
129
130 struct bnx2x_vlan_mac_data {
131 /* Requested command: BNX2X_VLAN_MAC_XX */
132 enum bnx2x_vlan_mac_cmd cmd;
133 /* used to contain the data related vlan_mac_flags bits from
134 * ramrod parameters.
135 */
136 unsigned long vlan_mac_flags;
137
138 /* Needed for MOVE command */
139 struct bnx2x_vlan_mac_obj *target_obj;
140
141 union bnx2x_classification_ramrod_data u;
142 };
143
144 /*************************** Exe Queue obj ************************************/
145 union bnx2x_exe_queue_cmd_data {
146 struct bnx2x_vlan_mac_data vlan_mac;
147
148 struct {
149 /* TODO */
150 } mcast;
151 };
152
153 struct bnx2x_exeq_elem {
154 struct list_head link;
155
156 /* Length of this element in the exe_chunk. */
157 int cmd_len;
158
159 union bnx2x_exe_queue_cmd_data cmd_data;
160 };
161
162 union bnx2x_qable_obj;
163
164 union bnx2x_exeq_comp_elem {
165 union event_ring_elem *elem;
166 };
167
168 struct bnx2x_exe_queue_obj;
169
170 typedef int (*exe_q_validate)(struct bnx2x *bp,
171 union bnx2x_qable_obj *o,
172 struct bnx2x_exeq_elem *elem);
173
174 typedef int (*exe_q_remove)(struct bnx2x *bp,
175 union bnx2x_qable_obj *o,
176 struct bnx2x_exeq_elem *elem);
177
178 /* Return positive if entry was optimized, 0 - if not, negative
179 * in case of an error.
180 */
181 typedef int (*exe_q_optimize)(struct bnx2x *bp,
182 union bnx2x_qable_obj *o,
183 struct bnx2x_exeq_elem *elem);
184 typedef int (*exe_q_execute)(struct bnx2x *bp,
185 union bnx2x_qable_obj *o,
186 struct list_head *exe_chunk,
187 unsigned long *ramrod_flags);
188 typedef struct bnx2x_exeq_elem *
189 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
190 struct bnx2x_exeq_elem *elem);
191
192 struct bnx2x_exe_queue_obj {
193 /* Commands pending for an execution. */
194 struct list_head exe_queue;
195
196 /* Commands pending for an completion. */
197 struct list_head pending_comp;
198
199 spinlock_t lock;
200
201 /* Maximum length of commands' list for one execution */
202 int exe_chunk_len;
203
204 union bnx2x_qable_obj *owner;
205
206 /****** Virtual functions ******/
207 /**
208 * Called before commands execution for commands that are really
209 * going to be executed (after 'optimize').
210 *
211 * Must run under exe_queue->lock
212 */
213 exe_q_validate validate;
214
215 /**
216 * Called before removing pending commands, cleaning allocated
217 * resources (e.g., credits from validate)
218 */
219 exe_q_remove remove;
220
221 /**
222 * This will try to cancel the current pending commands list
223 * considering the new command.
224 *
225 * Returns the number of optimized commands or a negative error code
226 *
227 * Must run under exe_queue->lock
228 */
229 exe_q_optimize optimize;
230
231 /**
232 * Run the next commands chunk (owner specific).
233 */
234 exe_q_execute execute;
235
236 /**
237 * Return the exe_queue element containing the specific command
238 * if any. Otherwise return NULL.
239 */
240 exe_q_get get;
241 };
242 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
243 /*
244 * Element in the VLAN_MAC registry list having all currently configured
245 * rules.
246 */
247 struct bnx2x_vlan_mac_registry_elem {
248 struct list_head link;
249
250 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
251 * Relevant for 57710 and 57711 only. VLANs and MACs share the
252 * same CAM for these chips.
253 */
254 int cam_offset;
255
256 /* Needed for DEL and RESTORE flows */
257 unsigned long vlan_mac_flags;
258
259 union bnx2x_classification_ramrod_data u;
260 };
261
262 /* Bits representing VLAN_MAC commands specific flags */
263 enum {
264 BNX2X_UC_LIST_MAC,
265 BNX2X_ETH_MAC,
266 BNX2X_ISCSI_ETH_MAC,
267 BNX2X_NETQ_ETH_MAC,
268 BNX2X_DONT_CONSUME_CAM_CREDIT,
269 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
270 };
271 /* When looking for matching filters, some flags are not interesting */
272 #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
273 1 << BNX2X_ETH_MAC | \
274 1 << BNX2X_ISCSI_ETH_MAC | \
275 1 << BNX2X_NETQ_ETH_MAC)
276 #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
277 ((flags) & BNX2X_VLAN_MAC_CMP_MASK)
278
279 struct bnx2x_vlan_mac_ramrod_params {
280 /* Object to run the command from */
281 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
282
283 /* General command flags: COMP_WAIT, etc. */
284 unsigned long ramrod_flags;
285
286 /* Command specific configuration request */
287 struct bnx2x_vlan_mac_data user_req;
288 };
289
290 struct bnx2x_vlan_mac_obj {
291 struct bnx2x_raw_obj raw;
292
293 /* Bookkeeping list: will prevent the addition of already existing
294 * entries.
295 */
296 struct list_head head;
297 /* Implement a simple reader/writer lock on the head list.
298 * all these fields should only be accessed under the exe_queue lock
299 */
300 u8 head_reader; /* Num. of readers accessing head list */
301 bool head_exe_request; /* Pending execution request. */
302 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
303
304 /* TODO: Add it's initialization in the init functions */
305 struct bnx2x_exe_queue_obj exe_queue;
306
307 /* MACs credit pool */
308 struct bnx2x_credit_pool_obj *macs_pool;
309
310 /* VLANs credit pool */
311 struct bnx2x_credit_pool_obj *vlans_pool;
312
313 /* RAMROD command to be used */
314 int ramrod_cmd;
315
316 /* copy first n elements onto preallocated buffer
317 *
318 * @param n number of elements to get
319 * @param buf buffer preallocated by caller into which elements
320 * will be copied. Note elements are 4-byte aligned
321 * so buffer size must be able to accommodate the
322 * aligned elements.
323 *
324 * @return number of copied bytes
325 */
326 int (*get_n_elements)(struct bnx2x *bp,
327 struct bnx2x_vlan_mac_obj *o, int n, u8 *base,
328 u8 stride, u8 size);
329
330 /**
331 * Checks if ADD-ramrod with the given params may be performed.
332 *
333 * @return zero if the element may be added
334 */
335
336 int (*check_add)(struct bnx2x *bp,
337 struct bnx2x_vlan_mac_obj *o,
338 union bnx2x_classification_ramrod_data *data);
339
340 /**
341 * Checks if DEL-ramrod with the given params may be performed.
342 *
343 * @return true if the element may be deleted
344 */
345 struct bnx2x_vlan_mac_registry_elem *
346 (*check_del)(struct bnx2x *bp,
347 struct bnx2x_vlan_mac_obj *o,
348 union bnx2x_classification_ramrod_data *data);
349
350 /**
351 * Checks if DEL-ramrod with the given params may be performed.
352 *
353 * @return true if the element may be deleted
354 */
355 bool (*check_move)(struct bnx2x *bp,
356 struct bnx2x_vlan_mac_obj *src_o,
357 struct bnx2x_vlan_mac_obj *dst_o,
358 union bnx2x_classification_ramrod_data *data);
359
360 /**
361 * Update the relevant credit object(s) (consume/return
362 * correspondingly).
363 */
364 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
365 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
366 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
367 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
368
369 /**
370 * Configures one rule in the ramrod data buffer.
371 */
372 void (*set_one_rule)(struct bnx2x *bp,
373 struct bnx2x_vlan_mac_obj *o,
374 struct bnx2x_exeq_elem *elem, int rule_idx,
375 int cam_offset);
376
377 /**
378 * Delete all configured elements having the given
379 * vlan_mac_flags specification. Assumes no pending for
380 * execution commands. Will schedule all all currently
381 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
382 * specification for deletion and will use the given
383 * ramrod_flags for the last DEL operation.
384 *
385 * @param bp
386 * @param o
387 * @param ramrod_flags RAMROD_XX flags
388 *
389 * @return 0 if the last operation has completed successfully
390 * and there are no more elements left, positive value
391 * if there are pending for completion commands,
392 * negative value in case of failure.
393 */
394 int (*delete_all)(struct bnx2x *bp,
395 struct bnx2x_vlan_mac_obj *o,
396 unsigned long *vlan_mac_flags,
397 unsigned long *ramrod_flags);
398
399 /**
400 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
401 * configured elements list.
402 *
403 * @param bp
404 * @param p Command parameters (RAMROD_COMP_WAIT bit in
405 * ramrod_flags is only taken into an account)
406 * @param ppos a pointer to the cookie that should be given back in the
407 * next call to make function handle the next element. If
408 * *ppos is set to NULL it will restart the iterator.
409 * If returned *ppos == NULL this means that the last
410 * element has been handled.
411 *
412 * @return int
413 */
414 int (*restore)(struct bnx2x *bp,
415 struct bnx2x_vlan_mac_ramrod_params *p,
416 struct bnx2x_vlan_mac_registry_elem **ppos);
417
418 /**
419 * Should be called on a completion arrival.
420 *
421 * @param bp
422 * @param o
423 * @param cqe Completion element we are handling
424 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
425 * pending commands will be executed.
426 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
427 * may also be set if needed.
428 *
429 * @return 0 if there are neither pending nor waiting for
430 * completion commands. Positive value if there are
431 * pending for execution or for completion commands.
432 * Negative value in case of an error (including an
433 * error in the cqe).
434 */
435 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
436 union event_ring_elem *cqe,
437 unsigned long *ramrod_flags);
438
439 /**
440 * Wait for completion of all commands. Don't schedule new ones,
441 * just wait. It assumes that the completion code will schedule
442 * for new commands.
443 */
444 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
445 };
446
447 enum {
448 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
449 BNX2X_LLH_CAM_ETH_LINE,
450 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
451 };
452
453 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
454
455 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
456 * a bnx2x_rx_mode_ramrod_params.
457 */
458 enum {
459 BNX2X_RX_MODE_FCOE_ETH,
460 BNX2X_RX_MODE_ISCSI_ETH,
461 };
462
463 enum {
464 BNX2X_ACCEPT_UNICAST,
465 BNX2X_ACCEPT_MULTICAST,
466 BNX2X_ACCEPT_ALL_UNICAST,
467 BNX2X_ACCEPT_ALL_MULTICAST,
468 BNX2X_ACCEPT_BROADCAST,
469 BNX2X_ACCEPT_UNMATCHED,
470 BNX2X_ACCEPT_ANY_VLAN
471 };
472
473 struct bnx2x_rx_mode_ramrod_params {
474 struct bnx2x_rx_mode_obj *rx_mode_obj;
475 unsigned long *pstate;
476 int state;
477 u8 cl_id;
478 u32 cid;
479 u8 func_id;
480 unsigned long ramrod_flags;
481 unsigned long rx_mode_flags;
482
483 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
484 * a tstorm_eth_mac_filter_config (e1x).
485 */
486 void *rdata;
487 dma_addr_t rdata_mapping;
488
489 /* Rx mode settings */
490 unsigned long rx_accept_flags;
491
492 /* internal switching settings */
493 unsigned long tx_accept_flags;
494 };
495
496 struct bnx2x_rx_mode_obj {
497 int (*config_rx_mode)(struct bnx2x *bp,
498 struct bnx2x_rx_mode_ramrod_params *p);
499
500 int (*wait_comp)(struct bnx2x *bp,
501 struct bnx2x_rx_mode_ramrod_params *p);
502 };
503
504 /********************** Set multicast group ***********************************/
505
506 struct bnx2x_mcast_list_elem {
507 struct list_head link;
508 u8 *mac;
509 };
510
511 union bnx2x_mcast_config_data {
512 u8 *mac;
513 u8 bin; /* used in a RESTORE flow */
514 };
515
516 struct bnx2x_mcast_ramrod_params {
517 struct bnx2x_mcast_obj *mcast_obj;
518
519 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
520 unsigned long ramrod_flags;
521
522 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
523 /** TODO:
524 * - rename it to macs_num.
525 * - Add a new command type for handling pending commands
526 * (remove "zero semantics").
527 *
528 * Length of mcast_list. If zero and ADD_CONT command - post
529 * pending commands.
530 */
531 int mcast_list_len;
532 };
533
534 enum bnx2x_mcast_cmd {
535 BNX2X_MCAST_CMD_ADD,
536 BNX2X_MCAST_CMD_CONT,
537 BNX2X_MCAST_CMD_DEL,
538 BNX2X_MCAST_CMD_RESTORE,
539 };
540
541 struct bnx2x_mcast_obj {
542 struct bnx2x_raw_obj raw;
543
544 union {
545 struct {
546 #define BNX2X_MCAST_BINS_NUM 256
547 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
548 u64 vec[BNX2X_MCAST_VEC_SZ];
549
550 /** Number of BINs to clear. Should be updated
551 * immediately when a command arrives in order to
552 * properly create DEL commands.
553 */
554 int num_bins_set;
555 } aprox_match;
556
557 struct {
558 struct list_head macs;
559 int num_macs_set;
560 } exact_match;
561 } registry;
562
563 /* Pending commands */
564 struct list_head pending_cmds_head;
565
566 /* A state that is set in raw.pstate, when there are pending commands */
567 int sched_state;
568
569 /* Maximal number of mcast MACs configured in one command */
570 int max_cmd_len;
571
572 /* Total number of currently pending MACs to configure: both
573 * in the pending commands list and in the current command.
574 */
575 int total_pending_num;
576
577 u8 engine_id;
578
579 /**
580 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
581 */
582 int (*config_mcast)(struct bnx2x *bp,
583 struct bnx2x_mcast_ramrod_params *p,
584 enum bnx2x_mcast_cmd cmd);
585
586 /**
587 * Fills the ramrod data during the RESTORE flow.
588 *
589 * @param bp
590 * @param o
591 * @param start_idx Registry index to start from
592 * @param rdata_idx Index in the ramrod data to start from
593 *
594 * @return -1 if we handled the whole registry or index of the last
595 * handled registry element.
596 */
597 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
598 int start_bin, int *rdata_idx);
599
600 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
601 struct bnx2x_mcast_ramrod_params *p,
602 enum bnx2x_mcast_cmd cmd);
603
604 void (*set_one_rule)(struct bnx2x *bp,
605 struct bnx2x_mcast_obj *o, int idx,
606 union bnx2x_mcast_config_data *cfg_data,
607 enum bnx2x_mcast_cmd cmd);
608
609 /** Checks if there are more mcast MACs to be set or a previous
610 * command is still pending.
611 */
612 bool (*check_pending)(struct bnx2x_mcast_obj *o);
613
614 /**
615 * Set/Clear/Check SCHEDULED state of the object
616 */
617 void (*set_sched)(struct bnx2x_mcast_obj *o);
618 void (*clear_sched)(struct bnx2x_mcast_obj *o);
619 bool (*check_sched)(struct bnx2x_mcast_obj *o);
620
621 /* Wait until all pending commands complete */
622 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
623
624 /**
625 * Handle the internal object counters needed for proper
626 * commands handling. Checks that the provided parameters are
627 * feasible.
628 */
629 int (*validate)(struct bnx2x *bp,
630 struct bnx2x_mcast_ramrod_params *p,
631 enum bnx2x_mcast_cmd cmd);
632
633 /**
634 * Restore the values of internal counters in case of a failure.
635 */
636 void (*revert)(struct bnx2x *bp,
637 struct bnx2x_mcast_ramrod_params *p,
638 int old_num_bins);
639
640 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
641 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
642 };
643
644 /*************************** Credit handling **********************************/
645 struct bnx2x_credit_pool_obj {
646
647 /* Current amount of credit in the pool */
648 atomic_t credit;
649
650 /* Maximum allowed credit. put() will check against it. */
651 int pool_sz;
652
653 /* Allocate a pool table statically.
654 *
655 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
656 *
657 * The set bit in the table will mean that the entry is available.
658 */
659 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
660 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
661
662 /* Base pool offset (initialized differently */
663 int base_pool_offset;
664
665 /**
666 * Get the next free pool entry.
667 *
668 * @return true if there was a free entry in the pool
669 */
670 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
671
672 /**
673 * Return the entry back to the pool.
674 *
675 * @return true if entry is legal and has been successfully
676 * returned to the pool.
677 */
678 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
679
680 /**
681 * Get the requested amount of credit from the pool.
682 *
683 * @param cnt Amount of requested credit
684 * @return true if the operation is successful
685 */
686 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
687
688 /**
689 * Returns the credit to the pool.
690 *
691 * @param cnt Amount of credit to return
692 * @return true if the operation is successful
693 */
694 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
695
696 /**
697 * Reads the current amount of credit.
698 */
699 int (*check)(struct bnx2x_credit_pool_obj *o);
700 };
701
702 /*************************** RSS configuration ********************************/
703 enum {
704 /* RSS_MODE bits are mutually exclusive */
705 BNX2X_RSS_MODE_DISABLED,
706 BNX2X_RSS_MODE_REGULAR,
707
708 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
709
710 BNX2X_RSS_IPV4,
711 BNX2X_RSS_IPV4_TCP,
712 BNX2X_RSS_IPV4_UDP,
713 BNX2X_RSS_IPV6,
714 BNX2X_RSS_IPV6_TCP,
715 BNX2X_RSS_IPV6_UDP,
716
717 BNX2X_RSS_IPV4_VXLAN,
718 BNX2X_RSS_IPV6_VXLAN,
719 BNX2X_RSS_TUNN_INNER_HDRS,
720 };
721
722 struct bnx2x_config_rss_params {
723 struct bnx2x_rss_config_obj *rss_obj;
724
725 /* may have RAMROD_COMP_WAIT set only */
726 unsigned long ramrod_flags;
727
728 /* BNX2X_RSS_X bits */
729 unsigned long rss_flags;
730
731 /* Number hash bits to take into an account */
732 u8 rss_result_mask;
733
734 /* Indirection table */
735 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
736
737 /* RSS hash values */
738 u32 rss_key[10];
739
740 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
741 u16 toe_rss_bitmap;
742 };
743
744 struct bnx2x_rss_config_obj {
745 struct bnx2x_raw_obj raw;
746
747 /* RSS engine to use */
748 u8 engine_id;
749
750 /* Last configured indirection table */
751 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
752
753 /* flags for enabling 4-tupple hash on UDP */
754 u8 udp_rss_v4;
755 u8 udp_rss_v6;
756
757 int (*config_rss)(struct bnx2x *bp,
758 struct bnx2x_config_rss_params *p);
759 };
760
761 /*********************** Queue state update ***********************************/
762
763 /* UPDATE command options */
764 enum {
765 BNX2X_Q_UPDATE_IN_VLAN_REM,
766 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
767 BNX2X_Q_UPDATE_OUT_VLAN_REM,
768 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
769 BNX2X_Q_UPDATE_ANTI_SPOOF,
770 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
771 BNX2X_Q_UPDATE_ACTIVATE,
772 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
773 BNX2X_Q_UPDATE_DEF_VLAN_EN,
774 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
775 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
776 BNX2X_Q_UPDATE_SILENT_VLAN_REM,
777 BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
778 BNX2X_Q_UPDATE_TX_SWITCHING,
779 BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
780 BNX2X_Q_UPDATE_PTP_PKTS,
781 };
782
783 /* Allowed Queue states */
784 enum bnx2x_q_state {
785 BNX2X_Q_STATE_RESET,
786 BNX2X_Q_STATE_INITIALIZED,
787 BNX2X_Q_STATE_ACTIVE,
788 BNX2X_Q_STATE_MULTI_COS,
789 BNX2X_Q_STATE_MCOS_TERMINATED,
790 BNX2X_Q_STATE_INACTIVE,
791 BNX2X_Q_STATE_STOPPED,
792 BNX2X_Q_STATE_TERMINATED,
793 BNX2X_Q_STATE_FLRED,
794 BNX2X_Q_STATE_MAX,
795 };
796
797 /* Allowed Queue states */
798 enum bnx2x_q_logical_state {
799 BNX2X_Q_LOGICAL_STATE_ACTIVE,
800 BNX2X_Q_LOGICAL_STATE_STOPPED,
801 };
802
803 /* Allowed commands */
804 enum bnx2x_queue_cmd {
805 BNX2X_Q_CMD_INIT,
806 BNX2X_Q_CMD_SETUP,
807 BNX2X_Q_CMD_SETUP_TX_ONLY,
808 BNX2X_Q_CMD_DEACTIVATE,
809 BNX2X_Q_CMD_ACTIVATE,
810 BNX2X_Q_CMD_UPDATE,
811 BNX2X_Q_CMD_UPDATE_TPA,
812 BNX2X_Q_CMD_HALT,
813 BNX2X_Q_CMD_CFC_DEL,
814 BNX2X_Q_CMD_TERMINATE,
815 BNX2X_Q_CMD_EMPTY,
816 BNX2X_Q_CMD_MAX,
817 };
818
819 /* queue SETUP + INIT flags */
820 enum {
821 BNX2X_Q_FLG_TPA,
822 BNX2X_Q_FLG_TPA_IPV6,
823 BNX2X_Q_FLG_TPA_GRO,
824 BNX2X_Q_FLG_STATS,
825 BNX2X_Q_FLG_ZERO_STATS,
826 BNX2X_Q_FLG_ACTIVE,
827 BNX2X_Q_FLG_OV,
828 BNX2X_Q_FLG_VLAN,
829 BNX2X_Q_FLG_COS,
830 BNX2X_Q_FLG_HC,
831 BNX2X_Q_FLG_HC_EN,
832 BNX2X_Q_FLG_DHC,
833 BNX2X_Q_FLG_FCOE,
834 BNX2X_Q_FLG_LEADING_RSS,
835 BNX2X_Q_FLG_MCAST,
836 BNX2X_Q_FLG_DEF_VLAN,
837 BNX2X_Q_FLG_TX_SWITCH,
838 BNX2X_Q_FLG_TX_SEC,
839 BNX2X_Q_FLG_ANTI_SPOOF,
840 BNX2X_Q_FLG_SILENT_VLAN_REM,
841 BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
842 BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
843 BNX2X_Q_FLG_PCSUM_ON_PKT,
844 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
845 };
846
847 /* Queue type options: queue type may be a combination of below. */
848 enum bnx2x_q_type {
849 /** TODO: Consider moving both these flags into the init()
850 * ramrod params.
851 */
852 BNX2X_Q_TYPE_HAS_RX,
853 BNX2X_Q_TYPE_HAS_TX,
854 };
855
856 #define BNX2X_PRIMARY_CID_INDEX 0
857 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */
858 #define BNX2X_MULTI_TX_COS_E2_E3A0 2
859 #define BNX2X_MULTI_TX_COS_E3B0 3
860 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */
861
862 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
863 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends
864 * timesync-related ramrods must not use this DMAE command ID.
865 */
866 #define FW_DMAE_CMD_ID 6
867
868 struct bnx2x_queue_init_params {
869 struct {
870 unsigned long flags;
871 u16 hc_rate;
872 u8 fw_sb_id;
873 u8 sb_cq_index;
874 } tx;
875
876 struct {
877 unsigned long flags;
878 u16 hc_rate;
879 u8 fw_sb_id;
880 u8 sb_cq_index;
881 } rx;
882
883 /* CID context in the host memory */
884 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
885
886 /* maximum number of cos supported by hardware */
887 u8 max_cos;
888 };
889
890 struct bnx2x_queue_terminate_params {
891 /* index within the tx_only cids of this queue object */
892 u8 cid_index;
893 };
894
895 struct bnx2x_queue_cfc_del_params {
896 /* index within the tx_only cids of this queue object */
897 u8 cid_index;
898 };
899
900 struct bnx2x_queue_update_params {
901 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */
902 u16 def_vlan;
903 u16 silent_removal_value;
904 u16 silent_removal_mask;
905 /* index within the tx_only cids of this queue object */
906 u8 cid_index;
907 };
908
909 struct bnx2x_queue_update_tpa_params {
910 dma_addr_t sge_map;
911 u8 update_ipv4;
912 u8 update_ipv6;
913 u8 max_tpa_queues;
914 u8 max_sges_pkt;
915 u8 complete_on_both_clients;
916 u8 dont_verify_thr;
917 u8 tpa_mode;
918 u8 _pad;
919
920 u16 sge_buff_sz;
921 u16 max_agg_sz;
922
923 u16 sge_pause_thr_low;
924 u16 sge_pause_thr_high;
925 };
926
927 struct rxq_pause_params {
928 u16 bd_th_lo;
929 u16 bd_th_hi;
930 u16 rcq_th_lo;
931 u16 rcq_th_hi;
932 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
933 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
934 u16 pri_map;
935 };
936
937 /* general */
938 struct bnx2x_general_setup_params {
939 /* valid iff BNX2X_Q_FLG_STATS */
940 u8 stat_id;
941
942 u8 spcl_id;
943 u16 mtu;
944 u8 cos;
945
946 u8 fp_hsi;
947 };
948
949 struct bnx2x_rxq_setup_params {
950 /* dma */
951 dma_addr_t dscr_map;
952 dma_addr_t sge_map;
953 dma_addr_t rcq_map;
954 dma_addr_t rcq_np_map;
955
956 u16 drop_flags;
957 u16 buf_sz;
958 u8 fw_sb_id;
959 u8 cl_qzone_id;
960
961 /* valid iff BNX2X_Q_FLG_TPA */
962 u16 tpa_agg_sz;
963 u16 sge_buf_sz;
964 u8 max_sges_pkt;
965 u8 max_tpa_queues;
966 u8 rss_engine_id;
967
968 /* valid iff BNX2X_Q_FLG_MCAST */
969 u8 mcast_engine_id;
970
971 u8 cache_line_log;
972
973 u8 sb_cq_index;
974
975 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
976 u16 silent_removal_value;
977 u16 silent_removal_mask;
978 };
979
980 struct bnx2x_txq_setup_params {
981 /* dma */
982 dma_addr_t dscr_map;
983
984 u8 fw_sb_id;
985 u8 sb_cq_index;
986 u8 cos; /* valid iff BNX2X_Q_FLG_COS */
987 u16 traffic_type;
988 /* equals to the leading rss client id, used for TX classification*/
989 u8 tss_leading_cl_id;
990
991 /* valid iff BNX2X_Q_FLG_DEF_VLAN */
992 u16 default_vlan;
993 };
994
995 struct bnx2x_queue_setup_params {
996 struct bnx2x_general_setup_params gen_params;
997 struct bnx2x_txq_setup_params txq_params;
998 struct bnx2x_rxq_setup_params rxq_params;
999 struct rxq_pause_params pause_params;
1000 unsigned long flags;
1001 };
1002
1003 struct bnx2x_queue_setup_tx_only_params {
1004 struct bnx2x_general_setup_params gen_params;
1005 struct bnx2x_txq_setup_params txq_params;
1006 unsigned long flags;
1007 /* index within the tx_only cids of this queue object */
1008 u8 cid_index;
1009 };
1010
1011 struct bnx2x_queue_state_params {
1012 struct bnx2x_queue_sp_obj *q_obj;
1013
1014 /* Current command */
1015 enum bnx2x_queue_cmd cmd;
1016
1017 /* may have RAMROD_COMP_WAIT set only */
1018 unsigned long ramrod_flags;
1019
1020 /* Params according to the current command */
1021 union {
1022 struct bnx2x_queue_update_params update;
1023 struct bnx2x_queue_update_tpa_params update_tpa;
1024 struct bnx2x_queue_setup_params setup;
1025 struct bnx2x_queue_init_params init;
1026 struct bnx2x_queue_setup_tx_only_params tx_only;
1027 struct bnx2x_queue_terminate_params terminate;
1028 struct bnx2x_queue_cfc_del_params cfc_del;
1029 } params;
1030 };
1031
1032 struct bnx2x_viflist_params {
1033 u8 echo_res;
1034 u8 func_bit_map_res;
1035 };
1036
1037 struct bnx2x_queue_sp_obj {
1038 u32 cids[BNX2X_MULTI_TX_COS];
1039 u8 cl_id;
1040 u8 func_id;
1041
1042 /* number of traffic classes supported by queue.
1043 * The primary connection of the queue supports the first traffic
1044 * class. Any further traffic class is supported by a tx-only
1045 * connection.
1046 *
1047 * Therefore max_cos is also a number of valid entries in the cids
1048 * array.
1049 */
1050 u8 max_cos;
1051 u8 num_tx_only, next_tx_only;
1052
1053 enum bnx2x_q_state state, next_state;
1054
1055 /* bits from enum bnx2x_q_type */
1056 unsigned long type;
1057
1058 /* BNX2X_Q_CMD_XX bits. This object implements "one
1059 * pending" paradigm but for debug and tracing purposes it's
1060 * more convenient to have different bits for different
1061 * commands.
1062 */
1063 unsigned long pending;
1064
1065 /* Buffer to use as a ramrod data and its mapping */
1066 void *rdata;
1067 dma_addr_t rdata_mapping;
1068
1069 /**
1070 * Performs one state change according to the given parameters.
1071 *
1072 * @return 0 in case of success and negative value otherwise.
1073 */
1074 int (*send_cmd)(struct bnx2x *bp,
1075 struct bnx2x_queue_state_params *params);
1076
1077 /**
1078 * Sets the pending bit according to the requested transition.
1079 */
1080 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1081 struct bnx2x_queue_state_params *params);
1082
1083 /**
1084 * Checks that the requested state transition is legal.
1085 */
1086 int (*check_transition)(struct bnx2x *bp,
1087 struct bnx2x_queue_sp_obj *o,
1088 struct bnx2x_queue_state_params *params);
1089
1090 /**
1091 * Completes the pending command.
1092 */
1093 int (*complete_cmd)(struct bnx2x *bp,
1094 struct bnx2x_queue_sp_obj *o,
1095 enum bnx2x_queue_cmd);
1096
1097 int (*wait_comp)(struct bnx2x *bp,
1098 struct bnx2x_queue_sp_obj *o,
1099 enum bnx2x_queue_cmd cmd);
1100 };
1101
1102 /********************** Function state update *********************************/
1103
1104 /* UPDATE command options */
1105 enum {
1106 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1107 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
1108 BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
1109 BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
1110 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
1111 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
1112 BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1113 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
1114 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
1115 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
1116 BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
1117 };
1118
1119 /* Allowed Function states */
1120 enum bnx2x_func_state {
1121 BNX2X_F_STATE_RESET,
1122 BNX2X_F_STATE_INITIALIZED,
1123 BNX2X_F_STATE_STARTED,
1124 BNX2X_F_STATE_TX_STOPPED,
1125 BNX2X_F_STATE_MAX,
1126 };
1127
1128 /* Allowed Function commands */
1129 enum bnx2x_func_cmd {
1130 BNX2X_F_CMD_HW_INIT,
1131 BNX2X_F_CMD_START,
1132 BNX2X_F_CMD_STOP,
1133 BNX2X_F_CMD_HW_RESET,
1134 BNX2X_F_CMD_AFEX_UPDATE,
1135 BNX2X_F_CMD_AFEX_VIFLISTS,
1136 BNX2X_F_CMD_TX_STOP,
1137 BNX2X_F_CMD_TX_START,
1138 BNX2X_F_CMD_SWITCH_UPDATE,
1139 BNX2X_F_CMD_SET_TIMESYNC,
1140 BNX2X_F_CMD_MAX,
1141 };
1142
1143 struct bnx2x_func_hw_init_params {
1144 /* A load phase returned by MCP.
1145 *
1146 * May be:
1147 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1148 * FW_MSG_CODE_DRV_LOAD_COMMON
1149 * FW_MSG_CODE_DRV_LOAD_PORT
1150 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1151 */
1152 u32 load_phase;
1153 };
1154
1155 struct bnx2x_func_hw_reset_params {
1156 /* A load phase returned by MCP.
1157 *
1158 * May be:
1159 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1160 * FW_MSG_CODE_DRV_LOAD_COMMON
1161 * FW_MSG_CODE_DRV_LOAD_PORT
1162 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1163 */
1164 u32 reset_phase;
1165 };
1166
1167 struct bnx2x_func_start_params {
1168 /* Multi Function mode:
1169 * - Single Function
1170 * - Switch Dependent
1171 * - Switch Independent
1172 */
1173 u16 mf_mode;
1174
1175 /* Switch Dependent mode outer VLAN tag */
1176 u16 sd_vlan_tag;
1177
1178 /* Function cos mode */
1179 u8 network_cos_mode;
1180
1181 /* UDP dest port for VXLAN */
1182 u16 vxlan_dst_port;
1183
1184 /* UDP dest port for Geneve */
1185 u16 geneve_dst_port;
1186
1187 /* Enable inner Rx classifications for L2GRE packets */
1188 u8 inner_clss_l2gre;
1189
1190 /* Enable inner Rx classifications for L2-Geneve packets */
1191 u8 inner_clss_l2geneve;
1192
1193 /* Enable inner Rx classification for vxlan packets */
1194 u8 inner_clss_vxlan;
1195
1196 /* Enable RSS according to inner header */
1197 u8 inner_rss;
1198
1199 /* Allows accepting of packets failing MF classification, possibly
1200 * only matching a given ethertype
1201 */
1202 u8 class_fail;
1203 u16 class_fail_ethtype;
1204
1205 /* Override priority of output packets */
1206 u8 sd_vlan_force_pri;
1207 u8 sd_vlan_force_pri_val;
1208
1209 /* Replace vlan's ethertype */
1210 u16 sd_vlan_eth_type;
1211
1212 /* Prevent inner vlans from being added by FW */
1213 u8 no_added_tags;
1214
1215 /* Inner-to-Outer vlan priority mapping */
1216 u8 c2s_pri[MAX_VLAN_PRIORITIES];
1217 u8 c2s_pri_default;
1218 u8 c2s_pri_valid;
1219 };
1220
1221 struct bnx2x_func_switch_update_params {
1222 unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
1223 u16 vlan;
1224 u16 vlan_eth_type;
1225 u8 vlan_force_prio;
1226 u16 vxlan_dst_port;
1227 u16 geneve_dst_port;
1228 };
1229
1230 struct bnx2x_func_afex_update_params {
1231 u16 vif_id;
1232 u16 afex_default_vlan;
1233 u8 allowed_priorities;
1234 };
1235
1236 struct bnx2x_func_afex_viflists_params {
1237 u16 vif_list_index;
1238 u8 func_bit_map;
1239 u8 afex_vif_list_command;
1240 u8 func_to_clear;
1241 };
1242
1243 struct bnx2x_func_tx_start_params {
1244 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1245 u8 dcb_enabled;
1246 u8 dcb_version;
1247 u8 dont_add_pri_0_en;
1248 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
1249 };
1250
1251 struct bnx2x_func_set_timesync_params {
1252 /* Reset, set or keep the current drift value */
1253 u8 drift_adjust_cmd;
1254
1255 /* Dec, inc or keep the current offset */
1256 u8 offset_cmd;
1257
1258 /* Drift value direction */
1259 u8 add_sub_drift_adjust_value;
1260
1261 /* Drift, period and offset values to be used according to the commands
1262 * above.
1263 */
1264 u8 drift_adjust_value;
1265 u32 drift_adjust_period;
1266 u64 offset_delta;
1267 };
1268
1269 struct bnx2x_func_state_params {
1270 struct bnx2x_func_sp_obj *f_obj;
1271
1272 /* Current command */
1273 enum bnx2x_func_cmd cmd;
1274
1275 /* may have RAMROD_COMP_WAIT set only */
1276 unsigned long ramrod_flags;
1277
1278 /* Params according to the current command */
1279 union {
1280 struct bnx2x_func_hw_init_params hw_init;
1281 struct bnx2x_func_hw_reset_params hw_reset;
1282 struct bnx2x_func_start_params start;
1283 struct bnx2x_func_switch_update_params switch_update;
1284 struct bnx2x_func_afex_update_params afex_update;
1285 struct bnx2x_func_afex_viflists_params afex_viflists;
1286 struct bnx2x_func_tx_start_params tx_start;
1287 struct bnx2x_func_set_timesync_params set_timesync;
1288 } params;
1289 };
1290
1291 struct bnx2x_func_sp_drv_ops {
1292 /* Init tool + runtime initialization:
1293 * - Common Chip
1294 * - Common (per Path)
1295 * - Port
1296 * - Function phases
1297 */
1298 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1299 int (*init_hw_cmn)(struct bnx2x *bp);
1300 int (*init_hw_port)(struct bnx2x *bp);
1301 int (*init_hw_func)(struct bnx2x *bp);
1302
1303 /* Reset Function HW: Common, Port, Function phases. */
1304 void (*reset_hw_cmn)(struct bnx2x *bp);
1305 void (*reset_hw_port)(struct bnx2x *bp);
1306 void (*reset_hw_func)(struct bnx2x *bp);
1307
1308 /* Init/Free GUNZIP resources */
1309 int (*gunzip_init)(struct bnx2x *bp);
1310 void (*gunzip_end)(struct bnx2x *bp);
1311
1312 /* Prepare/Release FW resources */
1313 int (*init_fw)(struct bnx2x *bp);
1314 void (*release_fw)(struct bnx2x *bp);
1315 };
1316
1317 struct bnx2x_func_sp_obj {
1318 enum bnx2x_func_state state, next_state;
1319
1320 /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1321 * pending" paradigm but for debug and tracing purposes it's
1322 * more convenient to have different bits for different
1323 * commands.
1324 */
1325 unsigned long pending;
1326
1327 /* Buffer to use as a ramrod data and its mapping */
1328 void *rdata;
1329 dma_addr_t rdata_mapping;
1330
1331 /* Buffer to use as a afex ramrod data and its mapping.
1332 * This can't be same rdata as above because afex ramrod requests
1333 * can arrive to the object in parallel to other ramrod requests.
1334 */
1335 void *afex_rdata;
1336 dma_addr_t afex_rdata_mapping;
1337
1338 /* this mutex validates that when pending flag is taken, the next
1339 * ramrod to be sent will be the one set the pending bit
1340 */
1341 struct mutex one_pending_mutex;
1342
1343 /* Driver interface */
1344 struct bnx2x_func_sp_drv_ops *drv;
1345
1346 /**
1347 * Performs one state change according to the given parameters.
1348 *
1349 * @return 0 in case of success and negative value otherwise.
1350 */
1351 int (*send_cmd)(struct bnx2x *bp,
1352 struct bnx2x_func_state_params *params);
1353
1354 /**
1355 * Checks that the requested state transition is legal.
1356 */
1357 int (*check_transition)(struct bnx2x *bp,
1358 struct bnx2x_func_sp_obj *o,
1359 struct bnx2x_func_state_params *params);
1360
1361 /**
1362 * Completes the pending command.
1363 */
1364 int (*complete_cmd)(struct bnx2x *bp,
1365 struct bnx2x_func_sp_obj *o,
1366 enum bnx2x_func_cmd cmd);
1367
1368 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1369 enum bnx2x_func_cmd cmd);
1370 };
1371
1372 /********************** Interfaces ********************************************/
1373 /* Queueable objects set */
1374 union bnx2x_qable_obj {
1375 struct bnx2x_vlan_mac_obj vlan_mac;
1376 };
1377 /************** Function state update *********/
1378 void bnx2x_init_func_obj(struct bnx2x *bp,
1379 struct bnx2x_func_sp_obj *obj,
1380 void *rdata, dma_addr_t rdata_mapping,
1381 void *afex_rdata, dma_addr_t afex_rdata_mapping,
1382 struct bnx2x_func_sp_drv_ops *drv_iface);
1383
1384 int bnx2x_func_state_change(struct bnx2x *bp,
1385 struct bnx2x_func_state_params *params);
1386
1387 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1388 struct bnx2x_func_sp_obj *o);
1389 /******************* Queue State **************/
1390 void bnx2x_init_queue_obj(struct bnx2x *bp,
1391 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1392 u8 cid_cnt, u8 func_id, void *rdata,
1393 dma_addr_t rdata_mapping, unsigned long type);
1394
1395 int bnx2x_queue_state_change(struct bnx2x *bp,
1396 struct bnx2x_queue_state_params *params);
1397
1398 int bnx2x_get_q_logical_state(struct bnx2x *bp,
1399 struct bnx2x_queue_sp_obj *obj);
1400
1401 /********************* VLAN-MAC ****************/
1402 void bnx2x_init_mac_obj(struct bnx2x *bp,
1403 struct bnx2x_vlan_mac_obj *mac_obj,
1404 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1405 dma_addr_t rdata_mapping, int state,
1406 unsigned long *pstate, bnx2x_obj_type type,
1407 struct bnx2x_credit_pool_obj *macs_pool);
1408
1409 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1410 struct bnx2x_vlan_mac_obj *vlan_obj,
1411 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1412 dma_addr_t rdata_mapping, int state,
1413 unsigned long *pstate, bnx2x_obj_type type,
1414 struct bnx2x_credit_pool_obj *vlans_pool);
1415
1416 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1417 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1418 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1419 dma_addr_t rdata_mapping, int state,
1420 unsigned long *pstate, bnx2x_obj_type type,
1421 struct bnx2x_credit_pool_obj *macs_pool,
1422 struct bnx2x_credit_pool_obj *vlans_pool);
1423
1424 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
1425 struct bnx2x_vlan_mac_obj *o);
1426 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
1427 struct bnx2x_vlan_mac_obj *o);
1428 int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp,
1429 struct bnx2x_vlan_mac_obj *o);
1430 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1431 struct bnx2x_vlan_mac_ramrod_params *p);
1432
1433 int bnx2x_vlan_mac_move(struct bnx2x *bp,
1434 struct bnx2x_vlan_mac_ramrod_params *p,
1435 struct bnx2x_vlan_mac_obj *dest_o);
1436
1437 /********************* RX MODE ****************/
1438
1439 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1440 struct bnx2x_rx_mode_obj *o);
1441
1442 /**
1443 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1444 *
1445 * @p: Command parameters
1446 *
1447 * Return: 0 - if operation was successful and there is no pending completions,
1448 * positive number - if there are pending completions,
1449 * negative - if there were errors
1450 */
1451 int bnx2x_config_rx_mode(struct bnx2x *bp,
1452 struct bnx2x_rx_mode_ramrod_params *p);
1453
1454 /****************** MULTICASTS ****************/
1455
1456 void bnx2x_init_mcast_obj(struct bnx2x *bp,
1457 struct bnx2x_mcast_obj *mcast_obj,
1458 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1459 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1460 int state, unsigned long *pstate,
1461 bnx2x_obj_type type);
1462
1463 /**
1464 * bnx2x_config_mcast - Configure multicast MACs list.
1465 *
1466 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1467 *
1468 * May configure a new list
1469 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1470 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1471 * configuration, continue to execute the pending commands
1472 * (BNX2X_MCAST_CMD_CONT).
1473 *
1474 * If previous command is still pending or if number of MACs to
1475 * configure is more that maximum number of MACs in one command,
1476 * the current command will be enqueued to the tail of the
1477 * pending commands list.
1478 *
1479 * Return: 0 is operation was successful and there are no pending completions,
1480 * negative if there were errors, positive if there are pending
1481 * completions.
1482 */
1483 int bnx2x_config_mcast(struct bnx2x *bp,
1484 struct bnx2x_mcast_ramrod_params *p,
1485 enum bnx2x_mcast_cmd cmd);
1486
1487 /****************** CREDIT POOL ****************/
1488 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1489 struct bnx2x_credit_pool_obj *p, u8 func_id,
1490 u8 func_num);
1491 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1492 struct bnx2x_credit_pool_obj *p, u8 func_id,
1493 u8 func_num);
1494 void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
1495 int base, int credit);
1496
1497 /****************** RSS CONFIGURATION ****************/
1498 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1499 struct bnx2x_rss_config_obj *rss_obj,
1500 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1501 void *rdata, dma_addr_t rdata_mapping,
1502 int state, unsigned long *pstate,
1503 bnx2x_obj_type type);
1504
1505 /**
1506 * bnx2x_config_rss - Updates RSS configuration according to provided parameters
1507 *
1508 * Return: 0 in case of success
1509 */
1510 int bnx2x_config_rss(struct bnx2x *bp,
1511 struct bnx2x_config_rss_params *p);
1512
1513 /**
1514 * bnx2x_get_rss_ind_table - Return the current ind_table configuration.
1515 *
1516 * @ind_table: buffer to fill with the current indirection
1517 * table content. Should be at least
1518 * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1519 */
1520 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1521 u8 *ind_table);
1522
1523 #define PF_MAC_CREDIT_E2(bp, func_num) \
1524 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_MAC_CREDIT_CNT) / \
1525 func_num + GET_NUM_VFS_PER_PF(bp) * VF_MAC_CREDIT_CNT)
1526
1527 #define PF_VLAN_CREDIT_E2(bp, func_num) \
1528 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_VLAN_CREDIT_CNT) / \
1529 func_num + GET_NUM_VFS_PER_PF(bp) * VF_VLAN_CREDIT_CNT)
1530
1531 #endif /* BNX2X_SP_VERBS */
Linux kernel - Deliverables
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