2 * Broadcom GENET MDIO routines
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/wait.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/bitops.h>
18 #include <linux/netdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/phy.h>
21 #include <linux/phy_fixed.h>
22 #include <linux/brcmphy.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <linux/platform_data/bcmgenet.h>
30 /* read a value from the MII */
31 static int bcmgenet_mii_read(struct mii_bus
*bus
, int phy_id
, int location
)
34 struct net_device
*dev
= bus
->priv
;
35 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
38 bcmgenet_umac_writel(priv
, (MDIO_RD
| (phy_id
<< MDIO_PMD_SHIFT
) |
39 (location
<< MDIO_REG_SHIFT
)), UMAC_MDIO_CMD
);
40 /* Start MDIO transaction*/
41 reg
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
42 reg
|= MDIO_START_BUSY
;
43 bcmgenet_umac_writel(priv
, reg
, UMAC_MDIO_CMD
);
44 wait_event_timeout(priv
->wq
,
45 !(bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
)
48 ret
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
50 /* Some broken devices are known not to release the line during
51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
52 * that condition here and ignore the MDIO controller read failure
55 if (!(bus
->phy_ignore_ta_mask
& 1 << phy_id
) && (ret
& MDIO_READ_FAIL
))
61 /* write a value to the MII */
62 static int bcmgenet_mii_write(struct mii_bus
*bus
, int phy_id
,
63 int location
, u16 val
)
65 struct net_device
*dev
= bus
->priv
;
66 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
69 bcmgenet_umac_writel(priv
, (MDIO_WR
| (phy_id
<< MDIO_PMD_SHIFT
) |
70 (location
<< MDIO_REG_SHIFT
) | (0xffff & val
)),
72 reg
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
73 reg
|= MDIO_START_BUSY
;
74 bcmgenet_umac_writel(priv
, reg
, UMAC_MDIO_CMD
);
75 wait_event_timeout(priv
->wq
,
76 !(bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
) &
83 /* setup netdev link state when PHY link status change and
84 * update UMAC and RGMII block when link up
86 void bcmgenet_mii_setup(struct net_device
*dev
)
88 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
89 struct phy_device
*phydev
= priv
->phydev
;
90 u32 reg
, cmd_bits
= 0;
91 bool status_changed
= false;
93 if (priv
->old_link
!= phydev
->link
) {
94 status_changed
= true;
95 priv
->old_link
= phydev
->link
;
99 /* check speed/duplex/pause changes */
100 if (priv
->old_speed
!= phydev
->speed
) {
101 status_changed
= true;
102 priv
->old_speed
= phydev
->speed
;
105 if (priv
->old_duplex
!= phydev
->duplex
) {
106 status_changed
= true;
107 priv
->old_duplex
= phydev
->duplex
;
110 if (priv
->old_pause
!= phydev
->pause
) {
111 status_changed
= true;
112 priv
->old_pause
= phydev
->pause
;
115 /* done if nothing has changed */
120 if (phydev
->speed
== SPEED_1000
)
121 cmd_bits
= UMAC_SPEED_1000
;
122 else if (phydev
->speed
== SPEED_100
)
123 cmd_bits
= UMAC_SPEED_100
;
125 cmd_bits
= UMAC_SPEED_10
;
126 cmd_bits
<<= CMD_SPEED_SHIFT
;
129 if (phydev
->duplex
!= DUPLEX_FULL
)
130 cmd_bits
|= CMD_HD_EN
;
132 /* pause capability */
134 cmd_bits
|= CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
;
137 * Program UMAC and RGMII block based on established
138 * link speed, duplex, and pause. The speed set in
139 * umac->cmd tell RGMII block which clock to use for
140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
141 * Receive clock is provided by the PHY.
143 reg
= bcmgenet_ext_readl(priv
, EXT_RGMII_OOB_CTRL
);
146 bcmgenet_ext_writel(priv
, reg
, EXT_RGMII_OOB_CTRL
);
148 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
149 reg
&= ~((CMD_SPEED_MASK
<< CMD_SPEED_SHIFT
) |
151 CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
);
153 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
155 /* done if nothing has changed */
159 /* needed for MoCA fixed PHY to reflect correct link status */
160 netif_carrier_off(dev
);
163 phy_print_status(phydev
);
166 static int bcmgenet_fixed_phy_link_update(struct net_device
*dev
,
167 struct fixed_phy_status
*status
)
169 if (dev
&& dev
->phydev
&& status
)
170 status
->link
= dev
->phydev
->link
;
175 void bcmgenet_phy_power_set(struct net_device
*dev
, bool enable
)
177 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
180 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
181 if (!GENET_IS_V4(priv
))
184 reg
= bcmgenet_ext_readl(priv
, EXT_GPHY_CTRL
);
186 reg
&= ~EXT_CK25_DIS
;
187 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
190 reg
&= ~(EXT_CFG_IDDQ_BIAS
| EXT_CFG_PWR_DOWN
);
191 reg
|= EXT_GPHY_RESET
;
192 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
195 reg
&= ~EXT_GPHY_RESET
;
197 reg
|= EXT_CFG_IDDQ_BIAS
| EXT_CFG_PWR_DOWN
| EXT_GPHY_RESET
;
198 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
202 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
206 static void bcmgenet_internal_phy_setup(struct net_device
*dev
)
208 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
212 bcmgenet_phy_power_set(dev
, true);
214 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
215 reg
|= EXT_PWR_DN_EN_LD
;
216 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
219 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv
*priv
)
223 /* Speed settings are set in bcmgenet_mii_setup() */
224 reg
= bcmgenet_sys_readl(priv
, SYS_PORT_CTRL
);
225 reg
|= LED_ACT_SOURCE_MAC
;
226 bcmgenet_sys_writel(priv
, reg
, SYS_PORT_CTRL
);
228 if (priv
->hw_params
->flags
& GENET_HAS_MOCA_LINK_DET
)
229 fixed_phy_set_link_update(priv
->phydev
,
230 bcmgenet_fixed_phy_link_update
);
233 int bcmgenet_mii_config(struct net_device
*dev
)
235 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
236 struct phy_device
*phydev
= priv
->phydev
;
237 struct device
*kdev
= &priv
->pdev
->dev
;
238 const char *phy_name
= NULL
;
243 priv
->ext_phy
= !priv
->internal_phy
&&
244 (priv
->phy_interface
!= PHY_INTERFACE_MODE_MOCA
);
246 if (priv
->internal_phy
)
247 priv
->phy_interface
= PHY_INTERFACE_MODE_NA
;
249 switch (priv
->phy_interface
) {
250 case PHY_INTERFACE_MODE_NA
:
251 case PHY_INTERFACE_MODE_MOCA
:
252 /* Irrespective of the actually configured PHY speed (100 or
253 * 1000) GENETv4 only has an internal GPHY so we will just end
254 * up masking the Gigabit features from what we support, not
255 * switching to the EPHY
257 if (GENET_IS_V4(priv
))
258 port_ctrl
= PORT_MODE_INT_GPHY
;
260 port_ctrl
= PORT_MODE_INT_EPHY
;
262 bcmgenet_sys_writel(priv
, port_ctrl
, SYS_PORT_CTRL
);
264 if (priv
->internal_phy
) {
265 phy_name
= "internal PHY";
266 bcmgenet_internal_phy_setup(dev
);
267 } else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
269 bcmgenet_moca_phy_setup(priv
);
273 case PHY_INTERFACE_MODE_MII
:
274 phy_name
= "external MII";
275 phydev
->supported
&= PHY_BASIC_FEATURES
;
276 bcmgenet_sys_writel(priv
,
277 PORT_MODE_EXT_EPHY
, SYS_PORT_CTRL
);
280 case PHY_INTERFACE_MODE_REVMII
:
281 phy_name
= "external RvMII";
282 /* of_mdiobus_register took care of reading the 'max-speed'
283 * PHY property for us, effectively limiting the PHY supported
284 * capabilities, use that knowledge to also configure the
285 * Reverse MII interface correctly.
287 if ((priv
->phydev
->supported
& PHY_BASIC_FEATURES
) ==
289 port_ctrl
= PORT_MODE_EXT_RVMII_25
;
291 port_ctrl
= PORT_MODE_EXT_RVMII_50
;
292 bcmgenet_sys_writel(priv
, port_ctrl
, SYS_PORT_CTRL
);
295 case PHY_INTERFACE_MODE_RGMII
:
296 /* RGMII_NO_ID: TXC transitions at the same time as TXD
297 * (requires PCB or receiver-side delay)
298 * RGMII: Add 2ns delay on TXC (90 degree shift)
300 * ID is implicitly disabled for 100Mbps (RG)MII operation.
302 id_mode_dis
= BIT(16);
304 case PHY_INTERFACE_MODE_RGMII_TXID
:
306 phy_name
= "external RGMII (no delay)";
308 phy_name
= "external RGMII (TX delay)";
309 bcmgenet_sys_writel(priv
,
310 PORT_MODE_EXT_GPHY
, SYS_PORT_CTRL
);
313 dev_err(kdev
, "unknown phy mode: %d\n", priv
->phy_interface
);
317 /* This is an external PHY (xMII), so we need to enable the RGMII
318 * block for the interface to work
321 reg
= bcmgenet_ext_readl(priv
, EXT_RGMII_OOB_CTRL
);
322 reg
|= RGMII_MODE_EN
| id_mode_dis
;
323 bcmgenet_ext_writel(priv
, reg
, EXT_RGMII_OOB_CTRL
);
326 dev_info_once(kdev
, "configuring instance for %s\n", phy_name
);
331 int bcmgenet_mii_probe(struct net_device
*dev
)
333 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
334 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
335 struct phy_device
*phydev
;
339 /* Communicate the integrated PHY revision */
340 phy_flags
= priv
->gphy_rev
;
342 /* Initialize link state variables that bcmgenet_mii_setup() uses */
344 priv
->old_speed
= -1;
345 priv
->old_duplex
= -1;
346 priv
->old_pause
= -1;
349 phydev
= of_phy_connect(dev
, priv
->phy_dn
, bcmgenet_mii_setup
,
350 phy_flags
, priv
->phy_interface
);
352 pr_err("could not attach to PHY\n");
356 phydev
= priv
->phydev
;
357 phydev
->dev_flags
= phy_flags
;
359 ret
= phy_connect_direct(dev
, phydev
, bcmgenet_mii_setup
,
360 priv
->phy_interface
);
362 pr_err("could not attach to PHY\n");
367 priv
->phydev
= phydev
;
369 /* Configure port multiplexer based on what the probed PHY device since
370 * reading the 'max-speed' property determines the maximum supported
371 * PHY speed which is needed for bcmgenet_mii_config() to configure
372 * things appropriately.
374 ret
= bcmgenet_mii_config(dev
);
376 phy_disconnect(priv
->phydev
);
380 phydev
->advertising
= phydev
->supported
;
382 /* The internal PHY has its link interrupts routed to the
385 if (priv
->internal_phy
)
386 priv
->mii_bus
->irq
[phydev
->addr
] = PHY_IGNORE_INTERRUPT
;
388 priv
->mii_bus
->irq
[phydev
->addr
] = PHY_POLL
;
393 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
394 * their internal MDIO management controller making them fail to successfully
395 * be read from or written to for the first transaction. We insert a dummy
396 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
397 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
398 * PHY device for this peripheral.
400 * Once the PHY driver is registered, we can workaround subsequent reads from
401 * there (e.g: during system-wide power management).
403 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
404 * therefore the right location to stick that workaround. Since we do not want
405 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
406 * Device Tree scan to limit the search area.
408 static int bcmgenet_mii_bus_reset(struct mii_bus
*bus
)
410 struct net_device
*dev
= bus
->priv
;
411 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
412 struct device_node
*np
= priv
->mdio_dn
;
413 struct device_node
*child
= NULL
;
418 read_mask
= 1 << priv
->phy_addr
;
420 for_each_available_child_of_node(np
, child
) {
421 addr
= of_mdio_parse_addr(&dev
->dev
, child
);
425 read_mask
|= 1 << addr
;
429 for (addr
= 0; addr
< PHY_MAX_ADDR
; addr
++) {
430 if (read_mask
& 1 << addr
) {
431 dev_dbg(&dev
->dev
, "Workaround for PHY @ %d\n", addr
);
432 mdiobus_read(bus
, addr
, MII_BMSR
);
439 static int bcmgenet_mii_alloc(struct bcmgenet_priv
*priv
)
446 priv
->mii_bus
= mdiobus_alloc();
447 if (!priv
->mii_bus
) {
448 pr_err("failed to allocate\n");
453 bus
->priv
= priv
->dev
;
454 bus
->name
= "bcmgenet MII bus";
455 bus
->parent
= &priv
->pdev
->dev
;
456 bus
->read
= bcmgenet_mii_read
;
457 bus
->write
= bcmgenet_mii_write
;
458 bus
->reset
= bcmgenet_mii_bus_reset
;
459 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
460 priv
->pdev
->name
, priv
->pdev
->id
);
462 bus
->irq
= kcalloc(PHY_MAX_ADDR
, sizeof(int), GFP_KERNEL
);
464 mdiobus_free(priv
->mii_bus
);
471 static int bcmgenet_mii_of_init(struct bcmgenet_priv
*priv
)
473 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
474 struct device
*kdev
= &priv
->pdev
->dev
;
475 const char *phy_mode_str
= NULL
;
476 struct phy_device
*phydev
= NULL
;
481 compat
= kasprintf(GFP_KERNEL
, "brcm,genet-mdio-v%d", priv
->version
);
485 priv
->mdio_dn
= of_find_compatible_node(dn
, NULL
, compat
);
487 if (!priv
->mdio_dn
) {
488 dev_err(kdev
, "unable to find MDIO bus node\n");
492 ret
= of_mdiobus_register(priv
->mii_bus
, priv
->mdio_dn
);
494 dev_err(kdev
, "failed to register MDIO bus\n");
498 /* Fetch the PHY phandle */
499 priv
->phy_dn
= of_parse_phandle(dn
, "phy-handle", 0);
501 /* In the case of a fixed PHY, the DT node associated
502 * to the PHY is the Ethernet MAC DT node.
504 if (!priv
->phy_dn
&& of_phy_is_fixed_link(dn
)) {
505 ret
= of_phy_register_fixed_link(dn
);
509 priv
->phy_dn
= of_node_get(dn
);
512 /* Get the link mode */
513 phy_mode
= of_get_phy_mode(dn
);
514 priv
->phy_interface
= phy_mode
;
516 /* We need to specifically look up whether this PHY interface is internal
517 * or not *before* we even try to probe the PHY driver over MDIO as we
518 * may have shut down the internal PHY for power saving purposes.
521 ret
= of_property_read_string(dn
, "phy-mode", &phy_mode_str
);
523 dev_err(kdev
, "invalid PHY mode property\n");
527 priv
->phy_interface
= PHY_INTERFACE_MODE_NA
;
528 if (!strcasecmp(phy_mode_str
, "internal"))
529 priv
->internal_phy
= true;
532 /* Make sure we initialize MoCA PHYs with a link down */
533 if (phy_mode
== PHY_INTERFACE_MODE_MOCA
) {
534 phydev
= of_phy_find_device(dn
);
542 static int bcmgenet_mii_pd_init(struct bcmgenet_priv
*priv
)
544 struct device
*kdev
= &priv
->pdev
->dev
;
545 struct bcmgenet_platform_data
*pd
= kdev
->platform_data
;
546 struct mii_bus
*mdio
= priv
->mii_bus
;
547 struct phy_device
*phydev
;
550 if (pd
->phy_interface
!= PHY_INTERFACE_MODE_MOCA
&& pd
->mdio_enabled
) {
552 * Internal or external PHY with MDIO access
554 if (pd
->phy_address
>= 0 && pd
->phy_address
< PHY_MAX_ADDR
)
555 mdio
->phy_mask
= ~(1 << pd
->phy_address
);
559 ret
= mdiobus_register(mdio
);
561 dev_err(kdev
, "failed to register MDIO bus\n");
565 if (pd
->phy_address
>= 0 && pd
->phy_address
< PHY_MAX_ADDR
)
566 phydev
= mdio
->phy_map
[pd
->phy_address
];
568 phydev
= phy_find_first(mdio
);
571 dev_err(kdev
, "failed to register PHY device\n");
572 mdiobus_unregister(mdio
);
577 * MoCA port or no MDIO access.
578 * Use fixed PHY to represent the link layer.
580 struct fixed_phy_status fphy_status
= {
582 .speed
= pd
->phy_speed
,
583 .duplex
= pd
->phy_duplex
,
588 phydev
= fixed_phy_register(PHY_POLL
, &fphy_status
, -1, NULL
);
589 if (!phydev
|| IS_ERR(phydev
)) {
590 dev_err(kdev
, "failed to register fixed PHY device\n");
594 /* Make sure we initialize MoCA PHYs with a link down */
599 priv
->phydev
= phydev
;
600 priv
->phy_interface
= pd
->phy_interface
;
605 static int bcmgenet_mii_bus_init(struct bcmgenet_priv
*priv
)
607 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
610 return bcmgenet_mii_of_init(priv
);
612 return bcmgenet_mii_pd_init(priv
);
615 int bcmgenet_mii_init(struct net_device
*dev
)
617 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
620 ret
= bcmgenet_mii_alloc(priv
);
624 ret
= bcmgenet_mii_bus_init(priv
);
631 of_node_put(priv
->phy_dn
);
632 mdiobus_unregister(priv
->mii_bus
);
633 kfree(priv
->mii_bus
->irq
);
634 mdiobus_free(priv
->mii_bus
);
638 void bcmgenet_mii_exit(struct net_device
*dev
)
640 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
642 of_node_put(priv
->phy_dn
);
643 mdiobus_unregister(priv
->mii_bus
);
644 kfree(priv
->mii_bus
->irq
);
645 mdiobus_free(priv
->mii_bus
);