2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
38 #define MACB_RX_BUFFER_SIZE 128
39 #define RX_BUFFER_MULTIPLE 64 /* bytes */
40 #define RX_RING_SIZE 512 /* must be power of 2 */
41 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
43 #define TX_RING_SIZE 128 /* must be power of 2 */
44 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
46 /* level of occupied TX descriptors under which we wake up TX process */
47 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
49 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
51 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
54 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
59 #define GEM_MTU_MIN_SIZE 68
61 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
62 #define MACB_WOL_ENABLED (0x1 << 1)
64 /* Graceful stop timeouts in us. We should allow up to
65 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
67 #define MACB_HALT_TIMEOUT 1230
69 /* Ring buffer accessors */
70 static unsigned int macb_tx_ring_wrap(unsigned int index
)
72 return index
& (TX_RING_SIZE
- 1);
75 static struct macb_dma_desc
*macb_tx_desc(struct macb_queue
*queue
,
78 return &queue
->tx_ring
[macb_tx_ring_wrap(index
)];
81 static struct macb_tx_skb
*macb_tx_skb(struct macb_queue
*queue
,
84 return &queue
->tx_skb
[macb_tx_ring_wrap(index
)];
87 static dma_addr_t
macb_tx_dma(struct macb_queue
*queue
, unsigned int index
)
91 offset
= macb_tx_ring_wrap(index
) * sizeof(struct macb_dma_desc
);
93 return queue
->tx_ring_dma
+ offset
;
96 static unsigned int macb_rx_ring_wrap(unsigned int index
)
98 return index
& (RX_RING_SIZE
- 1);
101 static struct macb_dma_desc
*macb_rx_desc(struct macb
*bp
, unsigned int index
)
103 return &bp
->rx_ring
[macb_rx_ring_wrap(index
)];
106 static void *macb_rx_buffer(struct macb
*bp
, unsigned int index
)
108 return bp
->rx_buffers
+ bp
->rx_buffer_size
* macb_rx_ring_wrap(index
);
112 static u32
hw_readl_native(struct macb
*bp
, int offset
)
114 return __raw_readl(bp
->regs
+ offset
);
117 static void hw_writel_native(struct macb
*bp
, int offset
, u32 value
)
119 __raw_writel(value
, bp
->regs
+ offset
);
122 static u32
hw_readl(struct macb
*bp
, int offset
)
124 return readl_relaxed(bp
->regs
+ offset
);
127 static void hw_writel(struct macb
*bp
, int offset
, u32 value
)
129 writel_relaxed(value
, bp
->regs
+ offset
);
132 /* Find the CPU endianness by using the loopback bit of NCR register. When the
133 * CPU is in big endian we need to program swapped mode for management
136 static bool hw_is_native_io(void __iomem
*addr
)
138 u32 value
= MACB_BIT(LLB
);
140 __raw_writel(value
, addr
+ MACB_NCR
);
141 value
= __raw_readl(addr
+ MACB_NCR
);
143 /* Write 0 back to disable everything */
144 __raw_writel(0, addr
+ MACB_NCR
);
146 return value
== MACB_BIT(LLB
);
149 static bool hw_is_gem(void __iomem
*addr
, bool native_io
)
154 id
= __raw_readl(addr
+ MACB_MID
);
156 id
= readl_relaxed(addr
+ MACB_MID
);
158 return MACB_BFEXT(IDNUM
, id
) >= 0x2;
161 static void macb_set_hwaddr(struct macb
*bp
)
166 bottom
= cpu_to_le32(*((u32
*)bp
->dev
->dev_addr
));
167 macb_or_gem_writel(bp
, SA1B
, bottom
);
168 top
= cpu_to_le16(*((u16
*)(bp
->dev
->dev_addr
+ 4)));
169 macb_or_gem_writel(bp
, SA1T
, top
);
171 /* Clear unused address register sets */
172 macb_or_gem_writel(bp
, SA2B
, 0);
173 macb_or_gem_writel(bp
, SA2T
, 0);
174 macb_or_gem_writel(bp
, SA3B
, 0);
175 macb_or_gem_writel(bp
, SA3T
, 0);
176 macb_or_gem_writel(bp
, SA4B
, 0);
177 macb_or_gem_writel(bp
, SA4T
, 0);
180 static void macb_get_hwaddr(struct macb
*bp
)
182 struct macb_platform_data
*pdata
;
188 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
190 /* Check all 4 address register for valid address */
191 for (i
= 0; i
< 4; i
++) {
192 bottom
= macb_or_gem_readl(bp
, SA1B
+ i
* 8);
193 top
= macb_or_gem_readl(bp
, SA1T
+ i
* 8);
195 if (pdata
&& pdata
->rev_eth_addr
) {
196 addr
[5] = bottom
& 0xff;
197 addr
[4] = (bottom
>> 8) & 0xff;
198 addr
[3] = (bottom
>> 16) & 0xff;
199 addr
[2] = (bottom
>> 24) & 0xff;
200 addr
[1] = top
& 0xff;
201 addr
[0] = (top
& 0xff00) >> 8;
203 addr
[0] = bottom
& 0xff;
204 addr
[1] = (bottom
>> 8) & 0xff;
205 addr
[2] = (bottom
>> 16) & 0xff;
206 addr
[3] = (bottom
>> 24) & 0xff;
207 addr
[4] = top
& 0xff;
208 addr
[5] = (top
>> 8) & 0xff;
211 if (is_valid_ether_addr(addr
)) {
212 memcpy(bp
->dev
->dev_addr
, addr
, sizeof(addr
));
217 dev_info(&bp
->pdev
->dev
, "invalid hw address, using random\n");
218 eth_hw_addr_random(bp
->dev
);
221 static int macb_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
223 struct macb
*bp
= bus
->priv
;
226 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
227 | MACB_BF(RW
, MACB_MAN_READ
)
228 | MACB_BF(PHYA
, mii_id
)
229 | MACB_BF(REGA
, regnum
)
230 | MACB_BF(CODE
, MACB_MAN_CODE
)));
232 /* wait for end of transfer */
233 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
236 value
= MACB_BFEXT(DATA
, macb_readl(bp
, MAN
));
241 static int macb_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
244 struct macb
*bp
= bus
->priv
;
246 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
247 | MACB_BF(RW
, MACB_MAN_WRITE
)
248 | MACB_BF(PHYA
, mii_id
)
249 | MACB_BF(REGA
, regnum
)
250 | MACB_BF(CODE
, MACB_MAN_CODE
)
251 | MACB_BF(DATA
, value
)));
253 /* wait for end of transfer */
254 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
261 * macb_set_tx_clk() - Set a clock to a new frequency
262 * @clk Pointer to the clock to change
263 * @rate New frequency in Hz
264 * @dev Pointer to the struct net_device
266 static void macb_set_tx_clk(struct clk
*clk
, int speed
, struct net_device
*dev
)
268 long ferr
, rate
, rate_rounded
;
287 rate_rounded
= clk_round_rate(clk
, rate
);
288 if (rate_rounded
< 0)
291 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
294 ferr
= abs(rate_rounded
- rate
);
295 ferr
= DIV_ROUND_UP(ferr
, rate
/ 100000);
297 netdev_warn(dev
, "unable to generate target frequency: %ld Hz\n",
300 if (clk_set_rate(clk
, rate_rounded
))
301 netdev_err(dev
, "adjusting tx_clk failed.\n");
304 static void macb_handle_link_change(struct net_device
*dev
)
306 struct macb
*bp
= netdev_priv(dev
);
307 struct phy_device
*phydev
= dev
->phydev
;
309 int status_change
= 0;
311 spin_lock_irqsave(&bp
->lock
, flags
);
314 if ((bp
->speed
!= phydev
->speed
) ||
315 (bp
->duplex
!= phydev
->duplex
)) {
318 reg
= macb_readl(bp
, NCFGR
);
319 reg
&= ~(MACB_BIT(SPD
) | MACB_BIT(FD
));
321 reg
&= ~GEM_BIT(GBE
);
325 if (phydev
->speed
== SPEED_100
)
326 reg
|= MACB_BIT(SPD
);
327 if (phydev
->speed
== SPEED_1000
&&
328 bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
331 macb_or_gem_writel(bp
, NCFGR
, reg
);
333 bp
->speed
= phydev
->speed
;
334 bp
->duplex
= phydev
->duplex
;
339 if (phydev
->link
!= bp
->link
) {
344 bp
->link
= phydev
->link
;
349 spin_unlock_irqrestore(&bp
->lock
, flags
);
353 /* Update the TX clock rate if and only if the link is
354 * up and there has been a link change.
356 macb_set_tx_clk(bp
->tx_clk
, phydev
->speed
, dev
);
358 netif_carrier_on(dev
);
359 netdev_info(dev
, "link up (%d/%s)\n",
361 phydev
->duplex
== DUPLEX_FULL
?
364 netif_carrier_off(dev
);
365 netdev_info(dev
, "link down\n");
370 /* based on au1000_eth. c*/
371 static int macb_mii_probe(struct net_device
*dev
)
373 struct macb
*bp
= netdev_priv(dev
);
374 struct macb_platform_data
*pdata
;
375 struct phy_device
*phydev
;
379 phydev
= phy_find_first(bp
->mii_bus
);
381 netdev_err(dev
, "no PHY found\n");
385 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
386 if (pdata
&& gpio_is_valid(pdata
->phy_irq_pin
)) {
387 ret
= devm_gpio_request(&bp
->pdev
->dev
, pdata
->phy_irq_pin
,
390 phy_irq
= gpio_to_irq(pdata
->phy_irq_pin
);
391 phydev
->irq
= (phy_irq
< 0) ? PHY_POLL
: phy_irq
;
395 /* attach the mac to the phy */
396 ret
= phy_connect_direct(dev
, phydev
, &macb_handle_link_change
,
399 netdev_err(dev
, "Could not attach to PHY\n");
403 /* mask with MAC supported features */
404 if (macb_is_gem(bp
) && bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
405 phydev
->supported
&= PHY_GBIT_FEATURES
;
407 phydev
->supported
&= PHY_BASIC_FEATURES
;
409 if (bp
->caps
& MACB_CAPS_NO_GIGABIT_HALF
)
410 phydev
->supported
&= ~SUPPORTED_1000baseT_Half
;
412 phydev
->advertising
= phydev
->supported
;
421 static int macb_mii_init(struct macb
*bp
)
423 struct macb_platform_data
*pdata
;
424 struct device_node
*np
;
427 /* Enable management port */
428 macb_writel(bp
, NCR
, MACB_BIT(MPE
));
430 bp
->mii_bus
= mdiobus_alloc();
436 bp
->mii_bus
->name
= "MACB_mii_bus";
437 bp
->mii_bus
->read
= &macb_mdio_read
;
438 bp
->mii_bus
->write
= &macb_mdio_write
;
439 snprintf(bp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
440 bp
->pdev
->name
, bp
->pdev
->id
);
441 bp
->mii_bus
->priv
= bp
;
442 bp
->mii_bus
->parent
= &bp
->pdev
->dev
;
443 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
445 dev_set_drvdata(&bp
->dev
->dev
, bp
->mii_bus
);
447 np
= bp
->pdev
->dev
.of_node
;
449 /* try dt phy registration */
450 err
= of_mdiobus_register(bp
->mii_bus
, np
);
452 /* fallback to standard phy registration if no phy were
453 * found during dt phy registration
455 if (!err
&& !phy_find_first(bp
->mii_bus
)) {
456 for (i
= 0; i
< PHY_MAX_ADDR
; i
++) {
457 struct phy_device
*phydev
;
459 phydev
= mdiobus_scan(bp
->mii_bus
, i
);
460 if (IS_ERR(phydev
) &&
461 PTR_ERR(phydev
) != -ENODEV
) {
462 err
= PTR_ERR(phydev
);
468 goto err_out_unregister_bus
;
472 bp
->mii_bus
->phy_mask
= pdata
->phy_mask
;
474 err
= mdiobus_register(bp
->mii_bus
);
478 goto err_out_free_mdiobus
;
480 err
= macb_mii_probe(bp
->dev
);
482 goto err_out_unregister_bus
;
486 err_out_unregister_bus
:
487 mdiobus_unregister(bp
->mii_bus
);
488 err_out_free_mdiobus
:
489 mdiobus_free(bp
->mii_bus
);
494 static void macb_update_stats(struct macb
*bp
)
496 u32
*p
= &bp
->hw_stats
.macb
.rx_pause_frames
;
497 u32
*end
= &bp
->hw_stats
.macb
.tx_pause_frames
+ 1;
498 int offset
= MACB_PFR
;
500 WARN_ON((unsigned long)(end
- p
- 1) != (MACB_TPF
- MACB_PFR
) / 4);
502 for (; p
< end
; p
++, offset
+= 4)
503 *p
+= bp
->macb_reg_readl(bp
, offset
);
506 static int macb_halt_tx(struct macb
*bp
)
508 unsigned long halt_time
, timeout
;
511 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(THALT
));
513 timeout
= jiffies
+ usecs_to_jiffies(MACB_HALT_TIMEOUT
);
516 status
= macb_readl(bp
, TSR
);
517 if (!(status
& MACB_BIT(TGO
)))
520 usleep_range(10, 250);
521 } while (time_before(halt_time
, timeout
));
526 static void macb_tx_unmap(struct macb
*bp
, struct macb_tx_skb
*tx_skb
)
528 if (tx_skb
->mapping
) {
529 if (tx_skb
->mapped_as_page
)
530 dma_unmap_page(&bp
->pdev
->dev
, tx_skb
->mapping
,
531 tx_skb
->size
, DMA_TO_DEVICE
);
533 dma_unmap_single(&bp
->pdev
->dev
, tx_skb
->mapping
,
534 tx_skb
->size
, DMA_TO_DEVICE
);
539 dev_kfree_skb_any(tx_skb
->skb
);
544 static void macb_tx_error_task(struct work_struct
*work
)
546 struct macb_queue
*queue
= container_of(work
, struct macb_queue
,
548 struct macb
*bp
= queue
->bp
;
549 struct macb_tx_skb
*tx_skb
;
550 struct macb_dma_desc
*desc
;
555 netdev_vdbg(bp
->dev
, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
556 (unsigned int)(queue
- bp
->queues
),
557 queue
->tx_tail
, queue
->tx_head
);
559 /* Prevent the queue IRQ handlers from running: each of them may call
560 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
561 * As explained below, we have to halt the transmission before updating
562 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
563 * network engine about the macb/gem being halted.
565 spin_lock_irqsave(&bp
->lock
, flags
);
567 /* Make sure nobody is trying to queue up new packets */
568 netif_tx_stop_all_queues(bp
->dev
);
570 /* Stop transmission now
571 * (in case we have just queued new packets)
572 * macb/gem must be halted to write TBQP register
574 if (macb_halt_tx(bp
))
575 /* Just complain for now, reinitializing TX path can be good */
576 netdev_err(bp
->dev
, "BUG: halt tx timed out\n");
578 /* Treat frames in TX queue including the ones that caused the error.
579 * Free transmit buffers in upper layer.
581 for (tail
= queue
->tx_tail
; tail
!= queue
->tx_head
; tail
++) {
584 desc
= macb_tx_desc(queue
, tail
);
586 tx_skb
= macb_tx_skb(queue
, tail
);
589 if (ctrl
& MACB_BIT(TX_USED
)) {
590 /* skb is set for the last buffer of the frame */
592 macb_tx_unmap(bp
, tx_skb
);
594 tx_skb
= macb_tx_skb(queue
, tail
);
598 /* ctrl still refers to the first buffer descriptor
599 * since it's the only one written back by the hardware
601 if (!(ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))) {
602 netdev_vdbg(bp
->dev
, "txerr skb %u (data %p) TX complete\n",
603 macb_tx_ring_wrap(tail
), skb
->data
);
604 bp
->stats
.tx_packets
++;
605 bp
->stats
.tx_bytes
+= skb
->len
;
608 /* "Buffers exhausted mid-frame" errors may only happen
609 * if the driver is buggy, so complain loudly about
610 * those. Statistics are updated by hardware.
612 if (ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))
614 "BUG: TX buffers exhausted mid-frame\n");
616 desc
->ctrl
= ctrl
| MACB_BIT(TX_USED
);
619 macb_tx_unmap(bp
, tx_skb
);
622 /* Set end of TX queue */
623 desc
= macb_tx_desc(queue
, 0);
625 desc
->ctrl
= MACB_BIT(TX_USED
);
627 /* Make descriptor updates visible to hardware */
630 /* Reinitialize the TX desc queue */
631 queue_writel(queue
, TBQP
, queue
->tx_ring_dma
);
632 /* Make TX ring reflect state of hardware */
636 /* Housework before enabling TX IRQ */
637 macb_writel(bp
, TSR
, macb_readl(bp
, TSR
));
638 queue_writel(queue
, IER
, MACB_TX_INT_FLAGS
);
640 /* Now we are ready to start transmission again */
641 netif_tx_start_all_queues(bp
->dev
);
642 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
644 spin_unlock_irqrestore(&bp
->lock
, flags
);
647 static void macb_tx_interrupt(struct macb_queue
*queue
)
652 struct macb
*bp
= queue
->bp
;
653 u16 queue_index
= queue
- bp
->queues
;
655 status
= macb_readl(bp
, TSR
);
656 macb_writel(bp
, TSR
, status
);
658 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
659 queue_writel(queue
, ISR
, MACB_BIT(TCOMP
));
661 netdev_vdbg(bp
->dev
, "macb_tx_interrupt status = 0x%03lx\n",
662 (unsigned long)status
);
664 head
= queue
->tx_head
;
665 for (tail
= queue
->tx_tail
; tail
!= head
; tail
++) {
666 struct macb_tx_skb
*tx_skb
;
668 struct macb_dma_desc
*desc
;
671 desc
= macb_tx_desc(queue
, tail
);
673 /* Make hw descriptor updates visible to CPU */
678 /* TX_USED bit is only set by hardware on the very first buffer
679 * descriptor of the transmitted frame.
681 if (!(ctrl
& MACB_BIT(TX_USED
)))
684 /* Process all buffers of the current transmitted frame */
686 tx_skb
= macb_tx_skb(queue
, tail
);
689 /* First, update TX stats if needed */
691 netdev_vdbg(bp
->dev
, "skb %u (data %p) TX complete\n",
692 macb_tx_ring_wrap(tail
), skb
->data
);
693 bp
->stats
.tx_packets
++;
694 bp
->stats
.tx_bytes
+= skb
->len
;
697 /* Now we can safely release resources */
698 macb_tx_unmap(bp
, tx_skb
);
700 /* skb is set only for the last buffer of the frame.
701 * WARNING: at this point skb has been freed by
709 queue
->tx_tail
= tail
;
710 if (__netif_subqueue_stopped(bp
->dev
, queue_index
) &&
711 CIRC_CNT(queue
->tx_head
, queue
->tx_tail
,
712 TX_RING_SIZE
) <= MACB_TX_WAKEUP_THRESH
)
713 netif_wake_subqueue(bp
->dev
, queue_index
);
716 static void gem_rx_refill(struct macb
*bp
)
722 while (CIRC_SPACE(bp
->rx_prepared_head
, bp
->rx_tail
,
724 entry
= macb_rx_ring_wrap(bp
->rx_prepared_head
);
726 /* Make hw descriptor updates visible to CPU */
729 bp
->rx_prepared_head
++;
731 if (!bp
->rx_skbuff
[entry
]) {
732 /* allocate sk_buff for this free entry in ring */
733 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buffer_size
);
734 if (unlikely(!skb
)) {
736 "Unable to allocate sk_buff\n");
740 /* now fill corresponding descriptor entry */
741 paddr
= dma_map_single(&bp
->pdev
->dev
, skb
->data
,
744 if (dma_mapping_error(&bp
->pdev
->dev
, paddr
)) {
749 bp
->rx_skbuff
[entry
] = skb
;
751 if (entry
== RX_RING_SIZE
- 1)
752 paddr
|= MACB_BIT(RX_WRAP
);
753 bp
->rx_ring
[entry
].addr
= paddr
;
754 bp
->rx_ring
[entry
].ctrl
= 0;
756 /* properly align Ethernet header */
757 skb_reserve(skb
, NET_IP_ALIGN
);
759 bp
->rx_ring
[entry
].addr
&= ~MACB_BIT(RX_USED
);
760 bp
->rx_ring
[entry
].ctrl
= 0;
764 /* Make descriptor updates visible to hardware */
767 netdev_vdbg(bp
->dev
, "rx ring: prepared head %d, tail %d\n",
768 bp
->rx_prepared_head
, bp
->rx_tail
);
771 /* Mark DMA descriptors from begin up to and not including end as unused */
772 static void discard_partial_frame(struct macb
*bp
, unsigned int begin
,
777 for (frag
= begin
; frag
!= end
; frag
++) {
778 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, frag
);
780 desc
->addr
&= ~MACB_BIT(RX_USED
);
783 /* Make descriptor updates visible to hardware */
786 /* When this happens, the hardware stats registers for
787 * whatever caused this is updated, so we don't have to record
792 static int gem_rx(struct macb
*bp
, int budget
)
797 struct macb_dma_desc
*desc
;
800 while (count
< budget
) {
803 entry
= macb_rx_ring_wrap(bp
->rx_tail
);
804 desc
= &bp
->rx_ring
[entry
];
806 /* Make hw descriptor updates visible to CPU */
812 if (!(addr
& MACB_BIT(RX_USED
)))
818 if (!(ctrl
& MACB_BIT(RX_SOF
) && ctrl
& MACB_BIT(RX_EOF
))) {
820 "not whole frame pointed by descriptor\n");
821 bp
->stats
.rx_dropped
++;
824 skb
= bp
->rx_skbuff
[entry
];
825 if (unlikely(!skb
)) {
827 "inconsistent Rx descriptor chain\n");
828 bp
->stats
.rx_dropped
++;
831 /* now everything is ready for receiving packet */
832 bp
->rx_skbuff
[entry
] = NULL
;
833 len
= ctrl
& bp
->rx_frm_len_mask
;
835 netdev_vdbg(bp
->dev
, "gem_rx %u (len %u)\n", entry
, len
);
838 addr
= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, addr
));
839 dma_unmap_single(&bp
->pdev
->dev
, addr
,
840 bp
->rx_buffer_size
, DMA_FROM_DEVICE
);
842 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
843 skb_checksum_none_assert(skb
);
844 if (bp
->dev
->features
& NETIF_F_RXCSUM
&&
845 !(bp
->dev
->flags
& IFF_PROMISC
) &&
846 GEM_BFEXT(RX_CSUM
, ctrl
) & GEM_RX_CSUM_CHECKED_MASK
)
847 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
849 bp
->stats
.rx_packets
++;
850 bp
->stats
.rx_bytes
+= skb
->len
;
852 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
853 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
854 skb
->len
, skb
->csum
);
855 print_hex_dump(KERN_DEBUG
, " mac: ", DUMP_PREFIX_ADDRESS
, 16, 1,
856 skb_mac_header(skb
), 16, true);
857 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_ADDRESS
, 16, 1,
858 skb
->data
, 32, true);
861 netif_receive_skb(skb
);
869 static int macb_rx_frame(struct macb
*bp
, unsigned int first_frag
,
870 unsigned int last_frag
)
876 struct macb_dma_desc
*desc
;
878 desc
= macb_rx_desc(bp
, last_frag
);
879 len
= desc
->ctrl
& bp
->rx_frm_len_mask
;
881 netdev_vdbg(bp
->dev
, "macb_rx_frame frags %u - %u (len %u)\n",
882 macb_rx_ring_wrap(first_frag
),
883 macb_rx_ring_wrap(last_frag
), len
);
885 /* The ethernet header starts NET_IP_ALIGN bytes into the
886 * first buffer. Since the header is 14 bytes, this makes the
887 * payload word-aligned.
889 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
890 * the two padding bytes into the skb so that we avoid hitting
891 * the slowpath in memcpy(), and pull them off afterwards.
893 skb
= netdev_alloc_skb(bp
->dev
, len
+ NET_IP_ALIGN
);
895 bp
->stats
.rx_dropped
++;
896 for (frag
= first_frag
; ; frag
++) {
897 desc
= macb_rx_desc(bp
, frag
);
898 desc
->addr
&= ~MACB_BIT(RX_USED
);
899 if (frag
== last_frag
)
903 /* Make descriptor updates visible to hardware */
911 skb_checksum_none_assert(skb
);
914 for (frag
= first_frag
; ; frag
++) {
915 unsigned int frag_len
= bp
->rx_buffer_size
;
917 if (offset
+ frag_len
> len
) {
918 if (unlikely(frag
!= last_frag
)) {
919 dev_kfree_skb_any(skb
);
922 frag_len
= len
- offset
;
924 skb_copy_to_linear_data_offset(skb
, offset
,
925 macb_rx_buffer(bp
, frag
),
927 offset
+= bp
->rx_buffer_size
;
928 desc
= macb_rx_desc(bp
, frag
);
929 desc
->addr
&= ~MACB_BIT(RX_USED
);
931 if (frag
== last_frag
)
935 /* Make descriptor updates visible to hardware */
938 __skb_pull(skb
, NET_IP_ALIGN
);
939 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
941 bp
->stats
.rx_packets
++;
942 bp
->stats
.rx_bytes
+= skb
->len
;
943 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
944 skb
->len
, skb
->csum
);
945 netif_receive_skb(skb
);
950 static inline void macb_init_rx_ring(struct macb
*bp
)
955 addr
= bp
->rx_buffers_dma
;
956 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
957 bp
->rx_ring
[i
].addr
= addr
;
958 bp
->rx_ring
[i
].ctrl
= 0;
959 addr
+= bp
->rx_buffer_size
;
961 bp
->rx_ring
[RX_RING_SIZE
- 1].addr
|= MACB_BIT(RX_WRAP
);
964 static int macb_rx(struct macb
*bp
, int budget
)
966 bool reset_rx_queue
= false;
971 for (tail
= bp
->rx_tail
; budget
> 0; tail
++) {
972 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, tail
);
975 /* Make hw descriptor updates visible to CPU */
981 if (!(addr
& MACB_BIT(RX_USED
)))
984 if (ctrl
& MACB_BIT(RX_SOF
)) {
985 if (first_frag
!= -1)
986 discard_partial_frame(bp
, first_frag
, tail
);
990 if (ctrl
& MACB_BIT(RX_EOF
)) {
993 if (unlikely(first_frag
== -1)) {
994 reset_rx_queue
= true;
998 dropped
= macb_rx_frame(bp
, first_frag
, tail
);
1000 if (unlikely(dropped
< 0)) {
1001 reset_rx_queue
= true;
1011 if (unlikely(reset_rx_queue
)) {
1012 unsigned long flags
;
1015 netdev_err(bp
->dev
, "RX queue corruption: reset it\n");
1017 spin_lock_irqsave(&bp
->lock
, flags
);
1019 ctrl
= macb_readl(bp
, NCR
);
1020 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1022 macb_init_rx_ring(bp
);
1023 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1025 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1027 spin_unlock_irqrestore(&bp
->lock
, flags
);
1031 if (first_frag
!= -1)
1032 bp
->rx_tail
= first_frag
;
1039 static int macb_poll(struct napi_struct
*napi
, int budget
)
1041 struct macb
*bp
= container_of(napi
, struct macb
, napi
);
1045 status
= macb_readl(bp
, RSR
);
1046 macb_writel(bp
, RSR
, status
);
1050 netdev_vdbg(bp
->dev
, "poll: status = %08lx, budget = %d\n",
1051 (unsigned long)status
, budget
);
1053 work_done
= bp
->macbgem_ops
.mog_rx(bp
, budget
);
1054 if (work_done
< budget
) {
1055 napi_complete(napi
);
1057 /* Packets received while interrupts were disabled */
1058 status
= macb_readl(bp
, RSR
);
1060 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1061 macb_writel(bp
, ISR
, MACB_BIT(RCOMP
));
1062 napi_reschedule(napi
);
1064 macb_writel(bp
, IER
, MACB_RX_INT_FLAGS
);
1068 /* TODO: Handle errors */
1073 static irqreturn_t
macb_interrupt(int irq
, void *dev_id
)
1075 struct macb_queue
*queue
= dev_id
;
1076 struct macb
*bp
= queue
->bp
;
1077 struct net_device
*dev
= bp
->dev
;
1080 status
= queue_readl(queue
, ISR
);
1082 if (unlikely(!status
))
1085 spin_lock(&bp
->lock
);
1088 /* close possible race with dev_close */
1089 if (unlikely(!netif_running(dev
))) {
1090 queue_writel(queue
, IDR
, -1);
1091 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1092 queue_writel(queue
, ISR
, -1);
1096 netdev_vdbg(bp
->dev
, "queue = %u, isr = 0x%08lx\n",
1097 (unsigned int)(queue
- bp
->queues
),
1098 (unsigned long)status
);
1100 if (status
& MACB_RX_INT_FLAGS
) {
1101 /* There's no point taking any more interrupts
1102 * until we have processed the buffers. The
1103 * scheduling call may fail if the poll routine
1104 * is already scheduled, so disable interrupts
1107 queue_writel(queue
, IDR
, MACB_RX_INT_FLAGS
);
1108 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1109 queue_writel(queue
, ISR
, MACB_BIT(RCOMP
));
1111 if (napi_schedule_prep(&bp
->napi
)) {
1112 netdev_vdbg(bp
->dev
, "scheduling RX softirq\n");
1113 __napi_schedule(&bp
->napi
);
1117 if (unlikely(status
& (MACB_TX_ERR_FLAGS
))) {
1118 queue_writel(queue
, IDR
, MACB_TX_INT_FLAGS
);
1119 schedule_work(&queue
->tx_error_task
);
1121 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1122 queue_writel(queue
, ISR
, MACB_TX_ERR_FLAGS
);
1127 if (status
& MACB_BIT(TCOMP
))
1128 macb_tx_interrupt(queue
);
1130 /* Link change detection isn't possible with RMII, so we'll
1131 * add that if/when we get our hands on a full-blown MII PHY.
1134 /* There is a hardware issue under heavy load where DMA can
1135 * stop, this causes endless "used buffer descriptor read"
1136 * interrupts but it can be cleared by re-enabling RX. See
1137 * the at91 manual, section 41.3.1 or the Zynq manual
1138 * section 16.7.4 for details.
1140 if (status
& MACB_BIT(RXUBR
)) {
1141 ctrl
= macb_readl(bp
, NCR
);
1142 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1143 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1145 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1146 queue_writel(queue
, ISR
, MACB_BIT(RXUBR
));
1149 if (status
& MACB_BIT(ISR_ROVR
)) {
1150 /* We missed at least one packet */
1151 if (macb_is_gem(bp
))
1152 bp
->hw_stats
.gem
.rx_overruns
++;
1154 bp
->hw_stats
.macb
.rx_overruns
++;
1156 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1157 queue_writel(queue
, ISR
, MACB_BIT(ISR_ROVR
));
1160 if (status
& MACB_BIT(HRESP
)) {
1161 /* TODO: Reset the hardware, and maybe move the
1162 * netdev_err to a lower-priority context as well
1165 netdev_err(dev
, "DMA bus error: HRESP not OK\n");
1167 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1168 queue_writel(queue
, ISR
, MACB_BIT(HRESP
));
1171 status
= queue_readl(queue
, ISR
);
1174 spin_unlock(&bp
->lock
);
1179 #ifdef CONFIG_NET_POLL_CONTROLLER
1180 /* Polling receive - used by netconsole and other diagnostic tools
1181 * to allow network i/o with interrupts disabled.
1183 static void macb_poll_controller(struct net_device
*dev
)
1185 struct macb
*bp
= netdev_priv(dev
);
1186 struct macb_queue
*queue
;
1187 unsigned long flags
;
1190 local_irq_save(flags
);
1191 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
)
1192 macb_interrupt(dev
->irq
, queue
);
1193 local_irq_restore(flags
);
1197 static unsigned int macb_tx_map(struct macb
*bp
,
1198 struct macb_queue
*queue
,
1199 struct sk_buff
*skb
)
1202 unsigned int len
, entry
, i
, tx_head
= queue
->tx_head
;
1203 struct macb_tx_skb
*tx_skb
= NULL
;
1204 struct macb_dma_desc
*desc
;
1205 unsigned int offset
, size
, count
= 0;
1206 unsigned int f
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1207 unsigned int eof
= 1;
1210 /* First, map non-paged data */
1211 len
= skb_headlen(skb
);
1214 size
= min(len
, bp
->max_tx_length
);
1215 entry
= macb_tx_ring_wrap(tx_head
);
1216 tx_skb
= &queue
->tx_skb
[entry
];
1218 mapping
= dma_map_single(&bp
->pdev
->dev
,
1220 size
, DMA_TO_DEVICE
);
1221 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1224 /* Save info to properly release resources */
1226 tx_skb
->mapping
= mapping
;
1227 tx_skb
->size
= size
;
1228 tx_skb
->mapped_as_page
= false;
1236 /* Then, map paged data from fragments */
1237 for (f
= 0; f
< nr_frags
; f
++) {
1238 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[f
];
1240 len
= skb_frag_size(frag
);
1243 size
= min(len
, bp
->max_tx_length
);
1244 entry
= macb_tx_ring_wrap(tx_head
);
1245 tx_skb
= &queue
->tx_skb
[entry
];
1247 mapping
= skb_frag_dma_map(&bp
->pdev
->dev
, frag
,
1248 offset
, size
, DMA_TO_DEVICE
);
1249 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1252 /* Save info to properly release resources */
1254 tx_skb
->mapping
= mapping
;
1255 tx_skb
->size
= size
;
1256 tx_skb
->mapped_as_page
= true;
1265 /* Should never happen */
1266 if (unlikely(!tx_skb
)) {
1267 netdev_err(bp
->dev
, "BUG! empty skb!\n");
1271 /* This is the last buffer of the frame: save socket buffer */
1274 /* Update TX ring: update buffer descriptors in reverse order
1275 * to avoid race condition
1278 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1279 * to set the end of TX queue
1282 entry
= macb_tx_ring_wrap(i
);
1283 ctrl
= MACB_BIT(TX_USED
);
1284 desc
= &queue
->tx_ring
[entry
];
1289 entry
= macb_tx_ring_wrap(i
);
1290 tx_skb
= &queue
->tx_skb
[entry
];
1291 desc
= &queue
->tx_ring
[entry
];
1293 ctrl
= (u32
)tx_skb
->size
;
1295 ctrl
|= MACB_BIT(TX_LAST
);
1298 if (unlikely(entry
== (TX_RING_SIZE
- 1)))
1299 ctrl
|= MACB_BIT(TX_WRAP
);
1301 /* Set TX buffer descriptor */
1302 desc
->addr
= tx_skb
->mapping
;
1303 /* desc->addr must be visible to hardware before clearing
1304 * 'TX_USED' bit in desc->ctrl.
1308 } while (i
!= queue
->tx_head
);
1310 queue
->tx_head
= tx_head
;
1315 netdev_err(bp
->dev
, "TX DMA map failed\n");
1317 for (i
= queue
->tx_head
; i
!= tx_head
; i
++) {
1318 tx_skb
= macb_tx_skb(queue
, i
);
1320 macb_tx_unmap(bp
, tx_skb
);
1326 static int macb_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1328 u16 queue_index
= skb_get_queue_mapping(skb
);
1329 struct macb
*bp
= netdev_priv(dev
);
1330 struct macb_queue
*queue
= &bp
->queues
[queue_index
];
1331 unsigned long flags
;
1332 unsigned int count
, nr_frags
, frag_size
, f
;
1334 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1335 netdev_vdbg(bp
->dev
,
1336 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1337 queue_index
, skb
->len
, skb
->head
, skb
->data
,
1338 skb_tail_pointer(skb
), skb_end_pointer(skb
));
1339 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_OFFSET
, 16, 1,
1340 skb
->data
, 16, true);
1343 /* Count how many TX buffer descriptors are needed to send this
1344 * socket buffer: skb fragments of jumbo frames may need to be
1345 * split into many buffer descriptors.
1347 count
= DIV_ROUND_UP(skb_headlen(skb
), bp
->max_tx_length
);
1348 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1349 for (f
= 0; f
< nr_frags
; f
++) {
1350 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[f
]);
1351 count
+= DIV_ROUND_UP(frag_size
, bp
->max_tx_length
);
1354 spin_lock_irqsave(&bp
->lock
, flags
);
1356 /* This is a hard error, log it. */
1357 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, TX_RING_SIZE
) < count
) {
1358 netif_stop_subqueue(dev
, queue_index
);
1359 spin_unlock_irqrestore(&bp
->lock
, flags
);
1360 netdev_dbg(bp
->dev
, "tx_head = %u, tx_tail = %u\n",
1361 queue
->tx_head
, queue
->tx_tail
);
1362 return NETDEV_TX_BUSY
;
1365 /* Map socket buffer for DMA transfer */
1366 if (!macb_tx_map(bp
, queue
, skb
)) {
1367 dev_kfree_skb_any(skb
);
1371 /* Make newly initialized descriptor visible to hardware */
1374 skb_tx_timestamp(skb
);
1376 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
1378 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, TX_RING_SIZE
) < 1)
1379 netif_stop_subqueue(dev
, queue_index
);
1382 spin_unlock_irqrestore(&bp
->lock
, flags
);
1384 return NETDEV_TX_OK
;
1387 static void macb_init_rx_buffer_size(struct macb
*bp
, size_t size
)
1389 if (!macb_is_gem(bp
)) {
1390 bp
->rx_buffer_size
= MACB_RX_BUFFER_SIZE
;
1392 bp
->rx_buffer_size
= size
;
1394 if (bp
->rx_buffer_size
% RX_BUFFER_MULTIPLE
) {
1396 "RX buffer must be multiple of %d bytes, expanding\n",
1397 RX_BUFFER_MULTIPLE
);
1398 bp
->rx_buffer_size
=
1399 roundup(bp
->rx_buffer_size
, RX_BUFFER_MULTIPLE
);
1403 netdev_dbg(bp
->dev
, "mtu [%u] rx_buffer_size [%Zu]\n",
1404 bp
->dev
->mtu
, bp
->rx_buffer_size
);
1407 static void gem_free_rx_buffers(struct macb
*bp
)
1409 struct sk_buff
*skb
;
1410 struct macb_dma_desc
*desc
;
1417 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1418 skb
= bp
->rx_skbuff
[i
];
1423 desc
= &bp
->rx_ring
[i
];
1424 addr
= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, desc
->addr
));
1425 dma_unmap_single(&bp
->pdev
->dev
, addr
, bp
->rx_buffer_size
,
1427 dev_kfree_skb_any(skb
);
1431 kfree(bp
->rx_skbuff
);
1432 bp
->rx_skbuff
= NULL
;
1435 static void macb_free_rx_buffers(struct macb
*bp
)
1437 if (bp
->rx_buffers
) {
1438 dma_free_coherent(&bp
->pdev
->dev
,
1439 RX_RING_SIZE
* bp
->rx_buffer_size
,
1440 bp
->rx_buffers
, bp
->rx_buffers_dma
);
1441 bp
->rx_buffers
= NULL
;
1445 static void macb_free_consistent(struct macb
*bp
)
1447 struct macb_queue
*queue
;
1450 bp
->macbgem_ops
.mog_free_rx_buffers(bp
);
1452 dma_free_coherent(&bp
->pdev
->dev
, RX_RING_BYTES
,
1453 bp
->rx_ring
, bp
->rx_ring_dma
);
1457 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1458 kfree(queue
->tx_skb
);
1459 queue
->tx_skb
= NULL
;
1460 if (queue
->tx_ring
) {
1461 dma_free_coherent(&bp
->pdev
->dev
, TX_RING_BYTES
,
1462 queue
->tx_ring
, queue
->tx_ring_dma
);
1463 queue
->tx_ring
= NULL
;
1468 static int gem_alloc_rx_buffers(struct macb
*bp
)
1472 size
= RX_RING_SIZE
* sizeof(struct sk_buff
*);
1473 bp
->rx_skbuff
= kzalloc(size
, GFP_KERNEL
);
1478 "Allocated %d RX struct sk_buff entries at %p\n",
1479 RX_RING_SIZE
, bp
->rx_skbuff
);
1483 static int macb_alloc_rx_buffers(struct macb
*bp
)
1487 size
= RX_RING_SIZE
* bp
->rx_buffer_size
;
1488 bp
->rx_buffers
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1489 &bp
->rx_buffers_dma
, GFP_KERNEL
);
1490 if (!bp
->rx_buffers
)
1494 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1495 size
, (unsigned long)bp
->rx_buffers_dma
, bp
->rx_buffers
);
1499 static int macb_alloc_consistent(struct macb
*bp
)
1501 struct macb_queue
*queue
;
1505 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1506 size
= TX_RING_BYTES
;
1507 queue
->tx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1508 &queue
->tx_ring_dma
,
1510 if (!queue
->tx_ring
)
1513 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1514 q
, size
, (unsigned long)queue
->tx_ring_dma
,
1517 size
= TX_RING_SIZE
* sizeof(struct macb_tx_skb
);
1518 queue
->tx_skb
= kmalloc(size
, GFP_KERNEL
);
1523 size
= RX_RING_BYTES
;
1524 bp
->rx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1525 &bp
->rx_ring_dma
, GFP_KERNEL
);
1529 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1530 size
, (unsigned long)bp
->rx_ring_dma
, bp
->rx_ring
);
1532 if (bp
->macbgem_ops
.mog_alloc_rx_buffers(bp
))
1538 macb_free_consistent(bp
);
1542 static void gem_init_rings(struct macb
*bp
)
1544 struct macb_queue
*queue
;
1548 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1549 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1550 queue
->tx_ring
[i
].addr
= 0;
1551 queue
->tx_ring
[i
].ctrl
= MACB_BIT(TX_USED
);
1553 queue
->tx_ring
[TX_RING_SIZE
- 1].ctrl
|= MACB_BIT(TX_WRAP
);
1559 bp
->rx_prepared_head
= 0;
1564 static void macb_init_rings(struct macb
*bp
)
1568 macb_init_rx_ring(bp
);
1570 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1571 bp
->queues
[0].tx_ring
[i
].addr
= 0;
1572 bp
->queues
[0].tx_ring
[i
].ctrl
= MACB_BIT(TX_USED
);
1574 bp
->queues
[0].tx_head
= 0;
1575 bp
->queues
[0].tx_tail
= 0;
1576 bp
->queues
[0].tx_ring
[TX_RING_SIZE
- 1].ctrl
|= MACB_BIT(TX_WRAP
);
1581 static void macb_reset_hw(struct macb
*bp
)
1583 struct macb_queue
*queue
;
1586 /* Disable RX and TX (XXX: Should we halt the transmission
1589 macb_writel(bp
, NCR
, 0);
1591 /* Clear the stats registers (XXX: Update stats first?) */
1592 macb_writel(bp
, NCR
, MACB_BIT(CLRSTAT
));
1594 /* Clear all status flags */
1595 macb_writel(bp
, TSR
, -1);
1596 macb_writel(bp
, RSR
, -1);
1598 /* Disable all interrupts */
1599 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1600 queue_writel(queue
, IDR
, -1);
1601 queue_readl(queue
, ISR
);
1602 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1603 queue_writel(queue
, ISR
, -1);
1607 static u32
gem_mdc_clk_div(struct macb
*bp
)
1610 unsigned long pclk_hz
= clk_get_rate(bp
->pclk
);
1612 if (pclk_hz
<= 20000000)
1613 config
= GEM_BF(CLK
, GEM_CLK_DIV8
);
1614 else if (pclk_hz
<= 40000000)
1615 config
= GEM_BF(CLK
, GEM_CLK_DIV16
);
1616 else if (pclk_hz
<= 80000000)
1617 config
= GEM_BF(CLK
, GEM_CLK_DIV32
);
1618 else if (pclk_hz
<= 120000000)
1619 config
= GEM_BF(CLK
, GEM_CLK_DIV48
);
1620 else if (pclk_hz
<= 160000000)
1621 config
= GEM_BF(CLK
, GEM_CLK_DIV64
);
1623 config
= GEM_BF(CLK
, GEM_CLK_DIV96
);
1628 static u32
macb_mdc_clk_div(struct macb
*bp
)
1631 unsigned long pclk_hz
;
1633 if (macb_is_gem(bp
))
1634 return gem_mdc_clk_div(bp
);
1636 pclk_hz
= clk_get_rate(bp
->pclk
);
1637 if (pclk_hz
<= 20000000)
1638 config
= MACB_BF(CLK
, MACB_CLK_DIV8
);
1639 else if (pclk_hz
<= 40000000)
1640 config
= MACB_BF(CLK
, MACB_CLK_DIV16
);
1641 else if (pclk_hz
<= 80000000)
1642 config
= MACB_BF(CLK
, MACB_CLK_DIV32
);
1644 config
= MACB_BF(CLK
, MACB_CLK_DIV64
);
1649 /* Get the DMA bus width field of the network configuration register that we
1650 * should program. We find the width from decoding the design configuration
1651 * register to find the maximum supported data bus width.
1653 static u32
macb_dbw(struct macb
*bp
)
1655 if (!macb_is_gem(bp
))
1658 switch (GEM_BFEXT(DBWDEF
, gem_readl(bp
, DCFG1
))) {
1660 return GEM_BF(DBW
, GEM_DBW128
);
1662 return GEM_BF(DBW
, GEM_DBW64
);
1665 return GEM_BF(DBW
, GEM_DBW32
);
1669 /* Configure the receive DMA engine
1670 * - use the correct receive buffer size
1671 * - set best burst length for DMA operations
1672 * (if not supported by FIFO, it will fallback to default)
1673 * - set both rx/tx packet buffers to full memory size
1674 * These are configurable parameters for GEM.
1676 static void macb_configure_dma(struct macb
*bp
)
1680 if (macb_is_gem(bp
)) {
1681 dmacfg
= gem_readl(bp
, DMACFG
) & ~GEM_BF(RXBS
, -1L);
1682 dmacfg
|= GEM_BF(RXBS
, bp
->rx_buffer_size
/ RX_BUFFER_MULTIPLE
);
1683 if (bp
->dma_burst_length
)
1684 dmacfg
= GEM_BFINS(FBLDO
, bp
->dma_burst_length
, dmacfg
);
1685 dmacfg
|= GEM_BIT(TXPBMS
) | GEM_BF(RXBMS
, -1L);
1686 dmacfg
&= ~GEM_BIT(ENDIA_PKT
);
1689 dmacfg
&= ~GEM_BIT(ENDIA_DESC
);
1691 dmacfg
|= GEM_BIT(ENDIA_DESC
); /* CPU in big endian */
1693 if (bp
->dev
->features
& NETIF_F_HW_CSUM
)
1694 dmacfg
|= GEM_BIT(TXCOEN
);
1696 dmacfg
&= ~GEM_BIT(TXCOEN
);
1697 netdev_dbg(bp
->dev
, "Cadence configure DMA with 0x%08x\n",
1699 gem_writel(bp
, DMACFG
, dmacfg
);
1703 static void macb_init_hw(struct macb
*bp
)
1705 struct macb_queue
*queue
;
1711 macb_set_hwaddr(bp
);
1713 config
= macb_mdc_clk_div(bp
);
1714 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
1715 config
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
1716 config
|= MACB_BF(RBOF
, NET_IP_ALIGN
); /* Make eth data aligned */
1717 config
|= MACB_BIT(PAE
); /* PAuse Enable */
1718 config
|= MACB_BIT(DRFCS
); /* Discard Rx FCS */
1719 if (bp
->caps
& MACB_CAPS_JUMBO
)
1720 config
|= MACB_BIT(JFRAME
); /* Enable jumbo frames */
1722 config
|= MACB_BIT(BIG
); /* Receive oversized frames */
1723 if (bp
->dev
->flags
& IFF_PROMISC
)
1724 config
|= MACB_BIT(CAF
); /* Copy All Frames */
1725 else if (macb_is_gem(bp
) && bp
->dev
->features
& NETIF_F_RXCSUM
)
1726 config
|= GEM_BIT(RXCOEN
);
1727 if (!(bp
->dev
->flags
& IFF_BROADCAST
))
1728 config
|= MACB_BIT(NBC
); /* No BroadCast */
1729 config
|= macb_dbw(bp
);
1730 macb_writel(bp
, NCFGR
, config
);
1731 if ((bp
->caps
& MACB_CAPS_JUMBO
) && bp
->jumbo_max_len
)
1732 gem_writel(bp
, JML
, bp
->jumbo_max_len
);
1733 bp
->speed
= SPEED_10
;
1734 bp
->duplex
= DUPLEX_HALF
;
1735 bp
->rx_frm_len_mask
= MACB_RX_FRMLEN_MASK
;
1736 if (bp
->caps
& MACB_CAPS_JUMBO
)
1737 bp
->rx_frm_len_mask
= MACB_RX_JFRMLEN_MASK
;
1739 macb_configure_dma(bp
);
1741 /* Initialize TX and RX buffers */
1742 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1743 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1744 queue_writel(queue
, TBQP
, queue
->tx_ring_dma
);
1746 /* Enable interrupts */
1747 queue_writel(queue
, IER
,
1753 /* Enable TX and RX */
1754 macb_writel(bp
, NCR
, MACB_BIT(RE
) | MACB_BIT(TE
) | MACB_BIT(MPE
));
1757 /* The hash address register is 64 bits long and takes up two
1758 * locations in the memory map. The least significant bits are stored
1759 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1761 * The unicast hash enable and the multicast hash enable bits in the
1762 * network configuration register enable the reception of hash matched
1763 * frames. The destination address is reduced to a 6 bit index into
1764 * the 64 bit hash register using the following hash function. The
1765 * hash function is an exclusive or of every sixth bit of the
1766 * destination address.
1768 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1769 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1770 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1771 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1772 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1773 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1775 * da[0] represents the least significant bit of the first byte
1776 * received, that is, the multicast/unicast indicator, and da[47]
1777 * represents the most significant bit of the last byte received. If
1778 * the hash index, hi[n], points to a bit that is set in the hash
1779 * register then the frame will be matched according to whether the
1780 * frame is multicast or unicast. A multicast match will be signalled
1781 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1782 * index points to a bit set in the hash register. A unicast match
1783 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1784 * and the hash index points to a bit set in the hash register. To
1785 * receive all multicast frames, the hash register should be set with
1786 * all ones and the multicast hash enable bit should be set in the
1787 * network configuration register.
1790 static inline int hash_bit_value(int bitnr
, __u8
*addr
)
1792 if (addr
[bitnr
/ 8] & (1 << (bitnr
% 8)))
1797 /* Return the hash index value for the specified address. */
1798 static int hash_get_index(__u8
*addr
)
1803 for (j
= 0; j
< 6; j
++) {
1804 for (i
= 0, bitval
= 0; i
< 8; i
++)
1805 bitval
^= hash_bit_value(i
* 6 + j
, addr
);
1807 hash_index
|= (bitval
<< j
);
1813 /* Add multicast addresses to the internal multicast-hash table. */
1814 static void macb_sethashtable(struct net_device
*dev
)
1816 struct netdev_hw_addr
*ha
;
1817 unsigned long mc_filter
[2];
1819 struct macb
*bp
= netdev_priv(dev
);
1824 netdev_for_each_mc_addr(ha
, dev
) {
1825 bitnr
= hash_get_index(ha
->addr
);
1826 mc_filter
[bitnr
>> 5] |= 1 << (bitnr
& 31);
1829 macb_or_gem_writel(bp
, HRB
, mc_filter
[0]);
1830 macb_or_gem_writel(bp
, HRT
, mc_filter
[1]);
1833 /* Enable/Disable promiscuous and multicast modes. */
1834 static void macb_set_rx_mode(struct net_device
*dev
)
1837 struct macb
*bp
= netdev_priv(dev
);
1839 cfg
= macb_readl(bp
, NCFGR
);
1841 if (dev
->flags
& IFF_PROMISC
) {
1842 /* Enable promiscuous mode */
1843 cfg
|= MACB_BIT(CAF
);
1845 /* Disable RX checksum offload */
1846 if (macb_is_gem(bp
))
1847 cfg
&= ~GEM_BIT(RXCOEN
);
1849 /* Disable promiscuous mode */
1850 cfg
&= ~MACB_BIT(CAF
);
1852 /* Enable RX checksum offload only if requested */
1853 if (macb_is_gem(bp
) && dev
->features
& NETIF_F_RXCSUM
)
1854 cfg
|= GEM_BIT(RXCOEN
);
1857 if (dev
->flags
& IFF_ALLMULTI
) {
1858 /* Enable all multicast mode */
1859 macb_or_gem_writel(bp
, HRB
, -1);
1860 macb_or_gem_writel(bp
, HRT
, -1);
1861 cfg
|= MACB_BIT(NCFGR_MTI
);
1862 } else if (!netdev_mc_empty(dev
)) {
1863 /* Enable specific multicasts */
1864 macb_sethashtable(dev
);
1865 cfg
|= MACB_BIT(NCFGR_MTI
);
1866 } else if (dev
->flags
& (~IFF_ALLMULTI
)) {
1867 /* Disable all multicast mode */
1868 macb_or_gem_writel(bp
, HRB
, 0);
1869 macb_or_gem_writel(bp
, HRT
, 0);
1870 cfg
&= ~MACB_BIT(NCFGR_MTI
);
1873 macb_writel(bp
, NCFGR
, cfg
);
1876 static int macb_open(struct net_device
*dev
)
1878 struct macb
*bp
= netdev_priv(dev
);
1879 size_t bufsz
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ NET_IP_ALIGN
;
1882 netdev_dbg(bp
->dev
, "open\n");
1884 /* carrier starts down */
1885 netif_carrier_off(dev
);
1887 /* if the phy is not yet register, retry later*/
1891 /* RX buffers initialization */
1892 macb_init_rx_buffer_size(bp
, bufsz
);
1894 err
= macb_alloc_consistent(bp
);
1896 netdev_err(dev
, "Unable to allocate DMA memory (error %d)\n",
1901 napi_enable(&bp
->napi
);
1903 bp
->macbgem_ops
.mog_init_rings(bp
);
1906 /* schedule a link state check */
1907 phy_start(dev
->phydev
);
1909 netif_tx_start_all_queues(dev
);
1914 static int macb_close(struct net_device
*dev
)
1916 struct macb
*bp
= netdev_priv(dev
);
1917 unsigned long flags
;
1919 netif_tx_stop_all_queues(dev
);
1920 napi_disable(&bp
->napi
);
1923 phy_stop(dev
->phydev
);
1925 spin_lock_irqsave(&bp
->lock
, flags
);
1927 netif_carrier_off(dev
);
1928 spin_unlock_irqrestore(&bp
->lock
, flags
);
1930 macb_free_consistent(bp
);
1935 static int macb_change_mtu(struct net_device
*dev
, int new_mtu
)
1937 struct macb
*bp
= netdev_priv(dev
);
1940 if (netif_running(dev
))
1943 max_mtu
= ETH_DATA_LEN
;
1944 if (bp
->caps
& MACB_CAPS_JUMBO
)
1945 max_mtu
= gem_readl(bp
, JML
) - ETH_HLEN
- ETH_FCS_LEN
;
1947 if ((new_mtu
> max_mtu
) || (new_mtu
< GEM_MTU_MIN_SIZE
))
1955 static void gem_update_stats(struct macb
*bp
)
1958 u32
*p
= &bp
->hw_stats
.gem
.tx_octets_31_0
;
1960 for (i
= 0; i
< GEM_STATS_LEN
; ++i
, ++p
) {
1961 u32 offset
= gem_statistics
[i
].offset
;
1962 u64 val
= bp
->macb_reg_readl(bp
, offset
);
1964 bp
->ethtool_stats
[i
] += val
;
1967 if (offset
== GEM_OCTTXL
|| offset
== GEM_OCTRXL
) {
1968 /* Add GEM_OCTTXH, GEM_OCTRXH */
1969 val
= bp
->macb_reg_readl(bp
, offset
+ 4);
1970 bp
->ethtool_stats
[i
] += ((u64
)val
) << 32;
1976 static struct net_device_stats
*gem_get_stats(struct macb
*bp
)
1978 struct gem_stats
*hwstat
= &bp
->hw_stats
.gem
;
1979 struct net_device_stats
*nstat
= &bp
->stats
;
1981 gem_update_stats(bp
);
1983 nstat
->rx_errors
= (hwstat
->rx_frame_check_sequence_errors
+
1984 hwstat
->rx_alignment_errors
+
1985 hwstat
->rx_resource_errors
+
1986 hwstat
->rx_overruns
+
1987 hwstat
->rx_oversize_frames
+
1988 hwstat
->rx_jabbers
+
1989 hwstat
->rx_undersized_frames
+
1990 hwstat
->rx_length_field_frame_errors
);
1991 nstat
->tx_errors
= (hwstat
->tx_late_collisions
+
1992 hwstat
->tx_excessive_collisions
+
1993 hwstat
->tx_underrun
+
1994 hwstat
->tx_carrier_sense_errors
);
1995 nstat
->multicast
= hwstat
->rx_multicast_frames
;
1996 nstat
->collisions
= (hwstat
->tx_single_collision_frames
+
1997 hwstat
->tx_multiple_collision_frames
+
1998 hwstat
->tx_excessive_collisions
);
1999 nstat
->rx_length_errors
= (hwstat
->rx_oversize_frames
+
2000 hwstat
->rx_jabbers
+
2001 hwstat
->rx_undersized_frames
+
2002 hwstat
->rx_length_field_frame_errors
);
2003 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
;
2004 nstat
->rx_crc_errors
= hwstat
->rx_frame_check_sequence_errors
;
2005 nstat
->rx_frame_errors
= hwstat
->rx_alignment_errors
;
2006 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2007 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_collisions
;
2008 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_sense_errors
;
2009 nstat
->tx_fifo_errors
= hwstat
->tx_underrun
;
2014 static void gem_get_ethtool_stats(struct net_device
*dev
,
2015 struct ethtool_stats
*stats
, u64
*data
)
2019 bp
= netdev_priv(dev
);
2020 gem_update_stats(bp
);
2021 memcpy(data
, &bp
->ethtool_stats
, sizeof(u64
) * GEM_STATS_LEN
);
2024 static int gem_get_sset_count(struct net_device
*dev
, int sset
)
2028 return GEM_STATS_LEN
;
2034 static void gem_get_ethtool_strings(struct net_device
*dev
, u32 sset
, u8
*p
)
2040 for (i
= 0; i
< GEM_STATS_LEN
; i
++, p
+= ETH_GSTRING_LEN
)
2041 memcpy(p
, gem_statistics
[i
].stat_string
,
2047 static struct net_device_stats
*macb_get_stats(struct net_device
*dev
)
2049 struct macb
*bp
= netdev_priv(dev
);
2050 struct net_device_stats
*nstat
= &bp
->stats
;
2051 struct macb_stats
*hwstat
= &bp
->hw_stats
.macb
;
2053 if (macb_is_gem(bp
))
2054 return gem_get_stats(bp
);
2056 /* read stats from hardware */
2057 macb_update_stats(bp
);
2059 /* Convert HW stats into netdevice stats */
2060 nstat
->rx_errors
= (hwstat
->rx_fcs_errors
+
2061 hwstat
->rx_align_errors
+
2062 hwstat
->rx_resource_errors
+
2063 hwstat
->rx_overruns
+
2064 hwstat
->rx_oversize_pkts
+
2065 hwstat
->rx_jabbers
+
2066 hwstat
->rx_undersize_pkts
+
2067 hwstat
->rx_length_mismatch
);
2068 nstat
->tx_errors
= (hwstat
->tx_late_cols
+
2069 hwstat
->tx_excessive_cols
+
2070 hwstat
->tx_underruns
+
2071 hwstat
->tx_carrier_errors
+
2072 hwstat
->sqe_test_errors
);
2073 nstat
->collisions
= (hwstat
->tx_single_cols
+
2074 hwstat
->tx_multiple_cols
+
2075 hwstat
->tx_excessive_cols
);
2076 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
2077 hwstat
->rx_jabbers
+
2078 hwstat
->rx_undersize_pkts
+
2079 hwstat
->rx_length_mismatch
);
2080 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
+
2081 hwstat
->rx_overruns
;
2082 nstat
->rx_crc_errors
= hwstat
->rx_fcs_errors
;
2083 nstat
->rx_frame_errors
= hwstat
->rx_align_errors
;
2084 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2085 /* XXX: What does "missed" mean? */
2086 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_cols
;
2087 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_errors
;
2088 nstat
->tx_fifo_errors
= hwstat
->tx_underruns
;
2089 /* Don't know about heartbeat or window errors... */
2094 static int macb_get_regs_len(struct net_device
*netdev
)
2096 return MACB_GREGS_NBR
* sizeof(u32
);
2099 static void macb_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2102 struct macb
*bp
= netdev_priv(dev
);
2103 unsigned int tail
, head
;
2106 regs
->version
= (macb_readl(bp
, MID
) & ((1 << MACB_REV_SIZE
) - 1))
2107 | MACB_GREGS_VERSION
;
2109 tail
= macb_tx_ring_wrap(bp
->queues
[0].tx_tail
);
2110 head
= macb_tx_ring_wrap(bp
->queues
[0].tx_head
);
2112 regs_buff
[0] = macb_readl(bp
, NCR
);
2113 regs_buff
[1] = macb_or_gem_readl(bp
, NCFGR
);
2114 regs_buff
[2] = macb_readl(bp
, NSR
);
2115 regs_buff
[3] = macb_readl(bp
, TSR
);
2116 regs_buff
[4] = macb_readl(bp
, RBQP
);
2117 regs_buff
[5] = macb_readl(bp
, TBQP
);
2118 regs_buff
[6] = macb_readl(bp
, RSR
);
2119 regs_buff
[7] = macb_readl(bp
, IMR
);
2121 regs_buff
[8] = tail
;
2122 regs_buff
[9] = head
;
2123 regs_buff
[10] = macb_tx_dma(&bp
->queues
[0], tail
);
2124 regs_buff
[11] = macb_tx_dma(&bp
->queues
[0], head
);
2126 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
))
2127 regs_buff
[12] = macb_or_gem_readl(bp
, USRIO
);
2128 if (macb_is_gem(bp
))
2129 regs_buff
[13] = gem_readl(bp
, DMACFG
);
2132 static void macb_get_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2134 struct macb
*bp
= netdev_priv(netdev
);
2139 if (bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) {
2140 wol
->supported
= WAKE_MAGIC
;
2142 if (bp
->wol
& MACB_WOL_ENABLED
)
2143 wol
->wolopts
|= WAKE_MAGIC
;
2147 static int macb_set_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2149 struct macb
*bp
= netdev_priv(netdev
);
2151 if (!(bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) ||
2152 (wol
->wolopts
& ~WAKE_MAGIC
))
2155 if (wol
->wolopts
& WAKE_MAGIC
)
2156 bp
->wol
|= MACB_WOL_ENABLED
;
2158 bp
->wol
&= ~MACB_WOL_ENABLED
;
2160 device_set_wakeup_enable(&bp
->pdev
->dev
, bp
->wol
& MACB_WOL_ENABLED
);
2165 static const struct ethtool_ops macb_ethtool_ops
= {
2166 .get_regs_len
= macb_get_regs_len
,
2167 .get_regs
= macb_get_regs
,
2168 .get_link
= ethtool_op_get_link
,
2169 .get_ts_info
= ethtool_op_get_ts_info
,
2170 .get_wol
= macb_get_wol
,
2171 .set_wol
= macb_set_wol
,
2172 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2173 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2176 static const struct ethtool_ops gem_ethtool_ops
= {
2177 .get_regs_len
= macb_get_regs_len
,
2178 .get_regs
= macb_get_regs
,
2179 .get_link
= ethtool_op_get_link
,
2180 .get_ts_info
= ethtool_op_get_ts_info
,
2181 .get_ethtool_stats
= gem_get_ethtool_stats
,
2182 .get_strings
= gem_get_ethtool_strings
,
2183 .get_sset_count
= gem_get_sset_count
,
2184 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2185 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2188 static int macb_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2190 struct phy_device
*phydev
= dev
->phydev
;
2192 if (!netif_running(dev
))
2198 return phy_mii_ioctl(phydev
, rq
, cmd
);
2201 static int macb_set_features(struct net_device
*netdev
,
2202 netdev_features_t features
)
2204 struct macb
*bp
= netdev_priv(netdev
);
2205 netdev_features_t changed
= features
^ netdev
->features
;
2207 /* TX checksum offload */
2208 if ((changed
& NETIF_F_HW_CSUM
) && macb_is_gem(bp
)) {
2211 dmacfg
= gem_readl(bp
, DMACFG
);
2212 if (features
& NETIF_F_HW_CSUM
)
2213 dmacfg
|= GEM_BIT(TXCOEN
);
2215 dmacfg
&= ~GEM_BIT(TXCOEN
);
2216 gem_writel(bp
, DMACFG
, dmacfg
);
2219 /* RX checksum offload */
2220 if ((changed
& NETIF_F_RXCSUM
) && macb_is_gem(bp
)) {
2223 netcfg
= gem_readl(bp
, NCFGR
);
2224 if (features
& NETIF_F_RXCSUM
&&
2225 !(netdev
->flags
& IFF_PROMISC
))
2226 netcfg
|= GEM_BIT(RXCOEN
);
2228 netcfg
&= ~GEM_BIT(RXCOEN
);
2229 gem_writel(bp
, NCFGR
, netcfg
);
2235 static const struct net_device_ops macb_netdev_ops
= {
2236 .ndo_open
= macb_open
,
2237 .ndo_stop
= macb_close
,
2238 .ndo_start_xmit
= macb_start_xmit
,
2239 .ndo_set_rx_mode
= macb_set_rx_mode
,
2240 .ndo_get_stats
= macb_get_stats
,
2241 .ndo_do_ioctl
= macb_ioctl
,
2242 .ndo_validate_addr
= eth_validate_addr
,
2243 .ndo_change_mtu
= macb_change_mtu
,
2244 .ndo_set_mac_address
= eth_mac_addr
,
2245 #ifdef CONFIG_NET_POLL_CONTROLLER
2246 .ndo_poll_controller
= macb_poll_controller
,
2248 .ndo_set_features
= macb_set_features
,
2251 /* Configure peripheral capabilities according to device tree
2252 * and integration options used
2254 static void macb_configure_caps(struct macb
*bp
,
2255 const struct macb_config
*dt_conf
)
2260 bp
->caps
= dt_conf
->caps
;
2262 if (hw_is_gem(bp
->regs
, bp
->native_io
)) {
2263 bp
->caps
|= MACB_CAPS_MACB_IS_GEM
;
2265 dcfg
= gem_readl(bp
, DCFG1
);
2266 if (GEM_BFEXT(IRQCOR
, dcfg
) == 0)
2267 bp
->caps
|= MACB_CAPS_ISR_CLEAR_ON_WRITE
;
2268 dcfg
= gem_readl(bp
, DCFG2
);
2269 if ((dcfg
& (GEM_BIT(RX_PKT_BUFF
) | GEM_BIT(TX_PKT_BUFF
))) == 0)
2270 bp
->caps
|= MACB_CAPS_FIFO_MODE
;
2273 dev_dbg(&bp
->pdev
->dev
, "Cadence caps 0x%08x\n", bp
->caps
);
2276 static void macb_probe_queues(void __iomem
*mem
,
2278 unsigned int *queue_mask
,
2279 unsigned int *num_queues
)
2286 /* is it macb or gem ?
2288 * We need to read directly from the hardware here because
2289 * we are early in the probe process and don't have the
2290 * MACB_CAPS_MACB_IS_GEM flag positioned
2292 if (!hw_is_gem(mem
, native_io
))
2295 /* bit 0 is never set but queue 0 always exists */
2296 *queue_mask
= readl_relaxed(mem
+ GEM_DCFG6
) & 0xff;
2300 for (hw_q
= 1; hw_q
< MACB_MAX_QUEUES
; ++hw_q
)
2301 if (*queue_mask
& (1 << hw_q
))
2305 static int macb_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2306 struct clk
**hclk
, struct clk
**tx_clk
)
2310 *pclk
= devm_clk_get(&pdev
->dev
, "pclk");
2311 if (IS_ERR(*pclk
)) {
2312 err
= PTR_ERR(*pclk
);
2313 dev_err(&pdev
->dev
, "failed to get macb_clk (%u)\n", err
);
2317 *hclk
= devm_clk_get(&pdev
->dev
, "hclk");
2318 if (IS_ERR(*hclk
)) {
2319 err
= PTR_ERR(*hclk
);
2320 dev_err(&pdev
->dev
, "failed to get hclk (%u)\n", err
);
2324 *tx_clk
= devm_clk_get(&pdev
->dev
, "tx_clk");
2325 if (IS_ERR(*tx_clk
))
2328 err
= clk_prepare_enable(*pclk
);
2330 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2334 err
= clk_prepare_enable(*hclk
);
2336 dev_err(&pdev
->dev
, "failed to enable hclk (%u)\n", err
);
2337 goto err_disable_pclk
;
2340 err
= clk_prepare_enable(*tx_clk
);
2342 dev_err(&pdev
->dev
, "failed to enable tx_clk (%u)\n", err
);
2343 goto err_disable_hclk
;
2349 clk_disable_unprepare(*hclk
);
2352 clk_disable_unprepare(*pclk
);
2357 static int macb_init(struct platform_device
*pdev
)
2359 struct net_device
*dev
= platform_get_drvdata(pdev
);
2360 unsigned int hw_q
, q
;
2361 struct macb
*bp
= netdev_priv(dev
);
2362 struct macb_queue
*queue
;
2366 /* set the queue register mapping once for all: queue0 has a special
2367 * register mapping but we don't want to test the queue index then
2368 * compute the corresponding register offset at run time.
2370 for (hw_q
= 0, q
= 0; hw_q
< MACB_MAX_QUEUES
; ++hw_q
) {
2371 if (!(bp
->queue_mask
& (1 << hw_q
)))
2374 queue
= &bp
->queues
[q
];
2377 queue
->ISR
= GEM_ISR(hw_q
- 1);
2378 queue
->IER
= GEM_IER(hw_q
- 1);
2379 queue
->IDR
= GEM_IDR(hw_q
- 1);
2380 queue
->IMR
= GEM_IMR(hw_q
- 1);
2381 queue
->TBQP
= GEM_TBQP(hw_q
- 1);
2383 /* queue0 uses legacy registers */
2384 queue
->ISR
= MACB_ISR
;
2385 queue
->IER
= MACB_IER
;
2386 queue
->IDR
= MACB_IDR
;
2387 queue
->IMR
= MACB_IMR
;
2388 queue
->TBQP
= MACB_TBQP
;
2391 /* get irq: here we use the linux queue index, not the hardware
2392 * queue index. the queue irq definitions in the device tree
2393 * must remove the optional gaps that could exist in the
2394 * hardware queue mask.
2396 queue
->irq
= platform_get_irq(pdev
, q
);
2397 err
= devm_request_irq(&pdev
->dev
, queue
->irq
, macb_interrupt
,
2398 IRQF_SHARED
, dev
->name
, queue
);
2401 "Unable to request IRQ %d (error %d)\n",
2406 INIT_WORK(&queue
->tx_error_task
, macb_tx_error_task
);
2410 dev
->netdev_ops
= &macb_netdev_ops
;
2411 netif_napi_add(dev
, &bp
->napi
, macb_poll
, 64);
2413 /* setup appropriated routines according to adapter type */
2414 if (macb_is_gem(bp
)) {
2415 bp
->max_tx_length
= GEM_MAX_TX_LEN
;
2416 bp
->macbgem_ops
.mog_alloc_rx_buffers
= gem_alloc_rx_buffers
;
2417 bp
->macbgem_ops
.mog_free_rx_buffers
= gem_free_rx_buffers
;
2418 bp
->macbgem_ops
.mog_init_rings
= gem_init_rings
;
2419 bp
->macbgem_ops
.mog_rx
= gem_rx
;
2420 dev
->ethtool_ops
= &gem_ethtool_ops
;
2422 bp
->max_tx_length
= MACB_MAX_TX_LEN
;
2423 bp
->macbgem_ops
.mog_alloc_rx_buffers
= macb_alloc_rx_buffers
;
2424 bp
->macbgem_ops
.mog_free_rx_buffers
= macb_free_rx_buffers
;
2425 bp
->macbgem_ops
.mog_init_rings
= macb_init_rings
;
2426 bp
->macbgem_ops
.mog_rx
= macb_rx
;
2427 dev
->ethtool_ops
= &macb_ethtool_ops
;
2431 dev
->hw_features
= NETIF_F_SG
;
2432 /* Checksum offload is only available on gem with packet buffer */
2433 if (macb_is_gem(bp
) && !(bp
->caps
& MACB_CAPS_FIFO_MODE
))
2434 dev
->hw_features
|= NETIF_F_HW_CSUM
| NETIF_F_RXCSUM
;
2435 if (bp
->caps
& MACB_CAPS_SG_DISABLED
)
2436 dev
->hw_features
&= ~NETIF_F_SG
;
2437 dev
->features
= dev
->hw_features
;
2439 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
)) {
2441 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RGMII
)
2442 val
= GEM_BIT(RGMII
);
2443 else if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
&&
2444 (bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2445 val
= MACB_BIT(RMII
);
2446 else if (!(bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2447 val
= MACB_BIT(MII
);
2449 if (bp
->caps
& MACB_CAPS_USRIO_HAS_CLKEN
)
2450 val
|= MACB_BIT(CLKEN
);
2452 macb_or_gem_writel(bp
, USRIO
, val
);
2455 /* Set MII management clock divider */
2456 val
= macb_mdc_clk_div(bp
);
2457 val
|= macb_dbw(bp
);
2458 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
2459 val
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
2460 macb_writel(bp
, NCFGR
, val
);
2465 #if defined(CONFIG_OF)
2466 /* 1518 rounded up */
2467 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2468 /* max number of receive buffers */
2469 #define AT91ETHER_MAX_RX_DESCR 9
2471 /* Initialize and start the Receiver and Transmit subsystems */
2472 static int at91ether_start(struct net_device
*dev
)
2474 struct macb
*lp
= netdev_priv(dev
);
2479 lp
->rx_ring
= dma_alloc_coherent(&lp
->pdev
->dev
,
2480 (AT91ETHER_MAX_RX_DESCR
*
2481 sizeof(struct macb_dma_desc
)),
2482 &lp
->rx_ring_dma
, GFP_KERNEL
);
2486 lp
->rx_buffers
= dma_alloc_coherent(&lp
->pdev
->dev
,
2487 AT91ETHER_MAX_RX_DESCR
*
2488 AT91ETHER_MAX_RBUFF_SZ
,
2489 &lp
->rx_buffers_dma
, GFP_KERNEL
);
2490 if (!lp
->rx_buffers
) {
2491 dma_free_coherent(&lp
->pdev
->dev
,
2492 AT91ETHER_MAX_RX_DESCR
*
2493 sizeof(struct macb_dma_desc
),
2494 lp
->rx_ring
, lp
->rx_ring_dma
);
2499 addr
= lp
->rx_buffers_dma
;
2500 for (i
= 0; i
< AT91ETHER_MAX_RX_DESCR
; i
++) {
2501 lp
->rx_ring
[i
].addr
= addr
;
2502 lp
->rx_ring
[i
].ctrl
= 0;
2503 addr
+= AT91ETHER_MAX_RBUFF_SZ
;
2506 /* Set the Wrap bit on the last descriptor */
2507 lp
->rx_ring
[AT91ETHER_MAX_RX_DESCR
- 1].addr
|= MACB_BIT(RX_WRAP
);
2509 /* Reset buffer index */
2512 /* Program address of descriptor list in Rx Buffer Queue register */
2513 macb_writel(lp
, RBQP
, lp
->rx_ring_dma
);
2515 /* Enable Receive and Transmit */
2516 ctl
= macb_readl(lp
, NCR
);
2517 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
) | MACB_BIT(TE
));
2522 /* Open the ethernet interface */
2523 static int at91ether_open(struct net_device
*dev
)
2525 struct macb
*lp
= netdev_priv(dev
);
2529 /* Clear internal statistics */
2530 ctl
= macb_readl(lp
, NCR
);
2531 macb_writel(lp
, NCR
, ctl
| MACB_BIT(CLRSTAT
));
2533 macb_set_hwaddr(lp
);
2535 ret
= at91ether_start(dev
);
2539 /* Enable MAC interrupts */
2540 macb_writel(lp
, IER
, MACB_BIT(RCOMP
) |
2542 MACB_BIT(ISR_TUND
) |
2545 MACB_BIT(ISR_ROVR
) |
2548 /* schedule a link state check */
2549 phy_start(dev
->phydev
);
2551 netif_start_queue(dev
);
2556 /* Close the interface */
2557 static int at91ether_close(struct net_device
*dev
)
2559 struct macb
*lp
= netdev_priv(dev
);
2562 /* Disable Receiver and Transmitter */
2563 ctl
= macb_readl(lp
, NCR
);
2564 macb_writel(lp
, NCR
, ctl
& ~(MACB_BIT(TE
) | MACB_BIT(RE
)));
2566 /* Disable MAC interrupts */
2567 macb_writel(lp
, IDR
, MACB_BIT(RCOMP
) |
2569 MACB_BIT(ISR_TUND
) |
2572 MACB_BIT(ISR_ROVR
) |
2575 netif_stop_queue(dev
);
2577 dma_free_coherent(&lp
->pdev
->dev
,
2578 AT91ETHER_MAX_RX_DESCR
*
2579 sizeof(struct macb_dma_desc
),
2580 lp
->rx_ring
, lp
->rx_ring_dma
);
2583 dma_free_coherent(&lp
->pdev
->dev
,
2584 AT91ETHER_MAX_RX_DESCR
* AT91ETHER_MAX_RBUFF_SZ
,
2585 lp
->rx_buffers
, lp
->rx_buffers_dma
);
2586 lp
->rx_buffers
= NULL
;
2591 /* Transmit packet */
2592 static int at91ether_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2594 struct macb
*lp
= netdev_priv(dev
);
2596 if (macb_readl(lp
, TSR
) & MACB_BIT(RM9200_BNQ
)) {
2597 netif_stop_queue(dev
);
2599 /* Store packet information (to free when Tx completed) */
2601 lp
->skb_length
= skb
->len
;
2602 lp
->skb_physaddr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
2605 /* Set address of the data in the Transmit Address register */
2606 macb_writel(lp
, TAR
, lp
->skb_physaddr
);
2607 /* Set length of the packet in the Transmit Control register */
2608 macb_writel(lp
, TCR
, skb
->len
);
2611 netdev_err(dev
, "%s called, but device is busy!\n", __func__
);
2612 return NETDEV_TX_BUSY
;
2615 return NETDEV_TX_OK
;
2618 /* Extract received frame from buffer descriptors and sent to upper layers.
2619 * (Called from interrupt context)
2621 static void at91ether_rx(struct net_device
*dev
)
2623 struct macb
*lp
= netdev_priv(dev
);
2624 unsigned char *p_recv
;
2625 struct sk_buff
*skb
;
2626 unsigned int pktlen
;
2628 while (lp
->rx_ring
[lp
->rx_tail
].addr
& MACB_BIT(RX_USED
)) {
2629 p_recv
= lp
->rx_buffers
+ lp
->rx_tail
* AT91ETHER_MAX_RBUFF_SZ
;
2630 pktlen
= MACB_BF(RX_FRMLEN
, lp
->rx_ring
[lp
->rx_tail
].ctrl
);
2631 skb
= netdev_alloc_skb(dev
, pktlen
+ 2);
2633 skb_reserve(skb
, 2);
2634 memcpy(skb_put(skb
, pktlen
), p_recv
, pktlen
);
2636 skb
->protocol
= eth_type_trans(skb
, dev
);
2637 lp
->stats
.rx_packets
++;
2638 lp
->stats
.rx_bytes
+= pktlen
;
2641 lp
->stats
.rx_dropped
++;
2644 if (lp
->rx_ring
[lp
->rx_tail
].ctrl
& MACB_BIT(RX_MHASH_MATCH
))
2645 lp
->stats
.multicast
++;
2647 /* reset ownership bit */
2648 lp
->rx_ring
[lp
->rx_tail
].addr
&= ~MACB_BIT(RX_USED
);
2650 /* wrap after last buffer */
2651 if (lp
->rx_tail
== AT91ETHER_MAX_RX_DESCR
- 1)
2658 /* MAC interrupt handler */
2659 static irqreturn_t
at91ether_interrupt(int irq
, void *dev_id
)
2661 struct net_device
*dev
= dev_id
;
2662 struct macb
*lp
= netdev_priv(dev
);
2665 /* MAC Interrupt Status register indicates what interrupts are pending.
2666 * It is automatically cleared once read.
2668 intstatus
= macb_readl(lp
, ISR
);
2670 /* Receive complete */
2671 if (intstatus
& MACB_BIT(RCOMP
))
2674 /* Transmit complete */
2675 if (intstatus
& MACB_BIT(TCOMP
)) {
2676 /* The TCOM bit is set even if the transmission failed */
2677 if (intstatus
& (MACB_BIT(ISR_TUND
) | MACB_BIT(ISR_RLE
)))
2678 lp
->stats
.tx_errors
++;
2681 dev_kfree_skb_irq(lp
->skb
);
2683 dma_unmap_single(NULL
, lp
->skb_physaddr
,
2684 lp
->skb_length
, DMA_TO_DEVICE
);
2685 lp
->stats
.tx_packets
++;
2686 lp
->stats
.tx_bytes
+= lp
->skb_length
;
2688 netif_wake_queue(dev
);
2691 /* Work-around for EMAC Errata section 41.3.1 */
2692 if (intstatus
& MACB_BIT(RXUBR
)) {
2693 ctl
= macb_readl(lp
, NCR
);
2694 macb_writel(lp
, NCR
, ctl
& ~MACB_BIT(RE
));
2695 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
));
2698 if (intstatus
& MACB_BIT(ISR_ROVR
))
2699 netdev_err(dev
, "ROVR error\n");
2704 #ifdef CONFIG_NET_POLL_CONTROLLER
2705 static void at91ether_poll_controller(struct net_device
*dev
)
2707 unsigned long flags
;
2709 local_irq_save(flags
);
2710 at91ether_interrupt(dev
->irq
, dev
);
2711 local_irq_restore(flags
);
2715 static const struct net_device_ops at91ether_netdev_ops
= {
2716 .ndo_open
= at91ether_open
,
2717 .ndo_stop
= at91ether_close
,
2718 .ndo_start_xmit
= at91ether_start_xmit
,
2719 .ndo_get_stats
= macb_get_stats
,
2720 .ndo_set_rx_mode
= macb_set_rx_mode
,
2721 .ndo_set_mac_address
= eth_mac_addr
,
2722 .ndo_do_ioctl
= macb_ioctl
,
2723 .ndo_validate_addr
= eth_validate_addr
,
2724 .ndo_change_mtu
= eth_change_mtu
,
2725 #ifdef CONFIG_NET_POLL_CONTROLLER
2726 .ndo_poll_controller
= at91ether_poll_controller
,
2730 static int at91ether_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2731 struct clk
**hclk
, struct clk
**tx_clk
)
2738 *pclk
= devm_clk_get(&pdev
->dev
, "ether_clk");
2740 return PTR_ERR(*pclk
);
2742 err
= clk_prepare_enable(*pclk
);
2744 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2751 static int at91ether_init(struct platform_device
*pdev
)
2753 struct net_device
*dev
= platform_get_drvdata(pdev
);
2754 struct macb
*bp
= netdev_priv(dev
);
2758 dev
->netdev_ops
= &at91ether_netdev_ops
;
2759 dev
->ethtool_ops
= &macb_ethtool_ops
;
2761 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, at91ether_interrupt
,
2766 macb_writel(bp
, NCR
, 0);
2768 reg
= MACB_BF(CLK
, MACB_CLK_DIV32
) | MACB_BIT(BIG
);
2769 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
2770 reg
|= MACB_BIT(RM9200_RMII
);
2772 macb_writel(bp
, NCFGR
, reg
);
2777 static const struct macb_config at91sam9260_config
= {
2778 .caps
= MACB_CAPS_USRIO_HAS_CLKEN
| MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2779 .clk_init
= macb_clk_init
,
2783 static const struct macb_config pc302gem_config
= {
2784 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
,
2785 .dma_burst_length
= 16,
2786 .clk_init
= macb_clk_init
,
2790 static const struct macb_config sama5d2_config
= {
2791 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2792 .dma_burst_length
= 16,
2793 .clk_init
= macb_clk_init
,
2797 static const struct macb_config sama5d3_config
= {
2798 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
2799 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2800 .dma_burst_length
= 16,
2801 .clk_init
= macb_clk_init
,
2805 static const struct macb_config sama5d4_config
= {
2806 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2807 .dma_burst_length
= 4,
2808 .clk_init
= macb_clk_init
,
2812 static const struct macb_config emac_config
= {
2813 .clk_init
= at91ether_clk_init
,
2814 .init
= at91ether_init
,
2817 static const struct macb_config np4_config
= {
2818 .caps
= MACB_CAPS_USRIO_DISABLED
,
2819 .clk_init
= macb_clk_init
,
2823 static const struct macb_config zynqmp_config
= {
2824 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_JUMBO
,
2825 .dma_burst_length
= 16,
2826 .clk_init
= macb_clk_init
,
2828 .jumbo_max_len
= 10240,
2831 static const struct macb_config zynq_config
= {
2832 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_NO_GIGABIT_HALF
,
2833 .dma_burst_length
= 16,
2834 .clk_init
= macb_clk_init
,
2838 static const struct of_device_id macb_dt_ids
[] = {
2839 { .compatible
= "cdns,at32ap7000-macb" },
2840 { .compatible
= "cdns,at91sam9260-macb", .data
= &at91sam9260_config
},
2841 { .compatible
= "cdns,macb" },
2842 { .compatible
= "cdns,np4-macb", .data
= &np4_config
},
2843 { .compatible
= "cdns,pc302-gem", .data
= &pc302gem_config
},
2844 { .compatible
= "cdns,gem", .data
= &pc302gem_config
},
2845 { .compatible
= "atmel,sama5d2-gem", .data
= &sama5d2_config
},
2846 { .compatible
= "atmel,sama5d3-gem", .data
= &sama5d3_config
},
2847 { .compatible
= "atmel,sama5d4-gem", .data
= &sama5d4_config
},
2848 { .compatible
= "cdns,at91rm9200-emac", .data
= &emac_config
},
2849 { .compatible
= "cdns,emac", .data
= &emac_config
},
2850 { .compatible
= "cdns,zynqmp-gem", .data
= &zynqmp_config
},
2851 { .compatible
= "cdns,zynq-gem", .data
= &zynq_config
},
2854 MODULE_DEVICE_TABLE(of
, macb_dt_ids
);
2855 #endif /* CONFIG_OF */
2857 static int macb_probe(struct platform_device
*pdev
)
2859 int (*clk_init
)(struct platform_device
*, struct clk
**,
2860 struct clk
**, struct clk
**)
2862 int (*init
)(struct platform_device
*) = macb_init
;
2863 struct device_node
*np
= pdev
->dev
.of_node
;
2864 struct device_node
*phy_node
;
2865 const struct macb_config
*macb_config
= NULL
;
2866 struct clk
*pclk
, *hclk
= NULL
, *tx_clk
= NULL
;
2867 unsigned int queue_mask
, num_queues
;
2868 struct macb_platform_data
*pdata
;
2870 struct phy_device
*phydev
;
2871 struct net_device
*dev
;
2872 struct resource
*regs
;
2878 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2879 mem
= devm_ioremap_resource(&pdev
->dev
, regs
);
2881 return PTR_ERR(mem
);
2884 const struct of_device_id
*match
;
2886 match
= of_match_node(macb_dt_ids
, np
);
2887 if (match
&& match
->data
) {
2888 macb_config
= match
->data
;
2889 clk_init
= macb_config
->clk_init
;
2890 init
= macb_config
->init
;
2894 err
= clk_init(pdev
, &pclk
, &hclk
, &tx_clk
);
2898 native_io
= hw_is_native_io(mem
);
2900 macb_probe_queues(mem
, native_io
, &queue_mask
, &num_queues
);
2901 dev
= alloc_etherdev_mq(sizeof(*bp
), num_queues
);
2904 goto err_disable_clocks
;
2907 dev
->base_addr
= regs
->start
;
2909 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2911 bp
= netdev_priv(dev
);
2915 bp
->native_io
= native_io
;
2917 bp
->macb_reg_readl
= hw_readl_native
;
2918 bp
->macb_reg_writel
= hw_writel_native
;
2920 bp
->macb_reg_readl
= hw_readl
;
2921 bp
->macb_reg_writel
= hw_writel
;
2923 bp
->num_queues
= num_queues
;
2924 bp
->queue_mask
= queue_mask
;
2926 bp
->dma_burst_length
= macb_config
->dma_burst_length
;
2929 bp
->tx_clk
= tx_clk
;
2931 bp
->jumbo_max_len
= macb_config
->jumbo_max_len
;
2934 if (of_get_property(np
, "magic-packet", NULL
))
2935 bp
->wol
|= MACB_WOL_HAS_MAGIC_PACKET
;
2936 device_init_wakeup(&pdev
->dev
, bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
);
2938 spin_lock_init(&bp
->lock
);
2940 /* setup capabilities */
2941 macb_configure_caps(bp
, macb_config
);
2943 platform_set_drvdata(pdev
, dev
);
2945 dev
->irq
= platform_get_irq(pdev
, 0);
2948 goto err_disable_clocks
;
2951 mac
= of_get_mac_address(np
);
2953 ether_addr_copy(bp
->dev
->dev_addr
, mac
);
2955 macb_get_hwaddr(bp
);
2957 /* Power up the PHY if there is a GPIO reset */
2958 phy_node
= of_get_next_available_child(np
, NULL
);
2960 int gpio
= of_get_named_gpio(phy_node
, "reset-gpios", 0);
2962 if (gpio_is_valid(gpio
)) {
2963 bp
->reset_gpio
= gpio_to_desc(gpio
);
2964 gpiod_direction_output(bp
->reset_gpio
, 1);
2967 of_node_put(phy_node
);
2969 err
= of_get_phy_mode(np
);
2971 pdata
= dev_get_platdata(&pdev
->dev
);
2972 if (pdata
&& pdata
->is_rmii
)
2973 bp
->phy_interface
= PHY_INTERFACE_MODE_RMII
;
2975 bp
->phy_interface
= PHY_INTERFACE_MODE_MII
;
2977 bp
->phy_interface
= err
;
2980 /* IP specific init */
2983 goto err_out_free_netdev
;
2985 err
= macb_mii_init(bp
);
2987 goto err_out_free_netdev
;
2989 phydev
= dev
->phydev
;
2991 netif_carrier_off(dev
);
2993 err
= register_netdev(dev
);
2995 dev_err(&pdev
->dev
, "Cannot register net device, aborting.\n");
2996 goto err_out_unregister_mdio
;
2999 phy_attached_info(phydev
);
3001 netdev_info(dev
, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3002 macb_is_gem(bp
) ? "GEM" : "MACB", macb_readl(bp
, MID
),
3003 dev
->base_addr
, dev
->irq
, dev
->dev_addr
);
3007 err_out_unregister_mdio
:
3008 phy_disconnect(dev
->phydev
);
3009 mdiobus_unregister(bp
->mii_bus
);
3010 mdiobus_free(bp
->mii_bus
);
3012 /* Shutdown the PHY if there is a GPIO reset */
3014 gpiod_set_value(bp
->reset_gpio
, 0);
3016 err_out_free_netdev
:
3020 clk_disable_unprepare(tx_clk
);
3021 clk_disable_unprepare(hclk
);
3022 clk_disable_unprepare(pclk
);
3027 static int macb_remove(struct platform_device
*pdev
)
3029 struct net_device
*dev
;
3032 dev
= platform_get_drvdata(pdev
);
3035 bp
= netdev_priv(dev
);
3037 phy_disconnect(dev
->phydev
);
3038 mdiobus_unregister(bp
->mii_bus
);
3039 mdiobus_free(bp
->mii_bus
);
3041 /* Shutdown the PHY if there is a GPIO reset */
3043 gpiod_set_value(bp
->reset_gpio
, 0);
3045 unregister_netdev(dev
);
3046 clk_disable_unprepare(bp
->tx_clk
);
3047 clk_disable_unprepare(bp
->hclk
);
3048 clk_disable_unprepare(bp
->pclk
);
3055 static int __maybe_unused
macb_suspend(struct device
*dev
)
3057 struct platform_device
*pdev
= to_platform_device(dev
);
3058 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3059 struct macb
*bp
= netdev_priv(netdev
);
3061 netif_carrier_off(netdev
);
3062 netif_device_detach(netdev
);
3064 if (bp
->wol
& MACB_WOL_ENABLED
) {
3065 macb_writel(bp
, IER
, MACB_BIT(WOL
));
3066 macb_writel(bp
, WOL
, MACB_BIT(MAG
));
3067 enable_irq_wake(bp
->queues
[0].irq
);
3069 clk_disable_unprepare(bp
->tx_clk
);
3070 clk_disable_unprepare(bp
->hclk
);
3071 clk_disable_unprepare(bp
->pclk
);
3077 static int __maybe_unused
macb_resume(struct device
*dev
)
3079 struct platform_device
*pdev
= to_platform_device(dev
);
3080 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3081 struct macb
*bp
= netdev_priv(netdev
);
3083 if (bp
->wol
& MACB_WOL_ENABLED
) {
3084 macb_writel(bp
, IDR
, MACB_BIT(WOL
));
3085 macb_writel(bp
, WOL
, 0);
3086 disable_irq_wake(bp
->queues
[0].irq
);
3088 clk_prepare_enable(bp
->pclk
);
3089 clk_prepare_enable(bp
->hclk
);
3090 clk_prepare_enable(bp
->tx_clk
);
3093 netif_device_attach(netdev
);
3098 static SIMPLE_DEV_PM_OPS(macb_pm_ops
, macb_suspend
, macb_resume
);
3100 static struct platform_driver macb_driver
= {
3101 .probe
= macb_probe
,
3102 .remove
= macb_remove
,
3105 .of_match_table
= of_match_ptr(macb_dt_ids
),
3110 module_platform_driver(macb_driver
);
3112 MODULE_LICENSE("GPL");
3113 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3114 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3115 MODULE_ALIAS("platform:macb");