drivers/net/ethernet/cavium/liquidio/liquidio_common.h

   1 /**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2015 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * This file may also be available under a different license from Cavium.
  20 * Contact Cavium, Inc. for more information
  21 **********************************************************************/
  22
  23 /*!  \file  liquidio_common.h
  24  *   \brief Common: Structures and macros used in PCI-NIC package by core and
  25  *   host driver.
  26  */
  27
  28 #ifndef __LIQUIDIO_COMMON_H__
  29 #define __LIQUIDIO_COMMON_H__
  30
  31 #include "octeon_config.h"
  32
  33 #define LIQUIDIO_PACKAGE ""
  34 #define LIQUIDIO_BASE_MAJOR_VERSION 1
  35 #define LIQUIDIO_BASE_MINOR_VERSION 4
  36 #define LIQUIDIO_BASE_MICRO_VERSION 1
  37 #define LIQUIDIO_BASE_VERSION   __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
  38                                 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
  39 #define LIQUIDIO_MICRO_VERSION  "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
  40 #define LIQUIDIO_VERSION        LIQUIDIO_PACKAGE \
  41                                 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
  42                                 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
  43                                 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
  44
  45 struct lio_version {
  46         u16  major;
  47         u16  minor;
  48         u16  micro;
  49         u16  reserved;
  50 };
  51
  52 #define CONTROL_IQ 0
  53 /** Tag types used by Octeon cores in its work. */
  54 enum octeon_tag_type {
  55         ORDERED_TAG = 0,
  56         ATOMIC_TAG = 1,
  57         NULL_TAG = 2,
  58         NULL_NULL_TAG = 3
  59 };
  60
  61 /* pre-defined host->NIC tag values */
  62 #define LIO_CONTROL  (0x11111110)
  63 #define LIO_DATA(i)  (0x11111111 + (i))
  64
  65 /* Opcodes used by host driver/apps to perform operations on the core.
  66  * These are used to identify the major subsystem that the operation
  67  * is for.
  68  */
  69 #define OPCODE_CORE 0           /* used for generic core operations */
  70 #define OPCODE_NIC  1           /* used for NIC operations */
  71 #define OPCODE_LAST OPCODE_NIC
  72
  73 /* Subcodes are used by host driver/apps to identify the sub-operation
  74  * for the core. They only need to by unique for a given subsystem.
  75  */
  76 #define OPCODE_SUBCODE(op, sub)       (((op & 0x0f) << 8) | ((sub) & 0x7f))
  77
  78 /** OPCODE_CORE subcodes. For future use. */
  79
  80 /** OPCODE_NIC subcodes */
  81
  82 /* This subcode is sent by core PCI driver to indicate cores are ready. */
  83 #define OPCODE_NIC_CORE_DRV_ACTIVE     0x01
  84 #define OPCODE_NIC_NW_DATA             0x02     /* network packet data */
  85 #define OPCODE_NIC_CMD                 0x03
  86 #define OPCODE_NIC_INFO                0x04
  87 #define OPCODE_NIC_PORT_STATS          0x05
  88 #define OPCODE_NIC_MDIO45              0x06
  89 #define OPCODE_NIC_TIMESTAMP           0x07
  90 #define OPCODE_NIC_INTRMOD_CFG         0x08
  91 #define OPCODE_NIC_IF_CFG              0x09
  92
  93 #define CORE_DRV_TEST_SCATTER_OP    0xFFF5
  94
  95 #define OPCODE_SLOW_PATH(rh)  \
  96         (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
  97                 OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
  98
  99 /* Application codes advertised by the core driver initialization packet. */
 100 #define CVM_DRV_APP_START           0x0
 101 #define CVM_DRV_NO_APP              0
 102 #define CVM_DRV_APP_COUNT           0x2
 103 #define CVM_DRV_BASE_APP            (CVM_DRV_APP_START + 0x0)
 104 #define CVM_DRV_NIC_APP             (CVM_DRV_APP_START + 0x1)
 105 #define CVM_DRV_INVALID_APP         (CVM_DRV_APP_START + 0x2)
 106 #define CVM_DRV_APP_END             (CVM_DRV_INVALID_APP - 1)
 107
 108 /* Macro to increment index.
 109  * Index is incremented by count; if the sum exceeds
 110  * max, index is wrapped-around to the start.
 111  */
 112 #define INCR_INDEX(index, count, max)                \
 113 do {                                                 \
 114         if (((index) + (count)) >= (max))            \
 115                 index = ((index) + (count)) - (max); \
 116         else                                         \
 117                 index += (count);                    \
 118 } while (0)
 119
 120 #define INCR_INDEX_BY1(index, max)      \
 121 do {                                    \
 122         if ((++(index)) == (max))       \
 123                 index = 0;              \
 124 } while (0)
 125
 126 #define DECR_INDEX(index, count, max)                  \
 127 do {                                                   \
 128         if ((count) > (index))                         \
 129                 index = ((max) - ((count - index)));   \
 130         else                                           \
 131                 index -= count;                        \
 132 } while (0)
 133
 134 #define OCT_BOARD_NAME 32
 135 #define OCT_SERIAL_LEN 64
 136
 137 /* Structure used by core driver to send indication that the Octeon
 138  * application is ready.
 139  */
 140 struct octeon_core_setup {
 141         u64 corefreq;
 142
 143         char boardname[OCT_BOARD_NAME];
 144
 145         char board_serial_number[OCT_SERIAL_LEN];
 146
 147         u64 board_rev_major;
 148
 149         u64 board_rev_minor;
 150
 151 };
 152
 153 /*---------------------------  SCATTER GATHER ENTRY  -----------------------*/
 154
 155 /* The Scatter-Gather List Entry. The scatter or gather component used with
 156  * a Octeon input instruction has this format.
 157  */
 158 struct octeon_sg_entry {
 159         /** The first 64 bit gives the size of data in each dptr.*/
 160         union {
 161                 u16 size[4];
 162                 u64 size64;
 163         } u;
 164
 165         /** The 4 dptr pointers for this entry. */
 166         u64 ptr[4];
 167
 168 };
 169
 170 #define OCT_SG_ENTRY_SIZE    (sizeof(struct octeon_sg_entry))
 171
 172 /* \brief Add size to gather list
 173  * @param sg_entry scatter/gather entry
 174  * @param size size to add
 175  * @param pos position to add it.
 176  */
 177 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
 178                                u16 size,
 179                                u32 pos)
 180 {
 181 #ifdef __BIG_ENDIAN_BITFIELD
 182         sg_entry->u.size[pos] = size;
 183 #else
 184         sg_entry->u.size[3 - pos] = size;
 185 #endif
 186 }
 187
 188 /*------------------------- End Scatter/Gather ---------------------------*/
 189
 190 #define   OCTNET_FRM_PTP_HEADER_SIZE  8
 191
 192 #define   OCTNET_FRM_HEADER_SIZE     22 /* VLAN + Ethernet */
 193
 194 #define   OCTNET_MIN_FRM_SIZE        64
 195
 196 #define   OCTNET_MAX_FRM_SIZE        (16000 + OCTNET_FRM_HEADER_SIZE)
 197
 198 #define   OCTNET_DEFAULT_FRM_SIZE    (1500 + OCTNET_FRM_HEADER_SIZE)
 199
 200 /** NIC Commands are sent using this Octeon Input Queue */
 201 #define   OCTNET_CMD_Q                0
 202
 203 /* NIC Command types */
 204 #define   OCTNET_CMD_CHANGE_MTU       0x1
 205 #define   OCTNET_CMD_CHANGE_MACADDR   0x2
 206 #define   OCTNET_CMD_CHANGE_DEVFLAGS  0x3
 207 #define   OCTNET_CMD_RX_CTL           0x4
 208
 209 #define   OCTNET_CMD_SET_MULTI_LIST   0x5
 210 #define   OCTNET_CMD_CLEAR_STATS      0x6
 211
 212 /* command for setting the speed, duplex & autoneg */
 213 #define   OCTNET_CMD_SET_SETTINGS     0x7
 214 #define   OCTNET_CMD_SET_FLOW_CTL     0x8
 215
 216 #define   OCTNET_CMD_MDIO_READ_WRITE  0x9
 217 #define   OCTNET_CMD_GPIO_ACCESS      0xA
 218 #define   OCTNET_CMD_LRO_ENABLE       0xB
 219 #define   OCTNET_CMD_LRO_DISABLE      0xC
 220 #define   OCTNET_CMD_SET_RSS          0xD
 221 #define   OCTNET_CMD_WRITE_SA         0xE
 222 #define   OCTNET_CMD_DELETE_SA        0xF
 223 #define   OCTNET_CMD_UPDATE_SA        0x12
 224
 225 #define   OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
 226 #define   OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
 227 #define   OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
 228 #define   OCTNET_CMD_VERBOSE_ENABLE   0x14
 229 #define   OCTNET_CMD_VERBOSE_DISABLE  0x15
 230
 231 #define   OCTNET_CMD_ENABLE_VLAN_FILTER 0x16
 232 #define   OCTNET_CMD_ADD_VLAN_FILTER  0x17
 233 #define   OCTNET_CMD_DEL_VLAN_FILTER  0x18
 234 #define   OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
 235
 236 #define   OCTNET_CMD_ID_ACTIVE         0x1a
 237
 238 #define   OCTNET_CMD_VXLAN_PORT_ADD    0x0
 239 #define   OCTNET_CMD_VXLAN_PORT_DEL    0x1
 240 #define   OCTNET_CMD_RXCSUM_ENABLE     0x0
 241 #define   OCTNET_CMD_RXCSUM_DISABLE    0x1
 242 #define   OCTNET_CMD_TXCSUM_ENABLE     0x0
 243 #define   OCTNET_CMD_TXCSUM_DISABLE    0x1
 244
 245 /* RX(packets coming from wire) Checksum verification flags */
 246 /* TCP/UDP csum */
 247 #define   CNNIC_L4SUM_VERIFIED             0x1
 248 #define   CNNIC_IPSUM_VERIFIED             0x2
 249 #define   CNNIC_TUN_CSUM_VERIFIED          0x4
 250 #define   CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
 251
 252 /*LROIPV4 and LROIPV6 Flags*/
 253 #define   OCTNIC_LROIPV4    0x1
 254 #define   OCTNIC_LROIPV6    0x2
 255
 256 /* Interface flags communicated between host driver and core app. */
 257 enum octnet_ifflags {
 258         OCTNET_IFFLAG_PROMISC   = 0x01,
 259         OCTNET_IFFLAG_ALLMULTI  = 0x02,
 260         OCTNET_IFFLAG_MULTICAST = 0x04,
 261         OCTNET_IFFLAG_BROADCAST = 0x08,
 262         OCTNET_IFFLAG_UNICAST   = 0x10
 263 };
 264
 265 /*   wqe
 266  *  ---------------  0
 267  * |  wqe  word0-3 |
 268  *  ---------------  32
 269  * |    PCI IH     |
 270  *  ---------------  40
 271  * |     RPTR      |
 272  *  ---------------  48
 273  * |    PCI IRH    |
 274  *  ---------------  56
 275  * |  OCT_NET_CMD  |
 276  *  ---------------  64
 277  * | Addtl 8-BData |
 278  * |               |
 279  *  ---------------
 280  */
 281
 282 union octnet_cmd {
 283         u64 u64;
 284
 285         struct {
 286 #ifdef __BIG_ENDIAN_BITFIELD
 287                 u64 cmd:5;
 288
 289                 u64 more:6; /* How many udd words follow the command */
 290
 291                 u64 reserved:29;
 292
 293                 u64 param1:16;
 294
 295                 u64 param2:8;
 296
 297 #else
 298
 299                 u64 param2:8;
 300
 301                 u64 param1:16;
 302
 303                 u64 reserved:29;
 304
 305                 u64 more:6;
 306
 307                 u64 cmd:5;
 308
 309 #endif
 310         } s;
 311
 312 };
 313
 314 #define   OCTNET_CMD_SIZE     (sizeof(union octnet_cmd))
 315
 316 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
 317 #define LIO_SOFTCMDRESP_IH2       40
 318 #define LIO_SOFTCMDRESP_IH3       (40 + 8)
 319
 320 #define LIO_PCICMD_O2             24
 321 #define LIO_PCICMD_O3             (24 + 8)
 322
 323 /* Instruction Header(DPI) - for OCTEON-III models */
 324 struct  octeon_instr_ih3 {
 325 #ifdef __BIG_ENDIAN_BITFIELD
 326
 327         /** Reserved3 */
 328         u64     reserved3:1;
 329
 330         /** Gather indicator 1=gather*/
 331         u64     gather:1;
 332
 333         /** Data length OR no. of entries in gather list */
 334         u64     dlengsz:14;
 335
 336         /** Front Data size */
 337         u64     fsz:6;
 338
 339         /** Reserved2 */
 340         u64     reserved2:4;
 341
 342         /** PKI port kind - PKIND */
 343         u64     pkind:6;
 344
 345         /** Reserved1 */
 346         u64     reserved1:32;
 347
 348 #else
 349         /** Reserved1 */
 350         u64     reserved1:32;
 351
 352         /** PKI port kind - PKIND */
 353         u64     pkind:6;
 354
 355         /** Reserved2 */
 356         u64     reserved2:4;
 357
 358         /** Front Data size */
 359         u64     fsz:6;
 360
 361         /** Data length OR no. of entries in gather list */
 362         u64     dlengsz:14;
 363
 364         /** Gather indicator 1=gather*/
 365         u64     gather:1;
 366
 367         /** Reserved3 */
 368         u64     reserved3:1;
 369
 370 #endif
 371 };
 372
 373 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
 374 /** BIG ENDIAN format.   */
 375 struct  octeon_instr_pki_ih3 {
 376 #ifdef __BIG_ENDIAN_BITFIELD
 377
 378         /** Wider bit */
 379         u64     w:1;
 380
 381         /** Raw mode indicator 1 = RAW */
 382         u64     raw:1;
 383
 384         /** Use Tag */
 385         u64     utag:1;
 386
 387         /** Use QPG */
 388         u64     uqpg:1;
 389
 390         /** Reserved2 */
 391         u64     reserved2:1;
 392
 393         /** Parse Mode */
 394         u64     pm:3;
 395
 396         /** Skip Length */
 397         u64     sl:8;
 398
 399         /** Use Tag Type */
 400         u64     utt:1;
 401
 402         /** Tag type */
 403         u64     tagtype:2;
 404
 405         /** Reserved1 */
 406         u64     reserved1:2;
 407
 408         /** QPG Value */
 409         u64     qpg:11;
 410
 411         /** Tag Value */
 412         u64     tag:32;
 413
 414 #else
 415
 416         /** Tag Value */
 417         u64     tag:32;
 418
 419         /** QPG Value */
 420         u64     qpg:11;
 421
 422         /** Reserved1 */
 423         u64     reserved1:2;
 424
 425         /** Tag type */
 426         u64     tagtype:2;
 427
 428         /** Use Tag Type */
 429         u64     utt:1;
 430
 431         /** Skip Length */
 432         u64     sl:8;
 433
 434         /** Parse Mode */
 435         u64     pm:3;
 436
 437         /** Reserved2 */
 438         u64     reserved2:1;
 439
 440         /** Use QPG */
 441         u64     uqpg:1;
 442
 443         /** Use Tag */
 444         u64     utag:1;
 445
 446         /** Raw mode indicator 1 = RAW */
 447         u64     raw:1;
 448
 449         /** Wider bit */
 450         u64     w:1;
 451 #endif
 452
 453 };
 454
 455 /** Instruction Header */
 456 struct octeon_instr_ih2 {
 457 #ifdef __BIG_ENDIAN_BITFIELD
 458         /** Raw mode indicator 1 = RAW */
 459         u64 raw:1;
 460
 461         /** Gather indicator 1=gather*/
 462         u64 gather:1;
 463
 464         /** Data length OR no. of entries in gather list */
 465         u64 dlengsz:14;
 466
 467         /** Front Data size */
 468         u64 fsz:6;
 469
 470         /** Packet Order / Work Unit selection (1 of 8)*/
 471         u64 qos:3;
 472
 473         /** Core group selection (1 of 16) */
 474         u64 grp:4;
 475
 476         /** Short Raw Packet Indicator 1=short raw pkt */
 477         u64 rs:1;
 478
 479         /** Tag type */
 480         u64 tagtype:2;
 481
 482         /** Tag Value */
 483         u64 tag:32;
 484 #else
 485         /** Tag Value */
 486         u64 tag:32;
 487
 488         /** Tag type */
 489         u64 tagtype:2;
 490
 491         /** Short Raw Packet Indicator 1=short raw pkt */
 492         u64 rs:1;
 493
 494         /** Core group selection (1 of 16) */
 495         u64 grp:4;
 496
 497         /** Packet Order / Work Unit selection (1 of 8)*/
 498         u64 qos:3;
 499
 500         /** Front Data size */
 501         u64 fsz:6;
 502
 503         /** Data length OR no. of entries in gather list */
 504         u64 dlengsz:14;
 505
 506         /** Gather indicator 1=gather*/
 507         u64 gather:1;
 508
 509         /** Raw mode indicator 1 = RAW */
 510         u64 raw:1;
 511 #endif
 512 };
 513
 514 /** Input Request Header */
 515 struct octeon_instr_irh {
 516 #ifdef __BIG_ENDIAN_BITFIELD
 517         u64 opcode:4;
 518         u64 rflag:1;
 519         u64 subcode:7;
 520         u64 vlan:12;
 521         u64 priority:3;
 522         u64 reserved:5;
 523         u64 ossp:32;             /* opcode/subcode specific parameters */
 524 #else
 525         u64 ossp:32;             /* opcode/subcode specific parameters */
 526         u64 reserved:5;
 527         u64 priority:3;
 528         u64 vlan:12;
 529         u64 subcode:7;
 530         u64 rflag:1;
 531         u64 opcode:4;
 532 #endif
 533 };
 534
 535 /** Return Data Parameters */
 536 struct octeon_instr_rdp {
 537 #ifdef __BIG_ENDIAN_BITFIELD
 538         u64 reserved:49;
 539         u64 pcie_port:3;
 540         u64 rlen:12;
 541 #else
 542         u64 rlen:12;
 543         u64 pcie_port:3;
 544         u64 reserved:49;
 545 #endif
 546 };
 547
 548 /** Receive Header */
 549 union octeon_rh {
 550 #ifdef __BIG_ENDIAN_BITFIELD
 551         u64 u64;
 552         struct {
 553                 u64 opcode:4;
 554                 u64 subcode:8;
 555                 u64 len:3;     /** additional 64-bit words */
 556                 u64 reserved:17;
 557                 u64 ossp:32;   /** opcode/subcode specific parameters */
 558         } r;
 559         struct {
 560                 u64 opcode:4;
 561                 u64 subcode:8;
 562                 u64 len:3;     /** additional 64-bit words */
 563                 u64 extra:28;
 564                 u64 vlan:12;
 565                 u64 priority:3;
 566                 u64 csum_verified:3;     /** checksum verified. */
 567                 u64 has_hwtstamp:1;      /** Has hardware timestamp. 1 = yes. */
 568                 u64 encap_on:1;
 569                 u64 has_hash:1;          /** Has hash (rth or rss). 1 = yes. */
 570         } r_dh;
 571         struct {
 572                 u64 opcode:4;
 573                 u64 subcode:8;
 574                 u64 len:3;     /** additional 64-bit words */
 575                 u64 reserved:11;
 576                 u64 num_gmx_ports:8;
 577                 u64 max_nic_ports:10;
 578                 u64 app_cap_flags:4;
 579                 u64 app_mode:8;
 580                 u64 pkind:8;
 581         } r_core_drv_init;
 582         struct {
 583                 u64 opcode:4;
 584                 u64 subcode:8;
 585                 u64 len:3;       /** additional 64-bit words */
 586                 u64 reserved:8;
 587                 u64 extra:25;
 588                 u64 gmxport:16;
 589         } r_nic_info;
 590 #else
 591         u64 u64;
 592         struct {
 593                 u64 ossp:32;  /** opcode/subcode specific parameters */
 594                 u64 reserved:17;
 595                 u64 len:3;    /** additional 64-bit words */
 596                 u64 subcode:8;
 597                 u64 opcode:4;
 598         } r;
 599         struct {
 600                 u64 has_hash:1;          /** Has hash (rth or rss). 1 = yes. */
 601                 u64 encap_on:1;
 602                 u64 has_hwtstamp:1;      /** 1 = has hwtstamp */
 603                 u64 csum_verified:3;     /** checksum verified. */
 604                 u64 priority:3;
 605                 u64 vlan:12;
 606                 u64 extra:28;
 607                 u64 len:3;    /** additional 64-bit words */
 608                 u64 subcode:8;
 609                 u64 opcode:4;
 610         } r_dh;
 611         struct {
 612                 u64 pkind:8;
 613                 u64 app_mode:8;
 614                 u64 app_cap_flags:4;
 615                 u64 max_nic_ports:10;
 616                 u64 num_gmx_ports:8;
 617                 u64 reserved:11;
 618                 u64 len:3;       /** additional 64-bit words */
 619                 u64 subcode:8;
 620                 u64 opcode:4;
 621         } r_core_drv_init;
 622         struct {
 623                 u64 gmxport:16;
 624                 u64 extra:25;
 625                 u64 reserved:8;
 626                 u64 len:3;       /** additional 64-bit words */
 627                 u64 subcode:8;
 628                 u64 opcode:4;
 629         } r_nic_info;
 630 #endif
 631 };
 632
 633 #define  OCT_RH_SIZE   (sizeof(union  octeon_rh))
 634
 635 union octnic_packet_params {
 636         u32 u32;
 637         struct {
 638 #ifdef __BIG_ENDIAN_BITFIELD
 639                 u32 reserved:24;
 640                 u32 ip_csum:1;          /* Perform IP header checksum(s) */
 641                 /* Perform Outer transport header checksum */
 642                 u32 transport_csum:1;
 643                 /* Find tunnel, and perform transport csum. */
 644                 u32 tnl_csum:1;
 645                 u32 tsflag:1;           /* Timestamp this packet */
 646                 u32 ipsec_ops:4;        /* IPsec operation */
 647 #else
 648                 u32 ipsec_ops:4;
 649                 u32 tsflag:1;
 650                 u32 tnl_csum:1;
 651                 u32 transport_csum:1;
 652                 u32 ip_csum:1;
 653                 u32 reserved:24;
 654 #endif
 655         } s;
 656 };
 657
 658 /** Status of a RGMII Link on Octeon as seen by core driver. */
 659 union oct_link_status {
 660         u64 u64;
 661
 662         struct {
 663 #ifdef __BIG_ENDIAN_BITFIELD
 664                 u64 duplex:8;
 665                 u64 mtu:16;
 666                 u64 speed:16;
 667                 u64 link_up:1;
 668                 u64 autoneg:1;
 669                 u64 if_mode:5;
 670                 u64 pause:1;
 671                 u64 flashing:1;
 672                 u64 reserved:15;
 673 #else
 674                 u64 reserved:15;
 675                 u64 flashing:1;
 676                 u64 pause:1;
 677                 u64 if_mode:5;
 678                 u64 autoneg:1;
 679                 u64 link_up:1;
 680                 u64 speed:16;
 681                 u64 mtu:16;
 682                 u64 duplex:8;
 683 #endif
 684         } s;
 685 };
 686
 687 /** The txpciq info passed to host from the firmware */
 688
 689 union oct_txpciq {
 690         u64 u64;
 691
 692         struct {
 693 #ifdef __BIG_ENDIAN_BITFIELD
 694                 u64 q_no:8;
 695                 u64 port:8;
 696                 u64 pkind:6;
 697                 u64 use_qpg:1;
 698                 u64 qpg:11;
 699                 u64 reserved:30;
 700 #else
 701                 u64 reserved:30;
 702                 u64 qpg:11;
 703                 u64 use_qpg:1;
 704                 u64 pkind:6;
 705                 u64 port:8;
 706                 u64 q_no:8;
 707 #endif
 708         } s;
 709 };
 710
 711 /** The rxpciq info passed to host from the firmware */
 712
 713 union oct_rxpciq {
 714         u64 u64;
 715
 716         struct {
 717 #ifdef __BIG_ENDIAN_BITFIELD
 718                 u64 q_no:8;
 719                 u64 reserved:56;
 720 #else
 721                 u64 reserved:56;
 722                 u64 q_no:8;
 723 #endif
 724         } s;
 725 };
 726
 727 /** Information for a OCTEON ethernet interface shared between core & host. */
 728 struct oct_link_info {
 729         union oct_link_status link;
 730         u64 hw_addr;
 731
 732 #ifdef __BIG_ENDIAN_BITFIELD
 733         u64 gmxport:16;
 734         u64 rsvd:32;
 735         u64 num_txpciq:8;
 736         u64 num_rxpciq:8;
 737 #else
 738         u64 num_rxpciq:8;
 739         u64 num_txpciq:8;
 740         u64 rsvd:32;
 741         u64 gmxport:16;
 742 #endif
 743
 744         union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
 745         union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
 746 };
 747
 748 #define OCT_LINK_INFO_SIZE   (sizeof(struct oct_link_info))
 749
 750 struct liquidio_if_cfg_info {
 751         u64 iqmask; /** mask for IQs enabled for  the port */
 752         u64 oqmask; /** mask for OQs enabled for the port */
 753         struct oct_link_info linfo; /** initial link information */
 754         char   liquidio_firmware_version[32];
 755 };
 756
 757 /** Stats for each NIC port in RX direction. */
 758 struct nic_rx_stats {
 759         /* link-level stats */
 760         u64 total_rcvd;
 761         u64 bytes_rcvd;
 762         u64 total_bcst;
 763         u64 total_mcst;
 764         u64 runts;
 765         u64 ctl_rcvd;
 766         u64 fifo_err;      /* Accounts for over/under-run of buffers */
 767         u64 dmac_drop;
 768         u64 fcs_err;
 769         u64 jabber_err;
 770         u64 l2_err;
 771         u64 frame_err;
 772
 773         /* firmware stats */
 774         u64 fw_total_rcvd;
 775         u64 fw_total_fwd;
 776         u64 fw_err_pko;
 777         u64 fw_err_link;
 778         u64 fw_err_drop;
 779         u64 fw_rx_vxlan;
 780         u64 fw_rx_vxlan_err;
 781
 782         /* LRO */
 783         u64 fw_lro_pkts;   /* Number of packets that are LROed      */
 784         u64 fw_lro_octs;   /* Number of octets that are LROed       */
 785         u64 fw_total_lro;  /* Number of LRO packets formed          */
 786         u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
 787         u64 fw_lro_aborts_port;
 788         u64 fw_lro_aborts_seq;
 789         u64 fw_lro_aborts_tsval;
 790         u64 fw_lro_aborts_timer;
 791         /* intrmod: packet forward rate */
 792         u64 fwd_rate;
 793 };
 794
 795 /** Stats for each NIC port in RX direction. */
 796 struct nic_tx_stats {
 797         /* link-level stats */
 798         u64 total_pkts_sent;
 799         u64 total_bytes_sent;
 800         u64 mcast_pkts_sent;
 801         u64 bcast_pkts_sent;
 802         u64 ctl_sent;
 803         u64 one_collision_sent;   /* Packets sent after one collision*/
 804         u64 multi_collision_sent; /* Packets sent after multiple collision*/
 805         u64 max_collision_fail;   /* Packets not sent due to max collisions */
 806         u64 max_deferral_fail;   /* Packets not sent due to max deferrals */
 807         u64 fifo_err;       /* Accounts for over/under-run of buffers */
 808         u64 runts;
 809         u64 total_collisions; /* Total number of collisions detected */
 810
 811         /* firmware stats */
 812         u64 fw_total_sent;
 813         u64 fw_total_fwd;
 814         u64 fw_total_fwd_bytes;
 815         u64 fw_err_pko;
 816         u64 fw_err_link;
 817         u64 fw_err_drop;
 818         u64 fw_err_tso;
 819         u64 fw_tso;             /* number of tso requests */
 820         u64 fw_tso_fwd;         /* number of packets segmented in tso */
 821         u64 fw_tx_vxlan;
 822 };
 823
 824 struct oct_link_stats {
 825         struct nic_rx_stats fromwire;
 826         struct nic_tx_stats fromhost;
 827
 828 };
 829
 830 #define LIO68XX_LED_CTRL_ADDR     0x3501
 831 #define LIO68XX_LED_CTRL_CFGON    0x1f
 832 #define LIO68XX_LED_CTRL_CFGOFF   0x100
 833 #define LIO68XX_LED_BEACON_ADDR   0x3508
 834 #define LIO68XX_LED_BEACON_CFGON  0x47fd
 835 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
 836 #define VITESSE_PHY_GPIO_DRIVEON  0x1
 837 #define VITESSE_PHY_GPIO_CFG      0x8
 838 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
 839 #define VITESSE_PHY_GPIO_HIGH     0x2
 840 #define VITESSE_PHY_GPIO_LOW      0x3
 841 #define LED_IDENTIFICATION_ON     0x1
 842 #define LED_IDENTIFICATION_OFF    0x0
 843
 844 struct oct_mdio_cmd {
 845         u64 op;
 846         u64 mdio_addr;
 847         u64 value1;
 848         u64 value2;
 849         u64 value3;
 850 };
 851
 852 #define OCT_LINK_STATS_SIZE   (sizeof(struct oct_link_stats))
 853
 854 /* intrmod: max. packet rate threshold */
 855 #define LIO_INTRMOD_MAXPKT_RATETHR      196608
 856 /* intrmod: min. packet rate threshold */
 857 #define LIO_INTRMOD_MINPKT_RATETHR      9216
 858 /* intrmod: max. packets to trigger interrupt */
 859 #define LIO_INTRMOD_RXMAXCNT_TRIGGER    384
 860 /* intrmod: min. packets to trigger interrupt */
 861 #define LIO_INTRMOD_RXMINCNT_TRIGGER    0
 862 /* intrmod: max. time to trigger interrupt */
 863 #define LIO_INTRMOD_RXMAXTMR_TRIGGER    128
 864 /* 66xx:intrmod: min. time to trigger interrupt
 865  * (value of 1 is optimum for TCP_RR)
 866  */
 867 #define LIO_INTRMOD_RXMINTMR_TRIGGER    1
 868
 869 /* intrmod: max. packets to trigger interrupt */
 870 #define LIO_INTRMOD_TXMAXCNT_TRIGGER    64
 871 /* intrmod: min. packets to trigger interrupt */
 872 #define LIO_INTRMOD_TXMINCNT_TRIGGER    0
 873
 874 /* intrmod: poll interval in seconds */
 875 #define LIO_INTRMOD_CHECK_INTERVAL  1
 876
 877 struct oct_intrmod_cfg {
 878         u64 rx_enable;
 879         u64 tx_enable;
 880         u64 check_intrvl;
 881         u64 maxpkt_ratethr;
 882         u64 minpkt_ratethr;
 883         u64 rx_maxcnt_trigger;
 884         u64 rx_mincnt_trigger;
 885         u64 rx_maxtmr_trigger;
 886         u64 rx_mintmr_trigger;
 887         u64 tx_mincnt_trigger;
 888         u64 tx_maxcnt_trigger;
 889         u64 rx_frames;
 890         u64 tx_frames;
 891         u64 rx_usecs;
 892 };
 893
 894 #define BASE_QUEUE_NOT_REQUESTED 65535
 895
 896 union oct_nic_if_cfg {
 897         u64 u64;
 898         struct {
 899 #ifdef __BIG_ENDIAN_BITFIELD
 900                 u64 base_queue:16;
 901                 u64 num_iqueues:16;
 902                 u64 num_oqueues:16;
 903                 u64 gmx_port_id:8;
 904                 u64 vf_id:8;
 905 #else
 906                 u64 vf_id:8;
 907                 u64 gmx_port_id:8;
 908                 u64 num_oqueues:16;
 909                 u64 num_iqueues:16;
 910                 u64 base_queue:16;
 911 #endif
 912         } s;
 913 };
 914
 915 #endif