drivers/net/ethernet/cavium/liquidio/liquidio_common.h

   1 /**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2015 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * This file may also be available under a different license from Cavium.
  20 * Contact Cavium, Inc. for more information
  21 **********************************************************************/
  22
  23 /*!  \file  liquidio_common.h
  24  *   \brief Common: Structures and macros used in PCI-NIC package by core and
  25  *   host driver.
  26  */
  27
  28 #ifndef __LIQUIDIO_COMMON_H__
  29 #define __LIQUIDIO_COMMON_H__
  30
  31 #include "octeon_config.h"
  32
  33 #define LIQUIDIO_BASE_VERSION   "1.4"
  34 #define LIQUIDIO_MICRO_VERSION  ".1"
  35 #define LIQUIDIO_PACKAGE ""
  36 #define LIQUIDIO_VERSION  "1.4.1"
  37
  38 #define CONTROL_IQ 0
  39 /** Tag types used by Octeon cores in its work. */
  40 enum octeon_tag_type {
  41         ORDERED_TAG = 0,
  42         ATOMIC_TAG = 1,
  43         NULL_TAG = 2,
  44         NULL_NULL_TAG = 3
  45 };
  46
  47 /* pre-defined host->NIC tag values */
  48 #define LIO_CONTROL  (0x11111110)
  49 #define LIO_DATA(i)  (0x11111111 + (i))
  50
  51 /* Opcodes used by host driver/apps to perform operations on the core.
  52  * These are used to identify the major subsystem that the operation
  53  * is for.
  54  */
  55 #define OPCODE_CORE 0           /* used for generic core operations */
  56 #define OPCODE_NIC  1           /* used for NIC operations */
  57 #define OPCODE_LAST OPCODE_NIC
  58
  59 /* Subcodes are used by host driver/apps to identify the sub-operation
  60  * for the core. They only need to by unique for a given subsystem.
  61  */
  62 #define OPCODE_SUBCODE(op, sub)       (((op & 0x0f) << 8) | ((sub) & 0x7f))
  63
  64 /** OPCODE_CORE subcodes. For future use. */
  65
  66 /** OPCODE_NIC subcodes */
  67
  68 /* This subcode is sent by core PCI driver to indicate cores are ready. */
  69 #define OPCODE_NIC_CORE_DRV_ACTIVE     0x01
  70 #define OPCODE_NIC_NW_DATA             0x02     /* network packet data */
  71 #define OPCODE_NIC_CMD                 0x03
  72 #define OPCODE_NIC_INFO                0x04
  73 #define OPCODE_NIC_PORT_STATS          0x05
  74 #define OPCODE_NIC_MDIO45              0x06
  75 #define OPCODE_NIC_TIMESTAMP           0x07
  76 #define OPCODE_NIC_INTRMOD_CFG         0x08
  77 #define OPCODE_NIC_IF_CFG              0x09
  78
  79 #define CORE_DRV_TEST_SCATTER_OP    0xFFF5
  80
  81 #define OPCODE_SLOW_PATH(rh)  \
  82         (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
  83                 OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
  84
  85 /* Application codes advertised by the core driver initialization packet. */
  86 #define CVM_DRV_APP_START           0x0
  87 #define CVM_DRV_NO_APP              0
  88 #define CVM_DRV_APP_COUNT           0x2
  89 #define CVM_DRV_BASE_APP            (CVM_DRV_APP_START + 0x0)
  90 #define CVM_DRV_NIC_APP             (CVM_DRV_APP_START + 0x1)
  91 #define CVM_DRV_INVALID_APP         (CVM_DRV_APP_START + 0x2)
  92 #define CVM_DRV_APP_END             (CVM_DRV_INVALID_APP - 1)
  93
  94 /* Macro to increment index.
  95  * Index is incremented by count; if the sum exceeds
  96  * max, index is wrapped-around to the start.
  97  */
  98 #define INCR_INDEX(index, count, max)                \
  99 do {                                                 \
 100         if (((index) + (count)) >= (max))            \
 101                 index = ((index) + (count)) - (max); \
 102         else                                         \
 103                 index += (count);                    \
 104 } while (0)
 105
 106 #define INCR_INDEX_BY1(index, max)      \
 107 do {                                    \
 108         if ((++(index)) == (max))       \
 109                 index = 0;              \
 110 } while (0)
 111
 112 #define DECR_INDEX(index, count, max)                  \
 113 do {                                                   \
 114         if ((count) > (index))                         \
 115                 index = ((max) - ((count - index)));   \
 116         else                                           \
 117                 index -= count;                        \
 118 } while (0)
 119
 120 #define OCT_BOARD_NAME 32
 121 #define OCT_SERIAL_LEN 64
 122
 123 /* Structure used by core driver to send indication that the Octeon
 124  * application is ready.
 125  */
 126 struct octeon_core_setup {
 127         u64 corefreq;
 128
 129         char boardname[OCT_BOARD_NAME];
 130
 131         char board_serial_number[OCT_SERIAL_LEN];
 132
 133         u64 board_rev_major;
 134
 135         u64 board_rev_minor;
 136
 137 };
 138
 139 /*---------------------------  SCATTER GATHER ENTRY  -----------------------*/
 140
 141 /* The Scatter-Gather List Entry. The scatter or gather component used with
 142  * a Octeon input instruction has this format.
 143  */
 144 struct octeon_sg_entry {
 145         /** The first 64 bit gives the size of data in each dptr.*/
 146         union {
 147                 u16 size[4];
 148                 u64 size64;
 149         } u;
 150
 151         /** The 4 dptr pointers for this entry. */
 152         u64 ptr[4];
 153
 154 };
 155
 156 #define OCT_SG_ENTRY_SIZE    (sizeof(struct octeon_sg_entry))
 157
 158 /* \brief Add size to gather list
 159  * @param sg_entry scatter/gather entry
 160  * @param size size to add
 161  * @param pos position to add it.
 162  */
 163 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
 164                                u16 size,
 165                                u32 pos)
 166 {
 167 #ifdef __BIG_ENDIAN_BITFIELD
 168         sg_entry->u.size[pos] = size;
 169 #else
 170         sg_entry->u.size[3 - pos] = size;
 171 #endif
 172 }
 173
 174 /*------------------------- End Scatter/Gather ---------------------------*/
 175
 176 #define   OCTNET_FRM_PTP_HEADER_SIZE  8
 177
 178 #define   OCTNET_FRM_HEADER_SIZE     22 /* VLAN + Ethernet */
 179
 180 #define   OCTNET_MIN_FRM_SIZE        64
 181
 182 #define   OCTNET_MAX_FRM_SIZE        (16000 + OCTNET_FRM_HEADER_SIZE)
 183
 184 #define   OCTNET_DEFAULT_FRM_SIZE    (1500 + OCTNET_FRM_HEADER_SIZE)
 185
 186 /** NIC Commands are sent using this Octeon Input Queue */
 187 #define   OCTNET_CMD_Q                0
 188
 189 /* NIC Command types */
 190 #define   OCTNET_CMD_CHANGE_MTU       0x1
 191 #define   OCTNET_CMD_CHANGE_MACADDR   0x2
 192 #define   OCTNET_CMD_CHANGE_DEVFLAGS  0x3
 193 #define   OCTNET_CMD_RX_CTL           0x4
 194
 195 #define   OCTNET_CMD_SET_MULTI_LIST   0x5
 196 #define   OCTNET_CMD_CLEAR_STATS      0x6
 197
 198 /* command for setting the speed, duplex & autoneg */
 199 #define   OCTNET_CMD_SET_SETTINGS     0x7
 200 #define   OCTNET_CMD_SET_FLOW_CTL     0x8
 201
 202 #define   OCTNET_CMD_MDIO_READ_WRITE  0x9
 203 #define   OCTNET_CMD_GPIO_ACCESS      0xA
 204 #define   OCTNET_CMD_LRO_ENABLE       0xB
 205 #define   OCTNET_CMD_LRO_DISABLE      0xC
 206 #define   OCTNET_CMD_SET_RSS          0xD
 207 #define   OCTNET_CMD_WRITE_SA         0xE
 208 #define   OCTNET_CMD_DELETE_SA        0xF
 209 #define   OCTNET_CMD_UPDATE_SA        0x12
 210
 211 #define   OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
 212 #define   OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
 213 #define   OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
 214 #define   OCTNET_CMD_VERBOSE_ENABLE   0x14
 215 #define   OCTNET_CMD_VERBOSE_DISABLE  0x15
 216
 217 #define   OCTNET_CMD_ENABLE_VLAN_FILTER 0x16
 218 #define   OCTNET_CMD_ADD_VLAN_FILTER  0x17
 219 #define   OCTNET_CMD_DEL_VLAN_FILTER  0x18
 220 #define   OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
 221 #define   OCTNET_CMD_VXLAN_PORT_ADD    0x0
 222 #define   OCTNET_CMD_VXLAN_PORT_DEL    0x1
 223 #define   OCTNET_CMD_RXCSUM_ENABLE     0x0
 224 #define   OCTNET_CMD_RXCSUM_DISABLE    0x1
 225 #define   OCTNET_CMD_TXCSUM_ENABLE     0x0
 226 #define   OCTNET_CMD_TXCSUM_DISABLE    0x1
 227
 228 /* RX(packets coming from wire) Checksum verification flags */
 229 /* TCP/UDP csum */
 230 #define   CNNIC_L4SUM_VERIFIED             0x1
 231 #define   CNNIC_IPSUM_VERIFIED             0x2
 232 #define   CNNIC_TUN_CSUM_VERIFIED          0x4
 233 #define   CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
 234
 235 /*LROIPV4 and LROIPV6 Flags*/
 236 #define   OCTNIC_LROIPV4    0x1
 237 #define   OCTNIC_LROIPV6    0x2
 238
 239 /* Interface flags communicated between host driver and core app. */
 240 enum octnet_ifflags {
 241         OCTNET_IFFLAG_PROMISC   = 0x01,
 242         OCTNET_IFFLAG_ALLMULTI  = 0x02,
 243         OCTNET_IFFLAG_MULTICAST = 0x04,
 244         OCTNET_IFFLAG_BROADCAST = 0x08,
 245         OCTNET_IFFLAG_UNICAST   = 0x10
 246 };
 247
 248 /*   wqe
 249  *  ---------------  0
 250  * |  wqe  word0-3 |
 251  *  ---------------  32
 252  * |    PCI IH     |
 253  *  ---------------  40
 254  * |     RPTR      |
 255  *  ---------------  48
 256  * |    PCI IRH    |
 257  *  ---------------  56
 258  * |  OCT_NET_CMD  |
 259  *  ---------------  64
 260  * | Addtl 8-BData |
 261  * |               |
 262  *  ---------------
 263  */
 264
 265 union octnet_cmd {
 266         u64 u64;
 267
 268         struct {
 269 #ifdef __BIG_ENDIAN_BITFIELD
 270                 u64 cmd:5;
 271
 272                 u64 more:6; /* How many udd words follow the command */
 273
 274                 u64 reserved:29;
 275
 276                 u64 param1:16;
 277
 278                 u64 param2:8;
 279
 280 #else
 281
 282                 u64 param2:8;
 283
 284                 u64 param1:16;
 285
 286                 u64 reserved:29;
 287
 288                 u64 more:6;
 289
 290                 u64 cmd:5;
 291
 292 #endif
 293         } s;
 294
 295 };
 296
 297 #define   OCTNET_CMD_SIZE     (sizeof(union octnet_cmd))
 298
 299 /* Instruction Header(DPI) - for OCTEON-III models */
 300 struct  octeon_instr_ih3 {
 301 #ifdef __BIG_ENDIAN_BITFIELD
 302
 303         /** Reserved3 */
 304         u64     reserved3:1;
 305
 306         /** Gather indicator 1=gather*/
 307         u64     gather:1;
 308
 309         /** Data length OR no. of entries in gather list */
 310         u64     dlengsz:14;
 311
 312         /** Front Data size */
 313         u64     fsz:6;
 314
 315         /** Reserved2 */
 316         u64     reserved2:4;
 317
 318         /** PKI port kind - PKIND */
 319         u64     pkind:6;
 320
 321         /** Reserved1 */
 322         u64     reserved1:32;
 323
 324 #else
 325         /** Reserved1 */
 326         u64     reserved1:32;
 327
 328         /** PKI port kind - PKIND */
 329         u64     pkind:6;
 330
 331         /** Reserved2 */
 332         u64     reserved2:4;
 333
 334         /** Front Data size */
 335         u64     fsz:6;
 336
 337         /** Data length OR no. of entries in gather list */
 338         u64     dlengsz:14;
 339
 340         /** Gather indicator 1=gather*/
 341         u64     gather:1;
 342
 343         /** Reserved3 */
 344         u64     reserved3:1;
 345
 346 #endif
 347 };
 348
 349 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
 350 /** BIG ENDIAN format.   */
 351 struct  octeon_instr_pki_ih3 {
 352 #ifdef __BIG_ENDIAN_BITFIELD
 353
 354         /** Wider bit */
 355         u64     w:1;
 356
 357         /** Raw mode indicator 1 = RAW */
 358         u64     raw:1;
 359
 360         /** Use Tag */
 361         u64     utag:1;
 362
 363         /** Use QPG */
 364         u64     uqpg:1;
 365
 366         /** Reserved2 */
 367         u64     reserved2:1;
 368
 369         /** Parse Mode */
 370         u64     pm:3;
 371
 372         /** Skip Length */
 373         u64     sl:8;
 374
 375         /** Use Tag Type */
 376         u64     utt:1;
 377
 378         /** Tag type */
 379         u64     tagtype:2;
 380
 381         /** Reserved1 */
 382         u64     reserved1:2;
 383
 384         /** QPG Value */
 385         u64     qpg:11;
 386
 387         /** Tag Value */
 388         u64     tag:32;
 389
 390 #else
 391
 392         /** Tag Value */
 393         u64     tag:32;
 394
 395         /** QPG Value */
 396         u64     qpg:11;
 397
 398         /** Reserved1 */
 399         u64     reserved1:2;
 400
 401         /** Tag type */
 402         u64     tagtype:2;
 403
 404         /** Use Tag Type */
 405         u64     utt:1;
 406
 407         /** Skip Length */
 408         u64     sl:8;
 409
 410         /** Parse Mode */
 411         u64     pm:3;
 412
 413         /** Reserved2 */
 414         u64     reserved2:1;
 415
 416         /** Use QPG */
 417         u64     uqpg:1;
 418
 419         /** Use Tag */
 420         u64     utag:1;
 421
 422         /** Raw mode indicator 1 = RAW */
 423         u64     raw:1;
 424
 425         /** Wider bit */
 426         u64     w:1;
 427 #endif
 428
 429 };
 430
 431 /** Instruction Header */
 432 struct octeon_instr_ih2 {
 433 #ifdef __BIG_ENDIAN_BITFIELD
 434         /** Raw mode indicator 1 = RAW */
 435         u64 raw:1;
 436
 437         /** Gather indicator 1=gather*/
 438         u64 gather:1;
 439
 440         /** Data length OR no. of entries in gather list */
 441         u64 dlengsz:14;
 442
 443         /** Front Data size */
 444         u64 fsz:6;
 445
 446         /** Packet Order / Work Unit selection (1 of 8)*/
 447         u64 qos:3;
 448
 449         /** Core group selection (1 of 16) */
 450         u64 grp:4;
 451
 452         /** Short Raw Packet Indicator 1=short raw pkt */
 453         u64 rs:1;
 454
 455         /** Tag type */
 456         u64 tagtype:2;
 457
 458         /** Tag Value */
 459         u64 tag:32;
 460 #else
 461         /** Tag Value */
 462         u64 tag:32;
 463
 464         /** Tag type */
 465         u64 tagtype:2;
 466
 467         /** Short Raw Packet Indicator 1=short raw pkt */
 468         u64 rs:1;
 469
 470         /** Core group selection (1 of 16) */
 471         u64 grp:4;
 472
 473         /** Packet Order / Work Unit selection (1 of 8)*/
 474         u64 qos:3;
 475
 476         /** Front Data size */
 477         u64 fsz:6;
 478
 479         /** Data length OR no. of entries in gather list */
 480         u64 dlengsz:14;
 481
 482         /** Gather indicator 1=gather*/
 483         u64 gather:1;
 484
 485         /** Raw mode indicator 1 = RAW */
 486         u64 raw:1;
 487 #endif
 488 };
 489
 490 /** Input Request Header */
 491 struct octeon_instr_irh {
 492 #ifdef __BIG_ENDIAN_BITFIELD
 493         u64 opcode:4;
 494         u64 rflag:1;
 495         u64 subcode:7;
 496         u64 vlan:12;
 497         u64 priority:3;
 498         u64 reserved:5;
 499         u64 ossp:32;             /* opcode/subcode specific parameters */
 500 #else
 501         u64 ossp:32;             /* opcode/subcode specific parameters */
 502         u64 reserved:5;
 503         u64 priority:3;
 504         u64 vlan:12;
 505         u64 subcode:7;
 506         u64 rflag:1;
 507         u64 opcode:4;
 508 #endif
 509 };
 510
 511 /** Return Data Parameters */
 512 struct octeon_instr_rdp {
 513 #ifdef __BIG_ENDIAN_BITFIELD
 514         u64 reserved:49;
 515         u64 pcie_port:3;
 516         u64 rlen:12;
 517 #else
 518         u64 rlen:12;
 519         u64 pcie_port:3;
 520         u64 reserved:49;
 521 #endif
 522 };
 523
 524 /** Receive Header */
 525 union octeon_rh {
 526 #ifdef __BIG_ENDIAN_BITFIELD
 527         u64 u64;
 528         struct {
 529                 u64 opcode:4;
 530                 u64 subcode:8;
 531                 u64 len:3;     /** additional 64-bit words */
 532                 u64 reserved:17;
 533                 u64 ossp:32;   /** opcode/subcode specific parameters */
 534         } r;
 535         struct {
 536                 u64 opcode:4;
 537                 u64 subcode:8;
 538                 u64 len:3;     /** additional 64-bit words */
 539                 u64 extra:28;
 540                 u64 vlan:12;
 541                 u64 priority:3;
 542                 u64 csum_verified:3;     /** checksum verified. */
 543                 u64 has_hwtstamp:1;      /** Has hardware timestamp. 1 = yes. */
 544                 u64 encap_on:1;
 545                 u64 has_hash:1;          /** Has hash (rth or rss). 1 = yes. */
 546         } r_dh;
 547         struct {
 548                 u64 opcode:4;
 549                 u64 subcode:8;
 550                 u64 len:3;     /** additional 64-bit words */
 551                 u64 reserved:11;
 552                 u64 num_gmx_ports:8;
 553                 u64 max_nic_ports:10;
 554                 u64 app_cap_flags:4;
 555                 u64 app_mode:8;
 556                 u64 pkind:8;
 557         } r_core_drv_init;
 558         struct {
 559                 u64 opcode:4;
 560                 u64 subcode:8;
 561                 u64 len:3;       /** additional 64-bit words */
 562                 u64 reserved:8;
 563                 u64 extra:25;
 564                 u64 gmxport:16;
 565         } r_nic_info;
 566 #else
 567         u64 u64;
 568         struct {
 569                 u64 ossp:32;  /** opcode/subcode specific parameters */
 570                 u64 reserved:17;
 571                 u64 len:3;    /** additional 64-bit words */
 572                 u64 subcode:8;
 573                 u64 opcode:4;
 574         } r;
 575         struct {
 576                 u64 has_hash:1;          /** Has hash (rth or rss). 1 = yes. */
 577                 u64 encap_on:1;
 578                 u64 has_hwtstamp:1;      /** 1 = has hwtstamp */
 579                 u64 csum_verified:3;     /** checksum verified. */
 580                 u64 priority:3;
 581                 u64 vlan:12;
 582                 u64 extra:28;
 583                 u64 len:3;    /** additional 64-bit words */
 584                 u64 subcode:8;
 585                 u64 opcode:4;
 586         } r_dh;
 587         struct {
 588                 u64 pkind:8;
 589                 u64 app_mode:8;
 590                 u64 app_cap_flags:4;
 591                 u64 max_nic_ports:10;
 592                 u64 num_gmx_ports:8;
 593                 u64 reserved:11;
 594                 u64 len:3;       /** additional 64-bit words */
 595                 u64 subcode:8;
 596                 u64 opcode:4;
 597         } r_core_drv_init;
 598         struct {
 599                 u64 gmxport:16;
 600                 u64 extra:25;
 601                 u64 reserved:8;
 602                 u64 len:3;       /** additional 64-bit words */
 603                 u64 subcode:8;
 604                 u64 opcode:4;
 605         } r_nic_info;
 606 #endif
 607 };
 608
 609 #define  OCT_RH_SIZE   (sizeof(union  octeon_rh))
 610
 611 union octnic_packet_params {
 612         u32 u32;
 613         struct {
 614 #ifdef __BIG_ENDIAN_BITFIELD
 615                 u32 reserved:24;
 616                 u32 ip_csum:1;          /* Perform IP header checksum(s) */
 617                 /* Perform Outer transport header checksum */
 618                 u32 transport_csum:1;
 619                 /* Find tunnel, and perform transport csum. */
 620                 u32 tnl_csum:1;
 621                 u32 tsflag:1;           /* Timestamp this packet */
 622                 u32 ipsec_ops:4;        /* IPsec operation */
 623 #else
 624                 u32 ipsec_ops:4;
 625                 u32 tsflag:1;
 626                 u32 tnl_csum:1;
 627                 u32 transport_csum:1;
 628                 u32 ip_csum:1;
 629                 u32 reserved:24;
 630 #endif
 631         } s;
 632 };
 633
 634 /** Status of a RGMII Link on Octeon as seen by core driver. */
 635 union oct_link_status {
 636         u64 u64;
 637
 638         struct {
 639 #ifdef __BIG_ENDIAN_BITFIELD
 640                 u64 duplex:8;
 641                 u64 mtu:16;
 642                 u64 speed:16;
 643                 u64 link_up:1;
 644                 u64 autoneg:1;
 645                 u64 if_mode:5;
 646                 u64 pause:1;
 647                 u64 flashing:1;
 648                 u64 reserved:15;
 649 #else
 650                 u64 reserved:15;
 651                 u64 flashing:1;
 652                 u64 pause:1;
 653                 u64 if_mode:5;
 654                 u64 autoneg:1;
 655                 u64 link_up:1;
 656                 u64 speed:16;
 657                 u64 mtu:16;
 658                 u64 duplex:8;
 659 #endif
 660         } s;
 661 };
 662
 663 /** The txpciq info passed to host from the firmware */
 664
 665 union oct_txpciq {
 666         u64 u64;
 667
 668         struct {
 669 #ifdef __BIG_ENDIAN_BITFIELD
 670                 u64 q_no:8;
 671                 u64 port:8;
 672                 u64 pkind:6;
 673                 u64 use_qpg:1;
 674                 u64 qpg:11;
 675                 u64 reserved:30;
 676 #else
 677                 u64 reserved:30;
 678                 u64 qpg:11;
 679                 u64 use_qpg:1;
 680                 u64 pkind:6;
 681                 u64 port:8;
 682                 u64 q_no:8;
 683 #endif
 684         } s;
 685 };
 686
 687 /** The rxpciq info passed to host from the firmware */
 688
 689 union oct_rxpciq {
 690         u64 u64;
 691
 692         struct {
 693 #ifdef __BIG_ENDIAN_BITFIELD
 694                 u64 q_no:8;
 695                 u64 reserved:56;
 696 #else
 697                 u64 reserved:56;
 698                 u64 q_no:8;
 699 #endif
 700         } s;
 701 };
 702
 703 /** Information for a OCTEON ethernet interface shared between core & host. */
 704 struct oct_link_info {
 705         union oct_link_status link;
 706         u64 hw_addr;
 707
 708 #ifdef __BIG_ENDIAN_BITFIELD
 709         u64 gmxport:16;
 710         u64 rsvd:32;
 711         u64 num_txpciq:8;
 712         u64 num_rxpciq:8;
 713 #else
 714         u64 num_rxpciq:8;
 715         u64 num_txpciq:8;
 716         u64 rsvd:32;
 717         u64 gmxport:16;
 718 #endif
 719
 720         union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
 721         union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
 722 };
 723
 724 #define OCT_LINK_INFO_SIZE   (sizeof(struct oct_link_info))
 725
 726 struct liquidio_if_cfg_info {
 727         u64 iqmask; /** mask for IQs enabled for  the port */
 728         u64 oqmask; /** mask for OQs enabled for the port */
 729         struct oct_link_info linfo; /** initial link information */
 730         char   liquidio_firmware_version[32];
 731 };
 732
 733 /** Stats for each NIC port in RX direction. */
 734 struct nic_rx_stats {
 735         /* link-level stats */
 736         u64 total_rcvd;
 737         u64 bytes_rcvd;
 738         u64 total_bcst;
 739         u64 total_mcst;
 740         u64 runts;
 741         u64 ctl_rcvd;
 742         u64 fifo_err;      /* Accounts for over/under-run of buffers */
 743         u64 dmac_drop;
 744         u64 fcs_err;
 745         u64 jabber_err;
 746         u64 l2_err;
 747         u64 frame_err;
 748
 749         /* firmware stats */
 750         u64 fw_total_rcvd;
 751         u64 fw_total_fwd;
 752         u64 fw_err_pko;
 753         u64 fw_err_link;
 754         u64 fw_err_drop;
 755         u64 fw_rx_vxlan;
 756         u64 fw_rx_vxlan_err;
 757
 758         /* LRO */
 759         u64 fw_lro_pkts;   /* Number of packets that are LROed      */
 760         u64 fw_lro_octs;   /* Number of octets that are LROed       */
 761         u64 fw_total_lro;  /* Number of LRO packets formed          */
 762         u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
 763         u64 fw_lro_aborts_port;
 764         u64 fw_lro_aborts_seq;
 765         u64 fw_lro_aborts_tsval;
 766         u64 fw_lro_aborts_timer;
 767         /* intrmod: packet forward rate */
 768         u64 fwd_rate;
 769 };
 770
 771 /** Stats for each NIC port in RX direction. */
 772 struct nic_tx_stats {
 773         /* link-level stats */
 774         u64 total_pkts_sent;
 775         u64 total_bytes_sent;
 776         u64 mcast_pkts_sent;
 777         u64 bcast_pkts_sent;
 778         u64 ctl_sent;
 779         u64 one_collision_sent;   /* Packets sent after one collision*/
 780         u64 multi_collision_sent; /* Packets sent after multiple collision*/
 781         u64 max_collision_fail;   /* Packets not sent due to max collisions */
 782         u64 max_deferral_fail;   /* Packets not sent due to max deferrals */
 783         u64 fifo_err;       /* Accounts for over/under-run of buffers */
 784         u64 runts;
 785         u64 total_collisions; /* Total number of collisions detected */
 786
 787         /* firmware stats */
 788         u64 fw_total_sent;
 789         u64 fw_total_fwd;
 790         u64 fw_total_fwd_bytes;
 791         u64 fw_err_pko;
 792         u64 fw_err_link;
 793         u64 fw_err_drop;
 794         u64 fw_err_tso;
 795         u64 fw_tso;             /* number of tso requests */
 796         u64 fw_tso_fwd;         /* number of packets segmented in tso */
 797         u64 fw_tx_vxlan;
 798 };
 799
 800 struct oct_link_stats {
 801         struct nic_rx_stats fromwire;
 802         struct nic_tx_stats fromhost;
 803
 804 };
 805
 806 #define LIO68XX_LED_CTRL_ADDR     0x3501
 807 #define LIO68XX_LED_CTRL_CFGON    0x1f
 808 #define LIO68XX_LED_CTRL_CFGOFF   0x100
 809 #define LIO68XX_LED_BEACON_ADDR   0x3508
 810 #define LIO68XX_LED_BEACON_CFGON  0x47fd
 811 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
 812 #define VITESSE_PHY_GPIO_DRIVEON  0x1
 813 #define VITESSE_PHY_GPIO_CFG      0x8
 814 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
 815 #define VITESSE_PHY_GPIO_HIGH     0x2
 816 #define VITESSE_PHY_GPIO_LOW      0x3
 817
 818 struct oct_mdio_cmd {
 819         u64 op;
 820         u64 mdio_addr;
 821         u64 value1;
 822         u64 value2;
 823         u64 value3;
 824 };
 825
 826 #define OCT_LINK_STATS_SIZE   (sizeof(struct oct_link_stats))
 827
 828 /* intrmod: max. packet rate threshold */
 829 #define LIO_INTRMOD_MAXPKT_RATETHR      196608
 830 /* intrmod: min. packet rate threshold */
 831 #define LIO_INTRMOD_MINPKT_RATETHR      9216
 832 /* intrmod: max. packets to trigger interrupt */
 833 #define LIO_INTRMOD_RXMAXCNT_TRIGGER    384
 834 /* intrmod: min. packets to trigger interrupt */
 835 #define LIO_INTRMOD_RXMINCNT_TRIGGER    1
 836 /* intrmod: max. time to trigger interrupt */
 837 #define LIO_INTRMOD_RXMAXTMR_TRIGGER    128
 838 /* 66xx:intrmod: min. time to trigger interrupt
 839  * (value of 1 is optimum for TCP_RR)
 840  */
 841 #define LIO_INTRMOD_RXMINTMR_TRIGGER    1
 842
 843 /* intrmod: max. packets to trigger interrupt */
 844 #define LIO_INTRMOD_TXMAXCNT_TRIGGER    64
 845 /* intrmod: min. packets to trigger interrupt */
 846 #define LIO_INTRMOD_TXMINCNT_TRIGGER    0
 847
 848 /* intrmod: poll interval in seconds */
 849 #define LIO_INTRMOD_CHECK_INTERVAL  1
 850
 851 struct oct_intrmod_cfg {
 852         u64 rx_enable;
 853         u64 tx_enable;
 854         u64 check_intrvl;
 855         u64 maxpkt_ratethr;
 856         u64 minpkt_ratethr;
 857         u64 rx_maxcnt_trigger;
 858         u64 rx_mincnt_trigger;
 859         u64 rx_maxtmr_trigger;
 860         u64 rx_mintmr_trigger;
 861         u64 tx_mincnt_trigger;
 862         u64 tx_maxcnt_trigger;
 863         u64 rx_frames;
 864         u64 tx_frames;
 865         u64 rx_usecs;
 866 };
 867
 868 #define BASE_QUEUE_NOT_REQUESTED 65535
 869
 870 union oct_nic_if_cfg {
 871         u64 u64;
 872         struct {
 873 #ifdef __BIG_ENDIAN_BITFIELD
 874                 u64 base_queue:16;
 875                 u64 num_iqueues:16;
 876                 u64 num_oqueues:16;
 877                 u64 gmx_port_id:8;
 878                 u64 vf_id:8;
 879 #else
 880                 u64 vf_id:8;
 881                 u64 gmx_port_id:8;
 882                 u64 num_oqueues:16;
 883                 u64 num_iqueues:16;
 884                 u64 base_queue:16;
 885 #endif
 886         } s;
 887 };
 888
 889 #endif