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5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
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15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
23 /*! \file octeon_config.h
24 * \brief Host Driver: Configuration data structures for the host driver.
27 #ifndef __OCTEON_CONFIG_H__
28 #define __OCTEON_CONFIG_H__
30 /*--------------------------CONFIG VALUES------------------------*/
32 /* The following macros affect the way the driver data structures
33 * are generated for Octeon devices.
34 * They can be modified.
37 /* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
38 * multiple(<= MAX_OCTEON_NICIF) Miniports
40 #define MAX_OCTEON_NICIF 128
41 #define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF
42 #define MAX_OCTEON_LINKS MAX_OCTEON_NICIF
43 #define MAX_OCTEON_MULTICAST_ADDR 32
45 /* CN6xxx IQ configuration macros */
46 #define CN6XXX_MAX_INPUT_QUEUES 32
47 #define CN6XXX_MAX_IQ_DESCRIPTORS 2048
48 #define CN6XXX_DB_MIN 1
49 #define CN6XXX_DB_MAX 8
50 #define CN6XXX_DB_TIMEOUT 1
52 /* CN6xxx OQ configuration macros */
53 #define CN6XXX_MAX_OUTPUT_QUEUES 32
54 #define CN6XXX_MAX_OQ_DESCRIPTORS 2048
55 #define CN6XXX_OQ_BUF_SIZE 1536
56 #define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
57 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
58 #define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
59 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
61 #define CN6XXX_OQ_INTR_PKT 64
62 #define CN6XXX_OQ_INTR_TIME 100
63 #define DEFAULT_NUM_NIC_PORTS_66XX 2
64 #define DEFAULT_NUM_NIC_PORTS_68XX 4
65 #define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
67 /* CN23xx IQ configuration macros */
68 #define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
69 #define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
70 #define CN23XX_MAX_RINGS_PER_PF 64
72 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
73 #define CN23XX_MAX_IQ_DESCRIPTORS 2048
74 #define CN23XX_DB_MIN 1
75 #define CN23XX_DB_MAX 8
76 #define CN23XX_DB_TIMEOUT 1
78 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
79 #define CN23XX_MAX_OQ_DESCRIPTORS 2048
80 #define CN23XX_OQ_BUF_SIZE 1536
81 #define CN23XX_OQ_PKTSPER_INTR 128
82 /*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
83 #define CN23XX_OQ_REFIL_THRESHOLD 128
85 #define CN23XX_OQ_INTR_PKT 64
86 #define CN23XX_OQ_INTR_TIME 100
87 #define DEFAULT_NUM_NIC_PORTS_23XX 1
89 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
91 #define CN23XX_MAX_MACS 4
93 #define CN23XX_DEF_IQ_INTR_THRESHOLD 32
94 #define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024)
95 /* common OCTEON configuration macros */
96 #define CN6XXX_CFG_IO_QUEUES 32
97 #define OCTEON_32BYTE_INSTR 32
98 #define OCTEON_64BYTE_INSTR 64
99 #define OCTEON_MAX_BASE_IOQ 4
100 #define OCTEON_OQ_BUFPTR_MODE 0
101 #define OCTEON_OQ_INFOPTR_MODE 1
103 #define OCTEON_DMA_INTR_PKT 64
104 #define OCTEON_DMA_INTR_TIME 1000
106 #define MAX_TXQS_PER_INTF 8
107 #define MAX_RXQS_PER_INTF 8
108 #define DEF_TXQS_PER_INTF 4
109 #define DEF_RXQS_PER_INTF 4
111 #define INVALID_IOQ_NO 0xff
113 #define DEFAULT_POW_GRP 0
115 /* Macros to get octeon config params */
116 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
117 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
118 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
119 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
120 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
121 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
123 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
124 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
126 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
127 #define CFG_GET_OQ_INFO_PTR(cfg) ((cfg)->oq.info_ptr)
128 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
129 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
130 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
131 #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
132 #define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val
133 #define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val
135 #define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt)
136 #define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time)
137 #define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports)
138 #define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs)
139 #define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs)
140 #define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size)
142 #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
143 ((cfg)->nic_if_cfg[idx].max_txqs)
144 #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
145 ((cfg)->nic_if_cfg[idx].num_txqs)
146 #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
147 ((cfg)->nic_if_cfg[idx].max_rxqs)
148 #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
149 ((cfg)->nic_if_cfg[idx].num_rxqs)
150 #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
151 ((cfg)->nic_if_cfg[idx].num_rx_descs)
152 #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
153 ((cfg)->nic_if_cfg[idx].num_tx_descs)
154 #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
155 ((cfg)->nic_if_cfg[idx].rx_buf_size)
156 #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
157 ((cfg)->nic_if_cfg[idx].base_queue)
158 #define CFG_GET_GMXID_NIC_IF(cfg, idx) \
159 ((cfg)->nic_if_cfg[idx].gmx_port_id)
161 #define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp)
162 #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
163 ((cfg)->misc.host_link_query_interval)
164 #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
165 ((cfg)->misc.oct_link_query_interval)
166 #define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp)
168 /* Max IOQs per OCTEON Link */
169 #define MAX_IOQS_PER_NICIF 64
172 LIO_210SV
= 0, /* Two port, 66xx */
173 LIO_210NV
, /* Two port, 68xx */
174 LIO_410NV
, /* Four port, 68xx */
178 #define LIO_210SV_NAME "210sv"
179 #define LIO_210NV_NAME "210nv"
180 #define LIO_410NV_NAME "410nv"
181 #define LIO_23XX_NAME "23xx"
183 /** Structure to define the configuration attributes for each Input queue.
184 * Applicable to all Octeon processors
186 struct octeon_iq_config
{
187 #ifdef __BIG_ENDIAN_BITFIELD
190 /** Tx interrupt packets. Applicable to 23xx only */
193 /** Minimum ticks to wait before checking for pending instructions. */
196 /** Minimum number of commands pending to be posted to Octeon
197 * before driver hits the Input queue doorbell.
201 /** Command size - 32 or 64 bytes */
204 /** Pending list size (usually set to the sum of the size of all Input
207 u64 pending_list_size
:32;
209 /* Max number of IQs available */
212 /* Max number of IQs available */
215 /** Pending list size (usually set to the sum of the size of all Input
218 u64 pending_list_size
:32;
220 /** Command size - 32 or 64 bytes */
223 /** Minimum number of commands pending to be posted to Octeon
224 * before driver hits the Input queue doorbell.
228 /** Minimum ticks to wait before checking for pending instructions. */
231 /** Tx interrupt packets. Applicable to 23xx only */
238 /** Structure to define the configuration attributes for each Output queue.
239 * Applicable to all Octeon processors
241 struct octeon_oq_config
{
242 #ifdef __BIG_ENDIAN_BITFIELD
245 u64 pkts_per_intr
:16;
247 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
248 * host if atleast one packet was sent in the time interval specified
249 * by this field. The driver uses time interval interrupt coalescing
250 * by default. The time is specified in microseconds.
254 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
255 * only if it sent as many packets as specified by this field.
257 * usually does not use packet count interrupt coalescing.
261 /** The number of buffers that were consumed during packet processing by
262 * the driver on this Output queue before the driver attempts to
264 * the descriptor ring with new buffers.
266 u64 refill_threshold
:16;
268 /** If set, the Output queue uses info-pointer mode. (Default: 1) */
271 /* Max number of OQs available */
275 /* Max number of OQs available */
278 /** If set, the Output queue uses info-pointer mode. (Default: 1) */
281 /** The number of buffers that were consumed during packet processing by
282 * the driver on this Output queue before the driver attempts to
284 * the descriptor ring with new buffers.
286 u64 refill_threshold
:16;
288 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
289 * only if it sent as many packets as specified by this field.
291 * usually does not use packet count interrupt coalescing.
295 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
296 * host if atleast one packet was sent in the time interval specified
297 * by this field. The driver uses time interval interrupt coalescing
298 * by default. The time is specified in microseconds.
302 u64 pkts_per_intr
:16;
309 /** This structure conatins the NIC link configuration attributes,
310 * common for all the OCTEON Modles.
312 struct octeon_nic_if_config
{
313 #ifdef __BIG_ENDIAN_BITFIELD
320 /* SKB size, We need not change buf size even for Jumbo frames.
321 * Octeon can send jumbo frames in 4 consecutive descriptors,
325 /* Num of desc for tx rings */
328 /* Num of desc for rx rings */
331 /* Actual configured value. Range could be: 1...max_rxqs */
334 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
337 /* Actual configured value. Range could be: 1...max_txqs */
340 /* Max Txqs: Half for each of the two ports :max_iq/2 */
343 /* Max Txqs: Half for each of the two ports :max_iq/2 */
346 /* Actual configured value. Range could be: 1...max_txqs */
349 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
352 /* Actual configured value. Range could be: 1...max_rxqs */
355 /* Num of desc for rx rings */
358 /* Num of desc for tx rings */
361 /* SKB size, We need not change buf size even for Jumbo frames.
362 * Octeon can send jumbo frames in 4 consecutive descriptors,
375 /** Structure to define the configuration attributes for meta data.
376 * Applicable to all Octeon processors.
379 struct octeon_misc_config
{
380 #ifdef __BIG_ENDIAN_BITFIELD
381 /** Host link status polling period */
382 u64 host_link_query_interval
:32;
383 /** Oct link status polling period */
384 u64 oct_link_query_interval
:32;
386 u64 enable_sli_oq_bp
:1;
387 /** Control IQ Group */
390 /** Control IQ Group */
393 u64 enable_sli_oq_bp
:1;
394 /** Host link status polling period */
395 u64 oct_link_query_interval
:32;
396 /** Oct link status polling period */
397 u64 host_link_query_interval
:32;
401 /** Structure to define the configuration for all OCTEON processors. */
402 struct octeon_config
{
406 /** Input Queue attributes. */
407 struct octeon_iq_config iq
;
409 /** Output Queue attributes. */
410 struct octeon_oq_config oq
;
412 /** NIC Port Configuration */
413 struct octeon_nic_if_config nic_if_cfg
[MAX_OCTEON_NICIF
];
415 /** Miscellaneous attributes */
416 struct octeon_misc_config misc
;
420 int num_def_tx_descs
;
422 /* Num of desc for rx rings */
423 int num_def_rx_descs
;
429 /* The following config values are fixed and should not be modified. */
431 /* Maximum address space to be mapped for Octeon's BAR1 index-based access. */
432 #define MAX_BAR1_MAP_INDEX 2
433 #define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024)
435 /* BAR1 Index 0 to (MAX_BAR1_MAP_INDEX - 1) for normal mapped memory access.
436 * Bar1 register at MAX_BAR1_MAP_INDEX used by driver for dynamic access.
438 #define MAX_BAR1_IOREMAP_SIZE ((MAX_BAR1_MAP_INDEX + 1) * \
439 OCTEON_BAR1_ENTRY_SIZE)
441 /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
442 * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
444 #define MAX_RESPONSE_LISTS 4
446 /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
449 #define OPCODE_MASK_BITS 6
451 /* Mask for the 6-bit lookup hash */
452 #define OCTEON_OPCODE_MASK 0x3f
454 /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
455 #define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS)
457 /* Maximum number of Octeon Instruction (command) queues */
458 #define MAX_OCTEON_INSTR_QUEUES(oct) \
459 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
460 CN6XXX_MAX_INPUT_QUEUES)
462 /* Maximum number of Octeon Instruction (command) queues */
463 #define MAX_OCTEON_OUTPUT_QUEUES(oct) \
464 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
465 CN6XXX_MAX_OUTPUT_QUEUES)
467 #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
468 #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
469 #endif /* __OCTEON_CONFIG_H__ */