2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
10 #include <linux/netdevice.h>
12 #include <linux/etherdevice.h>
19 #include "nicvf_queues.h"
21 static void nicvf_get_page(struct nicvf
*nic
)
23 if (!nic
->rb_pageref
|| !nic
->rb_page
)
26 page_ref_add(nic
->rb_page
, nic
->rb_pageref
);
30 /* Poll a register for a specific value */
31 static int nicvf_poll_reg(struct nicvf
*nic
, int qidx
,
32 u64 reg
, int bit_pos
, int bits
, int val
)
38 bit_mask
= (1ULL << bits
) - 1;
39 bit_mask
= (bit_mask
<< bit_pos
);
42 reg_val
= nicvf_queue_reg_read(nic
, reg
, qidx
);
43 if (((reg_val
& bit_mask
) >> bit_pos
) == val
)
45 usleep_range(1000, 2000);
48 netdev_err(nic
->netdev
, "Poll on reg 0x%llx failed\n", reg
);
52 /* Allocate memory for a queue's descriptors */
53 static int nicvf_alloc_q_desc_mem(struct nicvf
*nic
, struct q_desc_mem
*dmem
,
54 int q_len
, int desc_size
, int align_bytes
)
57 dmem
->size
= (desc_size
* q_len
) + align_bytes
;
58 /* Save address, need it while freeing */
59 dmem
->unalign_base
= dma_zalloc_coherent(&nic
->pdev
->dev
, dmem
->size
,
60 &dmem
->dma
, GFP_KERNEL
);
61 if (!dmem
->unalign_base
)
64 /* Align memory address for 'align_bytes' */
65 dmem
->phys_base
= NICVF_ALIGNED_ADDR((u64
)dmem
->dma
, align_bytes
);
66 dmem
->base
= dmem
->unalign_base
+ (dmem
->phys_base
- dmem
->dma
);
70 /* Free queue's descriptor memory */
71 static void nicvf_free_q_desc_mem(struct nicvf
*nic
, struct q_desc_mem
*dmem
)
76 dma_free_coherent(&nic
->pdev
->dev
, dmem
->size
,
77 dmem
->unalign_base
, dmem
->dma
);
78 dmem
->unalign_base
= NULL
;
82 /* Allocate buffer for packet reception
83 * HW returns memory address where packet is DMA'ed but not a pointer
84 * into RBDR ring, so save buffer address at the start of fragment and
85 * align the start address to a cache aligned address
87 static inline int nicvf_alloc_rcv_buffer(struct nicvf
*nic
, gfp_t gfp
,
88 u32 buf_len
, u64
**rbuf
)
90 int order
= (PAGE_SIZE
<= 4096) ? PAGE_ALLOC_COSTLY_ORDER
: 0;
92 /* Check if request can be accomodated in previous allocated page */
94 ((nic
->rb_page_offset
+ buf_len
) < (PAGE_SIZE
<< order
))) {
102 /* Allocate a new page */
104 nic
->rb_page
= alloc_pages(gfp
| __GFP_COMP
| __GFP_NOWARN
,
107 nic
->drv_stats
.rcv_buffer_alloc_failures
++;
110 nic
->rb_page_offset
= 0;
114 *rbuf
= (u64
*)((u64
)page_address(nic
->rb_page
) + nic
->rb_page_offset
);
115 nic
->rb_page_offset
+= buf_len
;
120 /* Build skb around receive buffer */
121 static struct sk_buff
*nicvf_rb_ptr_to_skb(struct nicvf
*nic
,
127 data
= phys_to_virt(rb_ptr
);
129 /* Now build an skb to give to stack */
130 skb
= build_skb(data
, RCV_FRAG_LEN
);
132 put_page(virt_to_page(data
));
140 /* Allocate RBDR ring and populate receive buffers */
141 static int nicvf_init_rbdr(struct nicvf
*nic
, struct rbdr
*rbdr
,
142 int ring_len
, int buf_size
)
146 struct rbdr_entry_t
*desc
;
149 err
= nicvf_alloc_q_desc_mem(nic
, &rbdr
->dmem
, ring_len
,
150 sizeof(struct rbdr_entry_t
),
151 NICVF_RCV_BUF_ALIGN_BYTES
);
155 rbdr
->desc
= rbdr
->dmem
.base
;
156 /* Buffer size has to be in multiples of 128 bytes */
157 rbdr
->dma_size
= buf_size
;
159 rbdr
->thresh
= RBDR_THRESH
;
162 for (idx
= 0; idx
< ring_len
; idx
++) {
163 err
= nicvf_alloc_rcv_buffer(nic
, GFP_KERNEL
, RCV_FRAG_LEN
,
168 desc
= GET_RBDR_DESC(rbdr
, idx
);
169 desc
->buf_addr
= virt_to_phys(rbuf
) >> NICVF_RCV_BUF_ALIGN
;
177 /* Free RBDR ring and its receive buffers */
178 static void nicvf_free_rbdr(struct nicvf
*nic
, struct rbdr
*rbdr
)
182 struct rbdr_entry_t
*desc
;
187 rbdr
->enable
= false;
188 if (!rbdr
->dmem
.base
)
195 while (head
!= tail
) {
196 desc
= GET_RBDR_DESC(rbdr
, head
);
197 buf_addr
= desc
->buf_addr
<< NICVF_RCV_BUF_ALIGN
;
198 put_page(virt_to_page(phys_to_virt(buf_addr
)));
200 head
&= (rbdr
->dmem
.q_len
- 1);
202 /* Free SKB of tail desc */
203 desc
= GET_RBDR_DESC(rbdr
, tail
);
204 buf_addr
= desc
->buf_addr
<< NICVF_RCV_BUF_ALIGN
;
205 put_page(virt_to_page(phys_to_virt(buf_addr
)));
208 nicvf_free_q_desc_mem(nic
, &rbdr
->dmem
);
211 /* Refill receive buffer descriptors with new buffers.
213 static void nicvf_refill_rbdr(struct nicvf
*nic
, gfp_t gfp
)
215 struct queue_set
*qs
= nic
->qs
;
216 int rbdr_idx
= qs
->rbdr_cnt
;
220 struct rbdr_entry_t
*desc
;
228 rbdr
= &qs
->rbdr
[rbdr_idx
];
229 /* Check if it's enabled */
233 /* Get no of desc's to be refilled */
234 qcount
= nicvf_queue_reg_read(nic
, NIC_QSET_RBDR_0_1_STATUS0
, rbdr_idx
);
236 /* Doorbell can be ringed with a max of ring size minus 1 */
237 if (qcount
>= (qs
->rbdr_len
- 1))
240 refill_rb_cnt
= qs
->rbdr_len
- qcount
- 1;
242 /* Start filling descs from tail */
243 tail
= nicvf_queue_reg_read(nic
, NIC_QSET_RBDR_0_1_TAIL
, rbdr_idx
) >> 3;
244 while (refill_rb_cnt
) {
246 tail
&= (rbdr
->dmem
.q_len
- 1);
248 if (nicvf_alloc_rcv_buffer(nic
, gfp
, RCV_FRAG_LEN
, &rbuf
))
251 desc
= GET_RBDR_DESC(rbdr
, tail
);
252 desc
->buf_addr
= virt_to_phys(rbuf
) >> NICVF_RCV_BUF_ALIGN
;
259 /* make sure all memory stores are done before ringing doorbell */
262 /* Check if buffer allocation failed */
264 nic
->rb_alloc_fail
= true;
266 nic
->rb_alloc_fail
= false;
269 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_DOOR
,
272 /* Re-enable RBDR interrupts only if buffer allocation is success */
273 if (!nic
->rb_alloc_fail
&& rbdr
->enable
)
274 nicvf_enable_intr(nic
, NICVF_INTR_RBDR
, rbdr_idx
);
280 /* Alloc rcv buffers in non-atomic mode for better success */
281 void nicvf_rbdr_work(struct work_struct
*work
)
283 struct nicvf
*nic
= container_of(work
, struct nicvf
, rbdr_work
.work
);
285 nicvf_refill_rbdr(nic
, GFP_KERNEL
);
286 if (nic
->rb_alloc_fail
)
287 schedule_delayed_work(&nic
->rbdr_work
, msecs_to_jiffies(10));
289 nic
->rb_work_scheduled
= false;
292 /* In Softirq context, alloc rcv buffers in atomic mode */
293 void nicvf_rbdr_task(unsigned long data
)
295 struct nicvf
*nic
= (struct nicvf
*)data
;
297 nicvf_refill_rbdr(nic
, GFP_ATOMIC
);
298 if (nic
->rb_alloc_fail
) {
299 nic
->rb_work_scheduled
= true;
300 schedule_delayed_work(&nic
->rbdr_work
, msecs_to_jiffies(10));
304 /* Initialize completion queue */
305 static int nicvf_init_cmp_queue(struct nicvf
*nic
,
306 struct cmp_queue
*cq
, int q_len
)
310 err
= nicvf_alloc_q_desc_mem(nic
, &cq
->dmem
, q_len
, CMP_QUEUE_DESC_SIZE
,
311 NICVF_CQ_BASE_ALIGN_BYTES
);
315 cq
->desc
= cq
->dmem
.base
;
316 cq
->thresh
= pass1_silicon(nic
->pdev
) ? 0 : CMP_QUEUE_CQE_THRESH
;
317 nic
->cq_coalesce_usecs
= (CMP_QUEUE_TIMER_THRESH
* 0.05) - 1;
322 static void nicvf_free_cmp_queue(struct nicvf
*nic
, struct cmp_queue
*cq
)
329 nicvf_free_q_desc_mem(nic
, &cq
->dmem
);
332 /* Initialize transmit queue */
333 static int nicvf_init_snd_queue(struct nicvf
*nic
,
334 struct snd_queue
*sq
, int q_len
)
338 err
= nicvf_alloc_q_desc_mem(nic
, &sq
->dmem
, q_len
, SND_QUEUE_DESC_SIZE
,
339 NICVF_SQ_BASE_ALIGN_BYTES
);
343 sq
->desc
= sq
->dmem
.base
;
344 sq
->skbuff
= kcalloc(q_len
, sizeof(u64
), GFP_KERNEL
);
349 atomic_set(&sq
->free_cnt
, q_len
- 1);
350 sq
->thresh
= SND_QUEUE_THRESH
;
352 /* Preallocate memory for TSO segment's header */
353 sq
->tso_hdrs
= dma_alloc_coherent(&nic
->pdev
->dev
,
354 q_len
* TSO_HEADER_SIZE
,
355 &sq
->tso_hdrs_phys
, GFP_KERNEL
);
362 static void nicvf_free_snd_queue(struct nicvf
*nic
, struct snd_queue
*sq
)
370 dma_free_coherent(&nic
->pdev
->dev
,
371 sq
->dmem
.q_len
* TSO_HEADER_SIZE
,
372 sq
->tso_hdrs
, sq
->tso_hdrs_phys
);
375 nicvf_free_q_desc_mem(nic
, &sq
->dmem
);
378 static void nicvf_reclaim_snd_queue(struct nicvf
*nic
,
379 struct queue_set
*qs
, int qidx
)
381 /* Disable send queue */
382 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
, 0);
383 /* Check if SQ is stopped */
384 if (nicvf_poll_reg(nic
, qidx
, NIC_QSET_SQ_0_7_STATUS
, 21, 1, 0x01))
386 /* Reset send queue */
387 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
, NICVF_SQ_RESET
);
390 static void nicvf_reclaim_rcv_queue(struct nicvf
*nic
,
391 struct queue_set
*qs
, int qidx
)
393 union nic_mbx mbx
= {};
395 /* Make sure all packets in the pipeline are written back into mem */
396 mbx
.msg
.msg
= NIC_MBOX_MSG_RQ_SW_SYNC
;
397 nicvf_send_msg_to_pf(nic
, &mbx
);
400 static void nicvf_reclaim_cmp_queue(struct nicvf
*nic
,
401 struct queue_set
*qs
, int qidx
)
403 /* Disable timer threshold (doesn't get reset upon CQ reset */
404 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_CFG2
, qidx
, 0);
405 /* Disable completion queue */
406 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_CFG
, qidx
, 0);
407 /* Reset completion queue */
408 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_CFG
, qidx
, NICVF_CQ_RESET
);
411 static void nicvf_reclaim_rbdr(struct nicvf
*nic
,
412 struct rbdr
*rbdr
, int qidx
)
417 /* Save head and tail pointers for feeing up buffers */
418 rbdr
->head
= nicvf_queue_reg_read(nic
,
419 NIC_QSET_RBDR_0_1_HEAD
,
421 rbdr
->tail
= nicvf_queue_reg_read(nic
,
422 NIC_QSET_RBDR_0_1_TAIL
,
425 /* If RBDR FIFO is in 'FAIL' state then do a reset first
428 fifo_state
= nicvf_queue_reg_read(nic
, NIC_QSET_RBDR_0_1_STATUS0
, qidx
);
429 if (((fifo_state
>> 62) & 0x03) == 0x3)
430 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_CFG
,
431 qidx
, NICVF_RBDR_RESET
);
434 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_CFG
, qidx
, 0);
435 if (nicvf_poll_reg(nic
, qidx
, NIC_QSET_RBDR_0_1_STATUS0
, 62, 2, 0x00))
438 tmp
= nicvf_queue_reg_read(nic
,
439 NIC_QSET_RBDR_0_1_PREFETCH_STATUS
,
441 if ((tmp
& 0xFFFFFFFF) == ((tmp
>> 32) & 0xFFFFFFFF))
443 usleep_range(1000, 2000);
446 netdev_err(nic
->netdev
,
447 "Failed polling on prefetch status\n");
451 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_CFG
,
452 qidx
, NICVF_RBDR_RESET
);
454 if (nicvf_poll_reg(nic
, qidx
, NIC_QSET_RBDR_0_1_STATUS0
, 62, 2, 0x02))
456 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_CFG
, qidx
, 0x00);
457 if (nicvf_poll_reg(nic
, qidx
, NIC_QSET_RBDR_0_1_STATUS0
, 62, 2, 0x00))
461 void nicvf_config_vlan_stripping(struct nicvf
*nic
, netdev_features_t features
)
466 rq_cfg
= nicvf_queue_reg_read(nic
, NIC_QSET_RQ_GEN_CFG
, 0);
468 /* Enable first VLAN stripping */
469 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
470 rq_cfg
|= (1ULL << 25);
472 rq_cfg
&= ~(1ULL << 25);
473 nicvf_queue_reg_write(nic
, NIC_QSET_RQ_GEN_CFG
, 0, rq_cfg
);
475 /* Configure Secondary Qsets, if any */
476 for (sqs
= 0; sqs
< nic
->sqs_count
; sqs
++)
477 if (nic
->snicvf
[sqs
])
478 nicvf_queue_reg_write(nic
->snicvf
[sqs
],
479 NIC_QSET_RQ_GEN_CFG
, 0, rq_cfg
);
482 static void nicvf_reset_rcv_queue_stats(struct nicvf
*nic
)
484 union nic_mbx mbx
= {};
486 /* Reset all RXQ's stats */
487 mbx
.reset_stat
.msg
= NIC_MBOX_MSG_RESET_STAT_COUNTER
;
488 mbx
.reset_stat
.rq_stat_mask
= 0xFFFF;
489 nicvf_send_msg_to_pf(nic
, &mbx
);
492 /* Configures receive queue */
493 static void nicvf_rcv_queue_config(struct nicvf
*nic
, struct queue_set
*qs
,
494 int qidx
, bool enable
)
496 union nic_mbx mbx
= {};
497 struct rcv_queue
*rq
;
498 struct rq_cfg rq_cfg
;
503 /* Disable receive queue */
504 nicvf_queue_reg_write(nic
, NIC_QSET_RQ_0_7_CFG
, qidx
, 0);
507 nicvf_reclaim_rcv_queue(nic
, qs
, qidx
);
511 rq
->cq_qs
= qs
->vnic_id
;
513 rq
->start_rbdr_qs
= qs
->vnic_id
;
514 rq
->start_qs_rbdr_idx
= qs
->rbdr_cnt
- 1;
515 rq
->cont_rbdr_qs
= qs
->vnic_id
;
516 rq
->cont_qs_rbdr_idx
= qs
->rbdr_cnt
- 1;
517 /* all writes of RBDR data to be loaded into L2 Cache as well*/
520 /* Send a mailbox msg to PF to config RQ */
521 mbx
.rq
.msg
= NIC_MBOX_MSG_RQ_CFG
;
522 mbx
.rq
.qs_num
= qs
->vnic_id
;
523 mbx
.rq
.rq_num
= qidx
;
524 mbx
.rq
.cfg
= (rq
->caching
<< 26) | (rq
->cq_qs
<< 19) |
525 (rq
->cq_idx
<< 16) | (rq
->cont_rbdr_qs
<< 9) |
526 (rq
->cont_qs_rbdr_idx
<< 8) |
527 (rq
->start_rbdr_qs
<< 1) | (rq
->start_qs_rbdr_idx
);
528 nicvf_send_msg_to_pf(nic
, &mbx
);
530 mbx
.rq
.msg
= NIC_MBOX_MSG_RQ_BP_CFG
;
531 mbx
.rq
.cfg
= (1ULL << 63) | (1ULL << 62) | (qs
->vnic_id
<< 0);
532 nicvf_send_msg_to_pf(nic
, &mbx
);
535 * Enable CQ drop to reserve sufficient CQEs for all tx packets
537 mbx
.rq
.msg
= NIC_MBOX_MSG_RQ_DROP_CFG
;
538 mbx
.rq
.cfg
= (1ULL << 62) | (RQ_CQ_DROP
<< 8);
539 nicvf_send_msg_to_pf(nic
, &mbx
);
541 nicvf_queue_reg_write(nic
, NIC_QSET_RQ_GEN_CFG
, 0, 0x00);
543 nicvf_config_vlan_stripping(nic
, nic
->netdev
->features
);
545 /* Enable Receive queue */
546 memset(&rq_cfg
, 0, sizeof(struct rq_cfg
));
549 nicvf_queue_reg_write(nic
, NIC_QSET_RQ_0_7_CFG
, qidx
, *(u64
*)&rq_cfg
);
552 /* Configures completion queue */
553 void nicvf_cmp_queue_config(struct nicvf
*nic
, struct queue_set
*qs
,
554 int qidx
, bool enable
)
556 struct cmp_queue
*cq
;
557 struct cq_cfg cq_cfg
;
563 nicvf_reclaim_cmp_queue(nic
, qs
, qidx
);
567 /* Reset completion queue */
568 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_CFG
, qidx
, NICVF_CQ_RESET
);
573 spin_lock_init(&cq
->lock
);
574 /* Set completion queue base address */
575 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_BASE
,
576 qidx
, (u64
)(cq
->dmem
.phys_base
));
578 /* Enable Completion queue */
579 memset(&cq_cfg
, 0, sizeof(struct cq_cfg
));
583 cq_cfg
.qsize
= CMP_QSIZE
;
585 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_CFG
, qidx
, *(u64
*)&cq_cfg
);
587 /* Set threshold value for interrupt generation */
588 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_THRESH
, qidx
, cq
->thresh
);
589 nicvf_queue_reg_write(nic
, NIC_QSET_CQ_0_7_CFG2
,
590 qidx
, CMP_QUEUE_TIMER_THRESH
);
593 /* Configures transmit queue */
594 static void nicvf_snd_queue_config(struct nicvf
*nic
, struct queue_set
*qs
,
595 int qidx
, bool enable
)
597 union nic_mbx mbx
= {};
598 struct snd_queue
*sq
;
599 struct sq_cfg sq_cfg
;
605 nicvf_reclaim_snd_queue(nic
, qs
, qidx
);
609 /* Reset send queue */
610 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
, NICVF_SQ_RESET
);
612 sq
->cq_qs
= qs
->vnic_id
;
615 /* Send a mailbox msg to PF to config SQ */
616 mbx
.sq
.msg
= NIC_MBOX_MSG_SQ_CFG
;
617 mbx
.sq
.qs_num
= qs
->vnic_id
;
618 mbx
.sq
.sq_num
= qidx
;
619 mbx
.sq
.sqs_mode
= nic
->sqs_mode
;
620 mbx
.sq
.cfg
= (sq
->cq_qs
<< 3) | sq
->cq_idx
;
621 nicvf_send_msg_to_pf(nic
, &mbx
);
623 /* Set queue base address */
624 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_BASE
,
625 qidx
, (u64
)(sq
->dmem
.phys_base
));
627 /* Enable send queue & set queue size */
628 memset(&sq_cfg
, 0, sizeof(struct sq_cfg
));
632 sq_cfg
.qsize
= SND_QSIZE
;
633 sq_cfg
.tstmp_bgx_intf
= 0;
634 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
, *(u64
*)&sq_cfg
);
636 /* Set threshold value for interrupt generation */
637 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_THRESH
, qidx
, sq
->thresh
);
639 /* Set queue:cpu affinity for better load distribution */
640 if (cpu_online(qidx
)) {
641 cpumask_set_cpu(qidx
, &sq
->affinity_mask
);
642 netif_set_xps_queue(nic
->netdev
,
643 &sq
->affinity_mask
, qidx
);
647 /* Configures receive buffer descriptor ring */
648 static void nicvf_rbdr_config(struct nicvf
*nic
, struct queue_set
*qs
,
649 int qidx
, bool enable
)
652 struct rbdr_cfg rbdr_cfg
;
654 rbdr
= &qs
->rbdr
[qidx
];
655 nicvf_reclaim_rbdr(nic
, rbdr
, qidx
);
659 /* Set descriptor base address */
660 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_BASE
,
661 qidx
, (u64
)(rbdr
->dmem
.phys_base
));
663 /* Enable RBDR & set queue size */
664 /* Buffer size should be in multiples of 128 bytes */
665 memset(&rbdr_cfg
, 0, sizeof(struct rbdr_cfg
));
669 rbdr_cfg
.qsize
= RBDR_SIZE
;
670 rbdr_cfg
.avg_con
= 0;
671 rbdr_cfg
.lines
= rbdr
->dma_size
/ 128;
672 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_CFG
,
673 qidx
, *(u64
*)&rbdr_cfg
);
676 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_DOOR
,
677 qidx
, qs
->rbdr_len
- 1);
679 /* Set threshold value for interrupt generation */
680 nicvf_queue_reg_write(nic
, NIC_QSET_RBDR_0_1_THRESH
,
681 qidx
, rbdr
->thresh
- 1);
684 /* Requests PF to assign and enable Qset */
685 void nicvf_qset_config(struct nicvf
*nic
, bool enable
)
687 union nic_mbx mbx
= {};
688 struct queue_set
*qs
= nic
->qs
;
689 struct qs_cfg
*qs_cfg
;
692 netdev_warn(nic
->netdev
,
693 "Qset is still not allocated, don't init queues\n");
698 qs
->vnic_id
= nic
->vf_id
;
700 /* Send a mailbox msg to PF to config Qset */
701 mbx
.qs
.msg
= NIC_MBOX_MSG_QS_CFG
;
702 mbx
.qs
.num
= qs
->vnic_id
;
703 mbx
.qs
.sqs_count
= nic
->sqs_count
;
706 qs_cfg
= (struct qs_cfg
*)&mbx
.qs
.cfg
;
712 qs_cfg
->vnic
= qs
->vnic_id
;
714 nicvf_send_msg_to_pf(nic
, &mbx
);
717 static void nicvf_free_resources(struct nicvf
*nic
)
720 struct queue_set
*qs
= nic
->qs
;
722 /* Free receive buffer descriptor ring */
723 for (qidx
= 0; qidx
< qs
->rbdr_cnt
; qidx
++)
724 nicvf_free_rbdr(nic
, &qs
->rbdr
[qidx
]);
726 /* Free completion queue */
727 for (qidx
= 0; qidx
< qs
->cq_cnt
; qidx
++)
728 nicvf_free_cmp_queue(nic
, &qs
->cq
[qidx
]);
730 /* Free send queue */
731 for (qidx
= 0; qidx
< qs
->sq_cnt
; qidx
++)
732 nicvf_free_snd_queue(nic
, &qs
->sq
[qidx
]);
735 static int nicvf_alloc_resources(struct nicvf
*nic
)
738 struct queue_set
*qs
= nic
->qs
;
740 /* Alloc receive buffer descriptor ring */
741 for (qidx
= 0; qidx
< qs
->rbdr_cnt
; qidx
++) {
742 if (nicvf_init_rbdr(nic
, &qs
->rbdr
[qidx
], qs
->rbdr_len
,
747 /* Alloc send queue */
748 for (qidx
= 0; qidx
< qs
->sq_cnt
; qidx
++) {
749 if (nicvf_init_snd_queue(nic
, &qs
->sq
[qidx
], qs
->sq_len
))
753 /* Alloc completion queue */
754 for (qidx
= 0; qidx
< qs
->cq_cnt
; qidx
++) {
755 if (nicvf_init_cmp_queue(nic
, &qs
->cq
[qidx
], qs
->cq_len
))
761 nicvf_free_resources(nic
);
765 int nicvf_set_qset_resources(struct nicvf
*nic
)
767 struct queue_set
*qs
;
769 qs
= devm_kzalloc(&nic
->pdev
->dev
, sizeof(*qs
), GFP_KERNEL
);
774 /* Set count of each queue */
775 qs
->rbdr_cnt
= DEFAULT_RBDR_CNT
;
776 qs
->rq_cnt
= min_t(u8
, MAX_RCV_QUEUES_PER_QS
, num_online_cpus());
777 qs
->sq_cnt
= min_t(u8
, MAX_SND_QUEUES_PER_QS
, num_online_cpus());
778 qs
->cq_cnt
= max_t(u8
, qs
->rq_cnt
, qs
->sq_cnt
);
780 /* Set queue lengths */
781 qs
->rbdr_len
= RCV_BUF_COUNT
;
782 qs
->sq_len
= SND_QUEUE_LEN
;
783 qs
->cq_len
= CMP_QUEUE_LEN
;
785 nic
->rx_queues
= qs
->rq_cnt
;
786 nic
->tx_queues
= qs
->sq_cnt
;
791 int nicvf_config_data_transfer(struct nicvf
*nic
, bool enable
)
793 bool disable
= false;
794 struct queue_set
*qs
= nic
->qs
;
801 if (nicvf_alloc_resources(nic
))
804 for (qidx
= 0; qidx
< qs
->sq_cnt
; qidx
++)
805 nicvf_snd_queue_config(nic
, qs
, qidx
, enable
);
806 for (qidx
= 0; qidx
< qs
->cq_cnt
; qidx
++)
807 nicvf_cmp_queue_config(nic
, qs
, qidx
, enable
);
808 for (qidx
= 0; qidx
< qs
->rbdr_cnt
; qidx
++)
809 nicvf_rbdr_config(nic
, qs
, qidx
, enable
);
810 for (qidx
= 0; qidx
< qs
->rq_cnt
; qidx
++)
811 nicvf_rcv_queue_config(nic
, qs
, qidx
, enable
);
813 for (qidx
= 0; qidx
< qs
->rq_cnt
; qidx
++)
814 nicvf_rcv_queue_config(nic
, qs
, qidx
, disable
);
815 for (qidx
= 0; qidx
< qs
->rbdr_cnt
; qidx
++)
816 nicvf_rbdr_config(nic
, qs
, qidx
, disable
);
817 for (qidx
= 0; qidx
< qs
->sq_cnt
; qidx
++)
818 nicvf_snd_queue_config(nic
, qs
, qidx
, disable
);
819 for (qidx
= 0; qidx
< qs
->cq_cnt
; qidx
++)
820 nicvf_cmp_queue_config(nic
, qs
, qidx
, disable
);
822 nicvf_free_resources(nic
);
825 /* Reset RXQ's stats.
826 * SQ's stats will get reset automatically once SQ is reset.
828 nicvf_reset_rcv_queue_stats(nic
);
833 /* Get a free desc from SQ
834 * returns descriptor ponter & descriptor number
836 static inline int nicvf_get_sq_desc(struct snd_queue
*sq
, int desc_cnt
)
841 atomic_sub(desc_cnt
, &sq
->free_cnt
);
842 sq
->tail
+= desc_cnt
;
843 sq
->tail
&= (sq
->dmem
.q_len
- 1);
848 /* Free descriptor back to SQ for future use */
849 void nicvf_put_sq_desc(struct snd_queue
*sq
, int desc_cnt
)
851 atomic_add(desc_cnt
, &sq
->free_cnt
);
852 sq
->head
+= desc_cnt
;
853 sq
->head
&= (sq
->dmem
.q_len
- 1);
856 static inline int nicvf_get_nxt_sqentry(struct snd_queue
*sq
, int qentry
)
859 qentry
&= (sq
->dmem
.q_len
- 1);
863 void nicvf_sq_enable(struct nicvf
*nic
, struct snd_queue
*sq
, int qidx
)
867 sq_cfg
= nicvf_queue_reg_read(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
);
868 sq_cfg
|= NICVF_SQ_EN
;
869 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
, sq_cfg
);
870 /* Ring doorbell so that H/W restarts processing SQEs */
871 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_DOOR
, qidx
, 0);
874 void nicvf_sq_disable(struct nicvf
*nic
, int qidx
)
878 sq_cfg
= nicvf_queue_reg_read(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
);
879 sq_cfg
&= ~NICVF_SQ_EN
;
880 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_CFG
, qidx
, sq_cfg
);
883 void nicvf_sq_free_used_descs(struct net_device
*netdev
, struct snd_queue
*sq
,
888 struct nicvf
*nic
= netdev_priv(netdev
);
889 struct sq_hdr_subdesc
*hdr
;
891 head
= nicvf_queue_reg_read(nic
, NIC_QSET_SQ_0_7_HEAD
, qidx
) >> 4;
892 tail
= nicvf_queue_reg_read(nic
, NIC_QSET_SQ_0_7_TAIL
, qidx
) >> 4;
893 while (sq
->head
!= head
) {
894 hdr
= (struct sq_hdr_subdesc
*)GET_SQ_DESC(sq
, sq
->head
);
895 if (hdr
->subdesc_type
!= SQ_DESC_TYPE_HEADER
) {
896 nicvf_put_sq_desc(sq
, 1);
899 skb
= (struct sk_buff
*)sq
->skbuff
[sq
->head
];
901 dev_kfree_skb_any(skb
);
902 atomic64_add(1, (atomic64_t
*)&netdev
->stats
.tx_packets
);
903 atomic64_add(hdr
->tot_len
,
904 (atomic64_t
*)&netdev
->stats
.tx_bytes
);
905 nicvf_put_sq_desc(sq
, hdr
->subdesc_cnt
+ 1);
909 /* Calculate no of SQ subdescriptors needed to transmit all
910 * segments of this TSO packet.
911 * Taken from 'Tilera network driver' with a minor modification.
913 static int nicvf_tso_count_subdescs(struct sk_buff
*skb
)
915 struct skb_shared_info
*sh
= skb_shinfo(skb
);
916 unsigned int sh_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
917 unsigned int data_len
= skb
->len
- sh_len
;
918 unsigned int p_len
= sh
->gso_size
;
919 long f_id
= -1; /* id of the current fragment */
920 long f_size
= skb_headlen(skb
) - sh_len
; /* current fragment size */
921 long f_used
= 0; /* bytes used from the current fragment */
922 long n
; /* size of the current piece of payload */
926 for (segment
= 0; segment
< sh
->gso_segs
; segment
++) {
927 unsigned int p_used
= 0;
929 /* One edesc for header and for each piece of the payload. */
930 for (num_edescs
++; p_used
< p_len
; num_edescs
++) {
931 /* Advance as needed. */
932 while (f_used
>= f_size
) {
934 f_size
= skb_frag_size(&sh
->frags
[f_id
]);
938 /* Use bytes from the current fragment. */
940 if (n
> f_size
- f_used
)
946 /* The last segment may be less than gso_size. */
948 if (data_len
< p_len
)
952 /* '+ gso_segs' for SQ_HDR_SUDESCs for each segment */
953 return num_edescs
+ sh
->gso_segs
;
956 #define POST_CQE_DESC_COUNT 2
958 /* Get the number of SQ descriptors needed to xmit this skb */
959 static int nicvf_sq_subdesc_required(struct nicvf
*nic
, struct sk_buff
*skb
)
961 int subdesc_cnt
= MIN_SQ_DESC_PER_PKT_XMIT
;
963 if (skb_shinfo(skb
)->gso_size
&& !nic
->hw_tso
) {
964 subdesc_cnt
= nicvf_tso_count_subdescs(skb
);
968 /* Dummy descriptors to get TSO pkt completion notification */
969 if (nic
->t88
&& nic
->hw_tso
&& skb_shinfo(skb
)->gso_size
)
970 subdesc_cnt
+= POST_CQE_DESC_COUNT
;
972 if (skb_shinfo(skb
)->nr_frags
)
973 subdesc_cnt
+= skb_shinfo(skb
)->nr_frags
;
978 /* Add SQ HEADER subdescriptor.
979 * First subdescriptor for every send descriptor.
982 nicvf_sq_add_hdr_subdesc(struct nicvf
*nic
, struct snd_queue
*sq
, int qentry
,
983 int subdesc_cnt
, struct sk_buff
*skb
, int len
)
986 struct sq_hdr_subdesc
*hdr
;
988 hdr
= (struct sq_hdr_subdesc
*)GET_SQ_DESC(sq
, qentry
);
989 memset(hdr
, 0, SND_QUEUE_DESC_SIZE
);
990 hdr
->subdesc_type
= SQ_DESC_TYPE_HEADER
;
992 if (nic
->t88
&& nic
->hw_tso
&& skb_shinfo(skb
)->gso_size
) {
993 /* post_cqe = 0, to avoid HW posting a CQE for every TSO
994 * segment transmitted on 88xx.
996 hdr
->subdesc_cnt
= subdesc_cnt
- POST_CQE_DESC_COUNT
;
998 sq
->skbuff
[qentry
] = (u64
)skb
;
999 /* Enable notification via CQE after processing SQE */
1001 /* No of subdescriptors following this */
1002 hdr
->subdesc_cnt
= subdesc_cnt
;
1006 /* Offload checksum calculation to HW */
1007 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1008 hdr
->csum_l3
= 1; /* Enable IP csum calculation */
1009 hdr
->l3_offset
= skb_network_offset(skb
);
1010 hdr
->l4_offset
= skb_transport_offset(skb
);
1012 proto
= ip_hdr(skb
)->protocol
;
1015 hdr
->csum_l4
= SEND_L4_CSUM_TCP
;
1018 hdr
->csum_l4
= SEND_L4_CSUM_UDP
;
1021 hdr
->csum_l4
= SEND_L4_CSUM_SCTP
;
1026 if (nic
->hw_tso
&& skb_shinfo(skb
)->gso_size
) {
1028 hdr
->tso_start
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
1029 hdr
->tso_max_paysize
= skb_shinfo(skb
)->gso_size
;
1030 /* For non-tunneled pkts, point this to L2 ethertype */
1031 hdr
->inner_l3_offset
= skb_network_offset(skb
) - 2;
1032 nic
->drv_stats
.tx_tso
++;
1036 /* SQ GATHER subdescriptor
1037 * Must follow HDR descriptor
1039 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue
*sq
, int qentry
,
1042 struct sq_gather_subdesc
*gather
;
1044 qentry
&= (sq
->dmem
.q_len
- 1);
1045 gather
= (struct sq_gather_subdesc
*)GET_SQ_DESC(sq
, qentry
);
1047 memset(gather
, 0, SND_QUEUE_DESC_SIZE
);
1048 gather
->subdesc_type
= SQ_DESC_TYPE_GATHER
;
1049 gather
->ld_type
= NIC_SEND_LD_TYPE_E_LDD
;
1050 gather
->size
= size
;
1051 gather
->addr
= data
;
1054 /* Add HDR + IMMEDIATE subdescriptors right after descriptors of a TSO
1055 * packet so that a CQE is posted as a notifation for transmission of
1058 static inline void nicvf_sq_add_cqe_subdesc(struct snd_queue
*sq
, int qentry
,
1059 int tso_sqe
, struct sk_buff
*skb
)
1061 struct sq_imm_subdesc
*imm
;
1062 struct sq_hdr_subdesc
*hdr
;
1064 sq
->skbuff
[qentry
] = (u64
)skb
;
1066 hdr
= (struct sq_hdr_subdesc
*)GET_SQ_DESC(sq
, qentry
);
1067 memset(hdr
, 0, SND_QUEUE_DESC_SIZE
);
1068 hdr
->subdesc_type
= SQ_DESC_TYPE_HEADER
;
1069 /* Enable notification via CQE after processing SQE */
1071 /* There is no packet to transmit here */
1073 hdr
->subdesc_cnt
= POST_CQE_DESC_COUNT
- 1;
1075 /* Actual TSO header SQE index, needed for cleanup */
1076 hdr
->rsvd2
= tso_sqe
;
1078 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1079 imm
= (struct sq_imm_subdesc
*)GET_SQ_DESC(sq
, qentry
);
1080 memset(imm
, 0, SND_QUEUE_DESC_SIZE
);
1081 imm
->subdesc_type
= SQ_DESC_TYPE_IMMEDIATE
;
1085 /* Segment a TSO packet into 'gso_size' segments and append
1086 * them to SQ for transfer
1088 static int nicvf_sq_append_tso(struct nicvf
*nic
, struct snd_queue
*sq
,
1089 int sq_num
, int qentry
, struct sk_buff
*skb
)
1092 int seg_subdescs
= 0, desc_cnt
= 0;
1093 int seg_len
, total_len
, data_left
;
1094 int hdr_qentry
= qentry
;
1095 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
1097 tso_start(skb
, &tso
);
1098 total_len
= skb
->len
- hdr_len
;
1099 while (total_len
> 0) {
1102 /* Save Qentry for adding HDR_SUBDESC at the end */
1103 hdr_qentry
= qentry
;
1105 data_left
= min_t(int, skb_shinfo(skb
)->gso_size
, total_len
);
1106 total_len
-= data_left
;
1108 /* Add segment's header */
1109 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1110 hdr
= sq
->tso_hdrs
+ qentry
* TSO_HEADER_SIZE
;
1111 tso_build_hdr(skb
, hdr
, &tso
, data_left
, total_len
== 0);
1112 nicvf_sq_add_gather_subdesc(sq
, qentry
, hdr_len
,
1114 qentry
* TSO_HEADER_SIZE
);
1115 /* HDR_SUDESC + GATHER */
1119 /* Add segment's payload fragments */
1120 while (data_left
> 0) {
1123 size
= min_t(int, tso
.size
, data_left
);
1125 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1126 nicvf_sq_add_gather_subdesc(sq
, qentry
, size
,
1127 virt_to_phys(tso
.data
));
1132 tso_build_data(skb
, &tso
, size
);
1134 nicvf_sq_add_hdr_subdesc(nic
, sq
, hdr_qentry
,
1135 seg_subdescs
- 1, skb
, seg_len
);
1136 sq
->skbuff
[hdr_qentry
] = (u64
)NULL
;
1137 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1139 desc_cnt
+= seg_subdescs
;
1141 /* Save SKB in the last segment for freeing */
1142 sq
->skbuff
[hdr_qentry
] = (u64
)skb
;
1144 /* make sure all memory stores are done before ringing doorbell */
1147 /* Inform HW to xmit all TSO segments */
1148 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_DOOR
,
1150 nic
->drv_stats
.tx_tso
++;
1154 /* Append an skb to a SQ for packet transfer. */
1155 int nicvf_sq_append_skb(struct nicvf
*nic
, struct sk_buff
*skb
)
1158 int subdesc_cnt
, tso_sqe
= 0;
1160 struct queue_set
*qs
;
1161 struct snd_queue
*sq
;
1163 sq_num
= skb_get_queue_mapping(skb
);
1164 if (sq_num
>= MAX_SND_QUEUES_PER_QS
) {
1165 /* Get secondary Qset's SQ structure */
1166 i
= sq_num
/ MAX_SND_QUEUES_PER_QS
;
1167 if (!nic
->snicvf
[i
- 1]) {
1168 netdev_warn(nic
->netdev
,
1169 "Secondary Qset#%d's ptr not initialized\n",
1173 nic
= (struct nicvf
*)nic
->snicvf
[i
- 1];
1174 sq_num
= sq_num
% MAX_SND_QUEUES_PER_QS
;
1178 sq
= &qs
->sq
[sq_num
];
1180 subdesc_cnt
= nicvf_sq_subdesc_required(nic
, skb
);
1181 if (subdesc_cnt
> atomic_read(&sq
->free_cnt
))
1184 qentry
= nicvf_get_sq_desc(sq
, subdesc_cnt
);
1186 /* Check if its a TSO packet */
1187 if (skb_shinfo(skb
)->gso_size
&& !nic
->hw_tso
)
1188 return nicvf_sq_append_tso(nic
, sq
, sq_num
, qentry
, skb
);
1190 /* Add SQ header subdesc */
1191 nicvf_sq_add_hdr_subdesc(nic
, sq
, qentry
, subdesc_cnt
- 1,
1195 /* Add SQ gather subdescs */
1196 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1197 size
= skb_is_nonlinear(skb
) ? skb_headlen(skb
) : skb
->len
;
1198 nicvf_sq_add_gather_subdesc(sq
, qentry
, size
, virt_to_phys(skb
->data
));
1200 /* Check for scattered buffer */
1201 if (!skb_is_nonlinear(skb
))
1204 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1205 const struct skb_frag_struct
*frag
;
1207 frag
= &skb_shinfo(skb
)->frags
[i
];
1209 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1210 size
= skb_frag_size(frag
);
1211 nicvf_sq_add_gather_subdesc(sq
, qentry
, size
,
1213 skb_frag_address(frag
)));
1217 if (nic
->t88
&& skb_shinfo(skb
)->gso_size
) {
1218 qentry
= nicvf_get_nxt_sqentry(sq
, qentry
);
1219 nicvf_sq_add_cqe_subdesc(sq
, qentry
, tso_sqe
, skb
);
1222 /* make sure all memory stores are done before ringing doorbell */
1225 /* Inform HW to xmit new packet */
1226 nicvf_queue_reg_write(nic
, NIC_QSET_SQ_0_7_DOOR
,
1227 sq_num
, subdesc_cnt
);
1231 /* Use original PCI dev for debug log */
1233 netdev_dbg(nic
->netdev
, "Not enough SQ descriptors to xmit pkt\n");
1237 static inline unsigned frag_num(unsigned i
)
1240 return (i
& ~3) + 3 - (i
& 3);
1246 /* Returns SKB for a received packet */
1247 struct sk_buff
*nicvf_get_rcv_skb(struct nicvf
*nic
, struct cqe_rx_t
*cqe_rx
)
1250 int payload_len
= 0;
1251 struct sk_buff
*skb
= NULL
;
1254 u16
*rb_lens
= NULL
;
1255 u64
*rb_ptrs
= NULL
;
1257 rb_lens
= (void *)cqe_rx
+ (3 * sizeof(u64
));
1258 /* Except 88xx pass1 on all other chips CQE_RX2_S is added to
1259 * CQE_RX at word6, hence buffer pointers move by word
1261 * Use existing 'hw_tso' flag which will be set for all chips
1262 * except 88xx pass1 instead of a additional cache line
1263 * access (or miss) by using pci dev's revision.
1266 rb_ptrs
= (void *)cqe_rx
+ (6 * sizeof(u64
));
1268 rb_ptrs
= (void *)cqe_rx
+ (7 * sizeof(u64
));
1270 netdev_dbg(nic
->netdev
, "%s rb_cnt %d rb0_ptr %llx rb0_sz %d\n",
1271 __func__
, cqe_rx
->rb_cnt
, cqe_rx
->rb0_ptr
, cqe_rx
->rb0_sz
);
1273 for (frag
= 0; frag
< cqe_rx
->rb_cnt
; frag
++) {
1274 payload_len
= rb_lens
[frag_num(frag
)];
1276 /* First fragment */
1277 skb
= nicvf_rb_ptr_to_skb(nic
,
1278 *rb_ptrs
- cqe_rx
->align_pad
,
1282 skb_reserve(skb
, cqe_rx
->align_pad
);
1283 skb_put(skb
, payload_len
);
1286 page
= virt_to_page(phys_to_virt(*rb_ptrs
));
1287 offset
= phys_to_virt(*rb_ptrs
) - page_address(page
);
1288 skb_add_rx_frag(skb
, skb_shinfo(skb
)->nr_frags
, page
,
1289 offset
, payload_len
, RCV_FRAG_LEN
);
1291 /* Next buffer pointer */
1297 static u64
nicvf_int_type_to_mask(int int_type
, int q_idx
)
1303 reg_val
= ((1ULL << q_idx
) << NICVF_INTR_CQ_SHIFT
);
1306 reg_val
= ((1ULL << q_idx
) << NICVF_INTR_SQ_SHIFT
);
1308 case NICVF_INTR_RBDR
:
1309 reg_val
= ((1ULL << q_idx
) << NICVF_INTR_RBDR_SHIFT
);
1311 case NICVF_INTR_PKT_DROP
:
1312 reg_val
= (1ULL << NICVF_INTR_PKT_DROP_SHIFT
);
1314 case NICVF_INTR_TCP_TIMER
:
1315 reg_val
= (1ULL << NICVF_INTR_TCP_TIMER_SHIFT
);
1317 case NICVF_INTR_MBOX
:
1318 reg_val
= (1ULL << NICVF_INTR_MBOX_SHIFT
);
1320 case NICVF_INTR_QS_ERR
:
1321 reg_val
= (1ULL << NICVF_INTR_QS_ERR_SHIFT
);
1330 /* Enable interrupt */
1331 void nicvf_enable_intr(struct nicvf
*nic
, int int_type
, int q_idx
)
1333 u64 mask
= nicvf_int_type_to_mask(int_type
, q_idx
);
1336 netdev_dbg(nic
->netdev
,
1337 "Failed to enable interrupt: unknown type\n");
1340 nicvf_reg_write(nic
, NIC_VF_ENA_W1S
,
1341 nicvf_reg_read(nic
, NIC_VF_ENA_W1S
) | mask
);
1344 /* Disable interrupt */
1345 void nicvf_disable_intr(struct nicvf
*nic
, int int_type
, int q_idx
)
1347 u64 mask
= nicvf_int_type_to_mask(int_type
, q_idx
);
1350 netdev_dbg(nic
->netdev
,
1351 "Failed to disable interrupt: unknown type\n");
1355 nicvf_reg_write(nic
, NIC_VF_ENA_W1C
, mask
);
1358 /* Clear interrupt */
1359 void nicvf_clear_intr(struct nicvf
*nic
, int int_type
, int q_idx
)
1361 u64 mask
= nicvf_int_type_to_mask(int_type
, q_idx
);
1364 netdev_dbg(nic
->netdev
,
1365 "Failed to clear interrupt: unknown type\n");
1369 nicvf_reg_write(nic
, NIC_VF_INT
, mask
);
1372 /* Check if interrupt is enabled */
1373 int nicvf_is_intr_enabled(struct nicvf
*nic
, int int_type
, int q_idx
)
1375 u64 mask
= nicvf_int_type_to_mask(int_type
, q_idx
);
1376 /* If interrupt type is unknown, we treat it disabled. */
1378 netdev_dbg(nic
->netdev
,
1379 "Failed to check interrupt enable: unknown type\n");
1383 return mask
& nicvf_reg_read(nic
, NIC_VF_ENA_W1S
);
1386 void nicvf_update_rq_stats(struct nicvf
*nic
, int rq_idx
)
1388 struct rcv_queue
*rq
;
1390 #define GET_RQ_STATS(reg) \
1391 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\
1392 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1394 rq
= &nic
->qs
->rq
[rq_idx
];
1395 rq
->stats
.bytes
= GET_RQ_STATS(RQ_SQ_STATS_OCTS
);
1396 rq
->stats
.pkts
= GET_RQ_STATS(RQ_SQ_STATS_PKTS
);
1399 void nicvf_update_sq_stats(struct nicvf
*nic
, int sq_idx
)
1401 struct snd_queue
*sq
;
1403 #define GET_SQ_STATS(reg) \
1404 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\
1405 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1407 sq
= &nic
->qs
->sq
[sq_idx
];
1408 sq
->stats
.bytes
= GET_SQ_STATS(RQ_SQ_STATS_OCTS
);
1409 sq
->stats
.pkts
= GET_SQ_STATS(RQ_SQ_STATS_PKTS
);
1412 /* Check for errors in the receive cmp.queue entry */
1413 int nicvf_check_cqe_rx_errs(struct nicvf
*nic
, struct cqe_rx_t
*cqe_rx
)
1415 struct nicvf_hw_stats
*stats
= &nic
->hw_stats
;
1417 if (!cqe_rx
->err_level
&& !cqe_rx
->err_opcode
)
1420 if (netif_msg_rx_err(nic
))
1421 netdev_err(nic
->netdev
,
1422 "%s: RX error CQE err_level 0x%x err_opcode 0x%x\n",
1424 cqe_rx
->err_level
, cqe_rx
->err_opcode
);
1426 switch (cqe_rx
->err_opcode
) {
1427 case CQ_RX_ERROP_RE_PARTIAL
:
1428 stats
->rx_bgx_truncated_pkts
++;
1430 case CQ_RX_ERROP_RE_JABBER
:
1431 stats
->rx_jabber_errs
++;
1433 case CQ_RX_ERROP_RE_FCS
:
1434 stats
->rx_fcs_errs
++;
1436 case CQ_RX_ERROP_RE_RX_CTL
:
1437 stats
->rx_bgx_errs
++;
1439 case CQ_RX_ERROP_PREL2_ERR
:
1440 stats
->rx_prel2_errs
++;
1442 case CQ_RX_ERROP_L2_MAL
:
1443 stats
->rx_l2_hdr_malformed
++;
1445 case CQ_RX_ERROP_L2_OVERSIZE
:
1446 stats
->rx_oversize
++;
1448 case CQ_RX_ERROP_L2_UNDERSIZE
:
1449 stats
->rx_undersize
++;
1451 case CQ_RX_ERROP_L2_LENMISM
:
1452 stats
->rx_l2_len_mismatch
++;
1454 case CQ_RX_ERROP_L2_PCLP
:
1455 stats
->rx_l2_pclp
++;
1457 case CQ_RX_ERROP_IP_NOT
:
1458 stats
->rx_ip_ver_errs
++;
1460 case CQ_RX_ERROP_IP_CSUM_ERR
:
1461 stats
->rx_ip_csum_errs
++;
1463 case CQ_RX_ERROP_IP_MAL
:
1464 stats
->rx_ip_hdr_malformed
++;
1466 case CQ_RX_ERROP_IP_MALD
:
1467 stats
->rx_ip_payload_malformed
++;
1469 case CQ_RX_ERROP_IP_HOP
:
1470 stats
->rx_ip_ttl_errs
++;
1472 case CQ_RX_ERROP_L3_PCLP
:
1473 stats
->rx_l3_pclp
++;
1475 case CQ_RX_ERROP_L4_MAL
:
1476 stats
->rx_l4_malformed
++;
1478 case CQ_RX_ERROP_L4_CHK
:
1479 stats
->rx_l4_csum_errs
++;
1481 case CQ_RX_ERROP_UDP_LEN
:
1482 stats
->rx_udp_len_errs
++;
1484 case CQ_RX_ERROP_L4_PORT
:
1485 stats
->rx_l4_port_errs
++;
1487 case CQ_RX_ERROP_TCP_FLAG
:
1488 stats
->rx_tcp_flag_errs
++;
1490 case CQ_RX_ERROP_TCP_OFFSET
:
1491 stats
->rx_tcp_offset_errs
++;
1493 case CQ_RX_ERROP_L4_PCLP
:
1494 stats
->rx_l4_pclp
++;
1496 case CQ_RX_ERROP_RBDR_TRUNC
:
1497 stats
->rx_truncated_pkts
++;
1504 /* Check for errors in the send cmp.queue entry */
1505 int nicvf_check_cqe_tx_errs(struct nicvf
*nic
,
1506 struct cmp_queue
*cq
, struct cqe_send_t
*cqe_tx
)
1508 struct cmp_queue_stats
*stats
= &cq
->stats
;
1510 switch (cqe_tx
->send_status
) {
1511 case CQ_TX_ERROP_GOOD
:
1514 case CQ_TX_ERROP_DESC_FAULT
:
1515 stats
->tx
.desc_fault
++;
1517 case CQ_TX_ERROP_HDR_CONS_ERR
:
1518 stats
->tx
.hdr_cons_err
++;
1520 case CQ_TX_ERROP_SUBDC_ERR
:
1521 stats
->tx
.subdesc_err
++;
1523 case CQ_TX_ERROP_IMM_SIZE_OFLOW
:
1524 stats
->tx
.imm_size_oflow
++;
1526 case CQ_TX_ERROP_DATA_SEQUENCE_ERR
:
1527 stats
->tx
.data_seq_err
++;
1529 case CQ_TX_ERROP_MEM_SEQUENCE_ERR
:
1530 stats
->tx
.mem_seq_err
++;
1532 case CQ_TX_ERROP_LOCK_VIOL
:
1533 stats
->tx
.lock_viol
++;
1535 case CQ_TX_ERROP_DATA_FAULT
:
1536 stats
->tx
.data_fault
++;
1538 case CQ_TX_ERROP_TSTMP_CONFLICT
:
1539 stats
->tx
.tstmp_conflict
++;
1541 case CQ_TX_ERROP_TSTMP_TIMEOUT
:
1542 stats
->tx
.tstmp_timeout
++;
1544 case CQ_TX_ERROP_MEM_FAULT
:
1545 stats
->tx
.mem_fault
++;
1547 case CQ_TX_ERROP_CK_OVERLAP
:
1548 stats
->tx
.csum_overlap
++;
1550 case CQ_TX_ERROP_CK_OFLOW
:
1551 stats
->tx
.csum_overflow
++;